pci.c 26 KB

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  1. /*
  2. * Sonics Silicon Backplane PCI-Hostbus related functions.
  3. *
  4. * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
  5. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  8. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. *
  10. * Derived from the Broadcom 4400 device driver.
  11. * Copyright (C) 2002 David S. Miller (davem@redhat.com)
  12. * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  13. * Copyright (C) 2006 Broadcom Corporation.
  14. *
  15. * Licensed under the GNU/GPL. See COPYING for details.
  16. */
  17. #include <linux/ssb/ssb.h>
  18. #include <linux/ssb/ssb_regs.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include "ssb_private.h"
  23. /* Define the following to 1 to enable a printk on each coreswitch. */
  24. #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
  25. /* Lowlevel coreswitching */
  26. int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
  27. {
  28. int err;
  29. int attempts = 0;
  30. u32 cur_core;
  31. while (1) {
  32. err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
  33. (coreidx * SSB_CORE_SIZE)
  34. + SSB_ENUM_BASE);
  35. if (err)
  36. goto error;
  37. err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
  38. &cur_core);
  39. if (err)
  40. goto error;
  41. cur_core = (cur_core - SSB_ENUM_BASE)
  42. / SSB_CORE_SIZE;
  43. if (cur_core == coreidx)
  44. break;
  45. if (attempts++ > SSB_BAR0_MAX_RETRIES)
  46. goto error;
  47. udelay(10);
  48. }
  49. return 0;
  50. error:
  51. ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
  52. return -ENODEV;
  53. }
  54. int ssb_pci_switch_core(struct ssb_bus *bus,
  55. struct ssb_device *dev)
  56. {
  57. int err;
  58. unsigned long flags;
  59. #if SSB_VERBOSE_PCICORESWITCH_DEBUG
  60. ssb_printk(KERN_INFO PFX
  61. "Switching to %s core, index %d\n",
  62. ssb_core_name(dev->id.coreid),
  63. dev->core_index);
  64. #endif
  65. spin_lock_irqsave(&bus->bar_lock, flags);
  66. err = ssb_pci_switch_coreidx(bus, dev->core_index);
  67. if (!err)
  68. bus->mapped_device = dev;
  69. spin_unlock_irqrestore(&bus->bar_lock, flags);
  70. return err;
  71. }
  72. /* Enable/disable the on board crystal oscillator and/or PLL. */
  73. int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
  74. {
  75. int err;
  76. u32 in, out, outenable;
  77. u16 pci_status;
  78. if (bus->bustype != SSB_BUSTYPE_PCI)
  79. return 0;
  80. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
  81. if (err)
  82. goto err_pci;
  83. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
  84. if (err)
  85. goto err_pci;
  86. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
  87. if (err)
  88. goto err_pci;
  89. outenable |= what;
  90. if (turn_on) {
  91. /* Avoid glitching the clock if GPRS is already using it.
  92. * We can't actually read the state of the PLLPD so we infer it
  93. * by the value of XTAL_PU which *is* readable via gpioin.
  94. */
  95. if (!(in & SSB_GPIO_XTAL)) {
  96. if (what & SSB_GPIO_XTAL) {
  97. /* Turn the crystal on */
  98. out |= SSB_GPIO_XTAL;
  99. if (what & SSB_GPIO_PLL)
  100. out |= SSB_GPIO_PLL;
  101. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  102. if (err)
  103. goto err_pci;
  104. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
  105. outenable);
  106. if (err)
  107. goto err_pci;
  108. msleep(1);
  109. }
  110. if (what & SSB_GPIO_PLL) {
  111. /* Turn the PLL on */
  112. out &= ~SSB_GPIO_PLL;
  113. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  114. if (err)
  115. goto err_pci;
  116. msleep(5);
  117. }
  118. }
  119. err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
  120. if (err)
  121. goto err_pci;
  122. pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
  123. err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
  124. if (err)
  125. goto err_pci;
  126. } else {
  127. if (what & SSB_GPIO_XTAL) {
  128. /* Turn the crystal off */
  129. out &= ~SSB_GPIO_XTAL;
  130. }
  131. if (what & SSB_GPIO_PLL) {
  132. /* Turn the PLL off */
  133. out |= SSB_GPIO_PLL;
  134. }
  135. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  136. if (err)
  137. goto err_pci;
  138. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
  139. if (err)
  140. goto err_pci;
  141. }
  142. out:
  143. return err;
  144. err_pci:
  145. printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
  146. err = -EBUSY;
  147. goto out;
  148. }
  149. /* Get the word-offset for a SSB_SPROM_XXX define. */
  150. #define SPOFF(offset) ((offset) / sizeof(u16))
  151. /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  152. #define SPEX16(_outvar, _offset, _mask, _shift) \
  153. out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  154. #define SPEX32(_outvar, _offset, _mask, _shift) \
  155. out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
  156. in[SPOFF(_offset)]) & (_mask)) >> (_shift))
  157. #define SPEX(_outvar, _offset, _mask, _shift) \
  158. SPEX16(_outvar, _offset, _mask, _shift)
  159. static inline u8 ssb_crc8(u8 crc, u8 data)
  160. {
  161. /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
  162. static const u8 t[] = {
  163. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  164. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  165. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  166. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  167. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  168. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  169. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  170. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  171. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  172. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  173. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  174. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  175. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  176. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  177. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  178. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  179. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  180. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  181. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  182. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  183. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  184. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  185. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  186. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  187. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  188. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  189. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  190. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  191. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  192. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  193. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  194. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  195. };
  196. return t[crc ^ data];
  197. }
  198. static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
  199. {
  200. int word;
  201. u8 crc = 0xFF;
  202. for (word = 0; word < size - 1; word++) {
  203. crc = ssb_crc8(crc, sprom[word] & 0x00FF);
  204. crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  205. }
  206. crc = ssb_crc8(crc, sprom[size - 1] & 0x00FF);
  207. crc ^= 0xFF;
  208. return crc;
  209. }
  210. static int sprom_check_crc(const u16 *sprom, size_t size)
  211. {
  212. u8 crc;
  213. u8 expected_crc;
  214. u16 tmp;
  215. crc = ssb_sprom_crc(sprom, size);
  216. tmp = sprom[size - 1] & SSB_SPROM_REVISION_CRC;
  217. expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
  218. if (crc != expected_crc)
  219. return -EPROTO;
  220. return 0;
  221. }
  222. static int sprom_do_read(struct ssb_bus *bus, u16 *sprom)
  223. {
  224. int i;
  225. for (i = 0; i < bus->sprom_size; i++)
  226. sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
  227. return 0;
  228. }
  229. static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
  230. {
  231. struct pci_dev *pdev = bus->host_pci;
  232. int i, err;
  233. u32 spromctl;
  234. u16 size = bus->sprom_size;
  235. ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  236. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  237. if (err)
  238. goto err_ctlreg;
  239. spromctl |= SSB_SPROMCTL_WE;
  240. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  241. if (err)
  242. goto err_ctlreg;
  243. ssb_printk(KERN_NOTICE PFX "[ 0%%");
  244. msleep(500);
  245. for (i = 0; i < size; i++) {
  246. if (i == size / 4)
  247. ssb_printk("25%%");
  248. else if (i == size / 2)
  249. ssb_printk("50%%");
  250. else if (i == (size * 3) / 4)
  251. ssb_printk("75%%");
  252. else if (i % 2)
  253. ssb_printk(".");
  254. writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
  255. mmiowb();
  256. msleep(20);
  257. }
  258. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  259. if (err)
  260. goto err_ctlreg;
  261. spromctl &= ~SSB_SPROMCTL_WE;
  262. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  263. if (err)
  264. goto err_ctlreg;
  265. msleep(500);
  266. ssb_printk("100%% ]\n");
  267. ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
  268. return 0;
  269. err_ctlreg:
  270. ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
  271. return err;
  272. }
  273. static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
  274. u16 mask, u16 shift)
  275. {
  276. u16 v;
  277. u8 gain;
  278. v = in[SPOFF(SSB_SPROM1_AGAIN)];
  279. gain = (v & mask) >> shift;
  280. if (gain == 0xFF)
  281. gain = 2; /* If unset use 2dBm */
  282. if (sprom_revision == 1) {
  283. /* Convert to Q5.2 */
  284. gain <<= 2;
  285. } else {
  286. /* Q5.2 Fractional part is stored in 0xC0 */
  287. gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
  288. }
  289. return (s8)gain;
  290. }
  291. static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
  292. {
  293. int i;
  294. u16 v;
  295. s8 gain;
  296. u16 loc[3];
  297. if (out->revision == 3) /* rev 3 moved MAC */
  298. loc[0] = SSB_SPROM3_IL0MAC;
  299. else {
  300. loc[0] = SSB_SPROM1_IL0MAC;
  301. loc[1] = SSB_SPROM1_ET0MAC;
  302. loc[2] = SSB_SPROM1_ET1MAC;
  303. }
  304. for (i = 0; i < 3; i++) {
  305. v = in[SPOFF(loc[0]) + i];
  306. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  307. }
  308. if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
  309. for (i = 0; i < 3; i++) {
  310. v = in[SPOFF(loc[1]) + i];
  311. *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
  312. }
  313. for (i = 0; i < 3; i++) {
  314. v = in[SPOFF(loc[2]) + i];
  315. *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
  316. }
  317. }
  318. SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  319. SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  320. SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  321. SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  322. SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  323. SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
  324. SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
  325. SSB_SPROM1_BINF_CCODE_SHIFT);
  326. SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
  327. SSB_SPROM1_BINF_ANTA_SHIFT);
  328. SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
  329. SSB_SPROM1_BINF_ANTBG_SHIFT);
  330. SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
  331. SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
  332. SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
  333. SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
  334. SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
  335. SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
  336. SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
  337. SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
  338. SSB_SPROM1_GPIOA_P1_SHIFT);
  339. SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
  340. SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
  341. SSB_SPROM1_GPIOB_P3_SHIFT);
  342. SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
  343. SSB_SPROM1_MAXPWR_A_SHIFT);
  344. SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
  345. SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
  346. SSB_SPROM1_ITSSI_A_SHIFT);
  347. SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  348. SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  349. if (out->revision >= 2)
  350. SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  351. /* Extract the antenna gain values. */
  352. gain = r123_extract_antgain(out->revision, in,
  353. SSB_SPROM1_AGAIN_BG,
  354. SSB_SPROM1_AGAIN_BG_SHIFT);
  355. out->antenna_gain.ghz24.a0 = gain;
  356. out->antenna_gain.ghz24.a1 = gain;
  357. out->antenna_gain.ghz24.a2 = gain;
  358. out->antenna_gain.ghz24.a3 = gain;
  359. gain = r123_extract_antgain(out->revision, in,
  360. SSB_SPROM1_AGAIN_A,
  361. SSB_SPROM1_AGAIN_A_SHIFT);
  362. out->antenna_gain.ghz5.a0 = gain;
  363. out->antenna_gain.ghz5.a1 = gain;
  364. out->antenna_gain.ghz5.a2 = gain;
  365. out->antenna_gain.ghz5.a3 = gain;
  366. }
  367. static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
  368. {
  369. int i;
  370. u16 v;
  371. u16 il0mac_offset;
  372. if (out->revision == 4)
  373. il0mac_offset = SSB_SPROM4_IL0MAC;
  374. else
  375. il0mac_offset = SSB_SPROM5_IL0MAC;
  376. /* extract the MAC address */
  377. for (i = 0; i < 3; i++) {
  378. v = in[SPOFF(il0mac_offset) + i];
  379. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  380. }
  381. SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
  382. SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
  383. SSB_SPROM4_ETHPHY_ET1A_SHIFT);
  384. if (out->revision == 4) {
  385. SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
  386. SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
  387. SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
  388. } else {
  389. SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
  390. SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
  391. SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
  392. }
  393. SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
  394. SSB_SPROM4_ANTAVAIL_A_SHIFT);
  395. SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
  396. SSB_SPROM4_ANTAVAIL_BG_SHIFT);
  397. SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
  398. SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
  399. SSB_SPROM4_ITSSI_BG_SHIFT);
  400. SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
  401. SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
  402. SSB_SPROM4_ITSSI_A_SHIFT);
  403. if (out->revision == 4) {
  404. SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
  405. SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
  406. SSB_SPROM4_GPIOA_P1_SHIFT);
  407. SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
  408. SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
  409. SSB_SPROM4_GPIOB_P3_SHIFT);
  410. } else {
  411. SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
  412. SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
  413. SSB_SPROM5_GPIOA_P1_SHIFT);
  414. SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
  415. SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
  416. SSB_SPROM5_GPIOB_P3_SHIFT);
  417. }
  418. /* Extract the antenna gain values. */
  419. SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
  420. SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
  421. SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
  422. SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
  423. SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
  424. SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
  425. SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
  426. SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
  427. memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  428. sizeof(out->antenna_gain.ghz5));
  429. /* TODO - get remaining rev 4 stuff needed */
  430. }
  431. static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
  432. {
  433. int i;
  434. u16 v;
  435. /* extract the MAC address */
  436. for (i = 0; i < 3; i++) {
  437. v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
  438. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  439. }
  440. SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
  441. SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
  442. SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
  443. SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
  444. SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
  445. SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
  446. SSB_SPROM8_ANTAVAIL_A_SHIFT);
  447. SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
  448. SSB_SPROM8_ANTAVAIL_BG_SHIFT);
  449. SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
  450. SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
  451. SSB_SPROM8_ITSSI_BG_SHIFT);
  452. SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
  453. SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
  454. SSB_SPROM8_ITSSI_A_SHIFT);
  455. SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
  456. SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
  457. SSB_SPROM8_MAXP_AL_SHIFT);
  458. SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
  459. SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
  460. SSB_SPROM8_GPIOA_P1_SHIFT);
  461. SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
  462. SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
  463. SSB_SPROM8_GPIOB_P3_SHIFT);
  464. SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
  465. SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
  466. SSB_SPROM8_TRI5G_SHIFT);
  467. SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
  468. SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
  469. SSB_SPROM8_TRI5GH_SHIFT);
  470. SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
  471. SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
  472. SSB_SPROM8_RXPO5G_SHIFT);
  473. SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
  474. SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
  475. SSB_SPROM8_RSSISMC2G_SHIFT);
  476. SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
  477. SSB_SPROM8_RSSISAV2G_SHIFT);
  478. SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
  479. SSB_SPROM8_BXA2G_SHIFT);
  480. SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
  481. SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
  482. SSB_SPROM8_RSSISMC5G_SHIFT);
  483. SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
  484. SSB_SPROM8_RSSISAV5G_SHIFT);
  485. SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
  486. SSB_SPROM8_BXA5G_SHIFT);
  487. SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
  488. SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
  489. SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
  490. SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
  491. SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
  492. SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
  493. SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
  494. SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
  495. SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
  496. SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
  497. SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
  498. SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
  499. SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
  500. SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
  501. SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
  502. SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
  503. SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
  504. /* Extract the antenna gain values. */
  505. SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
  506. SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
  507. SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
  508. SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
  509. SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
  510. SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
  511. SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
  512. SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
  513. memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  514. sizeof(out->antenna_gain.ghz5));
  515. /* TODO - get remaining rev 8 stuff needed */
  516. }
  517. static int sprom_extract(struct ssb_bus *bus, struct ssb_sprom *out,
  518. const u16 *in, u16 size)
  519. {
  520. memset(out, 0, sizeof(*out));
  521. out->revision = in[size - 1] & 0x00FF;
  522. ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
  523. memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
  524. memset(out->et1mac, 0xFF, 6);
  525. if ((bus->chip_id & 0xFF00) == 0x4400) {
  526. /* Workaround: The BCM44XX chip has a stupid revision
  527. * number stored in the SPROM.
  528. * Always extract r1. */
  529. out->revision = 1;
  530. sprom_extract_r123(out, in);
  531. } else if (bus->chip_id == 0x4321) {
  532. /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
  533. out->revision = 4;
  534. sprom_extract_r45(out, in);
  535. } else {
  536. switch (out->revision) {
  537. case 1:
  538. case 2:
  539. case 3:
  540. sprom_extract_r123(out, in);
  541. break;
  542. case 4:
  543. case 5:
  544. sprom_extract_r45(out, in);
  545. break;
  546. case 8:
  547. sprom_extract_r8(out, in);
  548. break;
  549. default:
  550. ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
  551. " revision %d detected. Will extract"
  552. " v1\n", out->revision);
  553. out->revision = 1;
  554. sprom_extract_r123(out, in);
  555. }
  556. }
  557. if (out->boardflags_lo == 0xFFFF)
  558. out->boardflags_lo = 0; /* per specs */
  559. if (out->boardflags_hi == 0xFFFF)
  560. out->boardflags_hi = 0; /* per specs */
  561. return 0;
  562. }
  563. static int ssb_pci_sprom_get(struct ssb_bus *bus,
  564. struct ssb_sprom *sprom)
  565. {
  566. const struct ssb_sprom *fallback;
  567. int err = -ENOMEM;
  568. u16 *buf;
  569. if (!ssb_is_sprom_available(bus)) {
  570. ssb_printk(KERN_ERR PFX "No SPROM available!\n");
  571. return -ENODEV;
  572. }
  573. bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
  574. SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
  575. buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
  576. if (!buf)
  577. goto out;
  578. bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
  579. sprom_do_read(bus, buf);
  580. err = sprom_check_crc(buf, bus->sprom_size);
  581. if (err) {
  582. /* try for a 440 byte SPROM - revision 4 and higher */
  583. kfree(buf);
  584. buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
  585. GFP_KERNEL);
  586. if (!buf)
  587. goto out;
  588. bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
  589. sprom_do_read(bus, buf);
  590. err = sprom_check_crc(buf, bus->sprom_size);
  591. if (err) {
  592. /* All CRC attempts failed.
  593. * Maybe there is no SPROM on the device?
  594. * If we have a fallback, use that. */
  595. fallback = ssb_get_fallback_sprom();
  596. if (fallback) {
  597. memcpy(sprom, fallback, sizeof(*sprom));
  598. err = 0;
  599. goto out_free;
  600. }
  601. ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
  602. " SPROM CRC (corrupt SPROM)\n");
  603. }
  604. }
  605. err = sprom_extract(bus, sprom, buf, bus->sprom_size);
  606. out_free:
  607. kfree(buf);
  608. out:
  609. return err;
  610. }
  611. static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
  612. struct ssb_boardinfo *bi)
  613. {
  614. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
  615. &bi->vendor);
  616. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
  617. &bi->type);
  618. pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
  619. &bi->rev);
  620. }
  621. int ssb_pci_get_invariants(struct ssb_bus *bus,
  622. struct ssb_init_invariants *iv)
  623. {
  624. int err;
  625. err = ssb_pci_sprom_get(bus, &iv->sprom);
  626. if (err)
  627. goto out;
  628. ssb_pci_get_boardinfo(bus, &iv->boardinfo);
  629. out:
  630. return err;
  631. }
  632. #ifdef CONFIG_SSB_DEBUG
  633. static int ssb_pci_assert_buspower(struct ssb_bus *bus)
  634. {
  635. if (likely(bus->powered_up))
  636. return 0;
  637. printk(KERN_ERR PFX "FATAL ERROR: Bus powered down "
  638. "while accessing PCI MMIO space\n");
  639. if (bus->power_warn_count <= 10) {
  640. bus->power_warn_count++;
  641. dump_stack();
  642. }
  643. return -ENODEV;
  644. }
  645. #else /* DEBUG */
  646. static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
  647. {
  648. return 0;
  649. }
  650. #endif /* DEBUG */
  651. static u8 ssb_pci_read8(struct ssb_device *dev, u16 offset)
  652. {
  653. struct ssb_bus *bus = dev->bus;
  654. if (unlikely(ssb_pci_assert_buspower(bus)))
  655. return 0xFF;
  656. if (unlikely(bus->mapped_device != dev)) {
  657. if (unlikely(ssb_pci_switch_core(bus, dev)))
  658. return 0xFF;
  659. }
  660. return ioread8(bus->mmio + offset);
  661. }
  662. static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
  663. {
  664. struct ssb_bus *bus = dev->bus;
  665. if (unlikely(ssb_pci_assert_buspower(bus)))
  666. return 0xFFFF;
  667. if (unlikely(bus->mapped_device != dev)) {
  668. if (unlikely(ssb_pci_switch_core(bus, dev)))
  669. return 0xFFFF;
  670. }
  671. return ioread16(bus->mmio + offset);
  672. }
  673. static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
  674. {
  675. struct ssb_bus *bus = dev->bus;
  676. if (unlikely(ssb_pci_assert_buspower(bus)))
  677. return 0xFFFFFFFF;
  678. if (unlikely(bus->mapped_device != dev)) {
  679. if (unlikely(ssb_pci_switch_core(bus, dev)))
  680. return 0xFFFFFFFF;
  681. }
  682. return ioread32(bus->mmio + offset);
  683. }
  684. #ifdef CONFIG_SSB_BLOCKIO
  685. static void ssb_pci_block_read(struct ssb_device *dev, void *buffer,
  686. size_t count, u16 offset, u8 reg_width)
  687. {
  688. struct ssb_bus *bus = dev->bus;
  689. void __iomem *addr = bus->mmio + offset;
  690. if (unlikely(ssb_pci_assert_buspower(bus)))
  691. goto error;
  692. if (unlikely(bus->mapped_device != dev)) {
  693. if (unlikely(ssb_pci_switch_core(bus, dev)))
  694. goto error;
  695. }
  696. switch (reg_width) {
  697. case sizeof(u8):
  698. ioread8_rep(addr, buffer, count);
  699. break;
  700. case sizeof(u16):
  701. SSB_WARN_ON(count & 1);
  702. ioread16_rep(addr, buffer, count >> 1);
  703. break;
  704. case sizeof(u32):
  705. SSB_WARN_ON(count & 3);
  706. ioread32_rep(addr, buffer, count >> 2);
  707. break;
  708. default:
  709. SSB_WARN_ON(1);
  710. }
  711. return;
  712. error:
  713. memset(buffer, 0xFF, count);
  714. }
  715. #endif /* CONFIG_SSB_BLOCKIO */
  716. static void ssb_pci_write8(struct ssb_device *dev, u16 offset, u8 value)
  717. {
  718. struct ssb_bus *bus = dev->bus;
  719. if (unlikely(ssb_pci_assert_buspower(bus)))
  720. return;
  721. if (unlikely(bus->mapped_device != dev)) {
  722. if (unlikely(ssb_pci_switch_core(bus, dev)))
  723. return;
  724. }
  725. iowrite8(value, bus->mmio + offset);
  726. }
  727. static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
  728. {
  729. struct ssb_bus *bus = dev->bus;
  730. if (unlikely(ssb_pci_assert_buspower(bus)))
  731. return;
  732. if (unlikely(bus->mapped_device != dev)) {
  733. if (unlikely(ssb_pci_switch_core(bus, dev)))
  734. return;
  735. }
  736. iowrite16(value, bus->mmio + offset);
  737. }
  738. static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
  739. {
  740. struct ssb_bus *bus = dev->bus;
  741. if (unlikely(ssb_pci_assert_buspower(bus)))
  742. return;
  743. if (unlikely(bus->mapped_device != dev)) {
  744. if (unlikely(ssb_pci_switch_core(bus, dev)))
  745. return;
  746. }
  747. iowrite32(value, bus->mmio + offset);
  748. }
  749. #ifdef CONFIG_SSB_BLOCKIO
  750. static void ssb_pci_block_write(struct ssb_device *dev, const void *buffer,
  751. size_t count, u16 offset, u8 reg_width)
  752. {
  753. struct ssb_bus *bus = dev->bus;
  754. void __iomem *addr = bus->mmio + offset;
  755. if (unlikely(ssb_pci_assert_buspower(bus)))
  756. return;
  757. if (unlikely(bus->mapped_device != dev)) {
  758. if (unlikely(ssb_pci_switch_core(bus, dev)))
  759. return;
  760. }
  761. switch (reg_width) {
  762. case sizeof(u8):
  763. iowrite8_rep(addr, buffer, count);
  764. break;
  765. case sizeof(u16):
  766. SSB_WARN_ON(count & 1);
  767. iowrite16_rep(addr, buffer, count >> 1);
  768. break;
  769. case sizeof(u32):
  770. SSB_WARN_ON(count & 3);
  771. iowrite32_rep(addr, buffer, count >> 2);
  772. break;
  773. default:
  774. SSB_WARN_ON(1);
  775. }
  776. }
  777. #endif /* CONFIG_SSB_BLOCKIO */
  778. /* Not "static", as it's used in main.c */
  779. const struct ssb_bus_ops ssb_pci_ops = {
  780. .read8 = ssb_pci_read8,
  781. .read16 = ssb_pci_read16,
  782. .read32 = ssb_pci_read32,
  783. .write8 = ssb_pci_write8,
  784. .write16 = ssb_pci_write16,
  785. .write32 = ssb_pci_write32,
  786. #ifdef CONFIG_SSB_BLOCKIO
  787. .block_read = ssb_pci_block_read,
  788. .block_write = ssb_pci_block_write,
  789. #endif
  790. };
  791. static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
  792. struct device_attribute *attr,
  793. char *buf)
  794. {
  795. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  796. struct ssb_bus *bus;
  797. bus = ssb_pci_dev_to_bus(pdev);
  798. if (!bus)
  799. return -ENODEV;
  800. return ssb_attr_sprom_show(bus, buf, sprom_do_read);
  801. }
  802. static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
  803. struct device_attribute *attr,
  804. const char *buf, size_t count)
  805. {
  806. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  807. struct ssb_bus *bus;
  808. bus = ssb_pci_dev_to_bus(pdev);
  809. if (!bus)
  810. return -ENODEV;
  811. return ssb_attr_sprom_store(bus, buf, count,
  812. sprom_check_crc, sprom_do_write);
  813. }
  814. static DEVICE_ATTR(ssb_sprom, 0600,
  815. ssb_pci_attr_sprom_show,
  816. ssb_pci_attr_sprom_store);
  817. void ssb_pci_exit(struct ssb_bus *bus)
  818. {
  819. struct pci_dev *pdev;
  820. if (bus->bustype != SSB_BUSTYPE_PCI)
  821. return;
  822. pdev = bus->host_pci;
  823. device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
  824. }
  825. int ssb_pci_init(struct ssb_bus *bus)
  826. {
  827. struct pci_dev *pdev;
  828. int err;
  829. if (bus->bustype != SSB_BUSTYPE_PCI)
  830. return 0;
  831. pdev = bus->host_pci;
  832. mutex_init(&bus->sprom_mutex);
  833. err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
  834. if (err)
  835. goto out;
  836. out:
  837. return err;
  838. }