main.c 32 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/ssb/ssb.h>
  14. #include <linux/ssb/ssb_regs.h>
  15. #include <linux/ssb/ssb_driver_gige.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/pci.h>
  18. #include <linux/mmc/sdio_func.h>
  19. #include <linux/slab.h>
  20. #include <pcmcia/cs_types.h>
  21. #include <pcmcia/cs.h>
  22. #include <pcmcia/cistpl.h>
  23. #include <pcmcia/ds.h>
  24. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  25. MODULE_LICENSE("GPL");
  26. /* Temporary list of yet-to-be-attached buses */
  27. static LIST_HEAD(attach_queue);
  28. /* List if running buses */
  29. static LIST_HEAD(buses);
  30. /* Software ID counter */
  31. static unsigned int next_busnumber;
  32. /* buses_mutes locks the two buslists and the next_busnumber.
  33. * Don't lock this directly, but use ssb_buses_[un]lock() below. */
  34. static DEFINE_MUTEX(buses_mutex);
  35. /* There are differences in the codeflow, if the bus is
  36. * initialized from early boot, as various needed services
  37. * are not available early. This is a mechanism to delay
  38. * these initializations to after early boot has finished.
  39. * It's also used to avoid mutex locking, as that's not
  40. * available and needed early. */
  41. static bool ssb_is_early_boot = 1;
  42. static void ssb_buses_lock(void);
  43. static void ssb_buses_unlock(void);
  44. #ifdef CONFIG_SSB_PCIHOST
  45. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  46. {
  47. struct ssb_bus *bus;
  48. ssb_buses_lock();
  49. list_for_each_entry(bus, &buses, list) {
  50. if (bus->bustype == SSB_BUSTYPE_PCI &&
  51. bus->host_pci == pdev)
  52. goto found;
  53. }
  54. bus = NULL;
  55. found:
  56. ssb_buses_unlock();
  57. return bus;
  58. }
  59. #endif /* CONFIG_SSB_PCIHOST */
  60. #ifdef CONFIG_SSB_PCMCIAHOST
  61. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  62. {
  63. struct ssb_bus *bus;
  64. ssb_buses_lock();
  65. list_for_each_entry(bus, &buses, list) {
  66. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  67. bus->host_pcmcia == pdev)
  68. goto found;
  69. }
  70. bus = NULL;
  71. found:
  72. ssb_buses_unlock();
  73. return bus;
  74. }
  75. #endif /* CONFIG_SSB_PCMCIAHOST */
  76. #ifdef CONFIG_SSB_SDIOHOST
  77. struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
  78. {
  79. struct ssb_bus *bus;
  80. ssb_buses_lock();
  81. list_for_each_entry(bus, &buses, list) {
  82. if (bus->bustype == SSB_BUSTYPE_SDIO &&
  83. bus->host_sdio == func)
  84. goto found;
  85. }
  86. bus = NULL;
  87. found:
  88. ssb_buses_unlock();
  89. return bus;
  90. }
  91. #endif /* CONFIG_SSB_SDIOHOST */
  92. int ssb_for_each_bus_call(unsigned long data,
  93. int (*func)(struct ssb_bus *bus, unsigned long data))
  94. {
  95. struct ssb_bus *bus;
  96. int res;
  97. ssb_buses_lock();
  98. list_for_each_entry(bus, &buses, list) {
  99. res = func(bus, data);
  100. if (res >= 0) {
  101. ssb_buses_unlock();
  102. return res;
  103. }
  104. }
  105. ssb_buses_unlock();
  106. return -ENODEV;
  107. }
  108. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  109. {
  110. if (dev)
  111. get_device(dev->dev);
  112. return dev;
  113. }
  114. static void ssb_device_put(struct ssb_device *dev)
  115. {
  116. if (dev)
  117. put_device(dev->dev);
  118. }
  119. static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
  120. {
  121. if (drv)
  122. get_driver(&drv->drv);
  123. return drv;
  124. }
  125. static inline void ssb_driver_put(struct ssb_driver *drv)
  126. {
  127. if (drv)
  128. put_driver(&drv->drv);
  129. }
  130. static int ssb_device_resume(struct device *dev)
  131. {
  132. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  133. struct ssb_driver *ssb_drv;
  134. int err = 0;
  135. if (dev->driver) {
  136. ssb_drv = drv_to_ssb_drv(dev->driver);
  137. if (ssb_drv && ssb_drv->resume)
  138. err = ssb_drv->resume(ssb_dev);
  139. if (err)
  140. goto out;
  141. }
  142. out:
  143. return err;
  144. }
  145. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  146. {
  147. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  148. struct ssb_driver *ssb_drv;
  149. int err = 0;
  150. if (dev->driver) {
  151. ssb_drv = drv_to_ssb_drv(dev->driver);
  152. if (ssb_drv && ssb_drv->suspend)
  153. err = ssb_drv->suspend(ssb_dev, state);
  154. if (err)
  155. goto out;
  156. }
  157. out:
  158. return err;
  159. }
  160. int ssb_bus_resume(struct ssb_bus *bus)
  161. {
  162. int err;
  163. /* Reset HW state information in memory, so that HW is
  164. * completely reinitialized. */
  165. bus->mapped_device = NULL;
  166. #ifdef CONFIG_SSB_DRIVER_PCICORE
  167. bus->pcicore.setup_done = 0;
  168. #endif
  169. err = ssb_bus_powerup(bus, 0);
  170. if (err)
  171. return err;
  172. err = ssb_pcmcia_hardware_setup(bus);
  173. if (err) {
  174. ssb_bus_may_powerdown(bus);
  175. return err;
  176. }
  177. ssb_chipco_resume(&bus->chipco);
  178. ssb_bus_may_powerdown(bus);
  179. return 0;
  180. }
  181. EXPORT_SYMBOL(ssb_bus_resume);
  182. int ssb_bus_suspend(struct ssb_bus *bus)
  183. {
  184. ssb_chipco_suspend(&bus->chipco);
  185. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  186. return 0;
  187. }
  188. EXPORT_SYMBOL(ssb_bus_suspend);
  189. #ifdef CONFIG_SSB_SPROM
  190. /** ssb_devices_freeze - Freeze all devices on the bus.
  191. *
  192. * After freezing no device driver will be handling a device
  193. * on this bus anymore. ssb_devices_thaw() must be called after
  194. * a successful freeze to reactivate the devices.
  195. *
  196. * @bus: The bus.
  197. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  198. */
  199. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  200. {
  201. struct ssb_device *sdev;
  202. struct ssb_driver *sdrv;
  203. unsigned int i;
  204. memset(ctx, 0, sizeof(*ctx));
  205. ctx->bus = bus;
  206. SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  207. for (i = 0; i < bus->nr_devices; i++) {
  208. sdev = ssb_device_get(&bus->devices[i]);
  209. if (!sdev->dev || !sdev->dev->driver ||
  210. !device_is_registered(sdev->dev)) {
  211. ssb_device_put(sdev);
  212. continue;
  213. }
  214. sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
  215. if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
  216. ssb_device_put(sdev);
  217. continue;
  218. }
  219. sdrv->remove(sdev);
  220. ctx->device_frozen[i] = 1;
  221. }
  222. return 0;
  223. }
  224. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  225. *
  226. * This will re-attach the device drivers and re-init the devices.
  227. *
  228. * @ctx: The context structure from ssb_devices_freeze()
  229. */
  230. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  231. {
  232. struct ssb_bus *bus = ctx->bus;
  233. struct ssb_device *sdev;
  234. struct ssb_driver *sdrv;
  235. unsigned int i;
  236. int err, result = 0;
  237. for (i = 0; i < bus->nr_devices; i++) {
  238. if (!ctx->device_frozen[i])
  239. continue;
  240. sdev = &bus->devices[i];
  241. if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
  242. continue;
  243. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  244. if (SSB_WARN_ON(!sdrv || !sdrv->probe))
  245. continue;
  246. err = sdrv->probe(sdev, &sdev->id);
  247. if (err) {
  248. ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
  249. dev_name(sdev->dev));
  250. result = err;
  251. }
  252. ssb_driver_put(sdrv);
  253. ssb_device_put(sdev);
  254. }
  255. return result;
  256. }
  257. #endif /* CONFIG_SSB_SPROM */
  258. static void ssb_device_shutdown(struct device *dev)
  259. {
  260. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  261. struct ssb_driver *ssb_drv;
  262. if (!dev->driver)
  263. return;
  264. ssb_drv = drv_to_ssb_drv(dev->driver);
  265. if (ssb_drv && ssb_drv->shutdown)
  266. ssb_drv->shutdown(ssb_dev);
  267. }
  268. static int ssb_device_remove(struct device *dev)
  269. {
  270. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  271. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  272. if (ssb_drv && ssb_drv->remove)
  273. ssb_drv->remove(ssb_dev);
  274. ssb_device_put(ssb_dev);
  275. return 0;
  276. }
  277. static int ssb_device_probe(struct device *dev)
  278. {
  279. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  280. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  281. int err = 0;
  282. ssb_device_get(ssb_dev);
  283. if (ssb_drv && ssb_drv->probe)
  284. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  285. if (err)
  286. ssb_device_put(ssb_dev);
  287. return err;
  288. }
  289. static int ssb_match_devid(const struct ssb_device_id *tabid,
  290. const struct ssb_device_id *devid)
  291. {
  292. if ((tabid->vendor != devid->vendor) &&
  293. tabid->vendor != SSB_ANY_VENDOR)
  294. return 0;
  295. if ((tabid->coreid != devid->coreid) &&
  296. tabid->coreid != SSB_ANY_ID)
  297. return 0;
  298. if ((tabid->revision != devid->revision) &&
  299. tabid->revision != SSB_ANY_REV)
  300. return 0;
  301. return 1;
  302. }
  303. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  304. {
  305. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  306. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  307. const struct ssb_device_id *id;
  308. for (id = ssb_drv->id_table;
  309. id->vendor || id->coreid || id->revision;
  310. id++) {
  311. if (ssb_match_devid(id, &ssb_dev->id))
  312. return 1; /* found */
  313. }
  314. return 0;
  315. }
  316. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  317. {
  318. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  319. if (!dev)
  320. return -ENODEV;
  321. return add_uevent_var(env,
  322. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  323. ssb_dev->id.vendor, ssb_dev->id.coreid,
  324. ssb_dev->id.revision);
  325. }
  326. static struct bus_type ssb_bustype = {
  327. .name = "ssb",
  328. .match = ssb_bus_match,
  329. .probe = ssb_device_probe,
  330. .remove = ssb_device_remove,
  331. .shutdown = ssb_device_shutdown,
  332. .suspend = ssb_device_suspend,
  333. .resume = ssb_device_resume,
  334. .uevent = ssb_device_uevent,
  335. };
  336. static void ssb_buses_lock(void)
  337. {
  338. /* See the comment at the ssb_is_early_boot definition */
  339. if (!ssb_is_early_boot)
  340. mutex_lock(&buses_mutex);
  341. }
  342. static void ssb_buses_unlock(void)
  343. {
  344. /* See the comment at the ssb_is_early_boot definition */
  345. if (!ssb_is_early_boot)
  346. mutex_unlock(&buses_mutex);
  347. }
  348. static void ssb_devices_unregister(struct ssb_bus *bus)
  349. {
  350. struct ssb_device *sdev;
  351. int i;
  352. for (i = bus->nr_devices - 1; i >= 0; i--) {
  353. sdev = &(bus->devices[i]);
  354. if (sdev->dev)
  355. device_unregister(sdev->dev);
  356. }
  357. }
  358. void ssb_bus_unregister(struct ssb_bus *bus)
  359. {
  360. ssb_buses_lock();
  361. ssb_devices_unregister(bus);
  362. list_del(&bus->list);
  363. ssb_buses_unlock();
  364. ssb_pcmcia_exit(bus);
  365. ssb_pci_exit(bus);
  366. ssb_iounmap(bus);
  367. }
  368. EXPORT_SYMBOL(ssb_bus_unregister);
  369. static void ssb_release_dev(struct device *dev)
  370. {
  371. struct __ssb_dev_wrapper *devwrap;
  372. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  373. kfree(devwrap);
  374. }
  375. static int ssb_devices_register(struct ssb_bus *bus)
  376. {
  377. struct ssb_device *sdev;
  378. struct device *dev;
  379. struct __ssb_dev_wrapper *devwrap;
  380. int i, err = 0;
  381. int dev_idx = 0;
  382. for (i = 0; i < bus->nr_devices; i++) {
  383. sdev = &(bus->devices[i]);
  384. /* We don't register SSB-system devices to the kernel,
  385. * as the drivers for them are built into SSB. */
  386. switch (sdev->id.coreid) {
  387. case SSB_DEV_CHIPCOMMON:
  388. case SSB_DEV_PCI:
  389. case SSB_DEV_PCIE:
  390. case SSB_DEV_PCMCIA:
  391. case SSB_DEV_MIPS:
  392. case SSB_DEV_MIPS_3302:
  393. case SSB_DEV_EXTIF:
  394. continue;
  395. }
  396. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  397. if (!devwrap) {
  398. ssb_printk(KERN_ERR PFX
  399. "Could not allocate device\n");
  400. err = -ENOMEM;
  401. goto error;
  402. }
  403. dev = &devwrap->dev;
  404. devwrap->sdev = sdev;
  405. dev->release = ssb_release_dev;
  406. dev->bus = &ssb_bustype;
  407. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  408. switch (bus->bustype) {
  409. case SSB_BUSTYPE_PCI:
  410. #ifdef CONFIG_SSB_PCIHOST
  411. sdev->irq = bus->host_pci->irq;
  412. dev->parent = &bus->host_pci->dev;
  413. #endif
  414. break;
  415. case SSB_BUSTYPE_PCMCIA:
  416. #ifdef CONFIG_SSB_PCMCIAHOST
  417. sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
  418. dev->parent = &bus->host_pcmcia->dev;
  419. #endif
  420. break;
  421. case SSB_BUSTYPE_SDIO:
  422. #ifdef CONFIG_SSB_SDIOHOST
  423. dev->parent = &bus->host_sdio->dev;
  424. #endif
  425. break;
  426. case SSB_BUSTYPE_SSB:
  427. dev->dma_mask = &dev->coherent_dma_mask;
  428. break;
  429. }
  430. sdev->dev = dev;
  431. err = device_register(dev);
  432. if (err) {
  433. ssb_printk(KERN_ERR PFX
  434. "Could not register %s\n",
  435. dev_name(dev));
  436. /* Set dev to NULL to not unregister
  437. * dev on error unwinding. */
  438. sdev->dev = NULL;
  439. kfree(devwrap);
  440. goto error;
  441. }
  442. dev_idx++;
  443. }
  444. return 0;
  445. error:
  446. /* Unwind the already registered devices. */
  447. ssb_devices_unregister(bus);
  448. return err;
  449. }
  450. /* Needs ssb_buses_lock() */
  451. static int ssb_attach_queued_buses(void)
  452. {
  453. struct ssb_bus *bus, *n;
  454. int err = 0;
  455. int drop_them_all = 0;
  456. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  457. if (drop_them_all) {
  458. list_del(&bus->list);
  459. continue;
  460. }
  461. /* Can't init the PCIcore in ssb_bus_register(), as that
  462. * is too early in boot for embedded systems
  463. * (no udelay() available). So do it here in attach stage.
  464. */
  465. err = ssb_bus_powerup(bus, 0);
  466. if (err)
  467. goto error;
  468. ssb_pcicore_init(&bus->pcicore);
  469. ssb_bus_may_powerdown(bus);
  470. err = ssb_devices_register(bus);
  471. error:
  472. if (err) {
  473. drop_them_all = 1;
  474. list_del(&bus->list);
  475. continue;
  476. }
  477. list_move_tail(&bus->list, &buses);
  478. }
  479. return err;
  480. }
  481. static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
  482. {
  483. struct ssb_bus *bus = dev->bus;
  484. offset += dev->core_index * SSB_CORE_SIZE;
  485. return readb(bus->mmio + offset);
  486. }
  487. static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
  488. {
  489. struct ssb_bus *bus = dev->bus;
  490. offset += dev->core_index * SSB_CORE_SIZE;
  491. return readw(bus->mmio + offset);
  492. }
  493. static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
  494. {
  495. struct ssb_bus *bus = dev->bus;
  496. offset += dev->core_index * SSB_CORE_SIZE;
  497. return readl(bus->mmio + offset);
  498. }
  499. #ifdef CONFIG_SSB_BLOCKIO
  500. static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
  501. size_t count, u16 offset, u8 reg_width)
  502. {
  503. struct ssb_bus *bus = dev->bus;
  504. void __iomem *addr;
  505. offset += dev->core_index * SSB_CORE_SIZE;
  506. addr = bus->mmio + offset;
  507. switch (reg_width) {
  508. case sizeof(u8): {
  509. u8 *buf = buffer;
  510. while (count) {
  511. *buf = __raw_readb(addr);
  512. buf++;
  513. count--;
  514. }
  515. break;
  516. }
  517. case sizeof(u16): {
  518. __le16 *buf = buffer;
  519. SSB_WARN_ON(count & 1);
  520. while (count) {
  521. *buf = (__force __le16)__raw_readw(addr);
  522. buf++;
  523. count -= 2;
  524. }
  525. break;
  526. }
  527. case sizeof(u32): {
  528. __le32 *buf = buffer;
  529. SSB_WARN_ON(count & 3);
  530. while (count) {
  531. *buf = (__force __le32)__raw_readl(addr);
  532. buf++;
  533. count -= 4;
  534. }
  535. break;
  536. }
  537. default:
  538. SSB_WARN_ON(1);
  539. }
  540. }
  541. #endif /* CONFIG_SSB_BLOCKIO */
  542. static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
  543. {
  544. struct ssb_bus *bus = dev->bus;
  545. offset += dev->core_index * SSB_CORE_SIZE;
  546. writeb(value, bus->mmio + offset);
  547. }
  548. static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
  549. {
  550. struct ssb_bus *bus = dev->bus;
  551. offset += dev->core_index * SSB_CORE_SIZE;
  552. writew(value, bus->mmio + offset);
  553. }
  554. static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
  555. {
  556. struct ssb_bus *bus = dev->bus;
  557. offset += dev->core_index * SSB_CORE_SIZE;
  558. writel(value, bus->mmio + offset);
  559. }
  560. #ifdef CONFIG_SSB_BLOCKIO
  561. static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
  562. size_t count, u16 offset, u8 reg_width)
  563. {
  564. struct ssb_bus *bus = dev->bus;
  565. void __iomem *addr;
  566. offset += dev->core_index * SSB_CORE_SIZE;
  567. addr = bus->mmio + offset;
  568. switch (reg_width) {
  569. case sizeof(u8): {
  570. const u8 *buf = buffer;
  571. while (count) {
  572. __raw_writeb(*buf, addr);
  573. buf++;
  574. count--;
  575. }
  576. break;
  577. }
  578. case sizeof(u16): {
  579. const __le16 *buf = buffer;
  580. SSB_WARN_ON(count & 1);
  581. while (count) {
  582. __raw_writew((__force u16)(*buf), addr);
  583. buf++;
  584. count -= 2;
  585. }
  586. break;
  587. }
  588. case sizeof(u32): {
  589. const __le32 *buf = buffer;
  590. SSB_WARN_ON(count & 3);
  591. while (count) {
  592. __raw_writel((__force u32)(*buf), addr);
  593. buf++;
  594. count -= 4;
  595. }
  596. break;
  597. }
  598. default:
  599. SSB_WARN_ON(1);
  600. }
  601. }
  602. #endif /* CONFIG_SSB_BLOCKIO */
  603. /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
  604. static const struct ssb_bus_ops ssb_ssb_ops = {
  605. .read8 = ssb_ssb_read8,
  606. .read16 = ssb_ssb_read16,
  607. .read32 = ssb_ssb_read32,
  608. .write8 = ssb_ssb_write8,
  609. .write16 = ssb_ssb_write16,
  610. .write32 = ssb_ssb_write32,
  611. #ifdef CONFIG_SSB_BLOCKIO
  612. .block_read = ssb_ssb_block_read,
  613. .block_write = ssb_ssb_block_write,
  614. #endif
  615. };
  616. static int ssb_fetch_invariants(struct ssb_bus *bus,
  617. ssb_invariants_func_t get_invariants)
  618. {
  619. struct ssb_init_invariants iv;
  620. int err;
  621. memset(&iv, 0, sizeof(iv));
  622. err = get_invariants(bus, &iv);
  623. if (err)
  624. goto out;
  625. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  626. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  627. bus->has_cardbus_slot = iv.has_cardbus_slot;
  628. out:
  629. return err;
  630. }
  631. static int ssb_bus_register(struct ssb_bus *bus,
  632. ssb_invariants_func_t get_invariants,
  633. unsigned long baseaddr)
  634. {
  635. int err;
  636. spin_lock_init(&bus->bar_lock);
  637. INIT_LIST_HEAD(&bus->list);
  638. #ifdef CONFIG_SSB_EMBEDDED
  639. spin_lock_init(&bus->gpio_lock);
  640. #endif
  641. /* Powerup the bus */
  642. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  643. if (err)
  644. goto out;
  645. /* Init SDIO-host device (if any), before the scan */
  646. err = ssb_sdio_init(bus);
  647. if (err)
  648. goto err_disable_xtal;
  649. ssb_buses_lock();
  650. bus->busnumber = next_busnumber;
  651. /* Scan for devices (cores) */
  652. err = ssb_bus_scan(bus, baseaddr);
  653. if (err)
  654. goto err_sdio_exit;
  655. /* Init PCI-host device (if any) */
  656. err = ssb_pci_init(bus);
  657. if (err)
  658. goto err_unmap;
  659. /* Init PCMCIA-host device (if any) */
  660. err = ssb_pcmcia_init(bus);
  661. if (err)
  662. goto err_pci_exit;
  663. /* Initialize basic system devices (if available) */
  664. err = ssb_bus_powerup(bus, 0);
  665. if (err)
  666. goto err_pcmcia_exit;
  667. ssb_chipcommon_init(&bus->chipco);
  668. ssb_mipscore_init(&bus->mipscore);
  669. err = ssb_fetch_invariants(bus, get_invariants);
  670. if (err) {
  671. ssb_bus_may_powerdown(bus);
  672. goto err_pcmcia_exit;
  673. }
  674. ssb_bus_may_powerdown(bus);
  675. /* Queue it for attach.
  676. * See the comment at the ssb_is_early_boot definition. */
  677. list_add_tail(&bus->list, &attach_queue);
  678. if (!ssb_is_early_boot) {
  679. /* This is not early boot, so we must attach the bus now */
  680. err = ssb_attach_queued_buses();
  681. if (err)
  682. goto err_dequeue;
  683. }
  684. next_busnumber++;
  685. ssb_buses_unlock();
  686. out:
  687. return err;
  688. err_dequeue:
  689. list_del(&bus->list);
  690. err_pcmcia_exit:
  691. ssb_pcmcia_exit(bus);
  692. err_pci_exit:
  693. ssb_pci_exit(bus);
  694. err_unmap:
  695. ssb_iounmap(bus);
  696. err_sdio_exit:
  697. ssb_sdio_exit(bus);
  698. err_disable_xtal:
  699. ssb_buses_unlock();
  700. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  701. return err;
  702. }
  703. #ifdef CONFIG_SSB_PCIHOST
  704. int ssb_bus_pcibus_register(struct ssb_bus *bus,
  705. struct pci_dev *host_pci)
  706. {
  707. int err;
  708. bus->bustype = SSB_BUSTYPE_PCI;
  709. bus->host_pci = host_pci;
  710. bus->ops = &ssb_pci_ops;
  711. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  712. if (!err) {
  713. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  714. "PCI device %s\n", dev_name(&host_pci->dev));
  715. } else {
  716. ssb_printk(KERN_ERR PFX "Failed to register PCI version"
  717. " of SSB with error %d\n", err);
  718. }
  719. return err;
  720. }
  721. EXPORT_SYMBOL(ssb_bus_pcibus_register);
  722. #endif /* CONFIG_SSB_PCIHOST */
  723. #ifdef CONFIG_SSB_PCMCIAHOST
  724. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  725. struct pcmcia_device *pcmcia_dev,
  726. unsigned long baseaddr)
  727. {
  728. int err;
  729. bus->bustype = SSB_BUSTYPE_PCMCIA;
  730. bus->host_pcmcia = pcmcia_dev;
  731. bus->ops = &ssb_pcmcia_ops;
  732. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  733. if (!err) {
  734. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  735. "PCMCIA device %s\n", pcmcia_dev->devname);
  736. }
  737. return err;
  738. }
  739. EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
  740. #endif /* CONFIG_SSB_PCMCIAHOST */
  741. #ifdef CONFIG_SSB_SDIOHOST
  742. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  743. unsigned int quirks)
  744. {
  745. int err;
  746. bus->bustype = SSB_BUSTYPE_SDIO;
  747. bus->host_sdio = func;
  748. bus->ops = &ssb_sdio_ops;
  749. bus->quirks = quirks;
  750. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  751. if (!err) {
  752. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
  753. "SDIO device %s\n", sdio_func_id(func));
  754. }
  755. return err;
  756. }
  757. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  758. #endif /* CONFIG_SSB_PCMCIAHOST */
  759. int ssb_bus_ssbbus_register(struct ssb_bus *bus,
  760. unsigned long baseaddr,
  761. ssb_invariants_func_t get_invariants)
  762. {
  763. int err;
  764. bus->bustype = SSB_BUSTYPE_SSB;
  765. bus->ops = &ssb_ssb_ops;
  766. err = ssb_bus_register(bus, get_invariants, baseaddr);
  767. if (!err) {
  768. ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
  769. "address 0x%08lX\n", baseaddr);
  770. }
  771. return err;
  772. }
  773. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  774. {
  775. drv->drv.name = drv->name;
  776. drv->drv.bus = &ssb_bustype;
  777. drv->drv.owner = owner;
  778. return driver_register(&drv->drv);
  779. }
  780. EXPORT_SYMBOL(__ssb_driver_register);
  781. void ssb_driver_unregister(struct ssb_driver *drv)
  782. {
  783. driver_unregister(&drv->drv);
  784. }
  785. EXPORT_SYMBOL(ssb_driver_unregister);
  786. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  787. {
  788. struct ssb_bus *bus = dev->bus;
  789. struct ssb_device *ent;
  790. int i;
  791. for (i = 0; i < bus->nr_devices; i++) {
  792. ent = &(bus->devices[i]);
  793. if (ent->id.vendor != dev->id.vendor)
  794. continue;
  795. if (ent->id.coreid != dev->id.coreid)
  796. continue;
  797. ent->devtypedata = data;
  798. }
  799. }
  800. EXPORT_SYMBOL(ssb_set_devtypedata);
  801. static u32 clkfactor_f6_resolve(u32 v)
  802. {
  803. /* map the magic values */
  804. switch (v) {
  805. case SSB_CHIPCO_CLK_F6_2:
  806. return 2;
  807. case SSB_CHIPCO_CLK_F6_3:
  808. return 3;
  809. case SSB_CHIPCO_CLK_F6_4:
  810. return 4;
  811. case SSB_CHIPCO_CLK_F6_5:
  812. return 5;
  813. case SSB_CHIPCO_CLK_F6_6:
  814. return 6;
  815. case SSB_CHIPCO_CLK_F6_7:
  816. return 7;
  817. }
  818. return 0;
  819. }
  820. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  821. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  822. {
  823. u32 n1, n2, clock, m1, m2, m3, mc;
  824. n1 = (n & SSB_CHIPCO_CLK_N1);
  825. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  826. switch (plltype) {
  827. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  828. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  829. return SSB_CHIPCO_CLK_T6_M0;
  830. return SSB_CHIPCO_CLK_T6_M1;
  831. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  832. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  833. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  834. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  835. n1 = clkfactor_f6_resolve(n1);
  836. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  837. break;
  838. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  839. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  840. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  841. SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  842. SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  843. break;
  844. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  845. return 100000000;
  846. default:
  847. SSB_WARN_ON(1);
  848. }
  849. switch (plltype) {
  850. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  851. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  852. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  853. break;
  854. default:
  855. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  856. }
  857. if (!clock)
  858. return 0;
  859. m1 = (m & SSB_CHIPCO_CLK_M1);
  860. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  861. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  862. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  863. switch (plltype) {
  864. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  865. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  866. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  867. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  868. m1 = clkfactor_f6_resolve(m1);
  869. if ((plltype == SSB_PLLTYPE_1) ||
  870. (plltype == SSB_PLLTYPE_3))
  871. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  872. else
  873. m2 = clkfactor_f6_resolve(m2);
  874. m3 = clkfactor_f6_resolve(m3);
  875. switch (mc) {
  876. case SSB_CHIPCO_CLK_MC_BYPASS:
  877. return clock;
  878. case SSB_CHIPCO_CLK_MC_M1:
  879. return (clock / m1);
  880. case SSB_CHIPCO_CLK_MC_M1M2:
  881. return (clock / (m1 * m2));
  882. case SSB_CHIPCO_CLK_MC_M1M2M3:
  883. return (clock / (m1 * m2 * m3));
  884. case SSB_CHIPCO_CLK_MC_M1M3:
  885. return (clock / (m1 * m3));
  886. }
  887. return 0;
  888. case SSB_PLLTYPE_2:
  889. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  890. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  891. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  892. SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  893. SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  894. SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  895. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  896. clock /= m1;
  897. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  898. clock /= m2;
  899. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  900. clock /= m3;
  901. return clock;
  902. default:
  903. SSB_WARN_ON(1);
  904. }
  905. return 0;
  906. }
  907. /* Get the current speed the backplane is running at */
  908. u32 ssb_clockspeed(struct ssb_bus *bus)
  909. {
  910. u32 rate;
  911. u32 plltype;
  912. u32 clkctl_n, clkctl_m;
  913. if (ssb_extif_available(&bus->extif))
  914. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  915. &clkctl_n, &clkctl_m);
  916. else if (bus->chipco.dev)
  917. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  918. &clkctl_n, &clkctl_m);
  919. else
  920. return 0;
  921. if (bus->chip_id == 0x5365) {
  922. rate = 100000000;
  923. } else {
  924. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  925. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  926. rate /= 2;
  927. }
  928. return rate;
  929. }
  930. EXPORT_SYMBOL(ssb_clockspeed);
  931. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  932. {
  933. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  934. /* The REJECT bit changed position in TMSLOW between
  935. * Backplane revisions. */
  936. switch (rev) {
  937. case SSB_IDLOW_SSBREV_22:
  938. return SSB_TMSLOW_REJECT_22;
  939. case SSB_IDLOW_SSBREV_23:
  940. return SSB_TMSLOW_REJECT_23;
  941. case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
  942. case SSB_IDLOW_SSBREV_25: /* same here */
  943. case SSB_IDLOW_SSBREV_26: /* same here */
  944. case SSB_IDLOW_SSBREV_27: /* same here */
  945. return SSB_TMSLOW_REJECT_23; /* this is a guess */
  946. default:
  947. printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  948. WARN_ON(1);
  949. }
  950. return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
  951. }
  952. int ssb_device_is_enabled(struct ssb_device *dev)
  953. {
  954. u32 val;
  955. u32 reject;
  956. reject = ssb_tmslow_reject_bitmask(dev);
  957. val = ssb_read32(dev, SSB_TMSLOW);
  958. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  959. return (val == SSB_TMSLOW_CLOCK);
  960. }
  961. EXPORT_SYMBOL(ssb_device_is_enabled);
  962. static void ssb_flush_tmslow(struct ssb_device *dev)
  963. {
  964. /* Make _really_ sure the device has finished the TMSLOW
  965. * register write transaction, as we risk running into
  966. * a machine check exception otherwise.
  967. * Do this by reading the register back to commit the
  968. * PCI write and delay an additional usec for the device
  969. * to react to the change. */
  970. ssb_read32(dev, SSB_TMSLOW);
  971. udelay(1);
  972. }
  973. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  974. {
  975. u32 val;
  976. ssb_device_disable(dev, core_specific_flags);
  977. ssb_write32(dev, SSB_TMSLOW,
  978. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  979. SSB_TMSLOW_FGC | core_specific_flags);
  980. ssb_flush_tmslow(dev);
  981. /* Clear SERR if set. This is a hw bug workaround. */
  982. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  983. ssb_write32(dev, SSB_TMSHIGH, 0);
  984. val = ssb_read32(dev, SSB_IMSTATE);
  985. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  986. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  987. ssb_write32(dev, SSB_IMSTATE, val);
  988. }
  989. ssb_write32(dev, SSB_TMSLOW,
  990. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  991. core_specific_flags);
  992. ssb_flush_tmslow(dev);
  993. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  994. core_specific_flags);
  995. ssb_flush_tmslow(dev);
  996. }
  997. EXPORT_SYMBOL(ssb_device_enable);
  998. /* Wait for a bit in a register to get set or unset.
  999. * timeout is in units of ten-microseconds */
  1000. static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
  1001. int timeout, int set)
  1002. {
  1003. int i;
  1004. u32 val;
  1005. for (i = 0; i < timeout; i++) {
  1006. val = ssb_read32(dev, reg);
  1007. if (set) {
  1008. if (val & bitmask)
  1009. return 0;
  1010. } else {
  1011. if (!(val & bitmask))
  1012. return 0;
  1013. }
  1014. udelay(10);
  1015. }
  1016. printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
  1017. "register %04X to %s.\n",
  1018. bitmask, reg, (set ? "set" : "clear"));
  1019. return -ETIMEDOUT;
  1020. }
  1021. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  1022. {
  1023. u32 reject;
  1024. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  1025. return;
  1026. reject = ssb_tmslow_reject_bitmask(dev);
  1027. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  1028. ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
  1029. ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  1030. ssb_write32(dev, SSB_TMSLOW,
  1031. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  1032. reject | SSB_TMSLOW_RESET |
  1033. core_specific_flags);
  1034. ssb_flush_tmslow(dev);
  1035. ssb_write32(dev, SSB_TMSLOW,
  1036. reject | SSB_TMSLOW_RESET |
  1037. core_specific_flags);
  1038. ssb_flush_tmslow(dev);
  1039. }
  1040. EXPORT_SYMBOL(ssb_device_disable);
  1041. u32 ssb_dma_translation(struct ssb_device *dev)
  1042. {
  1043. switch (dev->bus->bustype) {
  1044. case SSB_BUSTYPE_SSB:
  1045. return 0;
  1046. case SSB_BUSTYPE_PCI:
  1047. return SSB_PCI_DMA;
  1048. default:
  1049. __ssb_dma_not_implemented(dev);
  1050. }
  1051. return 0;
  1052. }
  1053. EXPORT_SYMBOL(ssb_dma_translation);
  1054. int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
  1055. {
  1056. #ifdef CONFIG_SSB_PCIHOST
  1057. int err;
  1058. #endif
  1059. switch (dev->bus->bustype) {
  1060. case SSB_BUSTYPE_PCI:
  1061. #ifdef CONFIG_SSB_PCIHOST
  1062. err = pci_set_dma_mask(dev->bus->host_pci, mask);
  1063. if (err)
  1064. return err;
  1065. err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
  1066. return err;
  1067. #endif
  1068. case SSB_BUSTYPE_SSB:
  1069. return dma_set_mask(dev->dev, mask);
  1070. default:
  1071. __ssb_dma_not_implemented(dev);
  1072. }
  1073. return -ENOSYS;
  1074. }
  1075. EXPORT_SYMBOL(ssb_dma_set_mask);
  1076. void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
  1077. dma_addr_t *dma_handle, gfp_t gfp_flags)
  1078. {
  1079. switch (dev->bus->bustype) {
  1080. case SSB_BUSTYPE_PCI:
  1081. #ifdef CONFIG_SSB_PCIHOST
  1082. if (gfp_flags & GFP_DMA) {
  1083. /* Workaround: The PCI API does not support passing
  1084. * a GFP flag. */
  1085. return dma_alloc_coherent(&dev->bus->host_pci->dev,
  1086. size, dma_handle, gfp_flags);
  1087. }
  1088. return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
  1089. #endif
  1090. case SSB_BUSTYPE_SSB:
  1091. return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
  1092. default:
  1093. __ssb_dma_not_implemented(dev);
  1094. }
  1095. return NULL;
  1096. }
  1097. EXPORT_SYMBOL(ssb_dma_alloc_consistent);
  1098. void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
  1099. void *vaddr, dma_addr_t dma_handle,
  1100. gfp_t gfp_flags)
  1101. {
  1102. switch (dev->bus->bustype) {
  1103. case SSB_BUSTYPE_PCI:
  1104. #ifdef CONFIG_SSB_PCIHOST
  1105. if (gfp_flags & GFP_DMA) {
  1106. /* Workaround: The PCI API does not support passing
  1107. * a GFP flag. */
  1108. dma_free_coherent(&dev->bus->host_pci->dev,
  1109. size, vaddr, dma_handle);
  1110. return;
  1111. }
  1112. pci_free_consistent(dev->bus->host_pci, size,
  1113. vaddr, dma_handle);
  1114. return;
  1115. #endif
  1116. case SSB_BUSTYPE_SSB:
  1117. dma_free_coherent(dev->dev, size, vaddr, dma_handle);
  1118. return;
  1119. default:
  1120. __ssb_dma_not_implemented(dev);
  1121. }
  1122. }
  1123. EXPORT_SYMBOL(ssb_dma_free_consistent);
  1124. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  1125. {
  1126. struct ssb_chipcommon *cc;
  1127. int err = 0;
  1128. /* On buses where more than one core may be working
  1129. * at a time, we must not powerdown stuff if there are
  1130. * still cores that may want to run. */
  1131. if (bus->bustype == SSB_BUSTYPE_SSB)
  1132. goto out;
  1133. cc = &bus->chipco;
  1134. if (!cc->dev)
  1135. goto out;
  1136. if (cc->dev->id.revision < 5)
  1137. goto out;
  1138. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1139. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1140. if (err)
  1141. goto error;
  1142. out:
  1143. #ifdef CONFIG_SSB_DEBUG
  1144. bus->powered_up = 0;
  1145. #endif
  1146. return err;
  1147. error:
  1148. ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
  1149. goto out;
  1150. }
  1151. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1152. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1153. {
  1154. struct ssb_chipcommon *cc;
  1155. int err;
  1156. enum ssb_clkmode mode;
  1157. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1158. if (err)
  1159. goto error;
  1160. cc = &bus->chipco;
  1161. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1162. ssb_chipco_set_clockmode(cc, mode);
  1163. #ifdef CONFIG_SSB_DEBUG
  1164. bus->powered_up = 1;
  1165. #endif
  1166. return 0;
  1167. error:
  1168. ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
  1169. return err;
  1170. }
  1171. EXPORT_SYMBOL(ssb_bus_powerup);
  1172. u32 ssb_admatch_base(u32 adm)
  1173. {
  1174. u32 base = 0;
  1175. switch (adm & SSB_ADM_TYPE) {
  1176. case SSB_ADM_TYPE0:
  1177. base = (adm & SSB_ADM_BASE0);
  1178. break;
  1179. case SSB_ADM_TYPE1:
  1180. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1181. base = (adm & SSB_ADM_BASE1);
  1182. break;
  1183. case SSB_ADM_TYPE2:
  1184. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1185. base = (adm & SSB_ADM_BASE2);
  1186. break;
  1187. default:
  1188. SSB_WARN_ON(1);
  1189. }
  1190. return base;
  1191. }
  1192. EXPORT_SYMBOL(ssb_admatch_base);
  1193. u32 ssb_admatch_size(u32 adm)
  1194. {
  1195. u32 size = 0;
  1196. switch (adm & SSB_ADM_TYPE) {
  1197. case SSB_ADM_TYPE0:
  1198. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1199. break;
  1200. case SSB_ADM_TYPE1:
  1201. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1202. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1203. break;
  1204. case SSB_ADM_TYPE2:
  1205. SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1206. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1207. break;
  1208. default:
  1209. SSB_WARN_ON(1);
  1210. }
  1211. size = (1 << (size + 1));
  1212. return size;
  1213. }
  1214. EXPORT_SYMBOL(ssb_admatch_size);
  1215. static int __init ssb_modinit(void)
  1216. {
  1217. int err;
  1218. /* See the comment at the ssb_is_early_boot definition */
  1219. ssb_is_early_boot = 0;
  1220. err = bus_register(&ssb_bustype);
  1221. if (err)
  1222. return err;
  1223. /* Maybe we already registered some buses at early boot.
  1224. * Check for this and attach them
  1225. */
  1226. ssb_buses_lock();
  1227. err = ssb_attach_queued_buses();
  1228. ssb_buses_unlock();
  1229. if (err) {
  1230. bus_unregister(&ssb_bustype);
  1231. goto out;
  1232. }
  1233. err = b43_pci_ssb_bridge_init();
  1234. if (err) {
  1235. ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
  1236. "initialization failed\n");
  1237. /* don't fail SSB init because of this */
  1238. err = 0;
  1239. }
  1240. err = ssb_gige_init();
  1241. if (err) {
  1242. ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
  1243. "driver initialization failed\n");
  1244. /* don't fail SSB init because of this */
  1245. err = 0;
  1246. }
  1247. out:
  1248. return err;
  1249. }
  1250. /* ssb must be initialized after PCI but before the ssb drivers.
  1251. * That means we must use some initcall between subsys_initcall
  1252. * and device_initcall. */
  1253. fs_initcall(ssb_modinit);
  1254. static void __exit ssb_modexit(void)
  1255. {
  1256. ssb_gige_exit();
  1257. b43_pci_ssb_bridge_exit();
  1258. bus_unregister(&ssb_bustype);
  1259. }
  1260. module_exit(ssb_modexit)