qlcnic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2009 - QLogic Corporation.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called "COPYING".
  22. *
  23. */
  24. #include <linux/netdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include "qlcnic.h"
  28. struct crb_addr_pair {
  29. u32 addr;
  30. u32 data;
  31. };
  32. #define QLCNIC_MAX_CRB_XFORM 60
  33. static unsigned int crb_addr_xform[QLCNIC_MAX_CRB_XFORM];
  34. #define crb_addr_transform(name) \
  35. (crb_addr_xform[QLCNIC_HW_PX_MAP_CRB_##name] = \
  36. QLCNIC_HW_CRB_HUB_AGT_ADR_##name << 20)
  37. #define QLCNIC_ADDR_ERROR (0xffffffff)
  38. static void
  39. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  40. struct qlcnic_host_rds_ring *rds_ring);
  41. static void crb_addr_transform_setup(void)
  42. {
  43. crb_addr_transform(XDMA);
  44. crb_addr_transform(TIMR);
  45. crb_addr_transform(SRE);
  46. crb_addr_transform(SQN3);
  47. crb_addr_transform(SQN2);
  48. crb_addr_transform(SQN1);
  49. crb_addr_transform(SQN0);
  50. crb_addr_transform(SQS3);
  51. crb_addr_transform(SQS2);
  52. crb_addr_transform(SQS1);
  53. crb_addr_transform(SQS0);
  54. crb_addr_transform(RPMX7);
  55. crb_addr_transform(RPMX6);
  56. crb_addr_transform(RPMX5);
  57. crb_addr_transform(RPMX4);
  58. crb_addr_transform(RPMX3);
  59. crb_addr_transform(RPMX2);
  60. crb_addr_transform(RPMX1);
  61. crb_addr_transform(RPMX0);
  62. crb_addr_transform(ROMUSB);
  63. crb_addr_transform(SN);
  64. crb_addr_transform(QMN);
  65. crb_addr_transform(QMS);
  66. crb_addr_transform(PGNI);
  67. crb_addr_transform(PGND);
  68. crb_addr_transform(PGN3);
  69. crb_addr_transform(PGN2);
  70. crb_addr_transform(PGN1);
  71. crb_addr_transform(PGN0);
  72. crb_addr_transform(PGSI);
  73. crb_addr_transform(PGSD);
  74. crb_addr_transform(PGS3);
  75. crb_addr_transform(PGS2);
  76. crb_addr_transform(PGS1);
  77. crb_addr_transform(PGS0);
  78. crb_addr_transform(PS);
  79. crb_addr_transform(PH);
  80. crb_addr_transform(NIU);
  81. crb_addr_transform(I2Q);
  82. crb_addr_transform(EG);
  83. crb_addr_transform(MN);
  84. crb_addr_transform(MS);
  85. crb_addr_transform(CAS2);
  86. crb_addr_transform(CAS1);
  87. crb_addr_transform(CAS0);
  88. crb_addr_transform(CAM);
  89. crb_addr_transform(C2C1);
  90. crb_addr_transform(C2C0);
  91. crb_addr_transform(SMB);
  92. crb_addr_transform(OCM0);
  93. crb_addr_transform(I2C0);
  94. }
  95. void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter)
  96. {
  97. struct qlcnic_recv_context *recv_ctx;
  98. struct qlcnic_host_rds_ring *rds_ring;
  99. struct qlcnic_rx_buffer *rx_buf;
  100. int i, ring;
  101. recv_ctx = &adapter->recv_ctx;
  102. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  103. rds_ring = &recv_ctx->rds_rings[ring];
  104. for (i = 0; i < rds_ring->num_desc; ++i) {
  105. rx_buf = &(rds_ring->rx_buf_arr[i]);
  106. if (rx_buf->state == QLCNIC_BUFFER_FREE)
  107. continue;
  108. pci_unmap_single(adapter->pdev,
  109. rx_buf->dma,
  110. rds_ring->dma_size,
  111. PCI_DMA_FROMDEVICE);
  112. if (rx_buf->skb != NULL)
  113. dev_kfree_skb_any(rx_buf->skb);
  114. }
  115. }
  116. }
  117. void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter)
  118. {
  119. struct qlcnic_cmd_buffer *cmd_buf;
  120. struct qlcnic_skb_frag *buffrag;
  121. int i, j;
  122. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  123. cmd_buf = tx_ring->cmd_buf_arr;
  124. for (i = 0; i < tx_ring->num_desc; i++) {
  125. buffrag = cmd_buf->frag_array;
  126. if (buffrag->dma) {
  127. pci_unmap_single(adapter->pdev, buffrag->dma,
  128. buffrag->length, PCI_DMA_TODEVICE);
  129. buffrag->dma = 0ULL;
  130. }
  131. for (j = 0; j < cmd_buf->frag_count; j++) {
  132. buffrag++;
  133. if (buffrag->dma) {
  134. pci_unmap_page(adapter->pdev, buffrag->dma,
  135. buffrag->length,
  136. PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. }
  140. if (cmd_buf->skb) {
  141. dev_kfree_skb_any(cmd_buf->skb);
  142. cmd_buf->skb = NULL;
  143. }
  144. cmd_buf++;
  145. }
  146. }
  147. void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter)
  148. {
  149. struct qlcnic_recv_context *recv_ctx;
  150. struct qlcnic_host_rds_ring *rds_ring;
  151. struct qlcnic_host_tx_ring *tx_ring;
  152. int ring;
  153. recv_ctx = &adapter->recv_ctx;
  154. if (recv_ctx->rds_rings == NULL)
  155. goto skip_rds;
  156. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  157. rds_ring = &recv_ctx->rds_rings[ring];
  158. vfree(rds_ring->rx_buf_arr);
  159. rds_ring->rx_buf_arr = NULL;
  160. }
  161. kfree(recv_ctx->rds_rings);
  162. skip_rds:
  163. if (adapter->tx_ring == NULL)
  164. return;
  165. tx_ring = adapter->tx_ring;
  166. vfree(tx_ring->cmd_buf_arr);
  167. kfree(adapter->tx_ring);
  168. }
  169. int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
  170. {
  171. struct qlcnic_recv_context *recv_ctx;
  172. struct qlcnic_host_rds_ring *rds_ring;
  173. struct qlcnic_host_sds_ring *sds_ring;
  174. struct qlcnic_host_tx_ring *tx_ring;
  175. struct qlcnic_rx_buffer *rx_buf;
  176. int ring, i, size;
  177. struct qlcnic_cmd_buffer *cmd_buf_arr;
  178. struct net_device *netdev = adapter->netdev;
  179. size = sizeof(struct qlcnic_host_tx_ring);
  180. tx_ring = kzalloc(size, GFP_KERNEL);
  181. if (tx_ring == NULL) {
  182. dev_err(&netdev->dev, "failed to allocate tx ring struct\n");
  183. return -ENOMEM;
  184. }
  185. adapter->tx_ring = tx_ring;
  186. tx_ring->num_desc = adapter->num_txd;
  187. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  188. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  189. if (cmd_buf_arr == NULL) {
  190. dev_err(&netdev->dev, "failed to allocate cmd buffer ring\n");
  191. return -ENOMEM;
  192. }
  193. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  194. tx_ring->cmd_buf_arr = cmd_buf_arr;
  195. recv_ctx = &adapter->recv_ctx;
  196. size = adapter->max_rds_rings * sizeof(struct qlcnic_host_rds_ring);
  197. rds_ring = kzalloc(size, GFP_KERNEL);
  198. if (rds_ring == NULL) {
  199. dev_err(&netdev->dev, "failed to allocate rds ring struct\n");
  200. return -ENOMEM;
  201. }
  202. recv_ctx->rds_rings = rds_ring;
  203. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  204. rds_ring = &recv_ctx->rds_rings[ring];
  205. switch (ring) {
  206. case RCV_RING_NORMAL:
  207. rds_ring->num_desc = adapter->num_rxd;
  208. if (adapter->ahw.cut_through) {
  209. rds_ring->dma_size =
  210. QLCNIC_CT_DEFAULT_RX_BUF_LEN;
  211. rds_ring->skb_size =
  212. QLCNIC_CT_DEFAULT_RX_BUF_LEN;
  213. } else {
  214. rds_ring->dma_size =
  215. QLCNIC_P3_RX_BUF_MAX_LEN;
  216. rds_ring->skb_size =
  217. rds_ring->dma_size + NET_IP_ALIGN;
  218. }
  219. break;
  220. case RCV_RING_JUMBO:
  221. rds_ring->num_desc = adapter->num_jumbo_rxd;
  222. rds_ring->dma_size =
  223. QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN;
  224. if (adapter->capabilities & QLCNIC_FW_CAPABILITY_HW_LRO)
  225. rds_ring->dma_size += QLCNIC_LRO_BUFFER_EXTRA;
  226. rds_ring->skb_size =
  227. rds_ring->dma_size + NET_IP_ALIGN;
  228. break;
  229. case RCV_RING_LRO:
  230. rds_ring->num_desc = adapter->num_lro_rxd;
  231. rds_ring->dma_size = QLCNIC_RX_LRO_BUFFER_LENGTH;
  232. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  233. break;
  234. }
  235. rds_ring->rx_buf_arr = (struct qlcnic_rx_buffer *)
  236. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  237. if (rds_ring->rx_buf_arr == NULL) {
  238. dev_err(&netdev->dev, "Failed to allocate "
  239. "rx buffer ring %d\n", ring);
  240. goto err_out;
  241. }
  242. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  243. INIT_LIST_HEAD(&rds_ring->free_list);
  244. /*
  245. * Now go through all of them, set reference handles
  246. * and put them in the queues.
  247. */
  248. rx_buf = rds_ring->rx_buf_arr;
  249. for (i = 0; i < rds_ring->num_desc; i++) {
  250. list_add_tail(&rx_buf->list,
  251. &rds_ring->free_list);
  252. rx_buf->ref_handle = i;
  253. rx_buf->state = QLCNIC_BUFFER_FREE;
  254. rx_buf++;
  255. }
  256. spin_lock_init(&rds_ring->lock);
  257. }
  258. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  259. sds_ring = &recv_ctx->sds_rings[ring];
  260. sds_ring->irq = adapter->msix_entries[ring].vector;
  261. sds_ring->adapter = adapter;
  262. sds_ring->num_desc = adapter->num_rxd;
  263. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  264. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  265. }
  266. return 0;
  267. err_out:
  268. qlcnic_free_sw_resources(adapter);
  269. return -ENOMEM;
  270. }
  271. /*
  272. * Utility to translate from internal Phantom CRB address
  273. * to external PCI CRB address.
  274. */
  275. static u32 qlcnic_decode_crb_addr(u32 addr)
  276. {
  277. int i;
  278. u32 base_addr, offset, pci_base;
  279. crb_addr_transform_setup();
  280. pci_base = QLCNIC_ADDR_ERROR;
  281. base_addr = addr & 0xfff00000;
  282. offset = addr & 0x000fffff;
  283. for (i = 0; i < QLCNIC_MAX_CRB_XFORM; i++) {
  284. if (crb_addr_xform[i] == base_addr) {
  285. pci_base = i << 20;
  286. break;
  287. }
  288. }
  289. if (pci_base == QLCNIC_ADDR_ERROR)
  290. return pci_base;
  291. else
  292. return pci_base + offset;
  293. }
  294. #define QLCNIC_MAX_ROM_WAIT_USEC 100
  295. static int qlcnic_wait_rom_done(struct qlcnic_adapter *adapter)
  296. {
  297. long timeout = 0;
  298. long done = 0;
  299. cond_resched();
  300. while (done == 0) {
  301. done = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_STATUS);
  302. done &= 2;
  303. if (++timeout >= QLCNIC_MAX_ROM_WAIT_USEC) {
  304. dev_err(&adapter->pdev->dev,
  305. "Timeout reached waiting for rom done");
  306. return -EIO;
  307. }
  308. udelay(1);
  309. }
  310. return 0;
  311. }
  312. static int do_rom_fast_read(struct qlcnic_adapter *adapter,
  313. int addr, int *valp)
  314. {
  315. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ADDRESS, addr);
  316. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  317. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 3);
  318. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  319. if (qlcnic_wait_rom_done(adapter)) {
  320. dev_err(&adapter->pdev->dev, "Error waiting for rom done\n");
  321. return -EIO;
  322. }
  323. /* reset abyte_cnt and dummy_byte_cnt */
  324. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_ABYTE_CNT, 0);
  325. udelay(10);
  326. QLCWR32(adapter, QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  327. *valp = QLCRD32(adapter, QLCNIC_ROMUSB_ROM_RDATA);
  328. return 0;
  329. }
  330. static int do_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  331. u8 *bytes, size_t size)
  332. {
  333. int addridx;
  334. int ret = 0;
  335. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  336. int v;
  337. ret = do_rom_fast_read(adapter, addridx, &v);
  338. if (ret != 0)
  339. break;
  340. *(__le32 *)bytes = cpu_to_le32(v);
  341. bytes += 4;
  342. }
  343. return ret;
  344. }
  345. int
  346. qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
  347. u8 *bytes, size_t size)
  348. {
  349. int ret;
  350. ret = qlcnic_rom_lock(adapter);
  351. if (ret < 0)
  352. return ret;
  353. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  354. qlcnic_rom_unlock(adapter);
  355. return ret;
  356. }
  357. int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp)
  358. {
  359. int ret;
  360. if (qlcnic_rom_lock(adapter) != 0)
  361. return -EIO;
  362. ret = do_rom_fast_read(adapter, addr, valp);
  363. qlcnic_rom_unlock(adapter);
  364. return ret;
  365. }
  366. int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
  367. {
  368. int addr, val;
  369. int i, n, init_delay;
  370. struct crb_addr_pair *buf;
  371. unsigned offset;
  372. u32 off;
  373. struct pci_dev *pdev = adapter->pdev;
  374. /* resetall */
  375. qlcnic_rom_lock(adapter);
  376. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xffffffff);
  377. qlcnic_rom_unlock(adapter);
  378. if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
  379. qlcnic_rom_fast_read(adapter, 4, &n) != 0) {
  380. dev_err(&pdev->dev, "ERROR Reading crb_init area: val:%x\n", n);
  381. return -EIO;
  382. }
  383. offset = n & 0xffffU;
  384. n = (n >> 16) & 0xffffU;
  385. if (n >= 1024) {
  386. dev_err(&pdev->dev, "QLOGIC card flash not initialized.\n");
  387. return -EIO;
  388. }
  389. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  390. if (buf == NULL) {
  391. dev_err(&pdev->dev, "Unable to calloc memory for rom read.\n");
  392. return -ENOMEM;
  393. }
  394. for (i = 0; i < n; i++) {
  395. if (qlcnic_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  396. qlcnic_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  397. kfree(buf);
  398. return -EIO;
  399. }
  400. buf[i].addr = addr;
  401. buf[i].data = val;
  402. }
  403. for (i = 0; i < n; i++) {
  404. off = qlcnic_decode_crb_addr(buf[i].addr);
  405. if (off == QLCNIC_ADDR_ERROR) {
  406. dev_err(&pdev->dev, "CRB init value out of range %x\n",
  407. buf[i].addr);
  408. continue;
  409. }
  410. off += QLCNIC_PCI_CRBSPACE;
  411. if (off & 1)
  412. continue;
  413. /* skipping cold reboot MAGIC */
  414. if (off == QLCNIC_CAM_RAM(0x1fc))
  415. continue;
  416. if (off == (QLCNIC_CRB_I2C0 + 0x1c))
  417. continue;
  418. if (off == (ROMUSB_GLB + 0xbc)) /* do not reset PCI */
  419. continue;
  420. if (off == (ROMUSB_GLB + 0xa8))
  421. continue;
  422. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  423. continue;
  424. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  425. continue;
  426. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  427. continue;
  428. if ((off & 0x0ff00000) == QLCNIC_CRB_DDR_NET)
  429. continue;
  430. /* skip the function enable register */
  431. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION))
  432. continue;
  433. if (off == QLCNIC_PCIE_REG(PCIE_SETUP_FUNCTION2))
  434. continue;
  435. if ((off & 0x0ff00000) == QLCNIC_CRB_SMB)
  436. continue;
  437. init_delay = 1;
  438. /* After writing this register, HW needs time for CRB */
  439. /* to quiet down (else crb_window returns 0xffffffff) */
  440. if (off == QLCNIC_ROMUSB_GLB_SW_RESET)
  441. init_delay = 1000;
  442. QLCWR32(adapter, off, buf[i].data);
  443. msleep(init_delay);
  444. }
  445. kfree(buf);
  446. /* p2dn replyCount */
  447. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0xec, 0x1e);
  448. /* disable_peg_cache 0 & 1*/
  449. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_D + 0x4c, 8);
  450. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_I + 0x4c, 8);
  451. /* peg_clr_all */
  452. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x8, 0);
  453. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0xc, 0);
  454. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x8, 0);
  455. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0xc, 0);
  456. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x8, 0);
  457. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0xc, 0);
  458. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x8, 0);
  459. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
  460. return 0;
  461. }
  462. void
  463. qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
  464. int timeo;
  465. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DEV_INIT_TIMEOUT, &timeo))
  466. timeo = 30;
  467. adapter->dev_init_timeo = timeo;
  468. if (qlcnic_rom_fast_read(adapter, QLCNIC_ROM_DRV_RESET_TIMEOUT, &timeo))
  469. timeo = 10;
  470. adapter->reset_ack_timeo = timeo;
  471. }
  472. static int
  473. qlcnic_has_mn(struct qlcnic_adapter *adapter)
  474. {
  475. u32 capability, flashed_ver;
  476. capability = 0;
  477. qlcnic_rom_fast_read(adapter,
  478. QLCNIC_FW_VERSION_OFFSET, (int *)&flashed_ver);
  479. flashed_ver = QLCNIC_DECODE_VERSION(flashed_ver);
  480. if (flashed_ver >= QLCNIC_VERSION_CODE(4, 0, 220)) {
  481. capability = QLCRD32(adapter, QLCNIC_PEG_TUNE_CAPABILITY);
  482. if (capability & QLCNIC_PEG_TUNE_MN_PRESENT)
  483. return 1;
  484. }
  485. return 0;
  486. }
  487. static
  488. struct uni_table_desc *qlcnic_get_table_desc(const u8 *unirom, int section)
  489. {
  490. u32 i;
  491. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  492. __le32 entries = cpu_to_le32(directory->num_entries);
  493. for (i = 0; i < entries; i++) {
  494. __le32 offs = cpu_to_le32(directory->findex) +
  495. (i * cpu_to_le32(directory->entry_size));
  496. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  497. if (tab_type == section)
  498. return (struct uni_table_desc *) &unirom[offs];
  499. }
  500. return NULL;
  501. }
  502. #define FILEHEADER_SIZE (14 * 4)
  503. static int
  504. qlcnic_validate_header(struct qlcnic_adapter *adapter)
  505. {
  506. const u8 *unirom = adapter->fw->data;
  507. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  508. __le32 fw_file_size = adapter->fw->size;
  509. __le32 entries;
  510. __le32 entry_size;
  511. __le32 tab_size;
  512. if (fw_file_size < FILEHEADER_SIZE)
  513. return -EINVAL;
  514. entries = cpu_to_le32(directory->num_entries);
  515. entry_size = cpu_to_le32(directory->entry_size);
  516. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  517. if (fw_file_size < tab_size)
  518. return -EINVAL;
  519. return 0;
  520. }
  521. static int
  522. qlcnic_validate_bootld(struct qlcnic_adapter *adapter)
  523. {
  524. struct uni_table_desc *tab_desc;
  525. struct uni_data_desc *descr;
  526. const u8 *unirom = adapter->fw->data;
  527. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  528. QLCNIC_UNI_BOOTLD_IDX_OFF));
  529. __le32 offs;
  530. __le32 tab_size;
  531. __le32 data_size;
  532. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_BOOTLD);
  533. if (!tab_desc)
  534. return -EINVAL;
  535. tab_size = cpu_to_le32(tab_desc->findex) +
  536. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  537. if (adapter->fw->size < tab_size)
  538. return -EINVAL;
  539. offs = cpu_to_le32(tab_desc->findex) +
  540. (cpu_to_le32(tab_desc->entry_size) * (idx));
  541. descr = (struct uni_data_desc *)&unirom[offs];
  542. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  543. if (adapter->fw->size < data_size)
  544. return -EINVAL;
  545. return 0;
  546. }
  547. static int
  548. qlcnic_validate_fw(struct qlcnic_adapter *adapter)
  549. {
  550. struct uni_table_desc *tab_desc;
  551. struct uni_data_desc *descr;
  552. const u8 *unirom = adapter->fw->data;
  553. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  554. QLCNIC_UNI_FIRMWARE_IDX_OFF));
  555. __le32 offs;
  556. __le32 tab_size;
  557. __le32 data_size;
  558. tab_desc = qlcnic_get_table_desc(unirom, QLCNIC_UNI_DIR_SECT_FW);
  559. if (!tab_desc)
  560. return -EINVAL;
  561. tab_size = cpu_to_le32(tab_desc->findex) +
  562. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  563. if (adapter->fw->size < tab_size)
  564. return -EINVAL;
  565. offs = cpu_to_le32(tab_desc->findex) +
  566. (cpu_to_le32(tab_desc->entry_size) * (idx));
  567. descr = (struct uni_data_desc *)&unirom[offs];
  568. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  569. if (adapter->fw->size < data_size)
  570. return -EINVAL;
  571. return 0;
  572. }
  573. static int
  574. qlcnic_validate_product_offs(struct qlcnic_adapter *adapter)
  575. {
  576. struct uni_table_desc *ptab_descr;
  577. const u8 *unirom = adapter->fw->data;
  578. int mn_present = qlcnic_has_mn(adapter);
  579. __le32 entries;
  580. __le32 entry_size;
  581. __le32 tab_size;
  582. u32 i;
  583. ptab_descr = qlcnic_get_table_desc(unirom,
  584. QLCNIC_UNI_DIR_SECT_PRODUCT_TBL);
  585. if (!ptab_descr)
  586. return -EINVAL;
  587. entries = cpu_to_le32(ptab_descr->num_entries);
  588. entry_size = cpu_to_le32(ptab_descr->entry_size);
  589. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  590. if (adapter->fw->size < tab_size)
  591. return -EINVAL;
  592. nomn:
  593. for (i = 0; i < entries; i++) {
  594. __le32 flags, file_chiprev, offs;
  595. u8 chiprev = adapter->ahw.revision_id;
  596. u32 flagbit;
  597. offs = cpu_to_le32(ptab_descr->findex) +
  598. (i * cpu_to_le32(ptab_descr->entry_size));
  599. flags = cpu_to_le32(*((int *)&unirom[offs] +
  600. QLCNIC_UNI_FLAGS_OFF));
  601. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  602. QLCNIC_UNI_CHIP_REV_OFF));
  603. flagbit = mn_present ? 1 : 2;
  604. if ((chiprev == file_chiprev) &&
  605. ((1ULL << flagbit) & flags)) {
  606. adapter->file_prd_off = offs;
  607. return 0;
  608. }
  609. }
  610. if (mn_present) {
  611. mn_present = 0;
  612. goto nomn;
  613. }
  614. return -EINVAL;
  615. }
  616. static int
  617. qlcnic_validate_unified_romimage(struct qlcnic_adapter *adapter)
  618. {
  619. if (qlcnic_validate_header(adapter)) {
  620. dev_err(&adapter->pdev->dev,
  621. "unified image: header validation failed\n");
  622. return -EINVAL;
  623. }
  624. if (qlcnic_validate_product_offs(adapter)) {
  625. dev_err(&adapter->pdev->dev,
  626. "unified image: product validation failed\n");
  627. return -EINVAL;
  628. }
  629. if (qlcnic_validate_bootld(adapter)) {
  630. dev_err(&adapter->pdev->dev,
  631. "unified image: bootld validation failed\n");
  632. return -EINVAL;
  633. }
  634. if (qlcnic_validate_fw(adapter)) {
  635. dev_err(&adapter->pdev->dev,
  636. "unified image: firmware validation failed\n");
  637. return -EINVAL;
  638. }
  639. return 0;
  640. }
  641. static
  642. struct uni_data_desc *qlcnic_get_data_desc(struct qlcnic_adapter *adapter,
  643. u32 section, u32 idx_offset)
  644. {
  645. const u8 *unirom = adapter->fw->data;
  646. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  647. idx_offset));
  648. struct uni_table_desc *tab_desc;
  649. __le32 offs;
  650. tab_desc = qlcnic_get_table_desc(unirom, section);
  651. if (tab_desc == NULL)
  652. return NULL;
  653. offs = cpu_to_le32(tab_desc->findex) +
  654. (cpu_to_le32(tab_desc->entry_size) * idx);
  655. return (struct uni_data_desc *)&unirom[offs];
  656. }
  657. static u8 *
  658. qlcnic_get_bootld_offs(struct qlcnic_adapter *adapter)
  659. {
  660. u32 offs = QLCNIC_BOOTLD_START;
  661. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  662. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  663. QLCNIC_UNI_DIR_SECT_BOOTLD,
  664. QLCNIC_UNI_BOOTLD_IDX_OFF))->findex);
  665. return (u8 *)&adapter->fw->data[offs];
  666. }
  667. static u8 *
  668. qlcnic_get_fw_offs(struct qlcnic_adapter *adapter)
  669. {
  670. u32 offs = QLCNIC_IMAGE_START;
  671. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  672. offs = cpu_to_le32((qlcnic_get_data_desc(adapter,
  673. QLCNIC_UNI_DIR_SECT_FW,
  674. QLCNIC_UNI_FIRMWARE_IDX_OFF))->findex);
  675. return (u8 *)&adapter->fw->data[offs];
  676. }
  677. static __le32
  678. qlcnic_get_fw_size(struct qlcnic_adapter *adapter)
  679. {
  680. if (adapter->fw_type == QLCNIC_UNIFIED_ROMIMAGE)
  681. return cpu_to_le32((qlcnic_get_data_desc(adapter,
  682. QLCNIC_UNI_DIR_SECT_FW,
  683. QLCNIC_UNI_FIRMWARE_IDX_OFF))->size);
  684. else
  685. return cpu_to_le32(
  686. *(u32 *)&adapter->fw->data[QLCNIC_FW_SIZE_OFFSET]);
  687. }
  688. static __le32
  689. qlcnic_get_fw_version(struct qlcnic_adapter *adapter)
  690. {
  691. struct uni_data_desc *fw_data_desc;
  692. const struct firmware *fw = adapter->fw;
  693. __le32 major, minor, sub;
  694. const u8 *ver_str;
  695. int i, ret;
  696. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  697. return cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_VERSION_OFFSET]);
  698. fw_data_desc = qlcnic_get_data_desc(adapter, QLCNIC_UNI_DIR_SECT_FW,
  699. QLCNIC_UNI_FIRMWARE_IDX_OFF);
  700. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  701. cpu_to_le32(fw_data_desc->size) - 17;
  702. for (i = 0; i < 12; i++) {
  703. if (!strncmp(&ver_str[i], "REV=", 4)) {
  704. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  705. &major, &minor, &sub);
  706. if (ret != 3)
  707. return 0;
  708. else
  709. return major + (minor << 8) + (sub << 16);
  710. }
  711. }
  712. return 0;
  713. }
  714. static __le32
  715. qlcnic_get_bios_version(struct qlcnic_adapter *adapter)
  716. {
  717. const struct firmware *fw = adapter->fw;
  718. __le32 bios_ver, prd_off = adapter->file_prd_off;
  719. if (adapter->fw_type != QLCNIC_UNIFIED_ROMIMAGE)
  720. return cpu_to_le32(
  721. *(u32 *)&fw->data[QLCNIC_BIOS_VERSION_OFFSET]);
  722. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  723. + QLCNIC_UNI_BIOS_VERSION_OFF));
  724. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) + (bios_ver >> 24);
  725. }
  726. int
  727. qlcnic_need_fw_reset(struct qlcnic_adapter *adapter)
  728. {
  729. u32 count, old_count;
  730. u32 val, version, major, minor, build;
  731. int i, timeout;
  732. if (adapter->need_fw_reset)
  733. return 1;
  734. /* last attempt had failed */
  735. if (QLCRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  736. return 1;
  737. old_count = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  738. for (i = 0; i < 10; i++) {
  739. timeout = msleep_interruptible(200);
  740. if (timeout) {
  741. QLCWR32(adapter, CRB_CMDPEG_STATE,
  742. PHAN_INITIALIZE_FAILED);
  743. return -EINTR;
  744. }
  745. count = QLCRD32(adapter, QLCNIC_PEG_ALIVE_COUNTER);
  746. if (count != old_count)
  747. break;
  748. }
  749. /* firmware is dead */
  750. if (count == old_count)
  751. return 1;
  752. /* check if we have got newer or different file firmware */
  753. if (adapter->fw) {
  754. val = qlcnic_get_fw_version(adapter);
  755. version = QLCNIC_DECODE_VERSION(val);
  756. major = QLCRD32(adapter, QLCNIC_FW_VERSION_MAJOR);
  757. minor = QLCRD32(adapter, QLCNIC_FW_VERSION_MINOR);
  758. build = QLCRD32(adapter, QLCNIC_FW_VERSION_SUB);
  759. if (version > QLCNIC_VERSION_CODE(major, minor, build))
  760. return 1;
  761. }
  762. return 0;
  763. }
  764. static const char *fw_name[] = {
  765. QLCNIC_UNIFIED_ROMIMAGE_NAME,
  766. QLCNIC_FLASH_ROMIMAGE_NAME,
  767. };
  768. int
  769. qlcnic_load_firmware(struct qlcnic_adapter *adapter)
  770. {
  771. u64 *ptr64;
  772. u32 i, flashaddr, size;
  773. const struct firmware *fw = adapter->fw;
  774. struct pci_dev *pdev = adapter->pdev;
  775. dev_info(&pdev->dev, "loading firmware from %s\n",
  776. fw_name[adapter->fw_type]);
  777. if (fw) {
  778. __le64 data;
  779. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  780. ptr64 = (u64 *)qlcnic_get_bootld_offs(adapter);
  781. flashaddr = QLCNIC_BOOTLD_START;
  782. for (i = 0; i < size; i++) {
  783. data = cpu_to_le64(ptr64[i]);
  784. if (qlcnic_pci_mem_write_2M(adapter, flashaddr, data))
  785. return -EIO;
  786. flashaddr += 8;
  787. }
  788. size = (__force u32)qlcnic_get_fw_size(adapter) / 8;
  789. ptr64 = (u64 *)qlcnic_get_fw_offs(adapter);
  790. flashaddr = QLCNIC_IMAGE_START;
  791. for (i = 0; i < size; i++) {
  792. data = cpu_to_le64(ptr64[i]);
  793. if (qlcnic_pci_mem_write_2M(adapter,
  794. flashaddr, data))
  795. return -EIO;
  796. flashaddr += 8;
  797. }
  798. size = (__force u32)qlcnic_get_fw_size(adapter) % 8;
  799. if (size) {
  800. data = cpu_to_le64(ptr64[i]);
  801. if (qlcnic_pci_mem_write_2M(adapter,
  802. flashaddr, data))
  803. return -EIO;
  804. }
  805. } else {
  806. u64 data;
  807. u32 hi, lo;
  808. size = (QLCNIC_IMAGE_START - QLCNIC_BOOTLD_START) / 8;
  809. flashaddr = QLCNIC_BOOTLD_START;
  810. for (i = 0; i < size; i++) {
  811. if (qlcnic_rom_fast_read(adapter,
  812. flashaddr, (int *)&lo) != 0)
  813. return -EIO;
  814. if (qlcnic_rom_fast_read(adapter,
  815. flashaddr + 4, (int *)&hi) != 0)
  816. return -EIO;
  817. data = (((u64)hi << 32) | lo);
  818. if (qlcnic_pci_mem_write_2M(adapter,
  819. flashaddr, data))
  820. return -EIO;
  821. flashaddr += 8;
  822. }
  823. }
  824. msleep(1);
  825. QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
  826. QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
  827. return 0;
  828. }
  829. static int
  830. qlcnic_validate_firmware(struct qlcnic_adapter *adapter)
  831. {
  832. __le32 val;
  833. u32 ver, min_ver, bios, min_size;
  834. struct pci_dev *pdev = adapter->pdev;
  835. const struct firmware *fw = adapter->fw;
  836. u8 fw_type = adapter->fw_type;
  837. if (fw_type == QLCNIC_UNIFIED_ROMIMAGE) {
  838. if (qlcnic_validate_unified_romimage(adapter))
  839. return -EINVAL;
  840. min_size = QLCNIC_UNI_FW_MIN_SIZE;
  841. } else {
  842. val = cpu_to_le32(*(u32 *)&fw->data[QLCNIC_FW_MAGIC_OFFSET]);
  843. if ((__force u32)val != QLCNIC_BDINFO_MAGIC)
  844. return -EINVAL;
  845. min_size = QLCNIC_FW_MIN_SIZE;
  846. }
  847. if (fw->size < min_size)
  848. return -EINVAL;
  849. val = qlcnic_get_fw_version(adapter);
  850. min_ver = QLCNIC_VERSION_CODE(4, 0, 216);
  851. ver = QLCNIC_DECODE_VERSION(val);
  852. if ((_major(ver) > _QLCNIC_LINUX_MAJOR) || (ver < min_ver)) {
  853. dev_err(&pdev->dev,
  854. "%s: firmware version %d.%d.%d unsupported\n",
  855. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  856. return -EINVAL;
  857. }
  858. val = qlcnic_get_bios_version(adapter);
  859. qlcnic_rom_fast_read(adapter, QLCNIC_BIOS_VERSION_OFFSET, (int *)&bios);
  860. if ((__force u32)val != bios) {
  861. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  862. fw_name[fw_type]);
  863. return -EINVAL;
  864. }
  865. /* check if flashed firmware is newer */
  866. if (qlcnic_rom_fast_read(adapter,
  867. QLCNIC_FW_VERSION_OFFSET, (int *)&val))
  868. return -EIO;
  869. val = QLCNIC_DECODE_VERSION(val);
  870. if (val > ver) {
  871. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  872. fw_name[fw_type]);
  873. return -EINVAL;
  874. }
  875. QLCWR32(adapter, QLCNIC_CAM_RAM(0x1fc), QLCNIC_BDINFO_MAGIC);
  876. return 0;
  877. }
  878. static void
  879. qlcnic_get_next_fwtype(struct qlcnic_adapter *adapter)
  880. {
  881. u8 fw_type;
  882. switch (adapter->fw_type) {
  883. case QLCNIC_UNKNOWN_ROMIMAGE:
  884. fw_type = QLCNIC_UNIFIED_ROMIMAGE;
  885. break;
  886. case QLCNIC_UNIFIED_ROMIMAGE:
  887. default:
  888. fw_type = QLCNIC_FLASH_ROMIMAGE;
  889. break;
  890. }
  891. adapter->fw_type = fw_type;
  892. }
  893. void qlcnic_request_firmware(struct qlcnic_adapter *adapter)
  894. {
  895. struct pci_dev *pdev = adapter->pdev;
  896. int rc;
  897. adapter->fw_type = QLCNIC_UNKNOWN_ROMIMAGE;
  898. next:
  899. qlcnic_get_next_fwtype(adapter);
  900. if (adapter->fw_type == QLCNIC_FLASH_ROMIMAGE) {
  901. adapter->fw = NULL;
  902. } else {
  903. rc = request_firmware(&adapter->fw,
  904. fw_name[adapter->fw_type], &pdev->dev);
  905. if (rc != 0)
  906. goto next;
  907. rc = qlcnic_validate_firmware(adapter);
  908. if (rc != 0) {
  909. release_firmware(adapter->fw);
  910. msleep(1);
  911. goto next;
  912. }
  913. }
  914. }
  915. void
  916. qlcnic_release_firmware(struct qlcnic_adapter *adapter)
  917. {
  918. if (adapter->fw)
  919. release_firmware(adapter->fw);
  920. adapter->fw = NULL;
  921. }
  922. int qlcnic_phantom_init(struct qlcnic_adapter *adapter)
  923. {
  924. u32 val;
  925. int retries = 60;
  926. do {
  927. val = QLCRD32(adapter, CRB_CMDPEG_STATE);
  928. switch (val) {
  929. case PHAN_INITIALIZE_COMPLETE:
  930. case PHAN_INITIALIZE_ACK:
  931. return 0;
  932. case PHAN_INITIALIZE_FAILED:
  933. goto out_err;
  934. default:
  935. break;
  936. }
  937. msleep(500);
  938. } while (--retries);
  939. QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  940. out_err:
  941. dev_err(&adapter->pdev->dev, "firmware init failed\n");
  942. return -EIO;
  943. }
  944. static int
  945. qlcnic_receive_peg_ready(struct qlcnic_adapter *adapter)
  946. {
  947. u32 val;
  948. int retries = 2000;
  949. do {
  950. val = QLCRD32(adapter, CRB_RCVPEG_STATE);
  951. if (val == PHAN_PEG_RCV_INITIALIZED)
  952. return 0;
  953. msleep(10);
  954. } while (--retries);
  955. if (!retries) {
  956. dev_err(&adapter->pdev->dev, "Receive Peg initialization not "
  957. "complete, state: 0x%x.\n", val);
  958. return -EIO;
  959. }
  960. return 0;
  961. }
  962. int qlcnic_init_firmware(struct qlcnic_adapter *adapter)
  963. {
  964. int err;
  965. err = qlcnic_receive_peg_ready(adapter);
  966. if (err)
  967. return err;
  968. QLCWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  969. QLCWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  970. QLCWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  971. QLCWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  972. return err;
  973. }
  974. static void
  975. qlcnic_handle_linkevent(struct qlcnic_adapter *adapter,
  976. struct qlcnic_fw_msg *msg)
  977. {
  978. u32 cable_OUI;
  979. u16 cable_len;
  980. u16 link_speed;
  981. u8 link_status, module, duplex, autoneg;
  982. struct net_device *netdev = adapter->netdev;
  983. adapter->has_link_events = 1;
  984. cable_OUI = msg->body[1] & 0xffffffff;
  985. cable_len = (msg->body[1] >> 32) & 0xffff;
  986. link_speed = (msg->body[1] >> 48) & 0xffff;
  987. link_status = msg->body[2] & 0xff;
  988. duplex = (msg->body[2] >> 16) & 0xff;
  989. autoneg = (msg->body[2] >> 24) & 0xff;
  990. module = (msg->body[2] >> 8) & 0xff;
  991. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE)
  992. dev_info(&netdev->dev, "unsupported cable: OUI 0x%x, "
  993. "length %d\n", cable_OUI, cable_len);
  994. else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN)
  995. dev_info(&netdev->dev, "unsupported cable length %d\n",
  996. cable_len);
  997. qlcnic_advert_link_change(adapter, link_status);
  998. if (duplex == LINKEVENT_FULL_DUPLEX)
  999. adapter->link_duplex = DUPLEX_FULL;
  1000. else
  1001. adapter->link_duplex = DUPLEX_HALF;
  1002. adapter->module_type = module;
  1003. adapter->link_autoneg = autoneg;
  1004. adapter->link_speed = link_speed;
  1005. }
  1006. static void
  1007. qlcnic_handle_fw_message(int desc_cnt, int index,
  1008. struct qlcnic_host_sds_ring *sds_ring)
  1009. {
  1010. struct qlcnic_fw_msg msg;
  1011. struct status_desc *desc;
  1012. int i = 0, opcode;
  1013. while (desc_cnt > 0 && i < 8) {
  1014. desc = &sds_ring->desc_head[index];
  1015. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1016. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1017. index = get_next_index(index, sds_ring->num_desc);
  1018. desc_cnt--;
  1019. }
  1020. opcode = qlcnic_get_nic_msg_opcode(msg.body[0]);
  1021. switch (opcode) {
  1022. case QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1023. qlcnic_handle_linkevent(sds_ring->adapter, &msg);
  1024. break;
  1025. default:
  1026. break;
  1027. }
  1028. }
  1029. static int
  1030. qlcnic_alloc_rx_skb(struct qlcnic_adapter *adapter,
  1031. struct qlcnic_host_rds_ring *rds_ring,
  1032. struct qlcnic_rx_buffer *buffer)
  1033. {
  1034. struct sk_buff *skb;
  1035. dma_addr_t dma;
  1036. struct pci_dev *pdev = adapter->pdev;
  1037. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1038. if (!buffer->skb) {
  1039. adapter->stats.skb_alloc_failure++;
  1040. return -ENOMEM;
  1041. }
  1042. skb = buffer->skb;
  1043. if (!adapter->ahw.cut_through)
  1044. skb_reserve(skb, 2);
  1045. dma = pci_map_single(pdev, skb->data,
  1046. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1047. if (pci_dma_mapping_error(pdev, dma)) {
  1048. adapter->stats.rx_dma_map_error++;
  1049. dev_kfree_skb_any(skb);
  1050. buffer->skb = NULL;
  1051. return -ENOMEM;
  1052. }
  1053. buffer->skb = skb;
  1054. buffer->dma = dma;
  1055. buffer->state = QLCNIC_BUFFER_BUSY;
  1056. return 0;
  1057. }
  1058. static struct sk_buff *qlcnic_process_rxbuf(struct qlcnic_adapter *adapter,
  1059. struct qlcnic_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1060. {
  1061. struct qlcnic_rx_buffer *buffer;
  1062. struct sk_buff *skb;
  1063. buffer = &rds_ring->rx_buf_arr[index];
  1064. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1065. PCI_DMA_FROMDEVICE);
  1066. skb = buffer->skb;
  1067. if (!skb) {
  1068. adapter->stats.null_skb++;
  1069. goto no_skb;
  1070. }
  1071. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1072. adapter->stats.csummed++;
  1073. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1074. } else {
  1075. skb->ip_summed = CHECKSUM_NONE;
  1076. }
  1077. skb->dev = adapter->netdev;
  1078. buffer->skb = NULL;
  1079. no_skb:
  1080. buffer->state = QLCNIC_BUFFER_FREE;
  1081. return skb;
  1082. }
  1083. static struct qlcnic_rx_buffer *
  1084. qlcnic_process_rcv(struct qlcnic_adapter *adapter,
  1085. struct qlcnic_host_sds_ring *sds_ring,
  1086. int ring, u64 sts_data0)
  1087. {
  1088. struct net_device *netdev = adapter->netdev;
  1089. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1090. struct qlcnic_rx_buffer *buffer;
  1091. struct sk_buff *skb;
  1092. struct qlcnic_host_rds_ring *rds_ring;
  1093. int index, length, cksum, pkt_offset;
  1094. if (unlikely(ring >= adapter->max_rds_rings))
  1095. return NULL;
  1096. rds_ring = &recv_ctx->rds_rings[ring];
  1097. index = qlcnic_get_sts_refhandle(sts_data0);
  1098. if (unlikely(index >= rds_ring->num_desc))
  1099. return NULL;
  1100. buffer = &rds_ring->rx_buf_arr[index];
  1101. length = qlcnic_get_sts_totallength(sts_data0);
  1102. cksum = qlcnic_get_sts_status(sts_data0);
  1103. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1104. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1105. if (!skb)
  1106. return buffer;
  1107. if (length > rds_ring->skb_size)
  1108. skb_put(skb, rds_ring->skb_size);
  1109. else
  1110. skb_put(skb, length);
  1111. if (pkt_offset)
  1112. skb_pull(skb, pkt_offset);
  1113. skb->truesize = skb->len + sizeof(struct sk_buff);
  1114. skb->protocol = eth_type_trans(skb, netdev);
  1115. napi_gro_receive(&sds_ring->napi, skb);
  1116. adapter->stats.rx_pkts++;
  1117. adapter->stats.rxbytes += length;
  1118. return buffer;
  1119. }
  1120. #define QLC_TCP_HDR_SIZE 20
  1121. #define QLC_TCP_TS_OPTION_SIZE 12
  1122. #define QLC_TCP_TS_HDR_SIZE (QLC_TCP_HDR_SIZE + QLC_TCP_TS_OPTION_SIZE)
  1123. static struct qlcnic_rx_buffer *
  1124. qlcnic_process_lro(struct qlcnic_adapter *adapter,
  1125. struct qlcnic_host_sds_ring *sds_ring,
  1126. int ring, u64 sts_data0, u64 sts_data1)
  1127. {
  1128. struct net_device *netdev = adapter->netdev;
  1129. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1130. struct qlcnic_rx_buffer *buffer;
  1131. struct sk_buff *skb;
  1132. struct qlcnic_host_rds_ring *rds_ring;
  1133. struct iphdr *iph;
  1134. struct tcphdr *th;
  1135. bool push, timestamp;
  1136. int l2_hdr_offset, l4_hdr_offset;
  1137. int index;
  1138. u16 lro_length, length, data_offset;
  1139. u32 seq_number;
  1140. if (unlikely(ring > adapter->max_rds_rings))
  1141. return NULL;
  1142. rds_ring = &recv_ctx->rds_rings[ring];
  1143. index = qlcnic_get_lro_sts_refhandle(sts_data0);
  1144. if (unlikely(index > rds_ring->num_desc))
  1145. return NULL;
  1146. buffer = &rds_ring->rx_buf_arr[index];
  1147. timestamp = qlcnic_get_lro_sts_timestamp(sts_data0);
  1148. lro_length = qlcnic_get_lro_sts_length(sts_data0);
  1149. l2_hdr_offset = qlcnic_get_lro_sts_l2_hdr_offset(sts_data0);
  1150. l4_hdr_offset = qlcnic_get_lro_sts_l4_hdr_offset(sts_data0);
  1151. push = qlcnic_get_lro_sts_push_flag(sts_data0);
  1152. seq_number = qlcnic_get_lro_sts_seq_number(sts_data1);
  1153. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1154. if (!skb)
  1155. return buffer;
  1156. if (timestamp)
  1157. data_offset = l4_hdr_offset + QLC_TCP_TS_HDR_SIZE;
  1158. else
  1159. data_offset = l4_hdr_offset + QLC_TCP_HDR_SIZE;
  1160. skb_put(skb, lro_length + data_offset);
  1161. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1162. skb_pull(skb, l2_hdr_offset);
  1163. skb->protocol = eth_type_trans(skb, netdev);
  1164. iph = (struct iphdr *)skb->data;
  1165. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1166. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1167. iph->tot_len = htons(length);
  1168. iph->check = 0;
  1169. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1170. th->psh = push;
  1171. th->seq = htonl(seq_number);
  1172. length = skb->len;
  1173. netif_receive_skb(skb);
  1174. adapter->stats.lro_pkts++;
  1175. adapter->stats.lrobytes += length;
  1176. return buffer;
  1177. }
  1178. int
  1179. qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max)
  1180. {
  1181. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1182. struct list_head *cur;
  1183. struct status_desc *desc;
  1184. struct qlcnic_rx_buffer *rxbuf;
  1185. u64 sts_data0, sts_data1;
  1186. int count = 0;
  1187. int opcode, ring, desc_cnt;
  1188. u32 consumer = sds_ring->consumer;
  1189. while (count < max) {
  1190. desc = &sds_ring->desc_head[consumer];
  1191. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1192. if (!(sts_data0 & STATUS_OWNER_HOST))
  1193. break;
  1194. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1195. opcode = qlcnic_get_sts_opcode(sts_data0);
  1196. switch (opcode) {
  1197. case QLCNIC_RXPKT_DESC:
  1198. case QLCNIC_OLD_RXPKT_DESC:
  1199. case QLCNIC_SYN_OFFLOAD:
  1200. ring = qlcnic_get_sts_type(sts_data0);
  1201. rxbuf = qlcnic_process_rcv(adapter, sds_ring,
  1202. ring, sts_data0);
  1203. break;
  1204. case QLCNIC_LRO_DESC:
  1205. ring = qlcnic_get_lro_sts_type(sts_data0);
  1206. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1207. rxbuf = qlcnic_process_lro(adapter, sds_ring,
  1208. ring, sts_data0, sts_data1);
  1209. break;
  1210. case QLCNIC_RESPONSE_DESC:
  1211. qlcnic_handle_fw_message(desc_cnt, consumer, sds_ring);
  1212. default:
  1213. goto skip;
  1214. }
  1215. WARN_ON(desc_cnt > 1);
  1216. if (rxbuf)
  1217. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1218. else
  1219. adapter->stats.null_rxbuf++;
  1220. skip:
  1221. for (; desc_cnt > 0; desc_cnt--) {
  1222. desc = &sds_ring->desc_head[consumer];
  1223. desc->status_desc_data[0] =
  1224. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1225. consumer = get_next_index(consumer, sds_ring->num_desc);
  1226. }
  1227. count++;
  1228. }
  1229. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1230. struct qlcnic_host_rds_ring *rds_ring =
  1231. &adapter->recv_ctx.rds_rings[ring];
  1232. if (!list_empty(&sds_ring->free_list[ring])) {
  1233. list_for_each(cur, &sds_ring->free_list[ring]) {
  1234. rxbuf = list_entry(cur,
  1235. struct qlcnic_rx_buffer, list);
  1236. qlcnic_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1237. }
  1238. spin_lock(&rds_ring->lock);
  1239. list_splice_tail_init(&sds_ring->free_list[ring],
  1240. &rds_ring->free_list);
  1241. spin_unlock(&rds_ring->lock);
  1242. }
  1243. qlcnic_post_rx_buffers_nodb(adapter, rds_ring);
  1244. }
  1245. if (count) {
  1246. sds_ring->consumer = consumer;
  1247. writel(consumer, sds_ring->crb_sts_consumer);
  1248. }
  1249. return count;
  1250. }
  1251. void
  1252. qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid,
  1253. struct qlcnic_host_rds_ring *rds_ring)
  1254. {
  1255. struct rcv_desc *pdesc;
  1256. struct qlcnic_rx_buffer *buffer;
  1257. int producer, count = 0;
  1258. struct list_head *head;
  1259. spin_lock(&rds_ring->lock);
  1260. producer = rds_ring->producer;
  1261. head = &rds_ring->free_list;
  1262. while (!list_empty(head)) {
  1263. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1264. if (!buffer->skb) {
  1265. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1266. break;
  1267. }
  1268. count++;
  1269. list_del(&buffer->list);
  1270. /* make a rcv descriptor */
  1271. pdesc = &rds_ring->desc_head[producer];
  1272. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1273. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1274. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1275. producer = get_next_index(producer, rds_ring->num_desc);
  1276. }
  1277. if (count) {
  1278. rds_ring->producer = producer;
  1279. writel((producer-1) & (rds_ring->num_desc-1),
  1280. rds_ring->crb_rcv_producer);
  1281. }
  1282. spin_unlock(&rds_ring->lock);
  1283. }
  1284. static void
  1285. qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
  1286. struct qlcnic_host_rds_ring *rds_ring)
  1287. {
  1288. struct rcv_desc *pdesc;
  1289. struct qlcnic_rx_buffer *buffer;
  1290. int producer, count = 0;
  1291. struct list_head *head;
  1292. if (!spin_trylock(&rds_ring->lock))
  1293. return;
  1294. producer = rds_ring->producer;
  1295. head = &rds_ring->free_list;
  1296. while (!list_empty(head)) {
  1297. buffer = list_entry(head->next, struct qlcnic_rx_buffer, list);
  1298. if (!buffer->skb) {
  1299. if (qlcnic_alloc_rx_skb(adapter, rds_ring, buffer))
  1300. break;
  1301. }
  1302. count++;
  1303. list_del(&buffer->list);
  1304. /* make a rcv descriptor */
  1305. pdesc = &rds_ring->desc_head[producer];
  1306. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1307. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1308. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1309. producer = get_next_index(producer, rds_ring->num_desc);
  1310. }
  1311. if (count) {
  1312. rds_ring->producer = producer;
  1313. writel((producer - 1) & (rds_ring->num_desc - 1),
  1314. rds_ring->crb_rcv_producer);
  1315. }
  1316. spin_unlock(&rds_ring->lock);
  1317. }
  1318. static struct qlcnic_rx_buffer *
  1319. qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
  1320. struct qlcnic_host_sds_ring *sds_ring,
  1321. int ring, u64 sts_data0)
  1322. {
  1323. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  1324. struct qlcnic_rx_buffer *buffer;
  1325. struct sk_buff *skb;
  1326. struct qlcnic_host_rds_ring *rds_ring;
  1327. int index, length, cksum, pkt_offset;
  1328. if (unlikely(ring >= adapter->max_rds_rings))
  1329. return NULL;
  1330. rds_ring = &recv_ctx->rds_rings[ring];
  1331. index = qlcnic_get_sts_refhandle(sts_data0);
  1332. if (unlikely(index >= rds_ring->num_desc))
  1333. return NULL;
  1334. buffer = &rds_ring->rx_buf_arr[index];
  1335. length = qlcnic_get_sts_totallength(sts_data0);
  1336. cksum = qlcnic_get_sts_status(sts_data0);
  1337. pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
  1338. skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
  1339. if (!skb)
  1340. return buffer;
  1341. skb_put(skb, rds_ring->skb_size);
  1342. if (pkt_offset)
  1343. skb_pull(skb, pkt_offset);
  1344. skb->truesize = skb->len + sizeof(struct sk_buff);
  1345. if (!qlcnic_check_loopback_buff(skb->data))
  1346. adapter->diag_cnt++;
  1347. dev_kfree_skb_any(skb);
  1348. adapter->stats.rx_pkts++;
  1349. adapter->stats.rxbytes += length;
  1350. return buffer;
  1351. }
  1352. void
  1353. qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
  1354. {
  1355. struct qlcnic_adapter *adapter = sds_ring->adapter;
  1356. struct status_desc *desc;
  1357. struct qlcnic_rx_buffer *rxbuf;
  1358. u64 sts_data0;
  1359. int opcode, ring, desc_cnt;
  1360. u32 consumer = sds_ring->consumer;
  1361. desc = &sds_ring->desc_head[consumer];
  1362. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1363. if (!(sts_data0 & STATUS_OWNER_HOST))
  1364. return;
  1365. desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
  1366. opcode = qlcnic_get_sts_opcode(sts_data0);
  1367. ring = qlcnic_get_sts_type(sts_data0);
  1368. rxbuf = qlcnic_process_rcv_diag(adapter, sds_ring,
  1369. ring, sts_data0);
  1370. desc->status_desc_data[0] = cpu_to_le64(STATUS_OWNER_PHANTOM);
  1371. consumer = get_next_index(consumer, sds_ring->num_desc);
  1372. sds_ring->consumer = consumer;
  1373. writel(consumer, sds_ring->crb_sts_consumer);
  1374. }