bfin_can.c 17 KB

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  1. /*
  2. * Blackfin On-Chip CAN Driver
  3. *
  4. * Copyright 2004-2009 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/kernel.h>
  13. #include <linux/bitops.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/errno.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/skbuff.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/can/dev.h>
  20. #include <linux/can/error.h>
  21. #include <asm/bfin_can.h>
  22. #include <asm/portmux.h>
  23. #define DRV_NAME "bfin_can"
  24. #define BFIN_CAN_TIMEOUT 100
  25. #define TX_ECHO_SKB_MAX 1
  26. /*
  27. * bfin can private data
  28. */
  29. struct bfin_can_priv {
  30. struct can_priv can; /* must be the first member */
  31. struct net_device *dev;
  32. void __iomem *membase;
  33. int rx_irq;
  34. int tx_irq;
  35. int err_irq;
  36. unsigned short *pin_list;
  37. };
  38. /*
  39. * bfin can timing parameters
  40. */
  41. static struct can_bittiming_const bfin_can_bittiming_const = {
  42. .name = DRV_NAME,
  43. .tseg1_min = 1,
  44. .tseg1_max = 16,
  45. .tseg2_min = 1,
  46. .tseg2_max = 8,
  47. .sjw_max = 4,
  48. /*
  49. * Although the BRP field can be set to any value, it is recommended
  50. * that the value be greater than or equal to 4, as restrictions
  51. * apply to the bit timing configuration when BRP is less than 4.
  52. */
  53. .brp_min = 4,
  54. .brp_max = 1024,
  55. .brp_inc = 1,
  56. };
  57. static int bfin_can_set_bittiming(struct net_device *dev)
  58. {
  59. struct bfin_can_priv *priv = netdev_priv(dev);
  60. struct bfin_can_regs __iomem *reg = priv->membase;
  61. struct can_bittiming *bt = &priv->can.bittiming;
  62. u16 clk, timing;
  63. clk = bt->brp - 1;
  64. timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
  65. ((bt->phase_seg2 - 1) << 4);
  66. /*
  67. * If the SAM bit is set, the input signal is oversampled three times
  68. * at the SCLK rate.
  69. */
  70. if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  71. timing |= SAM;
  72. bfin_write16(&reg->clock, clk);
  73. bfin_write16(&reg->timing, timing);
  74. dev_info(dev->dev.parent, "setting CLOCK=0x%04x TIMING=0x%04x\n",
  75. clk, timing);
  76. return 0;
  77. }
  78. static void bfin_can_set_reset_mode(struct net_device *dev)
  79. {
  80. struct bfin_can_priv *priv = netdev_priv(dev);
  81. struct bfin_can_regs __iomem *reg = priv->membase;
  82. int timeout = BFIN_CAN_TIMEOUT;
  83. int i;
  84. /* disable interrupts */
  85. bfin_write16(&reg->mbim1, 0);
  86. bfin_write16(&reg->mbim2, 0);
  87. bfin_write16(&reg->gim, 0);
  88. /* reset can and enter configuration mode */
  89. bfin_write16(&reg->control, SRS | CCR);
  90. SSYNC();
  91. bfin_write16(&reg->control, CCR);
  92. SSYNC();
  93. while (!(bfin_read16(&reg->control) & CCA)) {
  94. udelay(10);
  95. if (--timeout == 0) {
  96. dev_err(dev->dev.parent,
  97. "fail to enter configuration mode\n");
  98. BUG();
  99. }
  100. }
  101. /*
  102. * All mailbox configurations are marked as inactive
  103. * by writing to CAN Mailbox Configuration Registers 1 and 2
  104. * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
  105. */
  106. bfin_write16(&reg->mc1, 0);
  107. bfin_write16(&reg->mc2, 0);
  108. /* Set Mailbox Direction */
  109. bfin_write16(&reg->md1, 0xFFFF); /* mailbox 1-16 are RX */
  110. bfin_write16(&reg->md2, 0); /* mailbox 17-32 are TX */
  111. /* RECEIVE_STD_CHL */
  112. for (i = 0; i < 2; i++) {
  113. bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id0, 0);
  114. bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].id1, AME);
  115. bfin_write16(&reg->chl[RECEIVE_STD_CHL + i].dlc, 0);
  116. bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF);
  117. bfin_write16(&reg->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF);
  118. }
  119. /* RECEIVE_EXT_CHL */
  120. for (i = 0; i < 2; i++) {
  121. bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id0, 0);
  122. bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE);
  123. bfin_write16(&reg->chl[RECEIVE_EXT_CHL + i].dlc, 0);
  124. bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF);
  125. bfin_write16(&reg->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF);
  126. }
  127. bfin_write16(&reg->mc2, BIT(TRANSMIT_CHL - 16));
  128. bfin_write16(&reg->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
  129. SSYNC();
  130. priv->can.state = CAN_STATE_STOPPED;
  131. }
  132. static void bfin_can_set_normal_mode(struct net_device *dev)
  133. {
  134. struct bfin_can_priv *priv = netdev_priv(dev);
  135. struct bfin_can_regs __iomem *reg = priv->membase;
  136. int timeout = BFIN_CAN_TIMEOUT;
  137. /*
  138. * leave configuration mode
  139. */
  140. bfin_write16(&reg->control, bfin_read16(&reg->control) & ~CCR);
  141. while (bfin_read16(&reg->status) & CCA) {
  142. udelay(10);
  143. if (--timeout == 0) {
  144. dev_err(dev->dev.parent,
  145. "fail to leave configuration mode\n");
  146. BUG();
  147. }
  148. }
  149. /*
  150. * clear _All_ tx and rx interrupts
  151. */
  152. bfin_write16(&reg->mbtif1, 0xFFFF);
  153. bfin_write16(&reg->mbtif2, 0xFFFF);
  154. bfin_write16(&reg->mbrif1, 0xFFFF);
  155. bfin_write16(&reg->mbrif2, 0xFFFF);
  156. /*
  157. * clear global interrupt status register
  158. */
  159. bfin_write16(&reg->gis, 0x7FF); /* overwrites with '1' */
  160. /*
  161. * Initialize Interrupts
  162. * - set bits in the mailbox interrupt mask register
  163. * - global interrupt mask
  164. */
  165. bfin_write16(&reg->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
  166. bfin_write16(&reg->mbim2, BIT(TRANSMIT_CHL - 16));
  167. bfin_write16(&reg->gim, EPIM | BOIM | RMLIM);
  168. SSYNC();
  169. }
  170. static void bfin_can_start(struct net_device *dev)
  171. {
  172. struct bfin_can_priv *priv = netdev_priv(dev);
  173. /* enter reset mode */
  174. if (priv->can.state != CAN_STATE_STOPPED)
  175. bfin_can_set_reset_mode(dev);
  176. /* leave reset mode */
  177. bfin_can_set_normal_mode(dev);
  178. }
  179. static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
  180. {
  181. switch (mode) {
  182. case CAN_MODE_START:
  183. bfin_can_start(dev);
  184. if (netif_queue_stopped(dev))
  185. netif_wake_queue(dev);
  186. break;
  187. default:
  188. return -EOPNOTSUPP;
  189. }
  190. return 0;
  191. }
  192. static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
  193. {
  194. struct bfin_can_priv *priv = netdev_priv(dev);
  195. struct bfin_can_regs __iomem *reg = priv->membase;
  196. struct can_frame *cf = (struct can_frame *)skb->data;
  197. u8 dlc = cf->can_dlc;
  198. canid_t id = cf->can_id;
  199. u8 *data = cf->data;
  200. u16 val;
  201. int i;
  202. if (can_dropped_invalid_skb(dev, skb))
  203. return NETDEV_TX_OK;
  204. netif_stop_queue(dev);
  205. /* fill id */
  206. if (id & CAN_EFF_FLAG) {
  207. bfin_write16(&reg->chl[TRANSMIT_CHL].id0, id);
  208. if (id & CAN_RTR_FLAG)
  209. writew(((id & 0x1FFF0000) >> 16) | IDE | AME | RTR,
  210. &reg->chl[TRANSMIT_CHL].id1);
  211. else
  212. writew(((id & 0x1FFF0000) >> 16) | IDE | AME,
  213. &reg->chl[TRANSMIT_CHL].id1);
  214. } else {
  215. if (id & CAN_RTR_FLAG)
  216. writew((id << 2) | AME | RTR,
  217. &reg->chl[TRANSMIT_CHL].id1);
  218. else
  219. bfin_write16(&reg->chl[TRANSMIT_CHL].id1,
  220. (id << 2) | AME);
  221. }
  222. /* fill payload */
  223. for (i = 0; i < 8; i += 2) {
  224. val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
  225. ((6 - i) < dlc ? (data[6 - i] << 8) : 0);
  226. bfin_write16(&reg->chl[TRANSMIT_CHL].data[i], val);
  227. }
  228. /* fill data length code */
  229. bfin_write16(&reg->chl[TRANSMIT_CHL].dlc, dlc);
  230. dev->trans_start = jiffies;
  231. can_put_echo_skb(skb, dev, 0);
  232. /* set transmit request */
  233. bfin_write16(&reg->trs2, BIT(TRANSMIT_CHL - 16));
  234. return 0;
  235. }
  236. static void bfin_can_rx(struct net_device *dev, u16 isrc)
  237. {
  238. struct bfin_can_priv *priv = netdev_priv(dev);
  239. struct net_device_stats *stats = &dev->stats;
  240. struct bfin_can_regs __iomem *reg = priv->membase;
  241. struct can_frame *cf;
  242. struct sk_buff *skb;
  243. int obj;
  244. int i;
  245. u16 val;
  246. skb = alloc_can_skb(dev, &cf);
  247. if (skb == NULL)
  248. return;
  249. /* get id */
  250. if (isrc & BIT(RECEIVE_EXT_CHL)) {
  251. /* extended frame format (EFF) */
  252. cf->can_id = ((bfin_read16(&reg->chl[RECEIVE_EXT_CHL].id1)
  253. & 0x1FFF) << 16)
  254. + bfin_read16(&reg->chl[RECEIVE_EXT_CHL].id0);
  255. cf->can_id |= CAN_EFF_FLAG;
  256. obj = RECEIVE_EXT_CHL;
  257. } else {
  258. /* standard frame format (SFF) */
  259. cf->can_id = (bfin_read16(&reg->chl[RECEIVE_STD_CHL].id1)
  260. & 0x1ffc) >> 2;
  261. obj = RECEIVE_STD_CHL;
  262. }
  263. if (bfin_read16(&reg->chl[obj].id1) & RTR)
  264. cf->can_id |= CAN_RTR_FLAG;
  265. /* get data length code */
  266. cf->can_dlc = get_can_dlc(bfin_read16(&reg->chl[obj].dlc) & 0xF);
  267. /* get payload */
  268. for (i = 0; i < 8; i += 2) {
  269. val = bfin_read16(&reg->chl[obj].data[i]);
  270. cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
  271. cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
  272. }
  273. netif_rx(skb);
  274. stats->rx_packets++;
  275. stats->rx_bytes += cf->can_dlc;
  276. }
  277. static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
  278. {
  279. struct bfin_can_priv *priv = netdev_priv(dev);
  280. struct bfin_can_regs __iomem *reg = priv->membase;
  281. struct net_device_stats *stats = &dev->stats;
  282. struct can_frame *cf;
  283. struct sk_buff *skb;
  284. enum can_state state = priv->can.state;
  285. skb = alloc_can_err_skb(dev, &cf);
  286. if (skb == NULL)
  287. return -ENOMEM;
  288. if (isrc & RMLIS) {
  289. /* data overrun interrupt */
  290. dev_dbg(dev->dev.parent, "data overrun interrupt\n");
  291. cf->can_id |= CAN_ERR_CRTL;
  292. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  293. stats->rx_over_errors++;
  294. stats->rx_errors++;
  295. }
  296. if (isrc & BOIS) {
  297. dev_dbg(dev->dev.parent, "bus-off mode interrupt\n");
  298. state = CAN_STATE_BUS_OFF;
  299. cf->can_id |= CAN_ERR_BUSOFF;
  300. can_bus_off(dev);
  301. }
  302. if (isrc & EPIS) {
  303. /* error passive interrupt */
  304. dev_dbg(dev->dev.parent, "error passive interrupt\n");
  305. state = CAN_STATE_ERROR_PASSIVE;
  306. }
  307. if ((isrc & EWTIS) || (isrc & EWRIS)) {
  308. dev_dbg(dev->dev.parent,
  309. "Error Warning Transmit/Receive Interrupt\n");
  310. state = CAN_STATE_ERROR_WARNING;
  311. }
  312. if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
  313. state == CAN_STATE_ERROR_PASSIVE)) {
  314. u16 cec = bfin_read16(&reg->cec);
  315. u8 rxerr = cec;
  316. u8 txerr = cec >> 8;
  317. cf->can_id |= CAN_ERR_CRTL;
  318. if (state == CAN_STATE_ERROR_WARNING) {
  319. priv->can.can_stats.error_warning++;
  320. cf->data[1] = (txerr > rxerr) ?
  321. CAN_ERR_CRTL_TX_WARNING :
  322. CAN_ERR_CRTL_RX_WARNING;
  323. } else {
  324. priv->can.can_stats.error_passive++;
  325. cf->data[1] = (txerr > rxerr) ?
  326. CAN_ERR_CRTL_TX_PASSIVE :
  327. CAN_ERR_CRTL_RX_PASSIVE;
  328. }
  329. }
  330. if (status) {
  331. priv->can.can_stats.bus_error++;
  332. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  333. if (status & BEF)
  334. cf->data[2] |= CAN_ERR_PROT_BIT;
  335. else if (status & FER)
  336. cf->data[2] |= CAN_ERR_PROT_FORM;
  337. else if (status & SER)
  338. cf->data[2] |= CAN_ERR_PROT_STUFF;
  339. else
  340. cf->data[2] |= CAN_ERR_PROT_UNSPEC;
  341. }
  342. priv->can.state = state;
  343. netif_rx(skb);
  344. stats->rx_packets++;
  345. stats->rx_bytes += cf->can_dlc;
  346. return 0;
  347. }
  348. irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
  349. {
  350. struct net_device *dev = dev_id;
  351. struct bfin_can_priv *priv = netdev_priv(dev);
  352. struct bfin_can_regs __iomem *reg = priv->membase;
  353. struct net_device_stats *stats = &dev->stats;
  354. u16 status, isrc;
  355. if ((irq == priv->tx_irq) && bfin_read16(&reg->mbtif2)) {
  356. /* transmission complete interrupt */
  357. bfin_write16(&reg->mbtif2, 0xFFFF);
  358. stats->tx_packets++;
  359. stats->tx_bytes += bfin_read16(&reg->chl[TRANSMIT_CHL].dlc);
  360. can_get_echo_skb(dev, 0);
  361. netif_wake_queue(dev);
  362. } else if ((irq == priv->rx_irq) && bfin_read16(&reg->mbrif1)) {
  363. /* receive interrupt */
  364. isrc = bfin_read16(&reg->mbrif1);
  365. bfin_write16(&reg->mbrif1, 0xFFFF);
  366. bfin_can_rx(dev, isrc);
  367. } else if ((irq == priv->err_irq) && bfin_read16(&reg->gis)) {
  368. /* error interrupt */
  369. isrc = bfin_read16(&reg->gis);
  370. status = bfin_read16(&reg->esr);
  371. bfin_write16(&reg->gis, 0x7FF);
  372. bfin_can_err(dev, isrc, status);
  373. } else {
  374. return IRQ_NONE;
  375. }
  376. return IRQ_HANDLED;
  377. }
  378. static int bfin_can_open(struct net_device *dev)
  379. {
  380. struct bfin_can_priv *priv = netdev_priv(dev);
  381. int err;
  382. /* set chip into reset mode */
  383. bfin_can_set_reset_mode(dev);
  384. /* common open */
  385. err = open_candev(dev);
  386. if (err)
  387. goto exit_open;
  388. /* register interrupt handler */
  389. err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
  390. "bfin-can-rx", dev);
  391. if (err)
  392. goto exit_rx_irq;
  393. err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
  394. "bfin-can-tx", dev);
  395. if (err)
  396. goto exit_tx_irq;
  397. err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
  398. "bfin-can-err", dev);
  399. if (err)
  400. goto exit_err_irq;
  401. bfin_can_start(dev);
  402. netif_start_queue(dev);
  403. return 0;
  404. exit_err_irq:
  405. free_irq(priv->tx_irq, dev);
  406. exit_tx_irq:
  407. free_irq(priv->rx_irq, dev);
  408. exit_rx_irq:
  409. close_candev(dev);
  410. exit_open:
  411. return err;
  412. }
  413. static int bfin_can_close(struct net_device *dev)
  414. {
  415. struct bfin_can_priv *priv = netdev_priv(dev);
  416. netif_stop_queue(dev);
  417. bfin_can_set_reset_mode(dev);
  418. close_candev(dev);
  419. free_irq(priv->rx_irq, dev);
  420. free_irq(priv->tx_irq, dev);
  421. free_irq(priv->err_irq, dev);
  422. return 0;
  423. }
  424. struct net_device *alloc_bfin_candev(void)
  425. {
  426. struct net_device *dev;
  427. struct bfin_can_priv *priv;
  428. dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
  429. if (!dev)
  430. return NULL;
  431. priv = netdev_priv(dev);
  432. priv->dev = dev;
  433. priv->can.bittiming_const = &bfin_can_bittiming_const;
  434. priv->can.do_set_bittiming = bfin_can_set_bittiming;
  435. priv->can.do_set_mode = bfin_can_set_mode;
  436. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
  437. return dev;
  438. }
  439. static const struct net_device_ops bfin_can_netdev_ops = {
  440. .ndo_open = bfin_can_open,
  441. .ndo_stop = bfin_can_close,
  442. .ndo_start_xmit = bfin_can_start_xmit,
  443. };
  444. static int __devinit bfin_can_probe(struct platform_device *pdev)
  445. {
  446. int err;
  447. struct net_device *dev;
  448. struct bfin_can_priv *priv;
  449. struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
  450. unsigned short *pdata;
  451. pdata = pdev->dev.platform_data;
  452. if (!pdata) {
  453. dev_err(&pdev->dev, "No platform data provided!\n");
  454. err = -EINVAL;
  455. goto exit;
  456. }
  457. res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  458. rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  459. tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  460. err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
  461. if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
  462. err = -EINVAL;
  463. goto exit;
  464. }
  465. if (!request_mem_region(res_mem->start, resource_size(res_mem),
  466. dev_name(&pdev->dev))) {
  467. err = -EBUSY;
  468. goto exit;
  469. }
  470. /* request peripheral pins */
  471. err = peripheral_request_list(pdata, dev_name(&pdev->dev));
  472. if (err)
  473. goto exit_mem_release;
  474. dev = alloc_bfin_candev();
  475. if (!dev) {
  476. err = -ENOMEM;
  477. goto exit_peri_pin_free;
  478. }
  479. priv = netdev_priv(dev);
  480. priv->membase = (void __iomem *)res_mem->start;
  481. priv->rx_irq = rx_irq->start;
  482. priv->tx_irq = tx_irq->start;
  483. priv->err_irq = err_irq->start;
  484. priv->pin_list = pdata;
  485. priv->can.clock.freq = get_sclk();
  486. dev_set_drvdata(&pdev->dev, dev);
  487. SET_NETDEV_DEV(dev, &pdev->dev);
  488. dev->flags |= IFF_ECHO; /* we support local echo */
  489. dev->netdev_ops = &bfin_can_netdev_ops;
  490. bfin_can_set_reset_mode(dev);
  491. err = register_candev(dev);
  492. if (err) {
  493. dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
  494. goto exit_candev_free;
  495. }
  496. dev_info(&pdev->dev,
  497. "%s device registered"
  498. "(&reg_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
  499. DRV_NAME, (void *)priv->membase, priv->rx_irq,
  500. priv->tx_irq, priv->err_irq, priv->can.clock.freq);
  501. return 0;
  502. exit_candev_free:
  503. free_candev(dev);
  504. exit_peri_pin_free:
  505. peripheral_free_list(pdata);
  506. exit_mem_release:
  507. release_mem_region(res_mem->start, resource_size(res_mem));
  508. exit:
  509. return err;
  510. }
  511. static int __devexit bfin_can_remove(struct platform_device *pdev)
  512. {
  513. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  514. struct bfin_can_priv *priv = netdev_priv(dev);
  515. struct resource *res;
  516. bfin_can_set_reset_mode(dev);
  517. unregister_candev(dev);
  518. dev_set_drvdata(&pdev->dev, NULL);
  519. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  520. release_mem_region(res->start, resource_size(res));
  521. peripheral_free_list(priv->pin_list);
  522. free_candev(dev);
  523. return 0;
  524. }
  525. #ifdef CONFIG_PM
  526. static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
  527. {
  528. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  529. struct bfin_can_priv *priv = netdev_priv(dev);
  530. struct bfin_can_regs __iomem *reg = priv->membase;
  531. int timeout = BFIN_CAN_TIMEOUT;
  532. if (netif_running(dev)) {
  533. /* enter sleep mode */
  534. bfin_write16(&reg->control, bfin_read16(&reg->control) | SMR);
  535. SSYNC();
  536. while (!(bfin_read16(&reg->intr) & SMACK)) {
  537. udelay(10);
  538. if (--timeout == 0) {
  539. dev_err(dev->dev.parent,
  540. "fail to enter sleep mode\n");
  541. BUG();
  542. }
  543. }
  544. }
  545. return 0;
  546. }
  547. static int bfin_can_resume(struct platform_device *pdev)
  548. {
  549. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  550. struct bfin_can_priv *priv = netdev_priv(dev);
  551. struct bfin_can_regs __iomem *reg = priv->membase;
  552. if (netif_running(dev)) {
  553. /* leave sleep mode */
  554. bfin_write16(&reg->intr, 0);
  555. SSYNC();
  556. }
  557. return 0;
  558. }
  559. #else
  560. #define bfin_can_suspend NULL
  561. #define bfin_can_resume NULL
  562. #endif /* CONFIG_PM */
  563. static struct platform_driver bfin_can_driver = {
  564. .probe = bfin_can_probe,
  565. .remove = __devexit_p(bfin_can_remove),
  566. .suspend = bfin_can_suspend,
  567. .resume = bfin_can_resume,
  568. .driver = {
  569. .name = DRV_NAME,
  570. .owner = THIS_MODULE,
  571. },
  572. };
  573. static int __init bfin_can_init(void)
  574. {
  575. return platform_driver_register(&bfin_can_driver);
  576. }
  577. module_init(bfin_can_init);
  578. static void __exit bfin_can_exit(void)
  579. {
  580. platform_driver_unregister(&bfin_can_driver);
  581. }
  582. module_exit(bfin_can_exit);
  583. MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
  584. MODULE_LICENSE("GPL");
  585. MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");