w90p910_ether.c 26 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Nuvoton technology corporation.
  3. *
  4. * Wan ZongShun <mcuos.com@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation;version 2 of the License.
  9. *
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/mii.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/skbuff.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/clk.h>
  20. #include <linux/gfp.h>
  21. #define DRV_MODULE_NAME "w90p910-emc"
  22. #define DRV_MODULE_VERSION "0.1"
  23. /* Ethernet MAC Registers */
  24. #define REG_CAMCMR 0x00
  25. #define REG_CAMEN 0x04
  26. #define REG_CAMM_BASE 0x08
  27. #define REG_CAML_BASE 0x0c
  28. #define REG_TXDLSA 0x88
  29. #define REG_RXDLSA 0x8C
  30. #define REG_MCMDR 0x90
  31. #define REG_MIID 0x94
  32. #define REG_MIIDA 0x98
  33. #define REG_FFTCR 0x9C
  34. #define REG_TSDR 0xa0
  35. #define REG_RSDR 0xa4
  36. #define REG_DMARFC 0xa8
  37. #define REG_MIEN 0xac
  38. #define REG_MISTA 0xb0
  39. #define REG_CTXDSA 0xcc
  40. #define REG_CTXBSA 0xd0
  41. #define REG_CRXDSA 0xd4
  42. #define REG_CRXBSA 0xd8
  43. /* mac controller bit */
  44. #define MCMDR_RXON 0x01
  45. #define MCMDR_ACP (0x01 << 3)
  46. #define MCMDR_SPCRC (0x01 << 5)
  47. #define MCMDR_TXON (0x01 << 8)
  48. #define MCMDR_FDUP (0x01 << 18)
  49. #define MCMDR_ENMDC (0x01 << 19)
  50. #define MCMDR_OPMOD (0x01 << 20)
  51. #define SWR (0x01 << 24)
  52. /* cam command regiser */
  53. #define CAMCMR_AUP 0x01
  54. #define CAMCMR_AMP (0x01 << 1)
  55. #define CAMCMR_ABP (0x01 << 2)
  56. #define CAMCMR_CCAM (0x01 << 3)
  57. #define CAMCMR_ECMP (0x01 << 4)
  58. #define CAM0EN 0x01
  59. /* mac mii controller bit */
  60. #define MDCCR (0x0a << 20)
  61. #define PHYAD (0x01 << 8)
  62. #define PHYWR (0x01 << 16)
  63. #define PHYBUSY (0x01 << 17)
  64. #define PHYPRESP (0x01 << 18)
  65. #define CAM_ENTRY_SIZE 0x08
  66. /* rx and tx status */
  67. #define TXDS_TXCP (0x01 << 19)
  68. #define RXDS_CRCE (0x01 << 17)
  69. #define RXDS_PTLE (0x01 << 19)
  70. #define RXDS_RXGD (0x01 << 20)
  71. #define RXDS_ALIE (0x01 << 21)
  72. #define RXDS_RP (0x01 << 22)
  73. /* mac interrupt status*/
  74. #define MISTA_EXDEF (0x01 << 19)
  75. #define MISTA_TXBERR (0x01 << 24)
  76. #define MISTA_TDU (0x01 << 23)
  77. #define MISTA_RDU (0x01 << 10)
  78. #define MISTA_RXBERR (0x01 << 11)
  79. #define ENSTART 0x01
  80. #define ENRXINTR 0x01
  81. #define ENRXGD (0x01 << 4)
  82. #define ENRXBERR (0x01 << 11)
  83. #define ENTXINTR (0x01 << 16)
  84. #define ENTXCP (0x01 << 18)
  85. #define ENTXABT (0x01 << 21)
  86. #define ENTXBERR (0x01 << 24)
  87. #define ENMDC (0x01 << 19)
  88. #define PHYBUSY (0x01 << 17)
  89. #define MDCCR_VAL 0xa00000
  90. /* rx and tx owner bit */
  91. #define RX_OWEN_DMA (0x01 << 31)
  92. #define RX_OWEN_CPU (~(0x03 << 30))
  93. #define TX_OWEN_DMA (0x01 << 31)
  94. #define TX_OWEN_CPU (~(0x01 << 31))
  95. /* tx frame desc controller bit */
  96. #define MACTXINTEN 0x04
  97. #define CRCMODE 0x02
  98. #define PADDINGMODE 0x01
  99. /* fftcr controller bit */
  100. #define TXTHD (0x03 << 8)
  101. #define BLENGTH (0x01 << 20)
  102. /* global setting for driver */
  103. #define RX_DESC_SIZE 50
  104. #define TX_DESC_SIZE 10
  105. #define MAX_RBUFF_SZ 0x600
  106. #define MAX_TBUFF_SZ 0x600
  107. #define TX_TIMEOUT 50
  108. #define DELAY 1000
  109. #define CAM0 0x0
  110. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg);
  111. struct w90p910_rxbd {
  112. unsigned int sl;
  113. unsigned int buffer;
  114. unsigned int reserved;
  115. unsigned int next;
  116. };
  117. struct w90p910_txbd {
  118. unsigned int mode;
  119. unsigned int buffer;
  120. unsigned int sl;
  121. unsigned int next;
  122. };
  123. struct recv_pdesc {
  124. struct w90p910_rxbd desclist[RX_DESC_SIZE];
  125. char recv_buf[RX_DESC_SIZE][MAX_RBUFF_SZ];
  126. };
  127. struct tran_pdesc {
  128. struct w90p910_txbd desclist[TX_DESC_SIZE];
  129. char tran_buf[TX_DESC_SIZE][MAX_TBUFF_SZ];
  130. };
  131. struct w90p910_ether {
  132. struct recv_pdesc *rdesc;
  133. struct tran_pdesc *tdesc;
  134. dma_addr_t rdesc_phys;
  135. dma_addr_t tdesc_phys;
  136. struct net_device_stats stats;
  137. struct platform_device *pdev;
  138. struct resource *res;
  139. struct sk_buff *skb;
  140. struct clk *clk;
  141. struct clk *rmiiclk;
  142. struct mii_if_info mii;
  143. struct timer_list check_timer;
  144. void __iomem *reg;
  145. int rxirq;
  146. int txirq;
  147. unsigned int cur_tx;
  148. unsigned int cur_rx;
  149. unsigned int finish_tx;
  150. unsigned int rx_packets;
  151. unsigned int rx_bytes;
  152. unsigned int start_tx_ptr;
  153. unsigned int start_rx_ptr;
  154. unsigned int linkflag;
  155. };
  156. static void update_linkspeed_register(struct net_device *dev,
  157. unsigned int speed, unsigned int duplex)
  158. {
  159. struct w90p910_ether *ether = netdev_priv(dev);
  160. unsigned int val;
  161. val = __raw_readl(ether->reg + REG_MCMDR);
  162. if (speed == SPEED_100) {
  163. /* 100 full/half duplex */
  164. if (duplex == DUPLEX_FULL) {
  165. val |= (MCMDR_OPMOD | MCMDR_FDUP);
  166. } else {
  167. val |= MCMDR_OPMOD;
  168. val &= ~MCMDR_FDUP;
  169. }
  170. } else {
  171. /* 10 full/half duplex */
  172. if (duplex == DUPLEX_FULL) {
  173. val |= MCMDR_FDUP;
  174. val &= ~MCMDR_OPMOD;
  175. } else {
  176. val &= ~(MCMDR_FDUP | MCMDR_OPMOD);
  177. }
  178. }
  179. __raw_writel(val, ether->reg + REG_MCMDR);
  180. }
  181. static void update_linkspeed(struct net_device *dev)
  182. {
  183. struct w90p910_ether *ether = netdev_priv(dev);
  184. struct platform_device *pdev;
  185. unsigned int bmsr, bmcr, lpa, speed, duplex;
  186. pdev = ether->pdev;
  187. if (!mii_link_ok(&ether->mii)) {
  188. ether->linkflag = 0x0;
  189. netif_carrier_off(dev);
  190. dev_warn(&pdev->dev, "%s: Link down.\n", dev->name);
  191. return;
  192. }
  193. if (ether->linkflag == 1)
  194. return;
  195. bmsr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMSR);
  196. bmcr = w90p910_mdio_read(dev, ether->mii.phy_id, MII_BMCR);
  197. if (bmcr & BMCR_ANENABLE) {
  198. if (!(bmsr & BMSR_ANEGCOMPLETE))
  199. return;
  200. lpa = w90p910_mdio_read(dev, ether->mii.phy_id, MII_LPA);
  201. if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
  202. speed = SPEED_100;
  203. else
  204. speed = SPEED_10;
  205. if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
  206. duplex = DUPLEX_FULL;
  207. else
  208. duplex = DUPLEX_HALF;
  209. } else {
  210. speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
  211. duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  212. }
  213. update_linkspeed_register(dev, speed, duplex);
  214. dev_info(&pdev->dev, "%s: Link now %i-%s\n", dev->name, speed,
  215. (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
  216. ether->linkflag = 0x01;
  217. netif_carrier_on(dev);
  218. }
  219. static void w90p910_check_link(unsigned long dev_id)
  220. {
  221. struct net_device *dev = (struct net_device *) dev_id;
  222. struct w90p910_ether *ether = netdev_priv(dev);
  223. update_linkspeed(dev);
  224. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  225. }
  226. static void w90p910_write_cam(struct net_device *dev,
  227. unsigned int x, unsigned char *pval)
  228. {
  229. struct w90p910_ether *ether = netdev_priv(dev);
  230. unsigned int msw, lsw;
  231. msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
  232. lsw = (pval[4] << 24) | (pval[5] << 16);
  233. __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE);
  234. __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE);
  235. }
  236. static int w90p910_init_desc(struct net_device *dev)
  237. {
  238. struct w90p910_ether *ether;
  239. struct w90p910_txbd *tdesc;
  240. struct w90p910_rxbd *rdesc;
  241. struct platform_device *pdev;
  242. unsigned int i;
  243. ether = netdev_priv(dev);
  244. pdev = ether->pdev;
  245. ether->tdesc = (struct tran_pdesc *)
  246. dma_alloc_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  247. &ether->tdesc_phys, GFP_KERNEL);
  248. if (!ether->tdesc) {
  249. dev_err(&pdev->dev, "Failed to allocate memory for tx desc\n");
  250. return -ENOMEM;
  251. }
  252. ether->rdesc = (struct recv_pdesc *)
  253. dma_alloc_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  254. &ether->rdesc_phys, GFP_KERNEL);
  255. if (!ether->rdesc) {
  256. dev_err(&pdev->dev, "Failed to allocate memory for rx desc\n");
  257. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  258. ether->tdesc, ether->tdesc_phys);
  259. return -ENOMEM;
  260. }
  261. for (i = 0; i < TX_DESC_SIZE; i++) {
  262. unsigned int offset;
  263. tdesc = &(ether->tdesc->desclist[i]);
  264. if (i == TX_DESC_SIZE - 1)
  265. offset = offsetof(struct tran_pdesc, desclist[0]);
  266. else
  267. offset = offsetof(struct tran_pdesc, desclist[i + 1]);
  268. tdesc->next = ether->tdesc_phys + offset;
  269. tdesc->buffer = ether->tdesc_phys +
  270. offsetof(struct tran_pdesc, tran_buf[i]);
  271. tdesc->sl = 0;
  272. tdesc->mode = 0;
  273. }
  274. ether->start_tx_ptr = ether->tdesc_phys;
  275. for (i = 0; i < RX_DESC_SIZE; i++) {
  276. unsigned int offset;
  277. rdesc = &(ether->rdesc->desclist[i]);
  278. if (i == RX_DESC_SIZE - 1)
  279. offset = offsetof(struct recv_pdesc, desclist[0]);
  280. else
  281. offset = offsetof(struct recv_pdesc, desclist[i + 1]);
  282. rdesc->next = ether->rdesc_phys + offset;
  283. rdesc->sl = RX_OWEN_DMA;
  284. rdesc->buffer = ether->rdesc_phys +
  285. offsetof(struct recv_pdesc, recv_buf[i]);
  286. }
  287. ether->start_rx_ptr = ether->rdesc_phys;
  288. return 0;
  289. }
  290. static void w90p910_set_fifo_threshold(struct net_device *dev)
  291. {
  292. struct w90p910_ether *ether = netdev_priv(dev);
  293. unsigned int val;
  294. val = TXTHD | BLENGTH;
  295. __raw_writel(val, ether->reg + REG_FFTCR);
  296. }
  297. static void w90p910_return_default_idle(struct net_device *dev)
  298. {
  299. struct w90p910_ether *ether = netdev_priv(dev);
  300. unsigned int val;
  301. val = __raw_readl(ether->reg + REG_MCMDR);
  302. val |= SWR;
  303. __raw_writel(val, ether->reg + REG_MCMDR);
  304. }
  305. static void w90p910_trigger_rx(struct net_device *dev)
  306. {
  307. struct w90p910_ether *ether = netdev_priv(dev);
  308. __raw_writel(ENSTART, ether->reg + REG_RSDR);
  309. }
  310. static void w90p910_trigger_tx(struct net_device *dev)
  311. {
  312. struct w90p910_ether *ether = netdev_priv(dev);
  313. __raw_writel(ENSTART, ether->reg + REG_TSDR);
  314. }
  315. static void w90p910_enable_mac_interrupt(struct net_device *dev)
  316. {
  317. struct w90p910_ether *ether = netdev_priv(dev);
  318. unsigned int val;
  319. val = ENTXINTR | ENRXINTR | ENRXGD | ENTXCP;
  320. val |= ENTXBERR | ENRXBERR | ENTXABT;
  321. __raw_writel(val, ether->reg + REG_MIEN);
  322. }
  323. static void w90p910_get_and_clear_int(struct net_device *dev,
  324. unsigned int *val)
  325. {
  326. struct w90p910_ether *ether = netdev_priv(dev);
  327. *val = __raw_readl(ether->reg + REG_MISTA);
  328. __raw_writel(*val, ether->reg + REG_MISTA);
  329. }
  330. static void w90p910_set_global_maccmd(struct net_device *dev)
  331. {
  332. struct w90p910_ether *ether = netdev_priv(dev);
  333. unsigned int val;
  334. val = __raw_readl(ether->reg + REG_MCMDR);
  335. val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | ENMDC;
  336. __raw_writel(val, ether->reg + REG_MCMDR);
  337. }
  338. static void w90p910_enable_cam(struct net_device *dev)
  339. {
  340. struct w90p910_ether *ether = netdev_priv(dev);
  341. unsigned int val;
  342. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  343. val = __raw_readl(ether->reg + REG_CAMEN);
  344. val |= CAM0EN;
  345. __raw_writel(val, ether->reg + REG_CAMEN);
  346. }
  347. static void w90p910_enable_cam_command(struct net_device *dev)
  348. {
  349. struct w90p910_ether *ether = netdev_priv(dev);
  350. unsigned int val;
  351. val = CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AMP;
  352. __raw_writel(val, ether->reg + REG_CAMCMR);
  353. }
  354. static void w90p910_enable_tx(struct net_device *dev, unsigned int enable)
  355. {
  356. struct w90p910_ether *ether = netdev_priv(dev);
  357. unsigned int val;
  358. val = __raw_readl(ether->reg + REG_MCMDR);
  359. if (enable)
  360. val |= MCMDR_TXON;
  361. else
  362. val &= ~MCMDR_TXON;
  363. __raw_writel(val, ether->reg + REG_MCMDR);
  364. }
  365. static void w90p910_enable_rx(struct net_device *dev, unsigned int enable)
  366. {
  367. struct w90p910_ether *ether = netdev_priv(dev);
  368. unsigned int val;
  369. val = __raw_readl(ether->reg + REG_MCMDR);
  370. if (enable)
  371. val |= MCMDR_RXON;
  372. else
  373. val &= ~MCMDR_RXON;
  374. __raw_writel(val, ether->reg + REG_MCMDR);
  375. }
  376. static void w90p910_set_curdest(struct net_device *dev)
  377. {
  378. struct w90p910_ether *ether = netdev_priv(dev);
  379. __raw_writel(ether->start_rx_ptr, ether->reg + REG_RXDLSA);
  380. __raw_writel(ether->start_tx_ptr, ether->reg + REG_TXDLSA);
  381. }
  382. static void w90p910_reset_mac(struct net_device *dev)
  383. {
  384. struct w90p910_ether *ether = netdev_priv(dev);
  385. w90p910_enable_tx(dev, 0);
  386. w90p910_enable_rx(dev, 0);
  387. w90p910_set_fifo_threshold(dev);
  388. w90p910_return_default_idle(dev);
  389. if (!netif_queue_stopped(dev))
  390. netif_stop_queue(dev);
  391. w90p910_init_desc(dev);
  392. dev->trans_start = jiffies;
  393. ether->cur_tx = 0x0;
  394. ether->finish_tx = 0x0;
  395. ether->cur_rx = 0x0;
  396. w90p910_set_curdest(dev);
  397. w90p910_enable_cam(dev);
  398. w90p910_enable_cam_command(dev);
  399. w90p910_enable_mac_interrupt(dev);
  400. w90p910_enable_tx(dev, 1);
  401. w90p910_enable_rx(dev, 1);
  402. w90p910_trigger_tx(dev);
  403. w90p910_trigger_rx(dev);
  404. dev->trans_start = jiffies;
  405. if (netif_queue_stopped(dev))
  406. netif_wake_queue(dev);
  407. }
  408. static void w90p910_mdio_write(struct net_device *dev,
  409. int phy_id, int reg, int data)
  410. {
  411. struct w90p910_ether *ether = netdev_priv(dev);
  412. struct platform_device *pdev;
  413. unsigned int val, i;
  414. pdev = ether->pdev;
  415. __raw_writel(data, ether->reg + REG_MIID);
  416. val = (phy_id << 0x08) | reg;
  417. val |= PHYBUSY | PHYWR | MDCCR_VAL;
  418. __raw_writel(val, ether->reg + REG_MIIDA);
  419. for (i = 0; i < DELAY; i++) {
  420. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  421. break;
  422. }
  423. if (i == DELAY)
  424. dev_warn(&pdev->dev, "mdio write timed out\n");
  425. }
  426. static int w90p910_mdio_read(struct net_device *dev, int phy_id, int reg)
  427. {
  428. struct w90p910_ether *ether = netdev_priv(dev);
  429. struct platform_device *pdev;
  430. unsigned int val, i, data;
  431. pdev = ether->pdev;
  432. val = (phy_id << 0x08) | reg;
  433. val |= PHYBUSY | MDCCR_VAL;
  434. __raw_writel(val, ether->reg + REG_MIIDA);
  435. for (i = 0; i < DELAY; i++) {
  436. if ((__raw_readl(ether->reg + REG_MIIDA) & PHYBUSY) == 0)
  437. break;
  438. }
  439. if (i == DELAY) {
  440. dev_warn(&pdev->dev, "mdio read timed out\n");
  441. data = 0xffff;
  442. } else {
  443. data = __raw_readl(ether->reg + REG_MIID);
  444. }
  445. return data;
  446. }
  447. static int w90p910_set_mac_address(struct net_device *dev, void *addr)
  448. {
  449. struct sockaddr *address = addr;
  450. if (!is_valid_ether_addr(address->sa_data))
  451. return -EADDRNOTAVAIL;
  452. memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
  453. w90p910_write_cam(dev, CAM0, dev->dev_addr);
  454. return 0;
  455. }
  456. static int w90p910_ether_close(struct net_device *dev)
  457. {
  458. struct w90p910_ether *ether = netdev_priv(dev);
  459. struct platform_device *pdev;
  460. pdev = ether->pdev;
  461. dma_free_coherent(&pdev->dev, sizeof(struct recv_pdesc),
  462. ether->rdesc, ether->rdesc_phys);
  463. dma_free_coherent(&pdev->dev, sizeof(struct tran_pdesc),
  464. ether->tdesc, ether->tdesc_phys);
  465. netif_stop_queue(dev);
  466. del_timer_sync(&ether->check_timer);
  467. clk_disable(ether->rmiiclk);
  468. clk_disable(ether->clk);
  469. free_irq(ether->txirq, dev);
  470. free_irq(ether->rxirq, dev);
  471. return 0;
  472. }
  473. static struct net_device_stats *w90p910_ether_stats(struct net_device *dev)
  474. {
  475. struct w90p910_ether *ether;
  476. ether = netdev_priv(dev);
  477. return &ether->stats;
  478. }
  479. static int w90p910_send_frame(struct net_device *dev,
  480. unsigned char *data, int length)
  481. {
  482. struct w90p910_ether *ether;
  483. struct w90p910_txbd *txbd;
  484. struct platform_device *pdev;
  485. unsigned char *buffer;
  486. ether = netdev_priv(dev);
  487. pdev = ether->pdev;
  488. txbd = &ether->tdesc->desclist[ether->cur_tx];
  489. buffer = ether->tdesc->tran_buf[ether->cur_tx];
  490. if (length > 1514) {
  491. dev_err(&pdev->dev, "send data %d bytes, check it\n", length);
  492. length = 1514;
  493. }
  494. txbd->sl = length & 0xFFFF;
  495. memcpy(buffer, data, length);
  496. txbd->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN;
  497. w90p910_enable_tx(dev, 1);
  498. w90p910_trigger_tx(dev);
  499. if (++ether->cur_tx >= TX_DESC_SIZE)
  500. ether->cur_tx = 0;
  501. txbd = &ether->tdesc->desclist[ether->cur_tx];
  502. dev->trans_start = jiffies;
  503. if (txbd->mode & TX_OWEN_DMA)
  504. netif_stop_queue(dev);
  505. return 0;
  506. }
  507. static int w90p910_ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
  508. {
  509. struct w90p910_ether *ether = netdev_priv(dev);
  510. if (!(w90p910_send_frame(dev, skb->data, skb->len))) {
  511. ether->skb = skb;
  512. dev_kfree_skb_irq(skb);
  513. return 0;
  514. }
  515. return -EAGAIN;
  516. }
  517. static irqreturn_t w90p910_tx_interrupt(int irq, void *dev_id)
  518. {
  519. struct w90p910_ether *ether;
  520. struct w90p910_txbd *txbd;
  521. struct platform_device *pdev;
  522. struct net_device *dev;
  523. unsigned int cur_entry, entry, status;
  524. dev = dev_id;
  525. ether = netdev_priv(dev);
  526. pdev = ether->pdev;
  527. w90p910_get_and_clear_int(dev, &status);
  528. cur_entry = __raw_readl(ether->reg + REG_CTXDSA);
  529. entry = ether->tdesc_phys +
  530. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  531. while (entry != cur_entry) {
  532. txbd = &ether->tdesc->desclist[ether->finish_tx];
  533. if (++ether->finish_tx >= TX_DESC_SIZE)
  534. ether->finish_tx = 0;
  535. if (txbd->sl & TXDS_TXCP) {
  536. ether->stats.tx_packets++;
  537. ether->stats.tx_bytes += txbd->sl & 0xFFFF;
  538. } else {
  539. ether->stats.tx_errors++;
  540. }
  541. txbd->sl = 0x0;
  542. txbd->mode = 0x0;
  543. if (netif_queue_stopped(dev))
  544. netif_wake_queue(dev);
  545. entry = ether->tdesc_phys +
  546. offsetof(struct tran_pdesc, desclist[ether->finish_tx]);
  547. }
  548. if (status & MISTA_EXDEF) {
  549. dev_err(&pdev->dev, "emc defer exceed interrupt\n");
  550. } else if (status & MISTA_TXBERR) {
  551. dev_err(&pdev->dev, "emc bus error interrupt\n");
  552. w90p910_reset_mac(dev);
  553. } else if (status & MISTA_TDU) {
  554. if (netif_queue_stopped(dev))
  555. netif_wake_queue(dev);
  556. }
  557. return IRQ_HANDLED;
  558. }
  559. static void netdev_rx(struct net_device *dev)
  560. {
  561. struct w90p910_ether *ether;
  562. struct w90p910_rxbd *rxbd;
  563. struct platform_device *pdev;
  564. struct sk_buff *skb;
  565. unsigned char *data;
  566. unsigned int length, status, val, entry;
  567. ether = netdev_priv(dev);
  568. pdev = ether->pdev;
  569. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  570. do {
  571. val = __raw_readl(ether->reg + REG_CRXDSA);
  572. entry = ether->rdesc_phys +
  573. offsetof(struct recv_pdesc, desclist[ether->cur_rx]);
  574. if (val == entry)
  575. break;
  576. status = rxbd->sl;
  577. length = status & 0xFFFF;
  578. if (status & RXDS_RXGD) {
  579. data = ether->rdesc->recv_buf[ether->cur_rx];
  580. skb = dev_alloc_skb(length+2);
  581. if (!skb) {
  582. dev_err(&pdev->dev, "get skb buffer error\n");
  583. ether->stats.rx_dropped++;
  584. return;
  585. }
  586. skb_reserve(skb, 2);
  587. skb_put(skb, length);
  588. skb_copy_to_linear_data(skb, data, length);
  589. skb->protocol = eth_type_trans(skb, dev);
  590. ether->stats.rx_packets++;
  591. ether->stats.rx_bytes += length;
  592. netif_rx(skb);
  593. } else {
  594. ether->stats.rx_errors++;
  595. if (status & RXDS_RP) {
  596. dev_err(&pdev->dev, "rx runt err\n");
  597. ether->stats.rx_length_errors++;
  598. } else if (status & RXDS_CRCE) {
  599. dev_err(&pdev->dev, "rx crc err\n");
  600. ether->stats.rx_crc_errors++;
  601. } else if (status & RXDS_ALIE) {
  602. dev_err(&pdev->dev, "rx aligment err\n");
  603. ether->stats.rx_frame_errors++;
  604. } else if (status & RXDS_PTLE) {
  605. dev_err(&pdev->dev, "rx longer err\n");
  606. ether->stats.rx_over_errors++;
  607. }
  608. }
  609. rxbd->sl = RX_OWEN_DMA;
  610. rxbd->reserved = 0x0;
  611. if (++ether->cur_rx >= RX_DESC_SIZE)
  612. ether->cur_rx = 0;
  613. rxbd = &ether->rdesc->desclist[ether->cur_rx];
  614. } while (1);
  615. }
  616. static irqreturn_t w90p910_rx_interrupt(int irq, void *dev_id)
  617. {
  618. struct net_device *dev;
  619. struct w90p910_ether *ether;
  620. struct platform_device *pdev;
  621. unsigned int status;
  622. dev = dev_id;
  623. ether = netdev_priv(dev);
  624. pdev = ether->pdev;
  625. w90p910_get_and_clear_int(dev, &status);
  626. if (status & MISTA_RDU) {
  627. netdev_rx(dev);
  628. w90p910_trigger_rx(dev);
  629. return IRQ_HANDLED;
  630. } else if (status & MISTA_RXBERR) {
  631. dev_err(&pdev->dev, "emc rx bus error\n");
  632. w90p910_reset_mac(dev);
  633. }
  634. netdev_rx(dev);
  635. return IRQ_HANDLED;
  636. }
  637. static int w90p910_ether_open(struct net_device *dev)
  638. {
  639. struct w90p910_ether *ether;
  640. struct platform_device *pdev;
  641. ether = netdev_priv(dev);
  642. pdev = ether->pdev;
  643. w90p910_reset_mac(dev);
  644. w90p910_set_fifo_threshold(dev);
  645. w90p910_set_curdest(dev);
  646. w90p910_enable_cam(dev);
  647. w90p910_enable_cam_command(dev);
  648. w90p910_enable_mac_interrupt(dev);
  649. w90p910_set_global_maccmd(dev);
  650. w90p910_enable_rx(dev, 1);
  651. ether->rx_packets = 0x0;
  652. ether->rx_bytes = 0x0;
  653. if (request_irq(ether->txirq, w90p910_tx_interrupt,
  654. 0x0, pdev->name, dev)) {
  655. dev_err(&pdev->dev, "register irq tx failed\n");
  656. return -EAGAIN;
  657. }
  658. if (request_irq(ether->rxirq, w90p910_rx_interrupt,
  659. 0x0, pdev->name, dev)) {
  660. dev_err(&pdev->dev, "register irq rx failed\n");
  661. free_irq(ether->txirq, dev);
  662. return -EAGAIN;
  663. }
  664. mod_timer(&ether->check_timer, jiffies + msecs_to_jiffies(1000));
  665. netif_start_queue(dev);
  666. w90p910_trigger_rx(dev);
  667. dev_info(&pdev->dev, "%s is OPENED\n", dev->name);
  668. return 0;
  669. }
  670. static void w90p910_ether_set_multicast_list(struct net_device *dev)
  671. {
  672. struct w90p910_ether *ether;
  673. unsigned int rx_mode;
  674. ether = netdev_priv(dev);
  675. if (dev->flags & IFF_PROMISC)
  676. rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  677. else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev))
  678. rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP;
  679. else
  680. rx_mode = CAMCMR_ECMP | CAMCMR_ABP;
  681. __raw_writel(rx_mode, ether->reg + REG_CAMCMR);
  682. }
  683. static int w90p910_ether_ioctl(struct net_device *dev,
  684. struct ifreq *ifr, int cmd)
  685. {
  686. struct w90p910_ether *ether = netdev_priv(dev);
  687. struct mii_ioctl_data *data = if_mii(ifr);
  688. return generic_mii_ioctl(&ether->mii, data, cmd, NULL);
  689. }
  690. static void w90p910_get_drvinfo(struct net_device *dev,
  691. struct ethtool_drvinfo *info)
  692. {
  693. strcpy(info->driver, DRV_MODULE_NAME);
  694. strcpy(info->version, DRV_MODULE_VERSION);
  695. }
  696. static int w90p910_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  697. {
  698. struct w90p910_ether *ether = netdev_priv(dev);
  699. return mii_ethtool_gset(&ether->mii, cmd);
  700. }
  701. static int w90p910_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  702. {
  703. struct w90p910_ether *ether = netdev_priv(dev);
  704. return mii_ethtool_sset(&ether->mii, cmd);
  705. }
  706. static int w90p910_nway_reset(struct net_device *dev)
  707. {
  708. struct w90p910_ether *ether = netdev_priv(dev);
  709. return mii_nway_restart(&ether->mii);
  710. }
  711. static u32 w90p910_get_link(struct net_device *dev)
  712. {
  713. struct w90p910_ether *ether = netdev_priv(dev);
  714. return mii_link_ok(&ether->mii);
  715. }
  716. static const struct ethtool_ops w90p910_ether_ethtool_ops = {
  717. .get_settings = w90p910_get_settings,
  718. .set_settings = w90p910_set_settings,
  719. .get_drvinfo = w90p910_get_drvinfo,
  720. .nway_reset = w90p910_nway_reset,
  721. .get_link = w90p910_get_link,
  722. };
  723. static const struct net_device_ops w90p910_ether_netdev_ops = {
  724. .ndo_open = w90p910_ether_open,
  725. .ndo_stop = w90p910_ether_close,
  726. .ndo_start_xmit = w90p910_ether_start_xmit,
  727. .ndo_get_stats = w90p910_ether_stats,
  728. .ndo_set_multicast_list = w90p910_ether_set_multicast_list,
  729. .ndo_set_mac_address = w90p910_set_mac_address,
  730. .ndo_do_ioctl = w90p910_ether_ioctl,
  731. .ndo_validate_addr = eth_validate_addr,
  732. .ndo_change_mtu = eth_change_mtu,
  733. };
  734. static void __init get_mac_address(struct net_device *dev)
  735. {
  736. struct w90p910_ether *ether = netdev_priv(dev);
  737. struct platform_device *pdev;
  738. char addr[6];
  739. pdev = ether->pdev;
  740. addr[0] = 0x00;
  741. addr[1] = 0x02;
  742. addr[2] = 0xac;
  743. addr[3] = 0x55;
  744. addr[4] = 0x88;
  745. addr[5] = 0xa8;
  746. if (is_valid_ether_addr(addr))
  747. memcpy(dev->dev_addr, &addr, 0x06);
  748. else
  749. dev_err(&pdev->dev, "invalid mac address\n");
  750. }
  751. static int w90p910_ether_setup(struct net_device *dev)
  752. {
  753. struct w90p910_ether *ether = netdev_priv(dev);
  754. ether_setup(dev);
  755. dev->netdev_ops = &w90p910_ether_netdev_ops;
  756. dev->ethtool_ops = &w90p910_ether_ethtool_ops;
  757. dev->tx_queue_len = 16;
  758. dev->dma = 0x0;
  759. dev->watchdog_timeo = TX_TIMEOUT;
  760. get_mac_address(dev);
  761. ether->cur_tx = 0x0;
  762. ether->cur_rx = 0x0;
  763. ether->finish_tx = 0x0;
  764. ether->linkflag = 0x0;
  765. ether->mii.phy_id = 0x01;
  766. ether->mii.phy_id_mask = 0x1f;
  767. ether->mii.reg_num_mask = 0x1f;
  768. ether->mii.dev = dev;
  769. ether->mii.mdio_read = w90p910_mdio_read;
  770. ether->mii.mdio_write = w90p910_mdio_write;
  771. setup_timer(&ether->check_timer, w90p910_check_link,
  772. (unsigned long)dev);
  773. return 0;
  774. }
  775. static int __devinit w90p910_ether_probe(struct platform_device *pdev)
  776. {
  777. struct w90p910_ether *ether;
  778. struct net_device *dev;
  779. int error;
  780. dev = alloc_etherdev(sizeof(struct w90p910_ether));
  781. if (!dev)
  782. return -ENOMEM;
  783. ether = netdev_priv(dev);
  784. ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  785. if (ether->res == NULL) {
  786. dev_err(&pdev->dev, "failed to get I/O memory\n");
  787. error = -ENXIO;
  788. goto failed_free;
  789. }
  790. if (!request_mem_region(ether->res->start,
  791. resource_size(ether->res), pdev->name)) {
  792. dev_err(&pdev->dev, "failed to request I/O memory\n");
  793. error = -EBUSY;
  794. goto failed_free;
  795. }
  796. ether->reg = ioremap(ether->res->start, resource_size(ether->res));
  797. if (ether->reg == NULL) {
  798. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  799. error = -ENXIO;
  800. goto failed_free_mem;
  801. }
  802. ether->txirq = platform_get_irq(pdev, 0);
  803. if (ether->txirq < 0) {
  804. dev_err(&pdev->dev, "failed to get ether tx irq\n");
  805. error = -ENXIO;
  806. goto failed_free_io;
  807. }
  808. ether->rxirq = platform_get_irq(pdev, 1);
  809. if (ether->rxirq < 0) {
  810. dev_err(&pdev->dev, "failed to get ether rx irq\n");
  811. error = -ENXIO;
  812. goto failed_free_txirq;
  813. }
  814. platform_set_drvdata(pdev, dev);
  815. ether->clk = clk_get(&pdev->dev, NULL);
  816. if (IS_ERR(ether->clk)) {
  817. dev_err(&pdev->dev, "failed to get ether clock\n");
  818. error = PTR_ERR(ether->clk);
  819. goto failed_free_rxirq;
  820. }
  821. ether->rmiiclk = clk_get(&pdev->dev, "RMII");
  822. if (IS_ERR(ether->rmiiclk)) {
  823. dev_err(&pdev->dev, "failed to get ether clock\n");
  824. error = PTR_ERR(ether->rmiiclk);
  825. goto failed_put_clk;
  826. }
  827. ether->pdev = pdev;
  828. w90p910_ether_setup(dev);
  829. error = register_netdev(dev);
  830. if (error != 0) {
  831. dev_err(&pdev->dev, "Regiter EMC w90p910 FAILED\n");
  832. error = -ENODEV;
  833. goto failed_put_rmiiclk;
  834. }
  835. return 0;
  836. failed_put_rmiiclk:
  837. clk_put(ether->rmiiclk);
  838. failed_put_clk:
  839. clk_put(ether->clk);
  840. failed_free_rxirq:
  841. free_irq(ether->rxirq, pdev);
  842. platform_set_drvdata(pdev, NULL);
  843. failed_free_txirq:
  844. free_irq(ether->txirq, pdev);
  845. failed_free_io:
  846. iounmap(ether->reg);
  847. failed_free_mem:
  848. release_mem_region(ether->res->start, resource_size(ether->res));
  849. failed_free:
  850. free_netdev(dev);
  851. return error;
  852. }
  853. static int __devexit w90p910_ether_remove(struct platform_device *pdev)
  854. {
  855. struct net_device *dev = platform_get_drvdata(pdev);
  856. struct w90p910_ether *ether = netdev_priv(dev);
  857. unregister_netdev(dev);
  858. clk_put(ether->rmiiclk);
  859. clk_put(ether->clk);
  860. iounmap(ether->reg);
  861. release_mem_region(ether->res->start, resource_size(ether->res));
  862. free_irq(ether->txirq, dev);
  863. free_irq(ether->rxirq, dev);
  864. del_timer_sync(&ether->check_timer);
  865. platform_set_drvdata(pdev, NULL);
  866. free_netdev(dev);
  867. return 0;
  868. }
  869. static struct platform_driver w90p910_ether_driver = {
  870. .probe = w90p910_ether_probe,
  871. .remove = __devexit_p(w90p910_ether_remove),
  872. .driver = {
  873. .name = "nuc900-emc",
  874. .owner = THIS_MODULE,
  875. },
  876. };
  877. static int __init w90p910_ether_init(void)
  878. {
  879. return platform_driver_register(&w90p910_ether_driver);
  880. }
  881. static void __exit w90p910_ether_exit(void)
  882. {
  883. platform_driver_unregister(&w90p910_ether_driver);
  884. }
  885. module_init(w90p910_ether_init);
  886. module_exit(w90p910_ether_exit);
  887. MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
  888. MODULE_DESCRIPTION("w90p910 MAC driver!");
  889. MODULE_LICENSE("GPL");
  890. MODULE_ALIAS("platform:nuc900-emc");