nes_utils.c 31 KB

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  1. /*
  2. * Copyright (c) 2006 - 2009 Intel Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/mii.h>
  39. #include <linux/if_vlan.h>
  40. #include <linux/slab.h>
  41. #include <linux/crc32.h>
  42. #include <linux/in.h>
  43. #include <linux/ip.h>
  44. #include <linux/tcp.h>
  45. #include <linux/init.h>
  46. #include <asm/io.h>
  47. #include <asm/irq.h>
  48. #include <asm/byteorder.h>
  49. #include "nes.h"
  50. static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
  51. u32 mh_detected;
  52. u32 mh_pauses_sent;
  53. /**
  54. * nes_read_eeprom_values -
  55. */
  56. int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
  57. {
  58. u32 mac_addr_low;
  59. u16 mac_addr_high;
  60. u16 eeprom_data;
  61. u16 eeprom_offset;
  62. u16 next_section_address;
  63. u16 sw_section_ver;
  64. u8 major_ver = 0;
  65. u8 minor_ver = 0;
  66. /* TODO: deal with EEPROM endian issues */
  67. if (nesadapter->firmware_eeprom_offset == 0) {
  68. /* Read the EEPROM Parameters */
  69. eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
  70. nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
  71. eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
  72. ((eeprom_data & 0x0080) >> 7));
  73. nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
  74. nesadapter->firmware_eeprom_offset = eeprom_offset;
  75. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
  76. if (eeprom_data != 0x5746) {
  77. nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
  78. return -1;
  79. }
  80. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  81. nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
  82. eeprom_offset + 2, eeprom_data);
  83. eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
  84. nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
  85. nesadapter->software_eeprom_offset = eeprom_offset;
  86. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
  87. if (eeprom_data != 0x5753) {
  88. printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
  89. return -1;
  90. }
  91. sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
  92. nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
  93. sw_section_ver);
  94. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  95. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  96. eeprom_offset + 2, eeprom_data);
  97. next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
  98. ((eeprom_data & 0x0100) >> 8));
  99. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  100. if (eeprom_data != 0x414d) {
  101. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
  102. eeprom_data);
  103. goto no_fw_rev;
  104. }
  105. eeprom_offset = next_section_address;
  106. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  107. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  108. eeprom_offset + 2, eeprom_data);
  109. next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
  110. ((eeprom_data & 0x0100) >> 8));
  111. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  112. if (eeprom_data != 0x4f52) {
  113. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
  114. eeprom_data);
  115. goto no_fw_rev;
  116. }
  117. eeprom_offset = next_section_address;
  118. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  119. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  120. eeprom_offset + 2, eeprom_data);
  121. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  122. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  123. if (eeprom_data != 0x5746) {
  124. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
  125. eeprom_data);
  126. goto no_fw_rev;
  127. }
  128. eeprom_offset = next_section_address;
  129. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  130. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  131. eeprom_offset + 2, eeprom_data);
  132. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  133. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  134. if (eeprom_data != 0x5753) {
  135. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
  136. eeprom_data);
  137. goto no_fw_rev;
  138. }
  139. eeprom_offset = next_section_address;
  140. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  141. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  142. eeprom_offset + 2, eeprom_data);
  143. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  144. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  145. if (eeprom_data != 0x414d) {
  146. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
  147. eeprom_data);
  148. goto no_fw_rev;
  149. }
  150. eeprom_offset = next_section_address;
  151. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
  152. nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
  153. eeprom_offset + 2, eeprom_data);
  154. next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
  155. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
  156. if (eeprom_data != 0x464e) {
  157. nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
  158. eeprom_data);
  159. goto no_fw_rev;
  160. }
  161. eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
  162. printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
  163. major_ver = (u8)(eeprom_data >> 8);
  164. minor_ver = (u8)(eeprom_data);
  165. if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
  166. nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
  167. } else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
  168. nesadapter->virtwq = 1;
  169. }
  170. if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
  171. nesadapter->send_term_ok = 1;
  172. nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
  173. (u32)((u8)eeprom_data);
  174. no_fw_rev:
  175. /* eeprom is valid */
  176. eeprom_offset = nesadapter->software_eeprom_offset;
  177. eeprom_offset += 8;
  178. nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  179. eeprom_offset += 2;
  180. mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  181. eeprom_offset += 2;
  182. mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  183. eeprom_offset += 2;
  184. mac_addr_low <<= 16;
  185. mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
  186. nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
  187. mac_addr_high, mac_addr_low);
  188. nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
  189. nesadapter->mac_addr_low = mac_addr_low;
  190. nesadapter->mac_addr_high = mac_addr_high;
  191. /* Read the Phy Type array */
  192. eeprom_offset += 10;
  193. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  194. nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
  195. nesadapter->phy_type[1] = (u8)eeprom_data;
  196. /* Read the port array */
  197. eeprom_offset += 2;
  198. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  199. nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
  200. nesadapter->phy_type[3] = (u8)eeprom_data;
  201. /* port_count is set by soft reset reg */
  202. nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
  203. " port 2 -> %u, port 3 -> %u\n",
  204. nesadapter->port_count,
  205. nesadapter->phy_type[0], nesadapter->phy_type[1],
  206. nesadapter->phy_type[2], nesadapter->phy_type[3]);
  207. /* Read PD config array */
  208. eeprom_offset += 10;
  209. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  210. nesadapter->pd_config_size[0] = eeprom_data;
  211. eeprom_offset += 2;
  212. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  213. nesadapter->pd_config_base[0] = eeprom_data;
  214. nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
  215. nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
  216. eeprom_offset += 2;
  217. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  218. nesadapter->pd_config_size[1] = eeprom_data;
  219. eeprom_offset += 2;
  220. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  221. nesadapter->pd_config_base[1] = eeprom_data;
  222. nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
  223. nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
  224. eeprom_offset += 2;
  225. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  226. nesadapter->pd_config_size[2] = eeprom_data;
  227. eeprom_offset += 2;
  228. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  229. nesadapter->pd_config_base[2] = eeprom_data;
  230. nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
  231. nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
  232. eeprom_offset += 2;
  233. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  234. nesadapter->pd_config_size[3] = eeprom_data;
  235. eeprom_offset += 2;
  236. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  237. nesadapter->pd_config_base[3] = eeprom_data;
  238. nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
  239. nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
  240. /* Read Rx Pool Size */
  241. eeprom_offset += 22; /* 46 */
  242. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  243. eeprom_offset += 2;
  244. nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
  245. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  246. nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
  247. eeprom_offset += 2;
  248. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  249. eeprom_offset += 2;
  250. nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
  251. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  252. nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
  253. eeprom_offset += 2;
  254. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  255. eeprom_offset += 2;
  256. nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
  257. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  258. nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
  259. eeprom_offset += 2;
  260. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  261. eeprom_offset += 2;
  262. nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
  263. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  264. nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
  265. nesadapter->tcp_timer_core_clk_divisor);
  266. eeprom_offset += 2;
  267. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  268. eeprom_offset += 2;
  269. nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
  270. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  271. nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
  272. eeprom_offset += 2;
  273. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  274. eeprom_offset += 2;
  275. nesadapter->cm_config = (((u32)eeprom_data) << 16) +
  276. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  277. nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
  278. eeprom_offset += 2;
  279. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  280. eeprom_offset += 2;
  281. nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
  282. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  283. nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
  284. eeprom_offset += 2;
  285. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  286. eeprom_offset += 2;
  287. nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
  288. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  289. nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
  290. eeprom_offset += 2;
  291. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  292. eeprom_offset += 2;
  293. nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
  294. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  295. nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
  296. eeprom_offset += 2;
  297. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  298. eeprom_offset += 2;
  299. nesadapter->core_clock = (((u32)eeprom_data) << 16) +
  300. nes_read16_eeprom(nesdev->regs, eeprom_offset);
  301. nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
  302. if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
  303. eeprom_offset += 2;
  304. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  305. nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
  306. nesadapter->phy_index[1] = eeprom_data & 0x00ff;
  307. eeprom_offset += 2;
  308. eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
  309. nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
  310. nesadapter->phy_index[3] = eeprom_data & 0x00ff;
  311. } else {
  312. nesadapter->phy_index[0] = 4;
  313. nesadapter->phy_index[1] = 5;
  314. nesadapter->phy_index[2] = 6;
  315. nesadapter->phy_index[3] = 7;
  316. }
  317. nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
  318. nesadapter->phy_index[0],nesadapter->phy_index[1],
  319. nesadapter->phy_index[2],nesadapter->phy_index[3]);
  320. }
  321. return 0;
  322. }
  323. /**
  324. * nes_read16_eeprom
  325. */
  326. static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
  327. {
  328. writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
  329. (void __iomem *)addr + NES_EEPROM_COMMAND);
  330. do {
  331. } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
  332. NES_EEPROM_READ_REQUEST);
  333. return readw((void __iomem *)addr + NES_EEPROM_DATA);
  334. }
  335. /**
  336. * nes_write_1G_phy_reg
  337. */
  338. void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
  339. {
  340. struct nes_adapter *nesadapter = nesdev->nesadapter;
  341. u32 u32temp;
  342. u32 counter;
  343. unsigned long flags;
  344. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  345. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  346. 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
  347. for (counter = 0; counter < 100 ; counter++) {
  348. udelay(30);
  349. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  350. if (u32temp & 1) {
  351. /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
  352. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  353. break;
  354. }
  355. }
  356. if (!(u32temp & 1))
  357. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  358. u32temp);
  359. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  360. }
  361. /**
  362. * nes_read_1G_phy_reg
  363. * This routine only issues the read, the data must be read
  364. * separately.
  365. */
  366. void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
  367. {
  368. struct nes_adapter *nesadapter = nesdev->nesadapter;
  369. u32 u32temp;
  370. u32 counter;
  371. unsigned long flags;
  372. /* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
  373. phy_addr, nesdev->mac_index); */
  374. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  375. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  376. 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
  377. for (counter = 0; counter < 100 ; counter++) {
  378. udelay(30);
  379. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  380. if (u32temp & 1) {
  381. /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
  382. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  383. break;
  384. }
  385. }
  386. if (!(u32temp & 1)) {
  387. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  388. u32temp);
  389. *data = 0xffff;
  390. } else {
  391. *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
  392. }
  393. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  394. }
  395. /**
  396. * nes_write_10G_phy_reg
  397. */
  398. void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
  399. u16 data)
  400. {
  401. u32 port_addr;
  402. u32 u32temp;
  403. u32 counter;
  404. port_addr = phy_addr;
  405. /* set address */
  406. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  407. 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  408. for (counter = 0; counter < 100 ; counter++) {
  409. udelay(30);
  410. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  411. if (u32temp & 1) {
  412. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  413. break;
  414. }
  415. }
  416. if (!(u32temp & 1))
  417. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  418. u32temp);
  419. /* set data */
  420. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  421. 0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  422. for (counter = 0; counter < 100 ; counter++) {
  423. udelay(30);
  424. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  425. if (u32temp & 1) {
  426. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  427. break;
  428. }
  429. }
  430. if (!(u32temp & 1))
  431. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  432. u32temp);
  433. }
  434. /**
  435. * nes_read_10G_phy_reg
  436. * This routine only issues the read, the data must be read
  437. * separately.
  438. */
  439. void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
  440. {
  441. u32 port_addr;
  442. u32 u32temp;
  443. u32 counter;
  444. port_addr = phy_addr;
  445. /* set address */
  446. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  447. 0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  448. for (counter = 0; counter < 100 ; counter++) {
  449. udelay(30);
  450. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  451. if (u32temp & 1) {
  452. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  453. break;
  454. }
  455. }
  456. if (!(u32temp & 1))
  457. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  458. u32temp);
  459. /* issue read */
  460. nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
  461. 0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
  462. for (counter = 0; counter < 100 ; counter++) {
  463. udelay(30);
  464. u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
  465. if (u32temp & 1) {
  466. nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
  467. break;
  468. }
  469. }
  470. if (!(u32temp & 1))
  471. nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
  472. u32temp);
  473. }
  474. /**
  475. * nes_get_cqp_request
  476. */
  477. struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
  478. {
  479. unsigned long flags;
  480. struct nes_cqp_request *cqp_request = NULL;
  481. if (!list_empty(&nesdev->cqp_avail_reqs)) {
  482. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  483. if (!list_empty(&nesdev->cqp_avail_reqs)) {
  484. cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
  485. struct nes_cqp_request, list);
  486. list_del_init(&cqp_request->list);
  487. }
  488. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  489. }
  490. if (cqp_request == NULL) {
  491. cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
  492. if (cqp_request) {
  493. cqp_request->dynamic = 1;
  494. INIT_LIST_HEAD(&cqp_request->list);
  495. }
  496. }
  497. if (cqp_request) {
  498. init_waitqueue_head(&cqp_request->waitq);
  499. cqp_request->waiting = 0;
  500. cqp_request->request_done = 0;
  501. cqp_request->callback = 0;
  502. init_waitqueue_head(&cqp_request->waitq);
  503. nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
  504. cqp_request);
  505. } else
  506. printk(KERN_ERR PFX "%s: Could not allocated a CQP request.\n",
  507. __func__);
  508. return cqp_request;
  509. }
  510. void nes_free_cqp_request(struct nes_device *nesdev,
  511. struct nes_cqp_request *cqp_request)
  512. {
  513. unsigned long flags;
  514. nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
  515. cqp_request,
  516. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
  517. if (cqp_request->dynamic) {
  518. kfree(cqp_request);
  519. } else {
  520. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  521. list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
  522. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  523. }
  524. }
  525. void nes_put_cqp_request(struct nes_device *nesdev,
  526. struct nes_cqp_request *cqp_request)
  527. {
  528. if (atomic_dec_and_test(&cqp_request->refcount))
  529. nes_free_cqp_request(nesdev, cqp_request);
  530. }
  531. /**
  532. * nes_post_cqp_request
  533. */
  534. void nes_post_cqp_request(struct nes_device *nesdev,
  535. struct nes_cqp_request *cqp_request)
  536. {
  537. struct nes_hw_cqp_wqe *cqp_wqe;
  538. unsigned long flags;
  539. u32 cqp_head;
  540. u64 u64temp;
  541. spin_lock_irqsave(&nesdev->cqp.lock, flags);
  542. if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
  543. (nesdev->cqp.sq_size - 1)) != 1)
  544. && (list_empty(&nesdev->cqp_pending_reqs))) {
  545. cqp_head = nesdev->cqp.sq_head++;
  546. nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
  547. cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
  548. memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
  549. barrier();
  550. u64temp = (unsigned long)cqp_request;
  551. set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_SCRATCH_LOW_IDX,
  552. u64temp);
  553. nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
  554. " request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
  555. " waiting = %d, refcount = %d.\n",
  556. le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
  557. le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
  558. nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
  559. cqp_request->waiting, atomic_read(&cqp_request->refcount));
  560. barrier();
  561. /* Ring doorbell (1 WQEs) */
  562. nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
  563. barrier();
  564. } else {
  565. nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
  566. " put on the pending queue.\n",
  567. cqp_request,
  568. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
  569. le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
  570. list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
  571. }
  572. spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
  573. return;
  574. }
  575. /**
  576. * nes_arp_table
  577. */
  578. int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
  579. {
  580. struct nes_adapter *nesadapter = nesdev->nesadapter;
  581. int arp_index;
  582. int err = 0;
  583. __be32 tmp_addr;
  584. for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
  585. if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
  586. break;
  587. }
  588. if (action == NES_ARP_ADD) {
  589. if (arp_index != nesadapter->arp_table_size) {
  590. return -1;
  591. }
  592. arp_index = 0;
  593. err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
  594. nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index);
  595. if (err) {
  596. nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
  597. return err;
  598. }
  599. nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
  600. nesadapter->arp_table[arp_index].ip_addr = ip_addr;
  601. memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
  602. return arp_index;
  603. }
  604. /* DELETE or RESOLVE */
  605. if (arp_index == nesadapter->arp_table_size) {
  606. tmp_addr = cpu_to_be32(ip_addr);
  607. nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
  608. &tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
  609. return -1;
  610. }
  611. if (action == NES_ARP_RESOLVE) {
  612. nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
  613. return arp_index;
  614. }
  615. if (action == NES_ARP_DELETE) {
  616. nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
  617. nesadapter->arp_table[arp_index].ip_addr = 0;
  618. memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
  619. nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
  620. return arp_index;
  621. }
  622. return -1;
  623. }
  624. /**
  625. * nes_mh_fix
  626. */
  627. void nes_mh_fix(unsigned long parm)
  628. {
  629. unsigned long flags;
  630. struct nes_device *nesdev = (struct nes_device *)parm;
  631. struct nes_adapter *nesadapter = nesdev->nesadapter;
  632. struct nes_vnic *nesvnic;
  633. u32 used_chunks_tx;
  634. u32 temp_used_chunks_tx;
  635. u32 temp_last_used_chunks_tx;
  636. u32 used_chunks_mask;
  637. u32 mac_tx_frames_low;
  638. u32 mac_tx_frames_high;
  639. u32 mac_tx_pauses;
  640. u32 serdes_status;
  641. u32 reset_value;
  642. u32 tx_control;
  643. u32 tx_config;
  644. u32 tx_pause_quanta;
  645. u32 rx_control;
  646. u32 rx_config;
  647. u32 mac_exact_match;
  648. u32 mpp_debug;
  649. u32 i=0;
  650. u32 chunks_tx_progress = 0;
  651. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  652. if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
  653. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  654. goto no_mh_work;
  655. }
  656. nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
  657. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  658. do {
  659. mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
  660. mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
  661. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  662. used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
  663. nesdev->mac_pause_frames_sent += mac_tx_pauses;
  664. used_chunks_mask = 0;
  665. temp_used_chunks_tx = used_chunks_tx;
  666. temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
  667. if (nesdev->netdev[0]) {
  668. nesvnic = netdev_priv(nesdev->netdev[0]);
  669. } else {
  670. break;
  671. }
  672. for (i=0; i<4; i++) {
  673. used_chunks_mask <<= 8;
  674. if (nesvnic->qp_nic_index[i] != 0xff) {
  675. used_chunks_mask |= 0xff;
  676. if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
  677. chunks_tx_progress = 1;
  678. }
  679. }
  680. temp_used_chunks_tx >>= 8;
  681. temp_last_used_chunks_tx >>= 8;
  682. }
  683. if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
  684. (!(used_chunks_tx&used_chunks_mask)) ||
  685. (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
  686. (chunks_tx_progress) ) {
  687. nesdev->last_used_chunks_tx = used_chunks_tx;
  688. break;
  689. }
  690. nesdev->last_used_chunks_tx = used_chunks_tx;
  691. barrier();
  692. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
  693. mh_pauses_sent++;
  694. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  695. if (mac_tx_pauses) {
  696. nesdev->mac_pause_frames_sent += mac_tx_pauses;
  697. break;
  698. }
  699. tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
  700. tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
  701. tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
  702. rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
  703. rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
  704. mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
  705. mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
  706. /* one last ditch effort to avoid a false positive */
  707. mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
  708. if (mac_tx_pauses) {
  709. nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
  710. nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
  711. break;
  712. }
  713. mh_detected++;
  714. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
  715. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
  716. reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
  717. nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
  718. while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
  719. & 0x00000040) != 0x00000040) && (i++ < 5000)) {
  720. /* mdelay(1); */
  721. }
  722. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
  723. serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
  724. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
  725. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
  726. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
  727. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
  728. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
  729. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
  730. if (nesadapter->OneG_Mode) {
  731. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
  732. } else {
  733. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
  734. }
  735. serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
  736. nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
  737. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
  738. nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
  739. nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
  740. nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
  741. nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
  742. nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
  743. nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
  744. } while (0);
  745. nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
  746. no_mh_work:
  747. nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
  748. add_timer(&nesdev->nesadapter->mh_timer);
  749. }
  750. /**
  751. * nes_clc
  752. */
  753. void nes_clc(unsigned long parm)
  754. {
  755. unsigned long flags;
  756. struct nes_device *nesdev = (struct nes_device *)parm;
  757. struct nes_adapter *nesadapter = nesdev->nesadapter;
  758. spin_lock_irqsave(&nesadapter->phy_lock, flags);
  759. nesadapter->link_interrupt_count[0] = 0;
  760. nesadapter->link_interrupt_count[1] = 0;
  761. nesadapter->link_interrupt_count[2] = 0;
  762. nesadapter->link_interrupt_count[3] = 0;
  763. spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
  764. nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
  765. add_timer(&nesadapter->lc_timer);
  766. }
  767. /**
  768. * nes_dump_mem
  769. */
  770. void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
  771. {
  772. char xlate[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
  773. 'a', 'b', 'c', 'd', 'e', 'f'};
  774. char *ptr;
  775. char hex_buf[80];
  776. char ascii_buf[20];
  777. int num_char;
  778. int num_ascii;
  779. int num_hex;
  780. if (!(nes_debug_level & dump_debug_level)) {
  781. return;
  782. }
  783. ptr = addr;
  784. if (length > 0x100) {
  785. nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
  786. length = 0x100;
  787. }
  788. nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", ptr, length, length);
  789. memset(ascii_buf, 0, 20);
  790. memset(hex_buf, 0, 80);
  791. num_ascii = 0;
  792. num_hex = 0;
  793. for (num_char = 0; num_char < length; num_char++) {
  794. if (num_ascii == 8) {
  795. ascii_buf[num_ascii++] = ' ';
  796. hex_buf[num_hex++] = '-';
  797. hex_buf[num_hex++] = ' ';
  798. }
  799. if (*ptr < 0x20 || *ptr > 0x7e)
  800. ascii_buf[num_ascii++] = '.';
  801. else
  802. ascii_buf[num_ascii++] = *ptr;
  803. hex_buf[num_hex++] = xlate[((*ptr & 0xf0) >> 4)];
  804. hex_buf[num_hex++] = xlate[*ptr & 0x0f];
  805. hex_buf[num_hex++] = ' ';
  806. ptr++;
  807. if (num_ascii >= 17) {
  808. /* output line and reset */
  809. nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
  810. memset(ascii_buf, 0, 20);
  811. memset(hex_buf, 0, 80);
  812. num_ascii = 0;
  813. num_hex = 0;
  814. }
  815. }
  816. /* output the rest */
  817. if (num_ascii) {
  818. while (num_ascii < 17) {
  819. if (num_ascii == 8) {
  820. hex_buf[num_hex++] = ' ';
  821. hex_buf[num_hex++] = ' ';
  822. }
  823. hex_buf[num_hex++] = ' ';
  824. hex_buf[num_hex++] = ' ';
  825. hex_buf[num_hex++] = ' ';
  826. num_ascii++;
  827. }
  828. nes_debug(dump_debug_level, " %s | %s\n", hex_buf, ascii_buf);
  829. }
  830. }