s3c64xx-cpufreq.c 6.1 KB

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  1. /*
  2. * Copyright 2009 Wolfson Microelectronics plc
  3. *
  4. * S3C64xx CPUfreq Support
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #define pr_fmt(fmt) "cpufreq: " fmt
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/init.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/module.h>
  19. static struct clk *armclk;
  20. static struct regulator *vddarm;
  21. static unsigned long regulator_latency;
  22. #ifdef CONFIG_CPU_S3C6410
  23. struct s3c64xx_dvfs {
  24. unsigned int vddarm_min;
  25. unsigned int vddarm_max;
  26. };
  27. static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
  28. [0] = { 1000000, 1150000 },
  29. [1] = { 1050000, 1150000 },
  30. [2] = { 1100000, 1150000 },
  31. [3] = { 1200000, 1350000 },
  32. [4] = { 1300000, 1350000 },
  33. };
  34. static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
  35. { 0, 66000 },
  36. { 0, 100000 },
  37. { 0, 133000 },
  38. { 1, 200000 },
  39. { 1, 222000 },
  40. { 1, 266000 },
  41. { 2, 333000 },
  42. { 2, 400000 },
  43. { 2, 532000 },
  44. { 2, 533000 },
  45. { 3, 667000 },
  46. { 4, 800000 },
  47. { 0, CPUFREQ_TABLE_END },
  48. };
  49. #endif
  50. static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
  51. {
  52. if (cpu != 0)
  53. return 0;
  54. return clk_get_rate(armclk) / 1000;
  55. }
  56. static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
  57. unsigned int target_freq,
  58. unsigned int relation)
  59. {
  60. int ret;
  61. unsigned int i;
  62. struct cpufreq_freqs freqs;
  63. struct s3c64xx_dvfs *dvfs;
  64. ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
  65. target_freq, relation, &i);
  66. if (ret != 0)
  67. return ret;
  68. freqs.old = clk_get_rate(armclk) / 1000;
  69. freqs.new = s3c64xx_freq_table[i].frequency;
  70. freqs.flags = 0;
  71. dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].driver_data];
  72. if (freqs.old == freqs.new)
  73. return 0;
  74. pr_debug("Transition %d-%dkHz\n", freqs.old, freqs.new);
  75. cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  76. #ifdef CONFIG_REGULATOR
  77. if (vddarm && freqs.new > freqs.old) {
  78. ret = regulator_set_voltage(vddarm,
  79. dvfs->vddarm_min,
  80. dvfs->vddarm_max);
  81. if (ret != 0) {
  82. pr_err("Failed to set VDDARM for %dkHz: %d\n",
  83. freqs.new, ret);
  84. freqs.new = freqs.old;
  85. goto post_notify;
  86. }
  87. }
  88. #endif
  89. ret = clk_set_rate(armclk, freqs.new * 1000);
  90. if (ret < 0) {
  91. pr_err("Failed to set rate %dkHz: %d\n",
  92. freqs.new, ret);
  93. freqs.new = freqs.old;
  94. }
  95. post_notify:
  96. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  97. if (ret)
  98. goto err;
  99. #ifdef CONFIG_REGULATOR
  100. if (vddarm && freqs.new < freqs.old) {
  101. ret = regulator_set_voltage(vddarm,
  102. dvfs->vddarm_min,
  103. dvfs->vddarm_max);
  104. if (ret != 0) {
  105. pr_err("Failed to set VDDARM for %dkHz: %d\n",
  106. freqs.new, ret);
  107. goto err_clk;
  108. }
  109. }
  110. #endif
  111. pr_debug("Set actual frequency %lukHz\n",
  112. clk_get_rate(armclk) / 1000);
  113. return 0;
  114. err_clk:
  115. if (clk_set_rate(armclk, freqs.old * 1000) < 0)
  116. pr_err("Failed to restore original clock rate\n");
  117. err:
  118. cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
  119. return ret;
  120. }
  121. #ifdef CONFIG_REGULATOR
  122. static void __init s3c64xx_cpufreq_config_regulator(void)
  123. {
  124. int count, v, i, found;
  125. struct cpufreq_frequency_table *freq;
  126. struct s3c64xx_dvfs *dvfs;
  127. count = regulator_count_voltages(vddarm);
  128. if (count < 0) {
  129. pr_err("Unable to check supported voltages\n");
  130. }
  131. freq = s3c64xx_freq_table;
  132. while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
  133. if (freq->frequency == CPUFREQ_ENTRY_INVALID)
  134. continue;
  135. dvfs = &s3c64xx_dvfs_table[freq->driver_data];
  136. found = 0;
  137. for (i = 0; i < count; i++) {
  138. v = regulator_list_voltage(vddarm, i);
  139. if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
  140. found = 1;
  141. }
  142. if (!found) {
  143. pr_debug("%dkHz unsupported by regulator\n",
  144. freq->frequency);
  145. freq->frequency = CPUFREQ_ENTRY_INVALID;
  146. }
  147. freq++;
  148. }
  149. /* Guess based on having to do an I2C/SPI write; in future we
  150. * will be able to query the regulator performance here. */
  151. regulator_latency = 1 * 1000 * 1000;
  152. }
  153. #endif
  154. static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
  155. {
  156. int ret;
  157. struct cpufreq_frequency_table *freq;
  158. if (policy->cpu != 0)
  159. return -EINVAL;
  160. if (s3c64xx_freq_table == NULL) {
  161. pr_err("No frequency information for this CPU\n");
  162. return -ENODEV;
  163. }
  164. armclk = clk_get(NULL, "armclk");
  165. if (IS_ERR(armclk)) {
  166. pr_err("Unable to obtain ARMCLK: %ld\n",
  167. PTR_ERR(armclk));
  168. return PTR_ERR(armclk);
  169. }
  170. #ifdef CONFIG_REGULATOR
  171. vddarm = regulator_get(NULL, "vddarm");
  172. if (IS_ERR(vddarm)) {
  173. ret = PTR_ERR(vddarm);
  174. pr_err("Failed to obtain VDDARM: %d\n", ret);
  175. pr_err("Only frequency scaling available\n");
  176. vddarm = NULL;
  177. } else {
  178. s3c64xx_cpufreq_config_regulator();
  179. }
  180. #endif
  181. freq = s3c64xx_freq_table;
  182. while (freq->frequency != CPUFREQ_TABLE_END) {
  183. unsigned long r;
  184. /* Check for frequencies we can generate */
  185. r = clk_round_rate(armclk, freq->frequency * 1000);
  186. r /= 1000;
  187. if (r != freq->frequency) {
  188. pr_debug("%dkHz unsupported by clock\n",
  189. freq->frequency);
  190. freq->frequency = CPUFREQ_ENTRY_INVALID;
  191. }
  192. /* If we have no regulator then assume startup
  193. * frequency is the maximum we can support. */
  194. if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
  195. freq->frequency = CPUFREQ_ENTRY_INVALID;
  196. freq++;
  197. }
  198. /* Datasheet says PLL stabalisation time (if we were to use
  199. * the PLLs, which we don't currently) is ~300us worst case,
  200. * but add some fudge.
  201. */
  202. ret = cpufreq_generic_init(policy, s3c64xx_freq_table,
  203. (500 * 1000) + regulator_latency);
  204. if (ret != 0) {
  205. pr_err("Failed to configure frequency table: %d\n",
  206. ret);
  207. regulator_put(vddarm);
  208. clk_put(armclk);
  209. }
  210. return ret;
  211. }
  212. static struct cpufreq_driver s3c64xx_cpufreq_driver = {
  213. .flags = 0,
  214. .verify = cpufreq_generic_frequency_table_verify,
  215. .target = s3c64xx_cpufreq_set_target,
  216. .get = s3c64xx_cpufreq_get_speed,
  217. .init = s3c64xx_cpufreq_driver_init,
  218. .name = "s3c",
  219. };
  220. static int __init s3c64xx_cpufreq_init(void)
  221. {
  222. return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
  223. }
  224. module_init(s3c64xx_cpufreq_init);