tlb_32.c 6.0 KB

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  1. #include <linux/spinlock.h>
  2. #include <linux/cpu.h>
  3. #include <linux/interrupt.h>
  4. #include <asm/tlbflush.h>
  5. DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
  6. = { &init_mm, 0, };
  7. /* must come after the send_IPI functions above for inlining */
  8. #include <mach_ipi.h>
  9. /*
  10. * Smarter SMP flushing macros.
  11. * c/o Linus Torvalds.
  12. *
  13. * These mean you can really definitely utterly forget about
  14. * writing to user space from interrupts. (Its not allowed anyway).
  15. *
  16. * Optimizations Manfred Spraul <manfred@colorfullife.com>
  17. */
  18. static cpumask_var_t flush_cpumask;
  19. static struct mm_struct *flush_mm;
  20. static unsigned long flush_va;
  21. static DEFINE_SPINLOCK(tlbstate_lock);
  22. /*
  23. * We cannot call mmdrop() because we are in interrupt context,
  24. * instead update mm->cpu_vm_mask.
  25. *
  26. * We need to reload %cr3 since the page tables may be going
  27. * away from under us..
  28. */
  29. void leave_mm(int cpu)
  30. {
  31. BUG_ON(percpu_read(cpu_tlbstate.state) == TLBSTATE_OK);
  32. cpu_clear(cpu, percpu_read(cpu_tlbstate.active_mm)->cpu_vm_mask);
  33. load_cr3(swapper_pg_dir);
  34. }
  35. EXPORT_SYMBOL_GPL(leave_mm);
  36. /*
  37. *
  38. * The flush IPI assumes that a thread switch happens in this order:
  39. * [cpu0: the cpu that switches]
  40. * 1) switch_mm() either 1a) or 1b)
  41. * 1a) thread switch to a different mm
  42. * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
  43. * Stop ipi delivery for the old mm. This is not synchronized with
  44. * the other cpus, but smp_invalidate_interrupt ignore flush ipis
  45. * for the wrong mm, and in the worst case we perform a superfluous
  46. * tlb flush.
  47. * 1a2) set cpu_tlbstate to TLBSTATE_OK
  48. * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
  49. * was in lazy tlb mode.
  50. * 1a3) update cpu_tlbstate[].active_mm
  51. * Now cpu0 accepts tlb flushes for the new mm.
  52. * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
  53. * Now the other cpus will send tlb flush ipis.
  54. * 1a4) change cr3.
  55. * 1b) thread switch without mm change
  56. * cpu_tlbstate[].active_mm is correct, cpu0 already handles
  57. * flush ipis.
  58. * 1b1) set cpu_tlbstate to TLBSTATE_OK
  59. * 1b2) test_and_set the cpu bit in cpu_vm_mask.
  60. * Atomically set the bit [other cpus will start sending flush ipis],
  61. * and test the bit.
  62. * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
  63. * 2) switch %%esp, ie current
  64. *
  65. * The interrupt must handle 2 special cases:
  66. * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
  67. * - the cpu performs speculative tlb reads, i.e. even if the cpu only
  68. * runs in kernel space, the cpu could load tlb entries for user space
  69. * pages.
  70. *
  71. * The good news is that cpu_tlbstate is local to each cpu, no
  72. * write/read ordering problems.
  73. */
  74. /*
  75. * TLB flush IPI:
  76. *
  77. * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
  78. * 2) Leave the mm if we are in the lazy tlb mode.
  79. *
  80. * Interrupts are disabled.
  81. */
  82. void smp_invalidate_interrupt(struct pt_regs *regs)
  83. {
  84. unsigned int cpu;
  85. cpu = smp_processor_id();
  86. if (!cpumask_test_cpu(cpu, flush_cpumask))
  87. goto out;
  88. /*
  89. * This was a BUG() but until someone can quote me the
  90. * line from the intel manual that guarantees an IPI to
  91. * multiple CPUs is retried _only_ on the erroring CPUs
  92. * its staying as a return
  93. *
  94. * BUG();
  95. */
  96. if (flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
  97. if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
  98. if (flush_va == TLB_FLUSH_ALL)
  99. local_flush_tlb();
  100. else
  101. __flush_tlb_one(flush_va);
  102. } else
  103. leave_mm(cpu);
  104. }
  105. out:
  106. ack_APIC_irq();
  107. smp_mb__before_clear_bit();
  108. cpumask_clear_cpu(cpu, flush_cpumask);
  109. smp_mb__after_clear_bit();
  110. inc_irq_stat(irq_tlb_count);
  111. }
  112. void native_flush_tlb_others(const struct cpumask *cpumask,
  113. struct mm_struct *mm, unsigned long va)
  114. {
  115. /*
  116. * - mask must exist :)
  117. */
  118. BUG_ON(cpumask_empty(cpumask));
  119. BUG_ON(!mm);
  120. /*
  121. * i'm not happy about this global shared spinlock in the
  122. * MM hot path, but we'll see how contended it is.
  123. * AK: x86-64 has a faster method that could be ported.
  124. */
  125. spin_lock(&tlbstate_lock);
  126. cpumask_andnot(flush_cpumask, cpumask, cpumask_of(smp_processor_id()));
  127. #ifdef CONFIG_HOTPLUG_CPU
  128. /* If a CPU which we ran on has gone down, OK. */
  129. cpumask_and(flush_cpumask, flush_cpumask, cpu_online_mask);
  130. if (unlikely(cpumask_empty(flush_cpumask))) {
  131. spin_unlock(&tlbstate_lock);
  132. return;
  133. }
  134. #endif
  135. flush_mm = mm;
  136. flush_va = va;
  137. /*
  138. * Make the above memory operations globally visible before
  139. * sending the IPI.
  140. */
  141. smp_mb();
  142. /*
  143. * We have to send the IPI only to
  144. * CPUs affected.
  145. */
  146. send_IPI_mask(flush_cpumask, INVALIDATE_TLB_VECTOR);
  147. while (!cpumask_empty(flush_cpumask))
  148. /* nothing. lockup detection does not belong here */
  149. cpu_relax();
  150. flush_mm = NULL;
  151. flush_va = 0;
  152. spin_unlock(&tlbstate_lock);
  153. }
  154. void flush_tlb_current_task(void)
  155. {
  156. struct mm_struct *mm = current->mm;
  157. preempt_disable();
  158. local_flush_tlb();
  159. if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
  160. flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
  161. preempt_enable();
  162. }
  163. void flush_tlb_mm(struct mm_struct *mm)
  164. {
  165. preempt_disable();
  166. if (current->active_mm == mm) {
  167. if (current->mm)
  168. local_flush_tlb();
  169. else
  170. leave_mm(smp_processor_id());
  171. }
  172. if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
  173. flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
  174. preempt_enable();
  175. }
  176. void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
  177. {
  178. struct mm_struct *mm = vma->vm_mm;
  179. preempt_disable();
  180. if (current->active_mm == mm) {
  181. if (current->mm)
  182. __flush_tlb_one(va);
  183. else
  184. leave_mm(smp_processor_id());
  185. }
  186. if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
  187. flush_tlb_others(&mm->cpu_vm_mask, mm, va);
  188. preempt_enable();
  189. }
  190. static void do_flush_tlb_all(void *info)
  191. {
  192. unsigned long cpu = smp_processor_id();
  193. __flush_tlb_all();
  194. if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
  195. leave_mm(cpu);
  196. }
  197. void flush_tlb_all(void)
  198. {
  199. on_each_cpu(do_flush_tlb_all, NULL, 1);
  200. }
  201. static int init_flush_cpumask(void)
  202. {
  203. alloc_cpumask_var(&flush_cpumask, GFP_KERNEL);
  204. return 0;
  205. }
  206. early_initcall(init_flush_cpumask);