ioapic.c 8.6 KB

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  1. /*
  2. * Copyright (C) 2001 MandrakeSoft S.A.
  3. *
  4. * MandrakeSoft S.A.
  5. * 43, rue d'Aboukir
  6. * 75002 Paris - France
  7. * http://www.linux-mandrake.com/
  8. * http://www.mandrakesoft.com/
  9. *
  10. * This library is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU Lesser General Public
  12. * License as published by the Free Software Foundation; either
  13. * version 2 of the License, or (at your option) any later version.
  14. *
  15. * This library is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * Lesser General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU Lesser General Public
  21. * License along with this library; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. * Yunhong Jiang <yunhong.jiang@intel.com>
  25. * Yaozu (Eddie) Dong <eddie.dong@intel.com>
  26. * Based on Xen 3.1 code.
  27. */
  28. #include <linux/kvm_host.h>
  29. #include <linux/kvm.h>
  30. #include <linux/mm.h>
  31. #include <linux/highmem.h>
  32. #include <linux/smp.h>
  33. #include <linux/hrtimer.h>
  34. #include <linux/io.h>
  35. #include <asm/processor.h>
  36. #include <asm/page.h>
  37. #include <asm/current.h>
  38. #include "ioapic.h"
  39. #include "lapic.h"
  40. #include "irq.h"
  41. #if 0
  42. #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  43. #else
  44. #define ioapic_debug(fmt, arg...)
  45. #endif
  46. static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  47. static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  48. unsigned long addr,
  49. unsigned long length)
  50. {
  51. unsigned long result = 0;
  52. switch (ioapic->ioregsel) {
  53. case IOAPIC_REG_VERSION:
  54. result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  55. | (IOAPIC_VERSION_ID & 0xff));
  56. break;
  57. case IOAPIC_REG_APIC_ID:
  58. case IOAPIC_REG_ARB_ID:
  59. result = ((ioapic->id & 0xf) << 24);
  60. break;
  61. default:
  62. {
  63. u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  64. u64 redir_content;
  65. ASSERT(redir_index < IOAPIC_NUM_PINS);
  66. redir_content = ioapic->redirtbl[redir_index].bits;
  67. result = (ioapic->ioregsel & 0x1) ?
  68. (redir_content >> 32) & 0xffffffff :
  69. redir_content & 0xffffffff;
  70. break;
  71. }
  72. }
  73. return result;
  74. }
  75. static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  76. {
  77. union kvm_ioapic_redirect_entry *pent;
  78. int injected = -1;
  79. pent = &ioapic->redirtbl[idx];
  80. if (!pent->fields.mask) {
  81. injected = ioapic_deliver(ioapic, idx);
  82. if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  83. pent->fields.remote_irr = 1;
  84. }
  85. if (!pent->fields.trig_mode)
  86. ioapic->irr &= ~(1 << idx);
  87. return injected;
  88. }
  89. static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
  90. {
  91. unsigned index;
  92. bool mask_before, mask_after;
  93. switch (ioapic->ioregsel) {
  94. case IOAPIC_REG_VERSION:
  95. /* Writes are ignored. */
  96. break;
  97. case IOAPIC_REG_APIC_ID:
  98. ioapic->id = (val >> 24) & 0xf;
  99. break;
  100. case IOAPIC_REG_ARB_ID:
  101. break;
  102. default:
  103. index = (ioapic->ioregsel - 0x10) >> 1;
  104. ioapic_debug("change redir index %x val %x\n", index, val);
  105. if (index >= IOAPIC_NUM_PINS)
  106. return;
  107. mask_before = ioapic->redirtbl[index].fields.mask;
  108. if (ioapic->ioregsel & 1) {
  109. ioapic->redirtbl[index].bits &= 0xffffffff;
  110. ioapic->redirtbl[index].bits |= (u64) val << 32;
  111. } else {
  112. ioapic->redirtbl[index].bits &= ~0xffffffffULL;
  113. ioapic->redirtbl[index].bits |= (u32) val;
  114. ioapic->redirtbl[index].fields.remote_irr = 0;
  115. }
  116. mask_after = ioapic->redirtbl[index].fields.mask;
  117. if (mask_before != mask_after)
  118. kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
  119. if (ioapic->irr & (1 << index))
  120. ioapic_service(ioapic, index);
  121. break;
  122. }
  123. }
  124. static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
  125. {
  126. union kvm_ioapic_redirect_entry entry = ioapic->redirtbl[irq];
  127. DECLARE_BITMAP(deliver_bitmask, KVM_MAX_VCPUS);
  128. struct kvm_vcpu *vcpu;
  129. int vcpu_id, r = -1;
  130. ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
  131. "vector=%x trig_mode=%x\n",
  132. entry.fields.dest, entry.fields.dest_mode,
  133. entry.fields.delivery_mode, entry.fields.vector,
  134. entry.fields.trig_mode);
  135. /* Always delivery PIT interrupt to vcpu 0 */
  136. #ifdef CONFIG_X86
  137. if (irq == 0) {
  138. bitmap_zero(deliver_bitmask, KVM_MAX_VCPUS);
  139. __set_bit(0, deliver_bitmask);
  140. } else
  141. #endif
  142. kvm_get_intr_delivery_bitmask(ioapic, &entry, deliver_bitmask);
  143. if (find_first_bit(deliver_bitmask, KVM_MAX_VCPUS) >= KVM_MAX_VCPUS) {
  144. ioapic_debug("no target on destination\n");
  145. return 0;
  146. }
  147. while ((vcpu_id = find_first_bit(deliver_bitmask, KVM_MAX_VCPUS))
  148. < KVM_MAX_VCPUS) {
  149. __clear_bit(vcpu_id, deliver_bitmask);
  150. vcpu = ioapic->kvm->vcpus[vcpu_id];
  151. if (vcpu) {
  152. if (r < 0)
  153. r = 0;
  154. r += kvm_apic_set_irq(vcpu,
  155. entry.fields.vector,
  156. entry.fields.trig_mode,
  157. entry.fields.delivery_mode);
  158. } else
  159. ioapic_debug("null destination vcpu: "
  160. "mask=%x vector=%x delivery_mode=%x\n",
  161. entry.fields.deliver_bitmask,
  162. entry.fields.vector,
  163. entry.fields.delivery_mode);
  164. }
  165. return r;
  166. }
  167. int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
  168. {
  169. u32 old_irr = ioapic->irr;
  170. u32 mask = 1 << irq;
  171. union kvm_ioapic_redirect_entry entry;
  172. int ret = 1;
  173. if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
  174. entry = ioapic->redirtbl[irq];
  175. level ^= entry.fields.polarity;
  176. if (!level)
  177. ioapic->irr &= ~mask;
  178. else {
  179. ioapic->irr |= mask;
  180. if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
  181. || !entry.fields.remote_irr)
  182. ret = ioapic_service(ioapic, irq);
  183. }
  184. }
  185. return ret;
  186. }
  187. static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
  188. int trigger_mode)
  189. {
  190. union kvm_ioapic_redirect_entry *ent;
  191. ent = &ioapic->redirtbl[pin];
  192. kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
  193. if (trigger_mode == IOAPIC_LEVEL_TRIG) {
  194. ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
  195. ent->fields.remote_irr = 0;
  196. if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
  197. ioapic_service(ioapic, pin);
  198. }
  199. }
  200. void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
  201. {
  202. struct kvm_ioapic *ioapic = kvm->arch.vioapic;
  203. int i;
  204. for (i = 0; i < IOAPIC_NUM_PINS; i++)
  205. if (ioapic->redirtbl[i].fields.vector == vector)
  206. __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
  207. }
  208. static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
  209. int len, int is_write)
  210. {
  211. struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
  212. return ((addr >= ioapic->base_address &&
  213. (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
  214. }
  215. static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
  216. void *val)
  217. {
  218. struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
  219. u32 result;
  220. ioapic_debug("addr %lx\n", (unsigned long)addr);
  221. ASSERT(!(addr & 0xf)); /* check alignment */
  222. addr &= 0xff;
  223. switch (addr) {
  224. case IOAPIC_REG_SELECT:
  225. result = ioapic->ioregsel;
  226. break;
  227. case IOAPIC_REG_WINDOW:
  228. result = ioapic_read_indirect(ioapic, addr, len);
  229. break;
  230. default:
  231. result = 0;
  232. break;
  233. }
  234. switch (len) {
  235. case 8:
  236. *(u64 *) val = result;
  237. break;
  238. case 1:
  239. case 2:
  240. case 4:
  241. memcpy(val, (char *)&result, len);
  242. break;
  243. default:
  244. printk(KERN_WARNING "ioapic: wrong length %d\n", len);
  245. }
  246. }
  247. static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
  248. const void *val)
  249. {
  250. struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
  251. u32 data;
  252. ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
  253. (void*)addr, len, val);
  254. ASSERT(!(addr & 0xf)); /* check alignment */
  255. if (len == 4 || len == 8)
  256. data = *(u32 *) val;
  257. else {
  258. printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
  259. return;
  260. }
  261. addr &= 0xff;
  262. switch (addr) {
  263. case IOAPIC_REG_SELECT:
  264. ioapic->ioregsel = data;
  265. break;
  266. case IOAPIC_REG_WINDOW:
  267. ioapic_write_indirect(ioapic, data);
  268. break;
  269. #ifdef CONFIG_IA64
  270. case IOAPIC_REG_EOI:
  271. kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
  272. break;
  273. #endif
  274. default:
  275. break;
  276. }
  277. }
  278. void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
  279. {
  280. int i;
  281. for (i = 0; i < IOAPIC_NUM_PINS; i++)
  282. ioapic->redirtbl[i].fields.mask = 1;
  283. ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
  284. ioapic->ioregsel = 0;
  285. ioapic->irr = 0;
  286. ioapic->id = 0;
  287. }
  288. int kvm_ioapic_init(struct kvm *kvm)
  289. {
  290. struct kvm_ioapic *ioapic;
  291. ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
  292. if (!ioapic)
  293. return -ENOMEM;
  294. kvm->arch.vioapic = ioapic;
  295. kvm_ioapic_reset(ioapic);
  296. ioapic->dev.read = ioapic_mmio_read;
  297. ioapic->dev.write = ioapic_mmio_write;
  298. ioapic->dev.in_range = ioapic_in_range;
  299. ioapic->dev.private = ioapic;
  300. ioapic->kvm = kvm;
  301. kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
  302. return 0;
  303. }