main.c 211 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include <linux/pci_ids.h>
  18. #include <linux/if_ether.h>
  19. #include <net/cfg80211.h>
  20. #include <net/mac80211.h>
  21. #include <brcm_hw_ids.h>
  22. #include <aiutils.h>
  23. #include <chipcommon.h>
  24. #include "rate.h"
  25. #include "scb.h"
  26. #include "phy/phy_hal.h"
  27. #include "channel.h"
  28. #include "antsel.h"
  29. #include "stf.h"
  30. #include "ampdu.h"
  31. #include "mac80211_if.h"
  32. #include "ucode_loader.h"
  33. #include "main.h"
  34. #include "soc.h"
  35. #include "dma.h"
  36. #include "debug.h"
  37. #include "brcms_trace_events.h"
  38. /* watchdog timer, in unit of ms */
  39. #define TIMER_INTERVAL_WATCHDOG 1000
  40. /* radio monitor timer, in unit of ms */
  41. #define TIMER_INTERVAL_RADIOCHK 800
  42. /* beacon interval, in unit of 1024TU */
  43. #define BEACON_INTERVAL_DEFAULT 100
  44. /* n-mode support capability */
  45. /* 2x2 includes both 1x1 & 2x2 devices
  46. * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
  47. * control it independently
  48. */
  49. #define WL_11N_2x2 1
  50. #define WL_11N_3x3 3
  51. #define WL_11N_4x4 4
  52. #define EDCF_ACI_MASK 0x60
  53. #define EDCF_ACI_SHIFT 5
  54. #define EDCF_ECWMIN_MASK 0x0f
  55. #define EDCF_ECWMAX_SHIFT 4
  56. #define EDCF_AIFSN_MASK 0x0f
  57. #define EDCF_AIFSN_MAX 15
  58. #define EDCF_ECWMAX_MASK 0xf0
  59. #define EDCF_AC_BE_TXOP_STA 0x0000
  60. #define EDCF_AC_BK_TXOP_STA 0x0000
  61. #define EDCF_AC_VO_ACI_STA 0x62
  62. #define EDCF_AC_VO_ECW_STA 0x32
  63. #define EDCF_AC_VI_ACI_STA 0x42
  64. #define EDCF_AC_VI_ECW_STA 0x43
  65. #define EDCF_AC_BK_ECW_STA 0xA4
  66. #define EDCF_AC_VI_TXOP_STA 0x005e
  67. #define EDCF_AC_VO_TXOP_STA 0x002f
  68. #define EDCF_AC_BE_ACI_STA 0x03
  69. #define EDCF_AC_BE_ECW_STA 0xA4
  70. #define EDCF_AC_BK_ACI_STA 0x27
  71. #define EDCF_AC_VO_TXOP_AP 0x002f
  72. #define EDCF_TXOP2USEC(txop) ((txop) << 5)
  73. #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
  74. #define APHY_SYMBOL_TIME 4
  75. #define APHY_PREAMBLE_TIME 16
  76. #define APHY_SIGNAL_TIME 4
  77. #define APHY_SIFS_TIME 16
  78. #define APHY_SERVICE_NBITS 16
  79. #define APHY_TAIL_NBITS 6
  80. #define BPHY_SIFS_TIME 10
  81. #define BPHY_PLCP_SHORT_TIME 96
  82. #define PREN_PREAMBLE 24
  83. #define PREN_MM_EXT 12
  84. #define PREN_PREAMBLE_EXT 4
  85. #define DOT11_MAC_HDR_LEN 24
  86. #define DOT11_ACK_LEN 10
  87. #define DOT11_BA_LEN 4
  88. #define DOT11_OFDM_SIGNAL_EXTENSION 6
  89. #define DOT11_MIN_FRAG_LEN 256
  90. #define DOT11_RTS_LEN 16
  91. #define DOT11_CTS_LEN 10
  92. #define DOT11_BA_BITMAP_LEN 128
  93. #define DOT11_MAXNUMFRAGS 16
  94. #define DOT11_MAX_FRAG_LEN 2346
  95. #define BPHY_PLCP_TIME 192
  96. #define RIFS_11N_TIME 2
  97. /* length of the BCN template area */
  98. #define BCN_TMPL_LEN 512
  99. /* brcms_bss_info flag bit values */
  100. #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
  101. /* chip rx buffer offset */
  102. #define BRCMS_HWRXOFF 38
  103. /* rfdisable delay timer 500 ms, runs of ALP clock */
  104. #define RFDISABLE_DEFAULT 10000000
  105. #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
  106. /* synthpu_dly times in us */
  107. #define SYNTHPU_DLY_APHY_US 3700
  108. #define SYNTHPU_DLY_BPHY_US 1050
  109. #define SYNTHPU_DLY_NPHY_US 2048
  110. #define SYNTHPU_DLY_LPPHY_US 300
  111. #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
  112. /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
  113. #define EDCF_SHORT_S 0
  114. #define EDCF_SFB_S 4
  115. #define EDCF_LONG_S 8
  116. #define EDCF_LFB_S 12
  117. #define EDCF_SHORT_M BITFIELD_MASK(4)
  118. #define EDCF_SFB_M BITFIELD_MASK(4)
  119. #define EDCF_LONG_M BITFIELD_MASK(4)
  120. #define EDCF_LFB_M BITFIELD_MASK(4)
  121. #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
  122. #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
  123. #define RETRY_LONG_DEF 4 /* Default Long retry count */
  124. #define RETRY_SHORT_FB 3 /* Short count for fb rate */
  125. #define RETRY_LONG_FB 2 /* Long count for fb rate */
  126. #define APHY_CWMIN 15
  127. #define PHY_CWMAX 1023
  128. #define EDCF_AIFSN_MIN 1
  129. #define FRAGNUM_MASK 0xF
  130. #define APHY_SLOT_TIME 9
  131. #define BPHY_SLOT_TIME 20
  132. #define WL_SPURAVOID_OFF 0
  133. #define WL_SPURAVOID_ON1 1
  134. #define WL_SPURAVOID_ON2 2
  135. /* invalid core flags, use the saved coreflags */
  136. #define BRCMS_USE_COREFLAGS 0xffffffff
  137. /* values for PLCPHdr_override */
  138. #define BRCMS_PLCP_AUTO -1
  139. #define BRCMS_PLCP_SHORT 0
  140. #define BRCMS_PLCP_LONG 1
  141. /* values for g_protection_override and n_protection_override */
  142. #define BRCMS_PROTECTION_AUTO -1
  143. #define BRCMS_PROTECTION_OFF 0
  144. #define BRCMS_PROTECTION_ON 1
  145. #define BRCMS_PROTECTION_MMHDR_ONLY 2
  146. #define BRCMS_PROTECTION_CTS_ONLY 3
  147. /* values for g_protection_control and n_protection_control */
  148. #define BRCMS_PROTECTION_CTL_OFF 0
  149. #define BRCMS_PROTECTION_CTL_LOCAL 1
  150. #define BRCMS_PROTECTION_CTL_OVERLAP 2
  151. /* values for n_protection */
  152. #define BRCMS_N_PROTECTION_OFF 0
  153. #define BRCMS_N_PROTECTION_OPTIONAL 1
  154. #define BRCMS_N_PROTECTION_20IN40 2
  155. #define BRCMS_N_PROTECTION_MIXEDMODE 3
  156. /* values for band specific 40MHz capabilities */
  157. #define BRCMS_N_BW_20ALL 0
  158. #define BRCMS_N_BW_40ALL 1
  159. #define BRCMS_N_BW_20IN2G_40IN5G 2
  160. /* bitflags for SGI support (sgi_rx iovar) */
  161. #define BRCMS_N_SGI_20 0x01
  162. #define BRCMS_N_SGI_40 0x02
  163. /* defines used by the nrate iovar */
  164. /* MSC in use,indicates b0-6 holds an mcs */
  165. #define NRATE_MCS_INUSE 0x00000080
  166. /* rate/mcs value */
  167. #define NRATE_RATE_MASK 0x0000007f
  168. /* stf mode mask: siso, cdd, stbc, sdm */
  169. #define NRATE_STF_MASK 0x0000ff00
  170. /* stf mode shift */
  171. #define NRATE_STF_SHIFT 8
  172. /* bit indicate to override mcs only */
  173. #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
  174. #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
  175. #define NRATE_SGI_SHIFT 23 /* sgi mode */
  176. #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
  177. #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
  178. #define NRATE_STF_SISO 0 /* stf mode SISO */
  179. #define NRATE_STF_CDD 1 /* stf mode CDD */
  180. #define NRATE_STF_STBC 2 /* stf mode STBC */
  181. #define NRATE_STF_SDM 3 /* stf mode SDM */
  182. #define MAX_DMA_SEGS 4
  183. /* # of entries in Tx FIFO */
  184. #define NTXD 64
  185. /* Max # of entries in Rx FIFO based on 4kb page size */
  186. #define NRXD 256
  187. /* Amount of headroom to leave in Tx FIFO */
  188. #define TX_HEADROOM 4
  189. /* try to keep this # rbufs posted to the chip */
  190. #define NRXBUFPOST 32
  191. /* max # frames to process in brcms_c_recv() */
  192. #define RXBND 8
  193. /* max # tx status to process in wlc_txstatus() */
  194. #define TXSBND 8
  195. /* brcmu_format_flags() bit description structure */
  196. struct brcms_c_bit_desc {
  197. u32 bit;
  198. const char *name;
  199. };
  200. /*
  201. * The following table lists the buffer memory allocated to xmt fifos in HW.
  202. * the size is in units of 256bytes(one block), total size is HW dependent
  203. * ucode has default fifo partition, sw can overwrite if necessary
  204. *
  205. * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  206. * the twiki is updated before making changes.
  207. */
  208. /* Starting corerev for the fifo size table */
  209. #define XMTFIFOTBL_STARTREV 17
  210. struct d11init {
  211. __le16 addr;
  212. __le16 size;
  213. __le32 value;
  214. };
  215. struct edcf_acparam {
  216. u8 ACI;
  217. u8 ECW;
  218. u16 TXOP;
  219. } __packed;
  220. /* debug/trace */
  221. uint brcm_msg_level;
  222. /* TX FIFO number to WME/802.1E Access Category */
  223. static const u8 wme_fifo2ac[] = {
  224. IEEE80211_AC_BK,
  225. IEEE80211_AC_BE,
  226. IEEE80211_AC_VI,
  227. IEEE80211_AC_VO,
  228. IEEE80211_AC_BE,
  229. IEEE80211_AC_BE
  230. };
  231. /* ieee80211 Access Category to TX FIFO number */
  232. static const u8 wme_ac2fifo[] = {
  233. TX_AC_VO_FIFO,
  234. TX_AC_VI_FIFO,
  235. TX_AC_BE_FIFO,
  236. TX_AC_BK_FIFO
  237. };
  238. static const u16 xmtfifo_sz[][NFIFO] = {
  239. /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
  240. {20, 192, 192, 21, 17, 5},
  241. /* corerev 18: */
  242. {0, 0, 0, 0, 0, 0},
  243. /* corerev 19: */
  244. {0, 0, 0, 0, 0, 0},
  245. /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  246. {20, 192, 192, 21, 17, 5},
  247. /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  248. {9, 58, 22, 14, 14, 5},
  249. /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  250. {20, 192, 192, 21, 17, 5},
  251. /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  252. {20, 192, 192, 21, 17, 5},
  253. /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  254. {9, 58, 22, 14, 14, 5},
  255. /* corerev 25: */
  256. {0, 0, 0, 0, 0, 0},
  257. /* corerev 26: */
  258. {0, 0, 0, 0, 0, 0},
  259. /* corerev 27: */
  260. {0, 0, 0, 0, 0, 0},
  261. /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
  262. {9, 58, 22, 14, 14, 5},
  263. };
  264. #ifdef DEBUG
  265. static const char * const fifo_names[] = {
  266. "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
  267. #else
  268. static const char fifo_names[6][0];
  269. #endif
  270. #ifdef DEBUG
  271. /* pointer to most recently allocated wl/wlc */
  272. static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
  273. #endif
  274. /* Mapping of ieee80211 AC numbers to tx fifos */
  275. static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
  276. [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
  277. [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
  278. [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
  279. [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
  280. };
  281. /* Mapping of tx fifos to ieee80211 AC numbers */
  282. static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
  283. [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
  284. [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
  285. [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
  286. [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
  287. };
  288. static u8 brcms_ac_to_fifo(u8 ac)
  289. {
  290. if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
  291. return TX_AC_BE_FIFO;
  292. return ac_to_fifo_mapping[ac];
  293. }
  294. static u8 brcms_fifo_to_ac(u8 fifo)
  295. {
  296. if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
  297. return IEEE80211_AC_BE;
  298. return fifo_to_ac_mapping[fifo];
  299. }
  300. /* Find basic rate for a given rate */
  301. static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
  302. {
  303. if (is_mcs_rate(rspec))
  304. return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
  305. .leg_ofdm];
  306. return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
  307. }
  308. static u16 frametype(u32 rspec, u8 mimoframe)
  309. {
  310. if (is_mcs_rate(rspec))
  311. return mimoframe;
  312. return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
  313. }
  314. /* currently the best mechanism for determining SIFS is the band in use */
  315. static u16 get_sifs(struct brcms_band *band)
  316. {
  317. return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
  318. BPHY_SIFS_TIME;
  319. }
  320. /*
  321. * Detect Card removed.
  322. * Even checking an sbconfig register read will not false trigger when the core
  323. * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
  324. * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
  325. * reg with fixed 0/1 pattern (some platforms return all 0).
  326. * If clocks are present, call the sb routine which will figure out if the
  327. * device is removed.
  328. */
  329. static bool brcms_deviceremoved(struct brcms_c_info *wlc)
  330. {
  331. u32 macctrl;
  332. if (!wlc->hw->clk)
  333. return ai_deviceremoved(wlc->hw->sih);
  334. macctrl = bcma_read32(wlc->hw->d11core,
  335. D11REGOFFS(maccontrol));
  336. return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
  337. }
  338. /* sum the individual fifo tx pending packet counts */
  339. static int brcms_txpktpendtot(struct brcms_c_info *wlc)
  340. {
  341. int i;
  342. int pending = 0;
  343. for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
  344. if (wlc->hw->di[i])
  345. pending += dma_txpending(wlc->hw->di[i]);
  346. return pending;
  347. }
  348. static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
  349. {
  350. return wlc->pub->_nbands > 1 && !wlc->bandlocked;
  351. }
  352. static int brcms_chspec_bw(u16 chanspec)
  353. {
  354. if (CHSPEC_IS40(chanspec))
  355. return BRCMS_40_MHZ;
  356. if (CHSPEC_IS20(chanspec))
  357. return BRCMS_20_MHZ;
  358. return BRCMS_10_MHZ;
  359. }
  360. static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
  361. {
  362. if (cfg == NULL)
  363. return;
  364. kfree(cfg->current_bss);
  365. kfree(cfg);
  366. }
  367. static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
  368. {
  369. if (wlc == NULL)
  370. return;
  371. brcms_c_bsscfg_mfree(wlc->bsscfg);
  372. kfree(wlc->pub);
  373. kfree(wlc->modulecb);
  374. kfree(wlc->default_bss);
  375. kfree(wlc->protection);
  376. kfree(wlc->stf);
  377. kfree(wlc->bandstate[0]);
  378. kfree(wlc->corestate->macstat_snapshot);
  379. kfree(wlc->corestate);
  380. kfree(wlc->hw->bandstate[0]);
  381. kfree(wlc->hw);
  382. /* free the wlc */
  383. kfree(wlc);
  384. wlc = NULL;
  385. }
  386. static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
  387. {
  388. struct brcms_bss_cfg *cfg;
  389. cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
  390. if (cfg == NULL)
  391. goto fail;
  392. cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  393. if (cfg->current_bss == NULL)
  394. goto fail;
  395. return cfg;
  396. fail:
  397. brcms_c_bsscfg_mfree(cfg);
  398. return NULL;
  399. }
  400. static struct brcms_c_info *
  401. brcms_c_attach_malloc(uint unit, uint *err, uint devid)
  402. {
  403. struct brcms_c_info *wlc;
  404. wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
  405. if (wlc == NULL) {
  406. *err = 1002;
  407. goto fail;
  408. }
  409. /* allocate struct brcms_c_pub state structure */
  410. wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
  411. if (wlc->pub == NULL) {
  412. *err = 1003;
  413. goto fail;
  414. }
  415. wlc->pub->wlc = wlc;
  416. /* allocate struct brcms_hardware state structure */
  417. wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
  418. if (wlc->hw == NULL) {
  419. *err = 1005;
  420. goto fail;
  421. }
  422. wlc->hw->wlc = wlc;
  423. wlc->hw->bandstate[0] =
  424. kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
  425. if (wlc->hw->bandstate[0] == NULL) {
  426. *err = 1006;
  427. goto fail;
  428. } else {
  429. int i;
  430. for (i = 1; i < MAXBANDS; i++)
  431. wlc->hw->bandstate[i] = (struct brcms_hw_band *)
  432. ((unsigned long)wlc->hw->bandstate[0] +
  433. (sizeof(struct brcms_hw_band) * i));
  434. }
  435. wlc->modulecb =
  436. kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
  437. if (wlc->modulecb == NULL) {
  438. *err = 1009;
  439. goto fail;
  440. }
  441. wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  442. if (wlc->default_bss == NULL) {
  443. *err = 1010;
  444. goto fail;
  445. }
  446. wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
  447. if (wlc->bsscfg == NULL) {
  448. *err = 1011;
  449. goto fail;
  450. }
  451. wlc->protection = kzalloc(sizeof(struct brcms_protection),
  452. GFP_ATOMIC);
  453. if (wlc->protection == NULL) {
  454. *err = 1016;
  455. goto fail;
  456. }
  457. wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
  458. if (wlc->stf == NULL) {
  459. *err = 1017;
  460. goto fail;
  461. }
  462. wlc->bandstate[0] =
  463. kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
  464. if (wlc->bandstate[0] == NULL) {
  465. *err = 1025;
  466. goto fail;
  467. } else {
  468. int i;
  469. for (i = 1; i < MAXBANDS; i++)
  470. wlc->bandstate[i] = (struct brcms_band *)
  471. ((unsigned long)wlc->bandstate[0]
  472. + (sizeof(struct brcms_band)*i));
  473. }
  474. wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
  475. if (wlc->corestate == NULL) {
  476. *err = 1026;
  477. goto fail;
  478. }
  479. wlc->corestate->macstat_snapshot =
  480. kzalloc(sizeof(struct macstat), GFP_ATOMIC);
  481. if (wlc->corestate->macstat_snapshot == NULL) {
  482. *err = 1027;
  483. goto fail;
  484. }
  485. return wlc;
  486. fail:
  487. brcms_c_detach_mfree(wlc);
  488. return NULL;
  489. }
  490. /*
  491. * Update the slot timing for standard 11b/g (20us slots)
  492. * or shortslot 11g (9us slots)
  493. * The PSM needs to be suspended for this call.
  494. */
  495. static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
  496. bool shortslot)
  497. {
  498. struct bcma_device *core = wlc_hw->d11core;
  499. if (shortslot) {
  500. /* 11g short slot: 11a timing */
  501. bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
  502. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
  503. } else {
  504. /* 11g long slot: 11b timing */
  505. bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
  506. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
  507. }
  508. }
  509. /*
  510. * calculate frame duration of a given rate and length, return
  511. * time in usec unit
  512. */
  513. static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
  514. u8 preamble_type, uint mac_len)
  515. {
  516. uint nsyms, dur = 0, Ndps, kNdps;
  517. uint rate = rspec2rate(ratespec);
  518. if (rate == 0) {
  519. brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
  520. wlc->pub->unit);
  521. rate = BRCM_RATE_1M;
  522. }
  523. if (is_mcs_rate(ratespec)) {
  524. uint mcs = ratespec & RSPEC_RATE_MASK;
  525. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  526. dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  527. if (preamble_type == BRCMS_MM_PREAMBLE)
  528. dur += PREN_MM_EXT;
  529. /* 1000Ndbps = kbps * 4 */
  530. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  531. rspec_issgi(ratespec)) * 4;
  532. if (rspec_stc(ratespec) == 0)
  533. nsyms =
  534. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  535. APHY_TAIL_NBITS) * 1000, kNdps);
  536. else
  537. /* STBC needs to have even number of symbols */
  538. nsyms =
  539. 2 *
  540. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  541. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  542. dur += APHY_SYMBOL_TIME * nsyms;
  543. if (wlc->band->bandtype == BRCM_BAND_2G)
  544. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  545. } else if (is_ofdm_rate(rate)) {
  546. dur = APHY_PREAMBLE_TIME;
  547. dur += APHY_SIGNAL_TIME;
  548. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  549. Ndps = rate * 2;
  550. /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
  551. nsyms =
  552. CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
  553. Ndps);
  554. dur += APHY_SYMBOL_TIME * nsyms;
  555. if (wlc->band->bandtype == BRCM_BAND_2G)
  556. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  557. } else {
  558. /*
  559. * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
  560. * will divide out
  561. */
  562. mac_len = mac_len * 8 * 2;
  563. /* calc ceiling of bits/rate = microseconds of air time */
  564. dur = (mac_len + rate - 1) / rate;
  565. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  566. dur += BPHY_PLCP_SHORT_TIME;
  567. else
  568. dur += BPHY_PLCP_TIME;
  569. }
  570. return dur;
  571. }
  572. static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
  573. const struct d11init *inits)
  574. {
  575. struct bcma_device *core = wlc_hw->d11core;
  576. int i;
  577. uint offset;
  578. u16 size;
  579. u32 value;
  580. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  581. for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
  582. size = le16_to_cpu(inits[i].size);
  583. offset = le16_to_cpu(inits[i].addr);
  584. value = le32_to_cpu(inits[i].value);
  585. if (size == 2)
  586. bcma_write16(core, offset, value);
  587. else if (size == 4)
  588. bcma_write32(core, offset, value);
  589. else
  590. break;
  591. }
  592. }
  593. static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
  594. {
  595. u8 idx;
  596. u16 addr[] = {
  597. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  598. M_HOST_FLAGS5
  599. };
  600. for (idx = 0; idx < MHFMAX; idx++)
  601. brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
  602. }
  603. static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
  604. {
  605. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  606. /* init microcode host flags */
  607. brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
  608. /* do band-specific ucode IHR, SHM, and SCR inits */
  609. if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
  610. if (BRCMS_ISNPHY(wlc_hw->band))
  611. brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
  612. else
  613. brcms_err(wlc_hw->d11core,
  614. "%s: wl%d: unsupported phy in corerev %d\n",
  615. __func__, wlc_hw->unit,
  616. wlc_hw->corerev);
  617. } else {
  618. if (D11REV_IS(wlc_hw->corerev, 24)) {
  619. if (BRCMS_ISLCNPHY(wlc_hw->band))
  620. brcms_c_write_inits(wlc_hw,
  621. ucode->d11lcn0bsinitvals24);
  622. else
  623. brcms_err(wlc_hw->d11core,
  624. "%s: wl%d: unsupported phy in core rev %d\n",
  625. __func__, wlc_hw->unit,
  626. wlc_hw->corerev);
  627. } else {
  628. brcms_err(wlc_hw->d11core,
  629. "%s: wl%d: unsupported corerev %d\n",
  630. __func__, wlc_hw->unit, wlc_hw->corerev);
  631. }
  632. }
  633. }
  634. static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
  635. {
  636. struct bcma_device *core = wlc_hw->d11core;
  637. u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
  638. bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
  639. }
  640. static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
  641. {
  642. brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
  643. wlc_hw->phyclk = clk;
  644. if (OFF == clk) { /* clear gmode bit, put phy into reset */
  645. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
  646. (SICF_PRST | SICF_FGC));
  647. udelay(1);
  648. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
  649. udelay(1);
  650. } else { /* take phy out of reset */
  651. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
  652. udelay(1);
  653. brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
  654. udelay(1);
  655. }
  656. }
  657. /* low-level band switch utility routine */
  658. static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
  659. {
  660. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
  661. bandunit);
  662. wlc_hw->band = wlc_hw->bandstate[bandunit];
  663. /*
  664. * BMAC_NOTE:
  665. * until we eliminate need for wlc->band refs in low level code
  666. */
  667. wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
  668. /* set gmode core flag */
  669. if (wlc_hw->sbclk && !wlc_hw->noreset) {
  670. u32 gmode = 0;
  671. if (bandunit == 0)
  672. gmode = SICF_GMODE;
  673. brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
  674. }
  675. }
  676. /* switch to new band but leave it inactive */
  677. static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
  678. {
  679. struct brcms_hardware *wlc_hw = wlc->hw;
  680. u32 macintmask;
  681. u32 macctrl;
  682. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  683. macctrl = bcma_read32(wlc_hw->d11core,
  684. D11REGOFFS(maccontrol));
  685. WARN_ON((macctrl & MCTL_EN_MAC) != 0);
  686. /* disable interrupts */
  687. macintmask = brcms_intrsoff(wlc->wl);
  688. /* radio off */
  689. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  690. brcms_b_core_phy_clk(wlc_hw, OFF);
  691. brcms_c_setxband(wlc_hw, bandunit);
  692. return macintmask;
  693. }
  694. /* process an individual struct tx_status */
  695. static bool
  696. brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
  697. {
  698. struct sk_buff *p = NULL;
  699. uint queue = NFIFO;
  700. struct dma_pub *dma = NULL;
  701. struct d11txh *txh = NULL;
  702. struct scb *scb = NULL;
  703. bool free_pdu;
  704. int tx_rts, tx_frame_count, tx_rts_count;
  705. uint totlen, supr_status;
  706. bool lastframe;
  707. struct ieee80211_hdr *h;
  708. u16 mcl;
  709. struct ieee80211_tx_info *tx_info;
  710. struct ieee80211_tx_rate *txrate;
  711. int i;
  712. bool fatal = true;
  713. trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
  714. txs->frameid, txs->status, txs->lasttxtime,
  715. txs->sequence, txs->phyerr, txs->ackphyrxsh);
  716. /* discard intermediate indications for ucode with one legitimate case:
  717. * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
  718. * but the subsequent tx of DATA failed. so it will start rts/cts
  719. * from the beginning (resetting the rts transmission count)
  720. */
  721. if (!(txs->status & TX_STATUS_AMPDU)
  722. && (txs->status & TX_STATUS_INTERMEDIATE)) {
  723. brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
  724. fatal = false;
  725. goto out;
  726. }
  727. queue = txs->frameid & TXFID_QUEUE_MASK;
  728. if (queue >= NFIFO) {
  729. brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
  730. goto out;
  731. }
  732. dma = wlc->hw->di[queue];
  733. p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
  734. if (p == NULL) {
  735. brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
  736. goto out;
  737. }
  738. txh = (struct d11txh *) (p->data);
  739. mcl = le16_to_cpu(txh->MacTxControlLow);
  740. if (txs->phyerr)
  741. brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
  742. txs->phyerr, txh->MainRates);
  743. if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
  744. brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
  745. goto out;
  746. }
  747. tx_info = IEEE80211_SKB_CB(p);
  748. h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
  749. if (tx_info->rate_driver_data[0])
  750. scb = &wlc->pri_scb;
  751. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  752. brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
  753. fatal = false;
  754. goto out;
  755. }
  756. /*
  757. * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
  758. * frames; this traces them for the rest.
  759. */
  760. trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
  761. supr_status = txs->status & TX_STATUS_SUPR_MASK;
  762. if (supr_status == TX_STATUS_SUPR_BADCH) {
  763. unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
  764. brcms_dbg_tx(wlc->hw->d11core,
  765. "Pkt tx suppressed, dest chan %u, current %d\n",
  766. (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
  767. CHSPEC_CHANNEL(wlc->default_bss->chanspec));
  768. }
  769. tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
  770. tx_frame_count =
  771. (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
  772. tx_rts_count =
  773. (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
  774. lastframe = !ieee80211_has_morefrags(h->frame_control);
  775. if (!lastframe) {
  776. brcms_err(wlc->hw->d11core, "Not last frame!\n");
  777. } else {
  778. /*
  779. * Set information to be consumed by Minstrel ht.
  780. *
  781. * The "fallback limit" is the number of tx attempts a given
  782. * MPDU is sent at the "primary" rate. Tx attempts beyond that
  783. * limit are sent at the "secondary" rate.
  784. * A 'short frame' does not exceed RTS treshold.
  785. */
  786. u16 sfbl, /* Short Frame Rate Fallback Limit */
  787. lfbl, /* Long Frame Rate Fallback Limit */
  788. fbl;
  789. if (queue < IEEE80211_NUM_ACS) {
  790. sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  791. EDCF_SFB);
  792. lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  793. EDCF_LFB);
  794. } else {
  795. sfbl = wlc->SFBL;
  796. lfbl = wlc->LFBL;
  797. }
  798. txrate = tx_info->status.rates;
  799. if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
  800. fbl = lfbl;
  801. else
  802. fbl = sfbl;
  803. ieee80211_tx_info_clear_status(tx_info);
  804. if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
  805. /*
  806. * rate selection requested a fallback rate
  807. * and we used it
  808. */
  809. txrate[0].count = fbl;
  810. txrate[1].count = tx_frame_count - fbl;
  811. } else {
  812. /*
  813. * rate selection did not request fallback rate, or
  814. * we didn't need it
  815. */
  816. txrate[0].count = tx_frame_count;
  817. /*
  818. * rc80211_minstrel.c:minstrel_tx_status() expects
  819. * unused rates to be marked with idx = -1
  820. */
  821. txrate[1].idx = -1;
  822. txrate[1].count = 0;
  823. }
  824. /* clear the rest of the rates */
  825. for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
  826. txrate[i].idx = -1;
  827. txrate[i].count = 0;
  828. }
  829. if (txs->status & TX_STATUS_ACK_RCV)
  830. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  831. }
  832. totlen = p->len;
  833. free_pdu = true;
  834. if (lastframe) {
  835. /* remove PLCP & Broadcom tx descriptor header */
  836. skb_pull(p, D11_PHY_HDR_LEN);
  837. skb_pull(p, D11_TXH_LEN);
  838. ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
  839. } else {
  840. brcms_err(wlc->hw->d11core,
  841. "%s: Not last frame => not calling tx_status\n",
  842. __func__);
  843. }
  844. fatal = false;
  845. out:
  846. if (fatal) {
  847. if (txh)
  848. trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
  849. sizeof(*txh));
  850. if (p)
  851. brcmu_pkt_buf_free_skb(p);
  852. }
  853. if (dma && queue < NFIFO) {
  854. u16 ac_queue = brcms_fifo_to_ac(queue);
  855. if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
  856. ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
  857. ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
  858. dma_kick_tx(dma);
  859. }
  860. return fatal;
  861. }
  862. /* process tx completion events in BMAC
  863. * Return true if more tx status need to be processed. false otherwise.
  864. */
  865. static bool
  866. brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
  867. {
  868. struct bcma_device *core;
  869. struct tx_status txstatus, *txs;
  870. u32 s1, s2;
  871. uint n = 0;
  872. /*
  873. * Param 'max_tx_num' indicates max. # tx status to process before
  874. * break out.
  875. */
  876. uint max_tx_num = bound ? TXSBND : -1;
  877. txs = &txstatus;
  878. core = wlc_hw->d11core;
  879. *fatal = false;
  880. while (n < max_tx_num) {
  881. s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
  882. if (s1 == 0xffffffff) {
  883. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  884. __func__);
  885. *fatal = true;
  886. return false;
  887. }
  888. /* only process when valid */
  889. if (!(s1 & TXS_V))
  890. break;
  891. s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
  892. txs->status = s1 & TXS_STATUS_MASK;
  893. txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
  894. txs->sequence = s2 & TXS_SEQ_MASK;
  895. txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
  896. txs->lasttxtime = 0;
  897. *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
  898. if (*fatal == true)
  899. return false;
  900. n++;
  901. }
  902. return n >= max_tx_num;
  903. }
  904. static void brcms_c_tbtt(struct brcms_c_info *wlc)
  905. {
  906. if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
  907. /*
  908. * DirFrmQ is now valid...defer setting until end
  909. * of ATIM window
  910. */
  911. wlc->qvalid |= MCMD_DIRFRMQVAL;
  912. }
  913. /* set initial host flags value */
  914. static void
  915. brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
  916. {
  917. struct brcms_hardware *wlc_hw = wlc->hw;
  918. memset(mhfs, 0, MHFMAX * sizeof(u16));
  919. mhfs[MHF2] |= mhf2_init;
  920. /* prohibit use of slowclock on multifunction boards */
  921. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  922. mhfs[MHF1] |= MHF1_FORCEFASTCLK;
  923. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
  924. mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
  925. mhfs[MHF1] |= MHF1_IQSWAP_WAR;
  926. }
  927. }
  928. static uint
  929. dmareg(uint direction, uint fifonum)
  930. {
  931. if (direction == DMA_TX)
  932. return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
  933. return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
  934. }
  935. static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
  936. {
  937. uint i;
  938. char name[8];
  939. /*
  940. * ucode host flag 2 needed for pio mode, independent of band and fifo
  941. */
  942. u16 pio_mhf2 = 0;
  943. struct brcms_hardware *wlc_hw = wlc->hw;
  944. uint unit = wlc_hw->unit;
  945. /* name and offsets for dma_attach */
  946. snprintf(name, sizeof(name), "wl%d", unit);
  947. if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
  948. int dma_attach_err = 0;
  949. /*
  950. * FIFO 0
  951. * TX: TX_AC_BK_FIFO (TX AC Background data packets)
  952. * RX: RX_FIFO (RX data packets)
  953. */
  954. wlc_hw->di[0] = dma_attach(name, wlc,
  955. (wme ? dmareg(DMA_TX, 0) : 0),
  956. dmareg(DMA_RX, 0),
  957. (wme ? NTXD : 0), NRXD,
  958. RXBUFSZ, -1, NRXBUFPOST,
  959. BRCMS_HWRXOFF);
  960. dma_attach_err |= (NULL == wlc_hw->di[0]);
  961. /*
  962. * FIFO 1
  963. * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
  964. * (legacy) TX_DATA_FIFO (TX data packets)
  965. * RX: UNUSED
  966. */
  967. wlc_hw->di[1] = dma_attach(name, wlc,
  968. dmareg(DMA_TX, 1), 0,
  969. NTXD, 0, 0, -1, 0, 0);
  970. dma_attach_err |= (NULL == wlc_hw->di[1]);
  971. /*
  972. * FIFO 2
  973. * TX: TX_AC_VI_FIFO (TX AC Video data packets)
  974. * RX: UNUSED
  975. */
  976. wlc_hw->di[2] = dma_attach(name, wlc,
  977. dmareg(DMA_TX, 2), 0,
  978. NTXD, 0, 0, -1, 0, 0);
  979. dma_attach_err |= (NULL == wlc_hw->di[2]);
  980. /*
  981. * FIFO 3
  982. * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
  983. * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
  984. */
  985. wlc_hw->di[3] = dma_attach(name, wlc,
  986. dmareg(DMA_TX, 3),
  987. 0, NTXD, 0, 0, -1,
  988. 0, 0);
  989. dma_attach_err |= (NULL == wlc_hw->di[3]);
  990. /* Cleaner to leave this as if with AP defined */
  991. if (dma_attach_err) {
  992. brcms_err(wlc_hw->d11core,
  993. "wl%d: wlc_attach: dma_attach failed\n",
  994. unit);
  995. return false;
  996. }
  997. /* get pointer to dma engine tx flow control variable */
  998. for (i = 0; i < NFIFO; i++)
  999. if (wlc_hw->di[i])
  1000. wlc_hw->txavail[i] =
  1001. (uint *) dma_getvar(wlc_hw->di[i],
  1002. "&txavail");
  1003. }
  1004. /* initial ucode host flags */
  1005. brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
  1006. return true;
  1007. }
  1008. static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
  1009. {
  1010. uint j;
  1011. for (j = 0; j < NFIFO; j++) {
  1012. if (wlc_hw->di[j]) {
  1013. dma_detach(wlc_hw->di[j]);
  1014. wlc_hw->di[j] = NULL;
  1015. }
  1016. }
  1017. }
  1018. /*
  1019. * Initialize brcms_c_info default values ...
  1020. * may get overrides later in this function
  1021. * BMAC_NOTES, move low out and resolve the dangling ones
  1022. */
  1023. static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
  1024. {
  1025. struct brcms_c_info *wlc = wlc_hw->wlc;
  1026. /* set default sw macintmask value */
  1027. wlc->defmacintmask = DEF_MACINTMASK;
  1028. /* various 802.11g modes */
  1029. wlc_hw->shortslot = false;
  1030. wlc_hw->SFBL = RETRY_SHORT_FB;
  1031. wlc_hw->LFBL = RETRY_LONG_FB;
  1032. /* default mac retry limits */
  1033. wlc_hw->SRL = RETRY_SHORT_DEF;
  1034. wlc_hw->LRL = RETRY_LONG_DEF;
  1035. wlc_hw->chanspec = ch20mhz_chspec(1);
  1036. }
  1037. static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
  1038. {
  1039. /* delay before first read of ucode state */
  1040. udelay(40);
  1041. /* wait until ucode is no longer asleep */
  1042. SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
  1043. DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
  1044. }
  1045. /* control chip clock to save power, enable dynamic clock or force fast clock */
  1046. static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
  1047. {
  1048. if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
  1049. /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
  1050. * on backplane, but mac core will still run on ALP(not HT) when
  1051. * it enters powersave mode, which means the FCA bit may not be
  1052. * set. Should wakeup mac if driver wants it to run on HT.
  1053. */
  1054. if (wlc_hw->clk) {
  1055. if (mode == BCMA_CLKMODE_FAST) {
  1056. bcma_set32(wlc_hw->d11core,
  1057. D11REGOFFS(clk_ctl_st),
  1058. CCS_FORCEHT);
  1059. udelay(64);
  1060. SPINWAIT(
  1061. ((bcma_read32(wlc_hw->d11core,
  1062. D11REGOFFS(clk_ctl_st)) &
  1063. CCS_HTAVAIL) == 0),
  1064. PMU_MAX_TRANSITION_DLY);
  1065. WARN_ON(!(bcma_read32(wlc_hw->d11core,
  1066. D11REGOFFS(clk_ctl_st)) &
  1067. CCS_HTAVAIL));
  1068. } else {
  1069. if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
  1070. (bcma_read32(wlc_hw->d11core,
  1071. D11REGOFFS(clk_ctl_st)) &
  1072. (CCS_FORCEHT | CCS_HTAREQ)))
  1073. SPINWAIT(
  1074. ((bcma_read32(wlc_hw->d11core,
  1075. offsetof(struct d11regs,
  1076. clk_ctl_st)) &
  1077. CCS_HTAVAIL) == 0),
  1078. PMU_MAX_TRANSITION_DLY);
  1079. bcma_mask32(wlc_hw->d11core,
  1080. D11REGOFFS(clk_ctl_st),
  1081. ~CCS_FORCEHT);
  1082. }
  1083. }
  1084. wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
  1085. } else {
  1086. /* old chips w/o PMU, force HT through cc,
  1087. * then use FCA to verify mac is running fast clock
  1088. */
  1089. wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
  1090. /* check fast clock is available (if core is not in reset) */
  1091. if (wlc_hw->forcefastclk && wlc_hw->clk)
  1092. WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
  1093. SISF_FCLKA));
  1094. /*
  1095. * keep the ucode wake bit on if forcefastclk is on since we
  1096. * do not want ucode to put us back to slow clock when it dozes
  1097. * for PM mode. Code below matches the wake override bit with
  1098. * current forcefastclk state. Only setting bit in wake_override
  1099. * instead of waking ucode immediately since old code had this
  1100. * behavior. Older code set wlc->forcefastclk but only had the
  1101. * wake happen if the wakup_ucode work (protected by an up
  1102. * check) was executed just below.
  1103. */
  1104. if (wlc_hw->forcefastclk)
  1105. mboolset(wlc_hw->wake_override,
  1106. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1107. else
  1108. mboolclr(wlc_hw->wake_override,
  1109. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1110. }
  1111. }
  1112. /* set or clear ucode host flag bits
  1113. * it has an optimization for no-change write
  1114. * it only writes through shared memory when the core has clock;
  1115. * pre-CLK changes should use wlc_write_mhf to get around the optimization
  1116. *
  1117. *
  1118. * bands values are: BRCM_BAND_AUTO <--- Current band only
  1119. * BRCM_BAND_5G <--- 5G band only
  1120. * BRCM_BAND_2G <--- 2G band only
  1121. * BRCM_BAND_ALL <--- All bands
  1122. */
  1123. void
  1124. brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
  1125. int bands)
  1126. {
  1127. u16 save;
  1128. u16 addr[MHFMAX] = {
  1129. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  1130. M_HOST_FLAGS5
  1131. };
  1132. struct brcms_hw_band *band;
  1133. if ((val & ~mask) || idx >= MHFMAX)
  1134. return; /* error condition */
  1135. switch (bands) {
  1136. /* Current band only or all bands,
  1137. * then set the band to current band
  1138. */
  1139. case BRCM_BAND_AUTO:
  1140. case BRCM_BAND_ALL:
  1141. band = wlc_hw->band;
  1142. break;
  1143. case BRCM_BAND_5G:
  1144. band = wlc_hw->bandstate[BAND_5G_INDEX];
  1145. break;
  1146. case BRCM_BAND_2G:
  1147. band = wlc_hw->bandstate[BAND_2G_INDEX];
  1148. break;
  1149. default:
  1150. band = NULL; /* error condition */
  1151. }
  1152. if (band) {
  1153. save = band->mhfs[idx];
  1154. band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
  1155. /* optimization: only write through if changed, and
  1156. * changed band is the current band
  1157. */
  1158. if (wlc_hw->clk && (band->mhfs[idx] != save)
  1159. && (band == wlc_hw->band))
  1160. brcms_b_write_shm(wlc_hw, addr[idx],
  1161. (u16) band->mhfs[idx]);
  1162. }
  1163. if (bands == BRCM_BAND_ALL) {
  1164. wlc_hw->bandstate[0]->mhfs[idx] =
  1165. (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
  1166. wlc_hw->bandstate[1]->mhfs[idx] =
  1167. (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
  1168. }
  1169. }
  1170. /* set the maccontrol register to desired reset state and
  1171. * initialize the sw cache of the register
  1172. */
  1173. static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
  1174. {
  1175. /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
  1176. wlc_hw->maccontrol = 0;
  1177. wlc_hw->suspended_fifos = 0;
  1178. wlc_hw->wake_override = 0;
  1179. wlc_hw->mute_override = 0;
  1180. brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
  1181. }
  1182. /*
  1183. * write the software state of maccontrol and
  1184. * overrides to the maccontrol register
  1185. */
  1186. static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
  1187. {
  1188. u32 maccontrol = wlc_hw->maccontrol;
  1189. /* OR in the wake bit if overridden */
  1190. if (wlc_hw->wake_override)
  1191. maccontrol |= MCTL_WAKE;
  1192. /* set AP and INFRA bits for mute if needed */
  1193. if (wlc_hw->mute_override) {
  1194. maccontrol &= ~(MCTL_AP);
  1195. maccontrol |= MCTL_INFRA;
  1196. }
  1197. bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
  1198. maccontrol);
  1199. }
  1200. /* set or clear maccontrol bits */
  1201. void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
  1202. {
  1203. u32 maccontrol;
  1204. u32 new_maccontrol;
  1205. if (val & ~mask)
  1206. return; /* error condition */
  1207. maccontrol = wlc_hw->maccontrol;
  1208. new_maccontrol = (maccontrol & ~mask) | val;
  1209. /* if the new maccontrol value is the same as the old, nothing to do */
  1210. if (new_maccontrol == maccontrol)
  1211. return;
  1212. /* something changed, cache the new value */
  1213. wlc_hw->maccontrol = new_maccontrol;
  1214. /* write the new values with overrides applied */
  1215. brcms_c_mctrl_write(wlc_hw);
  1216. }
  1217. void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
  1218. u32 override_bit)
  1219. {
  1220. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
  1221. mboolset(wlc_hw->wake_override, override_bit);
  1222. return;
  1223. }
  1224. mboolset(wlc_hw->wake_override, override_bit);
  1225. brcms_c_mctrl_write(wlc_hw);
  1226. brcms_b_wait_for_wake(wlc_hw);
  1227. }
  1228. void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
  1229. u32 override_bit)
  1230. {
  1231. mboolclr(wlc_hw->wake_override, override_bit);
  1232. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
  1233. return;
  1234. brcms_c_mctrl_write(wlc_hw);
  1235. }
  1236. /* When driver needs ucode to stop beaconing, it has to make sure that
  1237. * MCTL_AP is clear and MCTL_INFRA is set
  1238. * Mode MCTL_AP MCTL_INFRA
  1239. * AP 1 1
  1240. * STA 0 1 <--- This will ensure no beacons
  1241. * IBSS 0 0
  1242. */
  1243. static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
  1244. {
  1245. wlc_hw->mute_override = 1;
  1246. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1247. * override, then there is no change to write
  1248. */
  1249. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1250. return;
  1251. brcms_c_mctrl_write(wlc_hw);
  1252. }
  1253. /* Clear the override on AP and INFRA bits */
  1254. static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
  1255. {
  1256. if (wlc_hw->mute_override == 0)
  1257. return;
  1258. wlc_hw->mute_override = 0;
  1259. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1260. * override, then there is no change to write
  1261. */
  1262. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1263. return;
  1264. brcms_c_mctrl_write(wlc_hw);
  1265. }
  1266. /*
  1267. * Write a MAC address to the given match reg offset in the RXE match engine.
  1268. */
  1269. static void
  1270. brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
  1271. const u8 *addr)
  1272. {
  1273. struct bcma_device *core = wlc_hw->d11core;
  1274. u16 mac_l;
  1275. u16 mac_m;
  1276. u16 mac_h;
  1277. brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
  1278. mac_l = addr[0] | (addr[1] << 8);
  1279. mac_m = addr[2] | (addr[3] << 8);
  1280. mac_h = addr[4] | (addr[5] << 8);
  1281. /* enter the MAC addr into the RXE match registers */
  1282. bcma_write16(core, D11REGOFFS(rcm_ctl),
  1283. RCM_INC_DATA | match_reg_offset);
  1284. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
  1285. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
  1286. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
  1287. }
  1288. void
  1289. brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
  1290. void *buf)
  1291. {
  1292. struct bcma_device *core = wlc_hw->d11core;
  1293. u32 word;
  1294. __le32 word_le;
  1295. __be32 word_be;
  1296. bool be_bit;
  1297. brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
  1298. bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
  1299. /* if MCTL_BIGEND bit set in mac control register,
  1300. * the chip swaps data in fifo, as well as data in
  1301. * template ram
  1302. */
  1303. be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
  1304. while (len > 0) {
  1305. memcpy(&word, buf, sizeof(u32));
  1306. if (be_bit) {
  1307. word_be = cpu_to_be32(word);
  1308. word = *(u32 *)&word_be;
  1309. } else {
  1310. word_le = cpu_to_le32(word);
  1311. word = *(u32 *)&word_le;
  1312. }
  1313. bcma_write32(core, D11REGOFFS(tplatewrdata), word);
  1314. buf = (u8 *) buf + sizeof(u32);
  1315. len -= sizeof(u32);
  1316. }
  1317. }
  1318. static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
  1319. {
  1320. wlc_hw->band->CWmin = newmin;
  1321. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  1322. OBJADDR_SCR_SEL | S_DOT11_CWMIN);
  1323. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  1324. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
  1325. }
  1326. static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
  1327. {
  1328. wlc_hw->band->CWmax = newmax;
  1329. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  1330. OBJADDR_SCR_SEL | S_DOT11_CWMAX);
  1331. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  1332. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
  1333. }
  1334. void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
  1335. {
  1336. bool fastclk;
  1337. /* request FAST clock if not on */
  1338. fastclk = wlc_hw->forcefastclk;
  1339. if (!fastclk)
  1340. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  1341. wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
  1342. brcms_b_phy_reset(wlc_hw);
  1343. wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
  1344. /* restore the clk */
  1345. if (!fastclk)
  1346. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  1347. }
  1348. static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
  1349. {
  1350. u16 v;
  1351. struct brcms_c_info *wlc = wlc_hw->wlc;
  1352. /* update SYNTHPU_DLY */
  1353. if (BRCMS_ISLCNPHY(wlc->band))
  1354. v = SYNTHPU_DLY_LPPHY_US;
  1355. else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
  1356. v = SYNTHPU_DLY_NPHY_US;
  1357. else
  1358. v = SYNTHPU_DLY_BPHY_US;
  1359. brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
  1360. }
  1361. static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
  1362. {
  1363. u16 phyctl;
  1364. u16 phytxant = wlc_hw->bmac_phytxant;
  1365. u16 mask = PHY_TXC_ANT_MASK;
  1366. /* set the Probe Response frame phy control word */
  1367. phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
  1368. phyctl = (phyctl & ~mask) | phytxant;
  1369. brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
  1370. /* set the Response (ACK/CTS) frame phy control word */
  1371. phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
  1372. phyctl = (phyctl & ~mask) | phytxant;
  1373. brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
  1374. }
  1375. static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
  1376. u8 rate)
  1377. {
  1378. uint i;
  1379. u8 plcp_rate = 0;
  1380. struct plcp_signal_rate_lookup {
  1381. u8 rate;
  1382. u8 signal_rate;
  1383. };
  1384. /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
  1385. const struct plcp_signal_rate_lookup rate_lookup[] = {
  1386. {BRCM_RATE_6M, 0xB},
  1387. {BRCM_RATE_9M, 0xF},
  1388. {BRCM_RATE_12M, 0xA},
  1389. {BRCM_RATE_18M, 0xE},
  1390. {BRCM_RATE_24M, 0x9},
  1391. {BRCM_RATE_36M, 0xD},
  1392. {BRCM_RATE_48M, 0x8},
  1393. {BRCM_RATE_54M, 0xC}
  1394. };
  1395. for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
  1396. if (rate == rate_lookup[i].rate) {
  1397. plcp_rate = rate_lookup[i].signal_rate;
  1398. break;
  1399. }
  1400. }
  1401. /* Find the SHM pointer to the rate table entry by looking in the
  1402. * Direct-map Table
  1403. */
  1404. return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
  1405. }
  1406. static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
  1407. {
  1408. u8 rate;
  1409. u8 rates[8] = {
  1410. BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
  1411. BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
  1412. };
  1413. u16 entry_ptr;
  1414. u16 pctl1;
  1415. uint i;
  1416. if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
  1417. return;
  1418. /* walk the phy rate table and update the entries */
  1419. for (i = 0; i < ARRAY_SIZE(rates); i++) {
  1420. rate = rates[i];
  1421. entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
  1422. /* read the SHM Rate Table entry OFDM PCTL1 values */
  1423. pctl1 =
  1424. brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
  1425. /* modify the value */
  1426. pctl1 &= ~PHY_TXC1_MODE_MASK;
  1427. pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
  1428. /* Update the SHM Rate Table entry OFDM PCTL1 values */
  1429. brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
  1430. pctl1);
  1431. }
  1432. }
  1433. /* band-specific init */
  1434. static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
  1435. {
  1436. struct brcms_hardware *wlc_hw = wlc->hw;
  1437. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
  1438. wlc_hw->band->bandunit);
  1439. brcms_c_ucode_bsinit(wlc_hw);
  1440. wlc_phy_init(wlc_hw->band->pi, chanspec);
  1441. brcms_c_ucode_txant_set(wlc_hw);
  1442. /*
  1443. * cwmin is band-specific, update hardware
  1444. * with value for current band
  1445. */
  1446. brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
  1447. brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
  1448. brcms_b_update_slot_timing(wlc_hw,
  1449. wlc_hw->band->bandtype == BRCM_BAND_5G ?
  1450. true : wlc_hw->shortslot);
  1451. /* write phytype and phyvers */
  1452. brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
  1453. brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
  1454. /*
  1455. * initialize the txphyctl1 rate table since
  1456. * shmem is shared between bands
  1457. */
  1458. brcms_upd_ofdm_pctl1_table(wlc_hw);
  1459. brcms_b_upd_synthpu(wlc_hw);
  1460. }
  1461. /* Perform a soft reset of the PHY PLL */
  1462. void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
  1463. {
  1464. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
  1465. ~0, 0);
  1466. udelay(1);
  1467. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1468. 0x4, 0);
  1469. udelay(1);
  1470. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1471. 0x4, 4);
  1472. udelay(1);
  1473. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1474. 0x4, 0);
  1475. udelay(1);
  1476. }
  1477. /* light way to turn on phy clock without reset for NPHY only
  1478. * refer to brcms_b_core_phy_clk for full version
  1479. */
  1480. void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
  1481. {
  1482. /* support(necessary for NPHY and HYPHY) only */
  1483. if (!BRCMS_ISNPHY(wlc_hw->band))
  1484. return;
  1485. if (ON == clk)
  1486. brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
  1487. else
  1488. brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
  1489. }
  1490. void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
  1491. {
  1492. if (ON == clk)
  1493. brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
  1494. else
  1495. brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
  1496. }
  1497. void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
  1498. {
  1499. struct brcms_phy_pub *pih = wlc_hw->band->pi;
  1500. u32 phy_bw_clkbits;
  1501. bool phy_in_reset = false;
  1502. brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
  1503. if (pih == NULL)
  1504. return;
  1505. phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
  1506. /* Specific reset sequence required for NPHY rev 3 and 4 */
  1507. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
  1508. NREV_LE(wlc_hw->band->phyrev, 4)) {
  1509. /* Set the PHY bandwidth */
  1510. brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
  1511. udelay(1);
  1512. /* Perform a soft reset of the PHY PLL */
  1513. brcms_b_core_phypll_reset(wlc_hw);
  1514. /* reset the PHY */
  1515. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
  1516. (SICF_PRST | SICF_PCLKE));
  1517. phy_in_reset = true;
  1518. } else {
  1519. brcms_b_core_ioctl(wlc_hw,
  1520. (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
  1521. (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
  1522. }
  1523. udelay(2);
  1524. brcms_b_core_phy_clk(wlc_hw, ON);
  1525. if (pih)
  1526. wlc_phy_anacore(pih, ON);
  1527. }
  1528. /* switch to and initialize new band */
  1529. static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
  1530. u16 chanspec) {
  1531. struct brcms_c_info *wlc = wlc_hw->wlc;
  1532. u32 macintmask;
  1533. /* Enable the d11 core before accessing it */
  1534. if (!bcma_core_is_enabled(wlc_hw->d11core)) {
  1535. bcma_core_enable(wlc_hw->d11core, 0);
  1536. brcms_c_mctrl_reset(wlc_hw);
  1537. }
  1538. macintmask = brcms_c_setband_inact(wlc, bandunit);
  1539. if (!wlc_hw->up)
  1540. return;
  1541. brcms_b_core_phy_clk(wlc_hw, ON);
  1542. /* band-specific initializations */
  1543. brcms_b_bsinit(wlc, chanspec);
  1544. /*
  1545. * If there are any pending software interrupt bits,
  1546. * then replace these with a harmless nonzero value
  1547. * so brcms_c_dpc() will re-enable interrupts when done.
  1548. */
  1549. if (wlc->macintstatus)
  1550. wlc->macintstatus = MI_DMAINT;
  1551. /* restore macintmask */
  1552. brcms_intrsrestore(wlc->wl, macintmask);
  1553. /* ucode should still be suspended.. */
  1554. WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
  1555. MCTL_EN_MAC) != 0);
  1556. }
  1557. static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
  1558. {
  1559. /* reject unsupported corerev */
  1560. if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
  1561. wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
  1562. wlc_hw->corerev);
  1563. return false;
  1564. }
  1565. return true;
  1566. }
  1567. /* Validate some board info parameters */
  1568. static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
  1569. {
  1570. uint boardrev = wlc_hw->boardrev;
  1571. /* 4 bits each for board type, major, minor, and tiny version */
  1572. uint brt = (boardrev & 0xf000) >> 12;
  1573. uint b0 = (boardrev & 0xf00) >> 8;
  1574. uint b1 = (boardrev & 0xf0) >> 4;
  1575. uint b2 = boardrev & 0xf;
  1576. /* voards from other vendors are always considered valid */
  1577. if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
  1578. return true;
  1579. /* do some boardrev sanity checks when boardvendor is Broadcom */
  1580. if (boardrev == 0)
  1581. return false;
  1582. if (boardrev <= 0xff)
  1583. return true;
  1584. if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
  1585. || (b2 > 9))
  1586. return false;
  1587. return true;
  1588. }
  1589. static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
  1590. {
  1591. struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
  1592. /* If macaddr exists, use it (Sromrev4, CIS, ...). */
  1593. if (!is_zero_ether_addr(sprom->il0mac)) {
  1594. memcpy(etheraddr, sprom->il0mac, 6);
  1595. return;
  1596. }
  1597. if (wlc_hw->_nbands > 1)
  1598. memcpy(etheraddr, sprom->et1mac, 6);
  1599. else
  1600. memcpy(etheraddr, sprom->il0mac, 6);
  1601. }
  1602. /* power both the pll and external oscillator on/off */
  1603. static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
  1604. {
  1605. brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
  1606. /*
  1607. * dont power down if plldown is false or
  1608. * we must poll hw radio disable
  1609. */
  1610. if (!want && wlc_hw->pllreq)
  1611. return;
  1612. wlc_hw->sbclk = want;
  1613. if (!wlc_hw->sbclk) {
  1614. wlc_hw->clk = false;
  1615. if (wlc_hw->band && wlc_hw->band->pi)
  1616. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  1617. }
  1618. }
  1619. /*
  1620. * Return true if radio is disabled, otherwise false.
  1621. * hw radio disable signal is an external pin, users activate it asynchronously
  1622. * this function could be called when driver is down and w/o clock
  1623. * it operates on different registers depending on corerev and boardflag.
  1624. */
  1625. static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
  1626. {
  1627. bool v, clk, xtal;
  1628. u32 flags = 0;
  1629. xtal = wlc_hw->sbclk;
  1630. if (!xtal)
  1631. brcms_b_xtal(wlc_hw, ON);
  1632. /* may need to take core out of reset first */
  1633. clk = wlc_hw->clk;
  1634. if (!clk) {
  1635. /*
  1636. * mac no longer enables phyclk automatically when driver
  1637. * accesses phyreg throughput mac. This can be skipped since
  1638. * only mac reg is accessed below
  1639. */
  1640. if (D11REV_GE(wlc_hw->corerev, 18))
  1641. flags |= SICF_PCLKE;
  1642. /*
  1643. * TODO: test suspend/resume
  1644. *
  1645. * AI chip doesn't restore bar0win2 on
  1646. * hibernation/resume, need sw fixup
  1647. */
  1648. bcma_core_enable(wlc_hw->d11core, flags);
  1649. brcms_c_mctrl_reset(wlc_hw);
  1650. }
  1651. v = ((bcma_read32(wlc_hw->d11core,
  1652. D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
  1653. /* put core back into reset */
  1654. if (!clk)
  1655. bcma_core_disable(wlc_hw->d11core, 0);
  1656. if (!xtal)
  1657. brcms_b_xtal(wlc_hw, OFF);
  1658. return v;
  1659. }
  1660. static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
  1661. {
  1662. struct dma_pub *di = wlc_hw->di[fifo];
  1663. return dma_rxreset(di);
  1664. }
  1665. /* d11 core reset
  1666. * ensure fask clock during reset
  1667. * reset dma
  1668. * reset d11(out of reset)
  1669. * reset phy(out of reset)
  1670. * clear software macintstatus for fresh new start
  1671. * one testing hack wlc_hw->noreset will bypass the d11/phy reset
  1672. */
  1673. void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
  1674. {
  1675. uint i;
  1676. bool fastclk;
  1677. if (flags == BRCMS_USE_COREFLAGS)
  1678. flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
  1679. brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
  1680. /* request FAST clock if not on */
  1681. fastclk = wlc_hw->forcefastclk;
  1682. if (!fastclk)
  1683. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  1684. /* reset the dma engines except first time thru */
  1685. if (bcma_core_is_enabled(wlc_hw->d11core)) {
  1686. for (i = 0; i < NFIFO; i++)
  1687. if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
  1688. brcms_err(wlc_hw->d11core, "wl%d: %s: "
  1689. "dma_txreset[%d]: cannot stop dma\n",
  1690. wlc_hw->unit, __func__, i);
  1691. if ((wlc_hw->di[RX_FIFO])
  1692. && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
  1693. brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
  1694. "[%d]: cannot stop dma\n",
  1695. wlc_hw->unit, __func__, RX_FIFO);
  1696. }
  1697. /* if noreset, just stop the psm and return */
  1698. if (wlc_hw->noreset) {
  1699. wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
  1700. brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
  1701. return;
  1702. }
  1703. /*
  1704. * mac no longer enables phyclk automatically when driver accesses
  1705. * phyreg throughput mac, AND phy_reset is skipped at early stage when
  1706. * band->pi is invalid. need to enable PHY CLK
  1707. */
  1708. if (D11REV_GE(wlc_hw->corerev, 18))
  1709. flags |= SICF_PCLKE;
  1710. /*
  1711. * reset the core
  1712. * In chips with PMU, the fastclk request goes through d11 core
  1713. * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
  1714. *
  1715. * This adds some delay and we can optimize it by also requesting
  1716. * fastclk through chipcommon during this period if necessary. But
  1717. * that has to work coordinate with other driver like mips/arm since
  1718. * they may touch chipcommon as well.
  1719. */
  1720. wlc_hw->clk = false;
  1721. bcma_core_enable(wlc_hw->d11core, flags);
  1722. wlc_hw->clk = true;
  1723. if (wlc_hw->band && wlc_hw->band->pi)
  1724. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
  1725. brcms_c_mctrl_reset(wlc_hw);
  1726. if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
  1727. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  1728. brcms_b_phy_reset(wlc_hw);
  1729. /* turn on PHY_PLL */
  1730. brcms_b_core_phypll_ctl(wlc_hw, true);
  1731. /* clear sw intstatus */
  1732. wlc_hw->wlc->macintstatus = 0;
  1733. /* restore the clk setting */
  1734. if (!fastclk)
  1735. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  1736. }
  1737. /* txfifo sizes needs to be modified(increased) since the newer cores
  1738. * have more memory.
  1739. */
  1740. static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
  1741. {
  1742. struct bcma_device *core = wlc_hw->d11core;
  1743. u16 fifo_nu;
  1744. u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
  1745. u16 txfifo_def, txfifo_def1;
  1746. u16 txfifo_cmd;
  1747. /* tx fifos start at TXFIFO_START_BLK from the Base address */
  1748. txfifo_startblk = TXFIFO_START_BLK;
  1749. /* sequence of operations: reset fifo, set fifo size, reset fifo */
  1750. for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
  1751. txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
  1752. txfifo_def = (txfifo_startblk & 0xff) |
  1753. (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
  1754. txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
  1755. ((((txfifo_endblk -
  1756. 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
  1757. txfifo_cmd =
  1758. TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
  1759. bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
  1760. bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
  1761. bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
  1762. bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
  1763. txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
  1764. }
  1765. /*
  1766. * need to propagate to shm location to be in sync since ucode/hw won't
  1767. * do this
  1768. */
  1769. brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
  1770. wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
  1771. brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
  1772. wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
  1773. brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
  1774. ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
  1775. xmtfifo_sz[TX_AC_BK_FIFO]));
  1776. brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
  1777. ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
  1778. xmtfifo_sz[TX_BCMC_FIFO]));
  1779. }
  1780. /* This function is used for changing the tsf frac register
  1781. * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
  1782. * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
  1783. * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
  1784. * HTPHY Formula is 2^26/freq(MHz) e.g.
  1785. * For spuron2 - 126MHz -> 2^26/126 = 532610.0
  1786. * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
  1787. * For spuron: 123MHz -> 2^26/123 = 545600.5
  1788. * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
  1789. * For spur off: 120MHz -> 2^26/120 = 559240.5
  1790. * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
  1791. */
  1792. void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
  1793. {
  1794. struct bcma_device *core = wlc_hw->d11core;
  1795. if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
  1796. (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
  1797. if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
  1798. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
  1799. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1800. } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
  1801. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
  1802. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1803. } else { /* 120Mhz */
  1804. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
  1805. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1806. }
  1807. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1808. if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
  1809. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
  1810. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
  1811. } else { /* 80Mhz */
  1812. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
  1813. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
  1814. }
  1815. }
  1816. }
  1817. void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
  1818. {
  1819. memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
  1820. wlc->bsscfg->type = BRCMS_TYPE_STATION;
  1821. }
  1822. /* Initialize GPIOs that are controlled by D11 core */
  1823. static void brcms_c_gpio_init(struct brcms_c_info *wlc)
  1824. {
  1825. struct brcms_hardware *wlc_hw = wlc->hw;
  1826. u32 gc, gm;
  1827. /* use GPIO select 0 to get all gpio signals from the gpio out reg */
  1828. brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
  1829. /*
  1830. * Common GPIO setup:
  1831. * G0 = LED 0 = WLAN Activity
  1832. * G1 = LED 1 = WLAN 2.4 GHz Radio State
  1833. * G2 = LED 2 = WLAN 5 GHz Radio State
  1834. * G4 = radio disable input (HI enabled, LO disabled)
  1835. */
  1836. gc = gm = 0;
  1837. /* Allocate GPIOs for mimo antenna diversity feature */
  1838. if (wlc_hw->antsel_type == ANTSEL_2x3) {
  1839. /* Enable antenna diversity, use 2x3 mode */
  1840. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1841. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1842. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
  1843. MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
  1844. /* init superswitch control */
  1845. wlc_phy_antsel_init(wlc_hw->band->pi, false);
  1846. } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
  1847. gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
  1848. /*
  1849. * The board itself is powered by these GPIOs
  1850. * (when not sending pattern) so set them high
  1851. */
  1852. bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
  1853. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1854. bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
  1855. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1856. /* Enable antenna diversity, use 2x4 mode */
  1857. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1858. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1859. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
  1860. BRCM_BAND_ALL);
  1861. /* Configure the desired clock to be 4Mhz */
  1862. brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
  1863. ANTSEL_CLKDIV_4MHZ);
  1864. }
  1865. /*
  1866. * gpio 9 controls the PA. ucode is responsible
  1867. * for wiggling out and oe
  1868. */
  1869. if (wlc_hw->boardflags & BFL_PACTRL)
  1870. gm |= gc |= BOARD_GPIO_PACTRL;
  1871. /* apply to gpiocontrol register */
  1872. bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
  1873. }
  1874. static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
  1875. const __le32 ucode[], const size_t nbytes)
  1876. {
  1877. struct bcma_device *core = wlc_hw->d11core;
  1878. uint i;
  1879. uint count;
  1880. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  1881. count = (nbytes / sizeof(u32));
  1882. bcma_write32(core, D11REGOFFS(objaddr),
  1883. OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
  1884. (void)bcma_read32(core, D11REGOFFS(objaddr));
  1885. for (i = 0; i < count; i++)
  1886. bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
  1887. }
  1888. static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
  1889. {
  1890. struct brcms_c_info *wlc;
  1891. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  1892. wlc = wlc_hw->wlc;
  1893. if (wlc_hw->ucode_loaded)
  1894. return;
  1895. if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
  1896. if (BRCMS_ISNPHY(wlc_hw->band)) {
  1897. brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
  1898. ucode->bcm43xx_16_mimosz);
  1899. wlc_hw->ucode_loaded = true;
  1900. } else
  1901. brcms_err(wlc_hw->d11core,
  1902. "%s: wl%d: unsupported phy in corerev %d\n",
  1903. __func__, wlc_hw->unit, wlc_hw->corerev);
  1904. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  1905. if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1906. brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
  1907. ucode->bcm43xx_24_lcnsz);
  1908. wlc_hw->ucode_loaded = true;
  1909. } else {
  1910. brcms_err(wlc_hw->d11core,
  1911. "%s: wl%d: unsupported phy in corerev %d\n",
  1912. __func__, wlc_hw->unit, wlc_hw->corerev);
  1913. }
  1914. }
  1915. }
  1916. void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
  1917. {
  1918. /* update sw state */
  1919. wlc_hw->bmac_phytxant = phytxant;
  1920. /* push to ucode if up */
  1921. if (!wlc_hw->up)
  1922. return;
  1923. brcms_c_ucode_txant_set(wlc_hw);
  1924. }
  1925. u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
  1926. {
  1927. return (u16) wlc_hw->wlc->stf->txant;
  1928. }
  1929. void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
  1930. {
  1931. wlc_hw->antsel_type = antsel_type;
  1932. /* Update the antsel type for phy module to use */
  1933. wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
  1934. }
  1935. static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
  1936. {
  1937. bool fatal = false;
  1938. uint unit;
  1939. uint intstatus, idx;
  1940. struct bcma_device *core = wlc_hw->d11core;
  1941. unit = wlc_hw->unit;
  1942. for (idx = 0; idx < NFIFO; idx++) {
  1943. /* read intstatus register and ignore any non-error bits */
  1944. intstatus =
  1945. bcma_read32(core,
  1946. D11REGOFFS(intctrlregs[idx].intstatus)) &
  1947. I_ERRORS;
  1948. if (!intstatus)
  1949. continue;
  1950. brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
  1951. unit, idx, intstatus);
  1952. if (intstatus & I_RO) {
  1953. brcms_err(core, "wl%d: fifo %d: receive fifo "
  1954. "overflow\n", unit, idx);
  1955. fatal = true;
  1956. }
  1957. if (intstatus & I_PC) {
  1958. brcms_err(core, "wl%d: fifo %d: descriptor error\n",
  1959. unit, idx);
  1960. fatal = true;
  1961. }
  1962. if (intstatus & I_PD) {
  1963. brcms_err(core, "wl%d: fifo %d: data error\n", unit,
  1964. idx);
  1965. fatal = true;
  1966. }
  1967. if (intstatus & I_DE) {
  1968. brcms_err(core, "wl%d: fifo %d: descriptor protocol "
  1969. "error\n", unit, idx);
  1970. fatal = true;
  1971. }
  1972. if (intstatus & I_RU)
  1973. brcms_err(core, "wl%d: fifo %d: receive descriptor "
  1974. "underflow\n", idx, unit);
  1975. if (intstatus & I_XU) {
  1976. brcms_err(core, "wl%d: fifo %d: transmit fifo "
  1977. "underflow\n", idx, unit);
  1978. fatal = true;
  1979. }
  1980. if (fatal) {
  1981. brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
  1982. break;
  1983. } else
  1984. bcma_write32(core,
  1985. D11REGOFFS(intctrlregs[idx].intstatus),
  1986. intstatus);
  1987. }
  1988. }
  1989. void brcms_c_intrson(struct brcms_c_info *wlc)
  1990. {
  1991. struct brcms_hardware *wlc_hw = wlc->hw;
  1992. wlc->macintmask = wlc->defmacintmask;
  1993. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
  1994. }
  1995. u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
  1996. {
  1997. struct brcms_hardware *wlc_hw = wlc->hw;
  1998. u32 macintmask;
  1999. if (!wlc_hw->clk)
  2000. return 0;
  2001. macintmask = wlc->macintmask; /* isr can still happen */
  2002. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
  2003. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
  2004. udelay(1); /* ensure int line is no longer driven */
  2005. wlc->macintmask = 0;
  2006. /* return previous macintmask; resolve race between us and our isr */
  2007. return wlc->macintstatus ? 0 : macintmask;
  2008. }
  2009. void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
  2010. {
  2011. struct brcms_hardware *wlc_hw = wlc->hw;
  2012. if (!wlc_hw->clk)
  2013. return;
  2014. wlc->macintmask = macintmask;
  2015. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
  2016. }
  2017. /* assumes that the d11 MAC is enabled */
  2018. static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
  2019. uint tx_fifo)
  2020. {
  2021. u8 fifo = 1 << tx_fifo;
  2022. /* Two clients of this code, 11h Quiet period and scanning. */
  2023. /* only suspend if not already suspended */
  2024. if ((wlc_hw->suspended_fifos & fifo) == fifo)
  2025. return;
  2026. /* force the core awake only if not already */
  2027. if (wlc_hw->suspended_fifos == 0)
  2028. brcms_c_ucode_wake_override_set(wlc_hw,
  2029. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2030. wlc_hw->suspended_fifos |= fifo;
  2031. if (wlc_hw->di[tx_fifo]) {
  2032. /*
  2033. * Suspending AMPDU transmissions in the middle can cause
  2034. * underflow which may result in mismatch between ucode and
  2035. * driver so suspend the mac before suspending the FIFO
  2036. */
  2037. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2038. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  2039. dma_txsuspend(wlc_hw->di[tx_fifo]);
  2040. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2041. brcms_c_enable_mac(wlc_hw->wlc);
  2042. }
  2043. }
  2044. static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
  2045. uint tx_fifo)
  2046. {
  2047. /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
  2048. * but need to be done here for PIO otherwise the watchdog will catch
  2049. * the inconsistency and fire
  2050. */
  2051. /* Two clients of this code, 11h Quiet period and scanning. */
  2052. if (wlc_hw->di[tx_fifo])
  2053. dma_txresume(wlc_hw->di[tx_fifo]);
  2054. /* allow core to sleep again */
  2055. if (wlc_hw->suspended_fifos == 0)
  2056. return;
  2057. else {
  2058. wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
  2059. if (wlc_hw->suspended_fifos == 0)
  2060. brcms_c_ucode_wake_override_clear(wlc_hw,
  2061. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2062. }
  2063. }
  2064. /* precondition: requires the mac core to be enabled */
  2065. static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
  2066. {
  2067. static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
  2068. u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
  2069. if (mute_tx) {
  2070. /* suspend tx fifos */
  2071. brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
  2072. brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
  2073. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
  2074. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
  2075. /* zero the address match register so we do not send ACKs */
  2076. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
  2077. } else {
  2078. /* resume tx fifos */
  2079. brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
  2080. brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
  2081. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
  2082. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
  2083. /* Restore address */
  2084. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
  2085. }
  2086. wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
  2087. if (mute_tx)
  2088. brcms_c_ucode_mute_override_set(wlc_hw);
  2089. else
  2090. brcms_c_ucode_mute_override_clear(wlc_hw);
  2091. }
  2092. void
  2093. brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
  2094. {
  2095. brcms_b_mute(wlc->hw, mute_tx);
  2096. }
  2097. /*
  2098. * Read and clear macintmask and macintstatus and intstatus registers.
  2099. * This routine should be called with interrupts off
  2100. * Return:
  2101. * -1 if brcms_deviceremoved(wlc) evaluates to true;
  2102. * 0 if the interrupt is not for us, or we are in some special cases;
  2103. * device interrupt status bits otherwise.
  2104. */
  2105. static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
  2106. {
  2107. struct brcms_hardware *wlc_hw = wlc->hw;
  2108. struct bcma_device *core = wlc_hw->d11core;
  2109. u32 macintstatus, mask;
  2110. /* macintstatus includes a DMA interrupt summary bit */
  2111. macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
  2112. mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
  2113. trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
  2114. /* detect cardbus removed, in power down(suspend) and in reset */
  2115. if (brcms_deviceremoved(wlc))
  2116. return -1;
  2117. /* brcms_deviceremoved() succeeds even when the core is still resetting,
  2118. * handle that case here.
  2119. */
  2120. if (macintstatus == 0xffffffff)
  2121. return 0;
  2122. /* defer unsolicited interrupts */
  2123. macintstatus &= mask;
  2124. /* if not for us */
  2125. if (macintstatus == 0)
  2126. return 0;
  2127. /* turn off the interrupts */
  2128. bcma_write32(core, D11REGOFFS(macintmask), 0);
  2129. (void)bcma_read32(core, D11REGOFFS(macintmask));
  2130. wlc->macintmask = 0;
  2131. /* clear device interrupts */
  2132. bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
  2133. /* MI_DMAINT is indication of non-zero intstatus */
  2134. if (macintstatus & MI_DMAINT)
  2135. /*
  2136. * only fifo interrupt enabled is I_RI in
  2137. * RX_FIFO. If MI_DMAINT is set, assume it
  2138. * is set and clear the interrupt.
  2139. */
  2140. bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
  2141. DEF_RXINTMASK);
  2142. return macintstatus;
  2143. }
  2144. /* Update wlc->macintstatus and wlc->intstatus[]. */
  2145. /* Return true if they are updated successfully. false otherwise */
  2146. bool brcms_c_intrsupd(struct brcms_c_info *wlc)
  2147. {
  2148. u32 macintstatus;
  2149. /* read and clear macintstatus and intstatus registers */
  2150. macintstatus = wlc_intstatus(wlc, false);
  2151. /* device is removed */
  2152. if (macintstatus == 0xffffffff)
  2153. return false;
  2154. /* update interrupt status in software */
  2155. wlc->macintstatus |= macintstatus;
  2156. return true;
  2157. }
  2158. /*
  2159. * First-level interrupt processing.
  2160. * Return true if this was our interrupt
  2161. * and if further brcms_c_dpc() processing is required,
  2162. * false otherwise.
  2163. */
  2164. bool brcms_c_isr(struct brcms_c_info *wlc)
  2165. {
  2166. struct brcms_hardware *wlc_hw = wlc->hw;
  2167. u32 macintstatus;
  2168. if (!wlc_hw->up || !wlc->macintmask)
  2169. return false;
  2170. /* read and clear macintstatus and intstatus registers */
  2171. macintstatus = wlc_intstatus(wlc, true);
  2172. if (macintstatus == 0xffffffff) {
  2173. brcms_err(wlc_hw->d11core,
  2174. "DEVICEREMOVED detected in the ISR code path\n");
  2175. return false;
  2176. }
  2177. /* it is not for us */
  2178. if (macintstatus == 0)
  2179. return false;
  2180. /* save interrupt status bits */
  2181. wlc->macintstatus = macintstatus;
  2182. return true;
  2183. }
  2184. void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
  2185. {
  2186. struct brcms_hardware *wlc_hw = wlc->hw;
  2187. struct bcma_device *core = wlc_hw->d11core;
  2188. u32 mc, mi;
  2189. brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
  2190. wlc_hw->band->bandunit);
  2191. /*
  2192. * Track overlapping suspend requests
  2193. */
  2194. wlc_hw->mac_suspend_depth++;
  2195. if (wlc_hw->mac_suspend_depth > 1)
  2196. return;
  2197. /* force the core awake */
  2198. brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2199. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2200. if (mc == 0xffffffff) {
  2201. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2202. __func__);
  2203. brcms_down(wlc->wl);
  2204. return;
  2205. }
  2206. WARN_ON(mc & MCTL_PSM_JMP_0);
  2207. WARN_ON(!(mc & MCTL_PSM_RUN));
  2208. WARN_ON(!(mc & MCTL_EN_MAC));
  2209. mi = bcma_read32(core, D11REGOFFS(macintstatus));
  2210. if (mi == 0xffffffff) {
  2211. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2212. __func__);
  2213. brcms_down(wlc->wl);
  2214. return;
  2215. }
  2216. WARN_ON(mi & MI_MACSSPNDD);
  2217. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
  2218. SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
  2219. BRCMS_MAX_MAC_SUSPEND);
  2220. if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
  2221. brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
  2222. " and MI_MACSSPNDD is still not on.\n",
  2223. wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
  2224. brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
  2225. "psm_brc 0x%04x\n", wlc_hw->unit,
  2226. bcma_read32(core, D11REGOFFS(psmdebug)),
  2227. bcma_read32(core, D11REGOFFS(phydebug)),
  2228. bcma_read16(core, D11REGOFFS(psm_brc)));
  2229. }
  2230. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2231. if (mc == 0xffffffff) {
  2232. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2233. __func__);
  2234. brcms_down(wlc->wl);
  2235. return;
  2236. }
  2237. WARN_ON(mc & MCTL_PSM_JMP_0);
  2238. WARN_ON(!(mc & MCTL_PSM_RUN));
  2239. WARN_ON(mc & MCTL_EN_MAC);
  2240. }
  2241. void brcms_c_enable_mac(struct brcms_c_info *wlc)
  2242. {
  2243. struct brcms_hardware *wlc_hw = wlc->hw;
  2244. struct bcma_device *core = wlc_hw->d11core;
  2245. u32 mc, mi;
  2246. brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
  2247. wlc->band->bandunit);
  2248. /*
  2249. * Track overlapping suspend requests
  2250. */
  2251. wlc_hw->mac_suspend_depth--;
  2252. if (wlc_hw->mac_suspend_depth > 0)
  2253. return;
  2254. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2255. WARN_ON(mc & MCTL_PSM_JMP_0);
  2256. WARN_ON(mc & MCTL_EN_MAC);
  2257. WARN_ON(!(mc & MCTL_PSM_RUN));
  2258. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
  2259. bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
  2260. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2261. WARN_ON(mc & MCTL_PSM_JMP_0);
  2262. WARN_ON(!(mc & MCTL_EN_MAC));
  2263. WARN_ON(!(mc & MCTL_PSM_RUN));
  2264. mi = bcma_read32(core, D11REGOFFS(macintstatus));
  2265. WARN_ON(mi & MI_MACSSPNDD);
  2266. brcms_c_ucode_wake_override_clear(wlc_hw,
  2267. BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2268. }
  2269. void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
  2270. {
  2271. wlc_hw->hw_stf_ss_opmode = stf_mode;
  2272. if (wlc_hw->clk)
  2273. brcms_upd_ofdm_pctl1_table(wlc_hw);
  2274. }
  2275. static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
  2276. {
  2277. struct bcma_device *core = wlc_hw->d11core;
  2278. u32 w, val;
  2279. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  2280. /* Validate dchip register access */
  2281. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2282. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2283. w = bcma_read32(core, D11REGOFFS(objdata));
  2284. /* Can we write and read back a 32bit register? */
  2285. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2286. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2287. bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
  2288. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2289. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2290. val = bcma_read32(core, D11REGOFFS(objdata));
  2291. if (val != (u32) 0xaa5555aa) {
  2292. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2293. "expected 0xaa5555aa\n", wlc_hw->unit, val);
  2294. return false;
  2295. }
  2296. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2297. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2298. bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
  2299. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2300. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2301. val = bcma_read32(core, D11REGOFFS(objdata));
  2302. if (val != (u32) 0x55aaaa55) {
  2303. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2304. "expected 0x55aaaa55\n", wlc_hw->unit, val);
  2305. return false;
  2306. }
  2307. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2308. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2309. bcma_write32(core, D11REGOFFS(objdata), w);
  2310. /* clear CFPStart */
  2311. bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
  2312. w = bcma_read32(core, D11REGOFFS(maccontrol));
  2313. if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
  2314. (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
  2315. wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
  2316. "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
  2317. (MCTL_IHR_EN | MCTL_WAKE),
  2318. (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
  2319. return false;
  2320. }
  2321. return true;
  2322. }
  2323. #define PHYPLL_WAIT_US 100000
  2324. void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
  2325. {
  2326. struct bcma_device *core = wlc_hw->d11core;
  2327. u32 tmp;
  2328. brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
  2329. tmp = 0;
  2330. if (on) {
  2331. if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
  2332. bcma_set32(core, D11REGOFFS(clk_ctl_st),
  2333. CCS_ERSRC_REQ_HT |
  2334. CCS_ERSRC_REQ_D11PLL |
  2335. CCS_ERSRC_REQ_PHYPLL);
  2336. SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
  2337. CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
  2338. PHYPLL_WAIT_US);
  2339. tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2340. if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
  2341. brcms_err(core, "%s: turn on PHY PLL failed\n",
  2342. __func__);
  2343. } else {
  2344. bcma_set32(core, D11REGOFFS(clk_ctl_st),
  2345. tmp | CCS_ERSRC_REQ_D11PLL |
  2346. CCS_ERSRC_REQ_PHYPLL);
  2347. SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
  2348. (CCS_ERSRC_AVAIL_D11PLL |
  2349. CCS_ERSRC_AVAIL_PHYPLL)) !=
  2350. (CCS_ERSRC_AVAIL_D11PLL |
  2351. CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
  2352. tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2353. if ((tmp &
  2354. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2355. !=
  2356. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2357. brcms_err(core, "%s: turn on PHY PLL failed\n",
  2358. __func__);
  2359. }
  2360. } else {
  2361. /*
  2362. * Since the PLL may be shared, other cores can still
  2363. * be requesting it; so we'll deassert the request but
  2364. * not wait for status to comply.
  2365. */
  2366. bcma_mask32(core, D11REGOFFS(clk_ctl_st),
  2367. ~CCS_ERSRC_REQ_PHYPLL);
  2368. (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2369. }
  2370. }
  2371. static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
  2372. {
  2373. bool dev_gone;
  2374. brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
  2375. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  2376. if (dev_gone)
  2377. return;
  2378. if (wlc_hw->noreset)
  2379. return;
  2380. /* radio off */
  2381. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  2382. /* turn off analog core */
  2383. wlc_phy_anacore(wlc_hw->band->pi, OFF);
  2384. /* turn off PHYPLL to save power */
  2385. brcms_b_core_phypll_ctl(wlc_hw, false);
  2386. wlc_hw->clk = false;
  2387. bcma_core_disable(wlc_hw->d11core, 0);
  2388. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  2389. }
  2390. static void brcms_c_flushqueues(struct brcms_c_info *wlc)
  2391. {
  2392. struct brcms_hardware *wlc_hw = wlc->hw;
  2393. uint i;
  2394. /* free any posted tx packets */
  2395. for (i = 0; i < NFIFO; i++) {
  2396. if (wlc_hw->di[i]) {
  2397. dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
  2398. if (i < TX_BCMC_FIFO)
  2399. ieee80211_wake_queue(wlc->pub->ieee_hw,
  2400. brcms_fifo_to_ac(i));
  2401. }
  2402. }
  2403. /* free any posted rx packets */
  2404. dma_rxreclaim(wlc_hw->di[RX_FIFO]);
  2405. }
  2406. static u16
  2407. brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
  2408. {
  2409. struct bcma_device *core = wlc_hw->d11core;
  2410. u16 objoff = D11REGOFFS(objdata);
  2411. bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
  2412. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2413. if (offset & 2)
  2414. objoff += 2;
  2415. return bcma_read16(core, objoff);
  2416. }
  2417. static void
  2418. brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
  2419. u32 sel)
  2420. {
  2421. struct bcma_device *core = wlc_hw->d11core;
  2422. u16 objoff = D11REGOFFS(objdata);
  2423. bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
  2424. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2425. if (offset & 2)
  2426. objoff += 2;
  2427. bcma_wflush16(core, objoff, v);
  2428. }
  2429. /*
  2430. * Read a single u16 from shared memory.
  2431. * SHM 'offset' needs to be an even address
  2432. */
  2433. u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
  2434. {
  2435. return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
  2436. }
  2437. /*
  2438. * Write a single u16 to shared memory.
  2439. * SHM 'offset' needs to be an even address
  2440. */
  2441. void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
  2442. {
  2443. brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
  2444. }
  2445. /*
  2446. * Copy a buffer to shared memory of specified type .
  2447. * SHM 'offset' needs to be an even address and
  2448. * Buffer length 'len' must be an even number of bytes
  2449. * 'sel' selects the type of memory
  2450. */
  2451. void
  2452. brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
  2453. const void *buf, int len, u32 sel)
  2454. {
  2455. u16 v;
  2456. const u8 *p = (const u8 *)buf;
  2457. int i;
  2458. if (len <= 0 || (offset & 1) || (len & 1))
  2459. return;
  2460. for (i = 0; i < len; i += 2) {
  2461. v = p[i] | (p[i + 1] << 8);
  2462. brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
  2463. }
  2464. }
  2465. /*
  2466. * Copy a piece of shared memory of specified type to a buffer .
  2467. * SHM 'offset' needs to be an even address and
  2468. * Buffer length 'len' must be an even number of bytes
  2469. * 'sel' selects the type of memory
  2470. */
  2471. void
  2472. brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
  2473. int len, u32 sel)
  2474. {
  2475. u16 v;
  2476. u8 *p = (u8 *) buf;
  2477. int i;
  2478. if (len <= 0 || (offset & 1) || (len & 1))
  2479. return;
  2480. for (i = 0; i < len; i += 2) {
  2481. v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
  2482. p[i] = v & 0xFF;
  2483. p[i + 1] = (v >> 8) & 0xFF;
  2484. }
  2485. }
  2486. /* Copy a buffer to shared memory.
  2487. * SHM 'offset' needs to be an even address and
  2488. * Buffer length 'len' must be an even number of bytes
  2489. */
  2490. static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
  2491. const void *buf, int len)
  2492. {
  2493. brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
  2494. }
  2495. static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
  2496. u16 SRL, u16 LRL)
  2497. {
  2498. wlc_hw->SRL = SRL;
  2499. wlc_hw->LRL = LRL;
  2500. /* write retry limit to SCR, shouldn't need to suspend */
  2501. if (wlc_hw->up) {
  2502. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  2503. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2504. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  2505. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
  2506. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  2507. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2508. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  2509. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
  2510. }
  2511. }
  2512. static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
  2513. {
  2514. if (set) {
  2515. if (mboolisset(wlc_hw->pllreq, req_bit))
  2516. return;
  2517. mboolset(wlc_hw->pllreq, req_bit);
  2518. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2519. if (!wlc_hw->sbclk)
  2520. brcms_b_xtal(wlc_hw, ON);
  2521. }
  2522. } else {
  2523. if (!mboolisset(wlc_hw->pllreq, req_bit))
  2524. return;
  2525. mboolclr(wlc_hw->pllreq, req_bit);
  2526. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2527. if (wlc_hw->sbclk)
  2528. brcms_b_xtal(wlc_hw, OFF);
  2529. }
  2530. }
  2531. }
  2532. static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
  2533. {
  2534. wlc_hw->antsel_avail = antsel_avail;
  2535. }
  2536. /*
  2537. * conditions under which the PM bit should be set in outgoing frames
  2538. * and STAY_AWAKE is meaningful
  2539. */
  2540. static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
  2541. {
  2542. /* disallow PS when one of the following global conditions meets */
  2543. if (!wlc->pub->associated)
  2544. return false;
  2545. /* disallow PS when one of these meets when not scanning */
  2546. if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
  2547. return false;
  2548. return true;
  2549. }
  2550. static void brcms_c_statsupd(struct brcms_c_info *wlc)
  2551. {
  2552. int i;
  2553. struct macstat macstats;
  2554. #ifdef DEBUG
  2555. u16 delta;
  2556. u16 rxf0ovfl;
  2557. u16 txfunfl[NFIFO];
  2558. #endif /* DEBUG */
  2559. /* if driver down, make no sense to update stats */
  2560. if (!wlc->pub->up)
  2561. return;
  2562. #ifdef DEBUG
  2563. /* save last rx fifo 0 overflow count */
  2564. rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
  2565. /* save last tx fifo underflow count */
  2566. for (i = 0; i < NFIFO; i++)
  2567. txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
  2568. #endif /* DEBUG */
  2569. /* Read mac stats from contiguous shared memory */
  2570. brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
  2571. sizeof(struct macstat), OBJADDR_SHM_SEL);
  2572. #ifdef DEBUG
  2573. /* check for rx fifo 0 overflow */
  2574. delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
  2575. if (delta)
  2576. brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
  2577. wlc->pub->unit, delta);
  2578. /* check for tx fifo underflows */
  2579. for (i = 0; i < NFIFO; i++) {
  2580. delta =
  2581. (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
  2582. txfunfl[i]);
  2583. if (delta)
  2584. brcms_err(wlc->hw->d11core,
  2585. "wl%d: %u tx fifo %d underflows!\n",
  2586. wlc->pub->unit, delta, i);
  2587. }
  2588. #endif /* DEBUG */
  2589. /* merge counters from dma module */
  2590. for (i = 0; i < NFIFO; i++) {
  2591. if (wlc->hw->di[i])
  2592. dma_counterreset(wlc->hw->di[i]);
  2593. }
  2594. }
  2595. static void brcms_b_reset(struct brcms_hardware *wlc_hw)
  2596. {
  2597. /* reset the core */
  2598. if (!brcms_deviceremoved(wlc_hw->wlc))
  2599. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  2600. /* purge the dma rings */
  2601. brcms_c_flushqueues(wlc_hw->wlc);
  2602. }
  2603. void brcms_c_reset(struct brcms_c_info *wlc)
  2604. {
  2605. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  2606. /* slurp up hw mac counters before core reset */
  2607. brcms_c_statsupd(wlc);
  2608. /* reset our snapshot of macstat counters */
  2609. memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
  2610. brcms_b_reset(wlc->hw);
  2611. }
  2612. void brcms_c_init_scb(struct scb *scb)
  2613. {
  2614. int i;
  2615. memset(scb, 0, sizeof(struct scb));
  2616. scb->flags = SCB_WMECAP | SCB_HTCAP;
  2617. for (i = 0; i < NUMPRIO; i++) {
  2618. scb->seqnum[i] = 0;
  2619. scb->seqctl[i] = 0xFFFF;
  2620. }
  2621. scb->seqctl_nonqos = 0xFFFF;
  2622. scb->magic = SCB_MAGIC;
  2623. }
  2624. /* d11 core init
  2625. * reset PSM
  2626. * download ucode/PCM
  2627. * let ucode run to suspended
  2628. * download ucode inits
  2629. * config other core registers
  2630. * init dma
  2631. */
  2632. static void brcms_b_coreinit(struct brcms_c_info *wlc)
  2633. {
  2634. struct brcms_hardware *wlc_hw = wlc->hw;
  2635. struct bcma_device *core = wlc_hw->d11core;
  2636. u32 sflags;
  2637. u32 bcnint_us;
  2638. uint i = 0;
  2639. bool fifosz_fixup = false;
  2640. int err = 0;
  2641. u16 buf[NFIFO];
  2642. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  2643. brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
  2644. /* reset PSM */
  2645. brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
  2646. brcms_ucode_download(wlc_hw);
  2647. /*
  2648. * FIFOSZ fixup. driver wants to controls the fifo allocation.
  2649. */
  2650. fifosz_fixup = true;
  2651. /* let the PSM run to the suspended state, set mode to BSS STA */
  2652. bcma_write32(core, D11REGOFFS(macintstatus), -1);
  2653. brcms_b_mctrl(wlc_hw, ~0,
  2654. (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
  2655. /* wait for ucode to self-suspend after auto-init */
  2656. SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
  2657. MI_MACSSPNDD) == 0), 1000 * 1000);
  2658. if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
  2659. brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
  2660. "suspend!\n", wlc_hw->unit);
  2661. brcms_c_gpio_init(wlc);
  2662. sflags = bcma_aread32(core, BCMA_IOST);
  2663. if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
  2664. if (BRCMS_ISNPHY(wlc_hw->band))
  2665. brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
  2666. else
  2667. brcms_err(core, "%s: wl%d: unsupported phy in corerev"
  2668. " %d\n", __func__, wlc_hw->unit,
  2669. wlc_hw->corerev);
  2670. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  2671. if (BRCMS_ISLCNPHY(wlc_hw->band))
  2672. brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
  2673. else
  2674. brcms_err(core, "%s: wl%d: unsupported phy in corerev"
  2675. " %d\n", __func__, wlc_hw->unit,
  2676. wlc_hw->corerev);
  2677. } else {
  2678. brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
  2679. __func__, wlc_hw->unit, wlc_hw->corerev);
  2680. }
  2681. /* For old ucode, txfifo sizes needs to be modified(increased) */
  2682. if (fifosz_fixup)
  2683. brcms_b_corerev_fifofixup(wlc_hw);
  2684. /* check txfifo allocations match between ucode and driver */
  2685. buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
  2686. if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
  2687. i = TX_AC_BE_FIFO;
  2688. err = -1;
  2689. }
  2690. buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
  2691. if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
  2692. i = TX_AC_VI_FIFO;
  2693. err = -1;
  2694. }
  2695. buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
  2696. buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
  2697. buf[TX_AC_BK_FIFO] &= 0xff;
  2698. if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
  2699. i = TX_AC_BK_FIFO;
  2700. err = -1;
  2701. }
  2702. if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
  2703. i = TX_AC_VO_FIFO;
  2704. err = -1;
  2705. }
  2706. buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
  2707. buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
  2708. buf[TX_BCMC_FIFO] &= 0xff;
  2709. if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
  2710. i = TX_BCMC_FIFO;
  2711. err = -1;
  2712. }
  2713. if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
  2714. i = TX_ATIM_FIFO;
  2715. err = -1;
  2716. }
  2717. if (err != 0)
  2718. brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
  2719. " driver size %d index %d\n", buf[i],
  2720. wlc_hw->xmtfifo_sz[i], i);
  2721. /* make sure we can still talk to the mac */
  2722. WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
  2723. /* band-specific inits done by wlc_bsinit() */
  2724. /* Set up frame burst size and antenna swap threshold init values */
  2725. brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
  2726. brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
  2727. /* enable one rx interrupt per received frame */
  2728. bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
  2729. /* set the station mode (BSS STA) */
  2730. brcms_b_mctrl(wlc_hw,
  2731. (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
  2732. (MCTL_INFRA | MCTL_DISCARD_PMQ));
  2733. /* set up Beacon interval */
  2734. bcnint_us = 0x8000 << 10;
  2735. bcma_write32(core, D11REGOFFS(tsf_cfprep),
  2736. (bcnint_us << CFPREP_CBI_SHIFT));
  2737. bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
  2738. bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
  2739. /* write interrupt mask */
  2740. bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
  2741. DEF_RXINTMASK);
  2742. /* allow the MAC to control the PHY clock (dynamic on/off) */
  2743. brcms_b_macphyclk_set(wlc_hw, ON);
  2744. /* program dynamic clock control fast powerup delay register */
  2745. wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
  2746. bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
  2747. /* tell the ucode the corerev */
  2748. brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
  2749. /* tell the ucode MAC capabilities */
  2750. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
  2751. (u16) (wlc_hw->machwcap & 0xffff));
  2752. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
  2753. (u16) ((wlc_hw->
  2754. machwcap >> 16) & 0xffff));
  2755. /* write retry limits to SCR, this done after PSM init */
  2756. bcma_write32(core, D11REGOFFS(objaddr),
  2757. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2758. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2759. bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
  2760. bcma_write32(core, D11REGOFFS(objaddr),
  2761. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2762. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2763. bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
  2764. /* write rate fallback retry limits */
  2765. brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
  2766. brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
  2767. bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
  2768. bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
  2769. /* init the tx dma engines */
  2770. for (i = 0; i < NFIFO; i++) {
  2771. if (wlc_hw->di[i])
  2772. dma_txinit(wlc_hw->di[i]);
  2773. }
  2774. /* init the rx dma engine(s) and post receive buffers */
  2775. dma_rxinit(wlc_hw->di[RX_FIFO]);
  2776. dma_rxfill(wlc_hw->di[RX_FIFO]);
  2777. }
  2778. void
  2779. static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
  2780. u32 macintmask;
  2781. bool fastclk;
  2782. struct brcms_c_info *wlc = wlc_hw->wlc;
  2783. /* request FAST clock if not on */
  2784. fastclk = wlc_hw->forcefastclk;
  2785. if (!fastclk)
  2786. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  2787. /* disable interrupts */
  2788. macintmask = brcms_intrsoff(wlc->wl);
  2789. /* set up the specified band and chanspec */
  2790. brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
  2791. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  2792. /* do one-time phy inits and calibration */
  2793. wlc_phy_cal_init(wlc_hw->band->pi);
  2794. /* core-specific initialization */
  2795. brcms_b_coreinit(wlc);
  2796. /* band-specific inits */
  2797. brcms_b_bsinit(wlc, chanspec);
  2798. /* restore macintmask */
  2799. brcms_intrsrestore(wlc->wl, macintmask);
  2800. /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
  2801. * is suspended and brcms_c_enable_mac() will clear this override bit.
  2802. */
  2803. mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2804. /*
  2805. * initialize mac_suspend_depth to 1 to match ucode
  2806. * initial suspended state
  2807. */
  2808. wlc_hw->mac_suspend_depth = 1;
  2809. /* restore the clk */
  2810. if (!fastclk)
  2811. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  2812. }
  2813. static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
  2814. u16 chanspec)
  2815. {
  2816. /* Save our copy of the chanspec */
  2817. wlc->chanspec = chanspec;
  2818. /* Set the chanspec and power limits for this locale */
  2819. brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
  2820. if (wlc->stf->ss_algosel_auto)
  2821. brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
  2822. chanspec);
  2823. brcms_c_stf_ss_update(wlc, wlc->band);
  2824. }
  2825. static void
  2826. brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
  2827. {
  2828. brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
  2829. wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
  2830. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  2831. brcms_chspec_bw(wlc->default_bss->chanspec),
  2832. wlc->stf->txstreams);
  2833. }
  2834. /* derive wlc->band->basic_rate[] table from 'rateset' */
  2835. static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
  2836. struct brcms_c_rateset *rateset)
  2837. {
  2838. u8 rate;
  2839. u8 mandatory;
  2840. u8 cck_basic = 0;
  2841. u8 ofdm_basic = 0;
  2842. u8 *br = wlc->band->basic_rate;
  2843. uint i;
  2844. /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
  2845. memset(br, 0, BRCM_MAXRATE + 1);
  2846. /* For each basic rate in the rates list, make an entry in the
  2847. * best basic lookup.
  2848. */
  2849. for (i = 0; i < rateset->count; i++) {
  2850. /* only make an entry for a basic rate */
  2851. if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
  2852. continue;
  2853. /* mask off basic bit */
  2854. rate = (rateset->rates[i] & BRCMS_RATE_MASK);
  2855. if (rate > BRCM_MAXRATE) {
  2856. brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
  2857. "invalid rate 0x%X in rate set\n",
  2858. rateset->rates[i]);
  2859. continue;
  2860. }
  2861. br[rate] = rate;
  2862. }
  2863. /* The rate lookup table now has non-zero entries for each
  2864. * basic rate, equal to the basic rate: br[basicN] = basicN
  2865. *
  2866. * To look up the best basic rate corresponding to any
  2867. * particular rate, code can use the basic_rate table
  2868. * like this
  2869. *
  2870. * basic_rate = wlc->band->basic_rate[tx_rate]
  2871. *
  2872. * Make sure there is a best basic rate entry for
  2873. * every rate by walking up the table from low rates
  2874. * to high, filling in holes in the lookup table
  2875. */
  2876. for (i = 0; i < wlc->band->hw_rateset.count; i++) {
  2877. rate = wlc->band->hw_rateset.rates[i];
  2878. if (br[rate] != 0) {
  2879. /* This rate is a basic rate.
  2880. * Keep track of the best basic rate so far by
  2881. * modulation type.
  2882. */
  2883. if (is_ofdm_rate(rate))
  2884. ofdm_basic = rate;
  2885. else
  2886. cck_basic = rate;
  2887. continue;
  2888. }
  2889. /* This rate is not a basic rate so figure out the
  2890. * best basic rate less than this rate and fill in
  2891. * the hole in the table
  2892. */
  2893. br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
  2894. if (br[rate] != 0)
  2895. continue;
  2896. if (is_ofdm_rate(rate)) {
  2897. /*
  2898. * In 11g and 11a, the OFDM mandatory rates
  2899. * are 6, 12, and 24 Mbps
  2900. */
  2901. if (rate >= BRCM_RATE_24M)
  2902. mandatory = BRCM_RATE_24M;
  2903. else if (rate >= BRCM_RATE_12M)
  2904. mandatory = BRCM_RATE_12M;
  2905. else
  2906. mandatory = BRCM_RATE_6M;
  2907. } else {
  2908. /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
  2909. mandatory = rate;
  2910. }
  2911. br[rate] = mandatory;
  2912. }
  2913. }
  2914. static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
  2915. u16 chanspec)
  2916. {
  2917. struct brcms_c_rateset default_rateset;
  2918. uint parkband;
  2919. uint i, band_order[2];
  2920. /*
  2921. * We might have been bandlocked during down and the chip
  2922. * power-cycled (hibernate). Figure out the right band to park on
  2923. */
  2924. if (wlc->bandlocked || wlc->pub->_nbands == 1) {
  2925. /* updated in brcms_c_bandlock() */
  2926. parkband = wlc->band->bandunit;
  2927. band_order[0] = band_order[1] = parkband;
  2928. } else {
  2929. /* park on the band of the specified chanspec */
  2930. parkband = chspec_bandunit(chanspec);
  2931. /* order so that parkband initialize last */
  2932. band_order[0] = parkband ^ 1;
  2933. band_order[1] = parkband;
  2934. }
  2935. /* make each band operational, software state init */
  2936. for (i = 0; i < wlc->pub->_nbands; i++) {
  2937. uint j = band_order[i];
  2938. wlc->band = wlc->bandstate[j];
  2939. brcms_default_rateset(wlc, &default_rateset);
  2940. /* fill in hw_rate */
  2941. brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
  2942. false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  2943. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  2944. /* init basic rate lookup */
  2945. brcms_c_rate_lookup_init(wlc, &default_rateset);
  2946. }
  2947. /* sync up phy/radio chanspec */
  2948. brcms_c_set_phy_chanspec(wlc, chanspec);
  2949. }
  2950. /*
  2951. * Set or clear filtering related maccontrol bits based on
  2952. * specified filter flags
  2953. */
  2954. void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
  2955. {
  2956. u32 promisc_bits = 0;
  2957. wlc->filter_flags = filter_flags;
  2958. if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
  2959. promisc_bits |= MCTL_PROMISC;
  2960. if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
  2961. promisc_bits |= MCTL_BCNS_PROMISC;
  2962. if (filter_flags & FIF_FCSFAIL)
  2963. promisc_bits |= MCTL_KEEPBADFCS;
  2964. if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
  2965. promisc_bits |= MCTL_KEEPCONTROL;
  2966. brcms_b_mctrl(wlc->hw,
  2967. MCTL_PROMISC | MCTL_BCNS_PROMISC |
  2968. MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
  2969. promisc_bits);
  2970. }
  2971. /*
  2972. * ucode, hwmac update
  2973. * Channel dependent updates for ucode and hw
  2974. */
  2975. static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
  2976. {
  2977. /* enable or disable any active IBSSs depending on whether or not
  2978. * we are on the home channel
  2979. */
  2980. if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
  2981. if (wlc->pub->associated) {
  2982. /*
  2983. * BMAC_NOTE: This is something that should be fixed
  2984. * in ucode inits. I think that the ucode inits set
  2985. * up the bcn templates and shm values with a bogus
  2986. * beacon. This should not be done in the inits. If
  2987. * ucode needs to set up a beacon for testing, the
  2988. * test routines should write it down, not expect the
  2989. * inits to populate a bogus beacon.
  2990. */
  2991. if (BRCMS_PHY_11N_CAP(wlc->band))
  2992. brcms_b_write_shm(wlc->hw,
  2993. M_BCN_TXTSF_OFFSET, 0);
  2994. }
  2995. } else {
  2996. /* disable an active IBSS if we are not on the home channel */
  2997. }
  2998. }
  2999. static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
  3000. u8 basic_rate)
  3001. {
  3002. u8 phy_rate, index;
  3003. u8 basic_phy_rate, basic_index;
  3004. u16 dir_table, basic_table;
  3005. u16 basic_ptr;
  3006. /* Shared memory address for the table we are reading */
  3007. dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
  3008. /* Shared memory address for the table we are writing */
  3009. basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
  3010. /*
  3011. * for a given rate, the LS-nibble of the PLCP SIGNAL field is
  3012. * the index into the rate table.
  3013. */
  3014. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  3015. basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
  3016. index = phy_rate & 0xf;
  3017. basic_index = basic_phy_rate & 0xf;
  3018. /* Find the SHM pointer to the ACK rate entry by looking in the
  3019. * Direct-map Table
  3020. */
  3021. basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
  3022. /* Update the SHM BSS-basic-rate-set mapping table with the pointer
  3023. * to the correct basic rate for the given incoming rate
  3024. */
  3025. brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
  3026. }
  3027. static const struct brcms_c_rateset *
  3028. brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
  3029. {
  3030. const struct brcms_c_rateset *rs_dflt;
  3031. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  3032. if (wlc->band->bandtype == BRCM_BAND_5G)
  3033. rs_dflt = &ofdm_mimo_rates;
  3034. else
  3035. rs_dflt = &cck_ofdm_mimo_rates;
  3036. } else if (wlc->band->gmode)
  3037. rs_dflt = &cck_ofdm_rates;
  3038. else
  3039. rs_dflt = &cck_rates;
  3040. return rs_dflt;
  3041. }
  3042. static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
  3043. {
  3044. const struct brcms_c_rateset *rs_dflt;
  3045. struct brcms_c_rateset rs;
  3046. u8 rate, basic_rate;
  3047. uint i;
  3048. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  3049. brcms_c_rateset_copy(rs_dflt, &rs);
  3050. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  3051. /* walk the phy rate table and update SHM basic rate lookup table */
  3052. for (i = 0; i < rs.count; i++) {
  3053. rate = rs.rates[i] & BRCMS_RATE_MASK;
  3054. /* for a given rate brcms_basic_rate returns the rate at
  3055. * which a response ACK/CTS should be sent.
  3056. */
  3057. basic_rate = brcms_basic_rate(wlc, rate);
  3058. if (basic_rate == 0)
  3059. /* This should only happen if we are using a
  3060. * restricted rateset.
  3061. */
  3062. basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
  3063. brcms_c_write_rate_shm(wlc, rate, basic_rate);
  3064. }
  3065. }
  3066. /* band-specific init */
  3067. static void brcms_c_bsinit(struct brcms_c_info *wlc)
  3068. {
  3069. brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
  3070. wlc->pub->unit, wlc->band->bandunit);
  3071. /* write ucode ACK/CTS rate table */
  3072. brcms_c_set_ratetable(wlc);
  3073. /* update some band specific mac configuration */
  3074. brcms_c_ucode_mac_upd(wlc);
  3075. /* init antenna selection */
  3076. brcms_c_antsel_init(wlc->asi);
  3077. }
  3078. /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
  3079. static int
  3080. brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
  3081. bool writeToShm)
  3082. {
  3083. int idle_busy_ratio_x_16 = 0;
  3084. uint offset =
  3085. isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
  3086. M_TX_IDLE_BUSY_RATIO_X_16_CCK;
  3087. if (duty_cycle > 100 || duty_cycle < 0) {
  3088. brcms_err(wlc->hw->d11core,
  3089. "wl%d: duty cycle value off limit\n",
  3090. wlc->pub->unit);
  3091. return -EINVAL;
  3092. }
  3093. if (duty_cycle)
  3094. idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
  3095. /* Only write to shared memory when wl is up */
  3096. if (writeToShm)
  3097. brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
  3098. if (isOFDM)
  3099. wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
  3100. else
  3101. wlc->tx_duty_cycle_cck = (u16) duty_cycle;
  3102. return 0;
  3103. }
  3104. /* push sw hps and wake state through hardware */
  3105. static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
  3106. {
  3107. u32 v1, v2;
  3108. bool hps;
  3109. bool awake_before;
  3110. hps = brcms_c_ps_allowed(wlc);
  3111. brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
  3112. hps);
  3113. v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
  3114. v2 = MCTL_WAKE;
  3115. if (hps)
  3116. v2 |= MCTL_HPS;
  3117. brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
  3118. awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
  3119. if (!awake_before)
  3120. brcms_b_wait_for_wake(wlc->hw);
  3121. }
  3122. /*
  3123. * Write this BSS config's MAC address to core.
  3124. * Updates RXE match engine.
  3125. */
  3126. static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
  3127. {
  3128. int err = 0;
  3129. struct brcms_c_info *wlc = bsscfg->wlc;
  3130. /* enter the MAC addr into the RXE match registers */
  3131. brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
  3132. brcms_c_ampdu_macaddr_upd(wlc);
  3133. return err;
  3134. }
  3135. /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
  3136. * Updates RXE match engine.
  3137. */
  3138. static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
  3139. {
  3140. /* we need to update BSSID in RXE match registers */
  3141. brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
  3142. }
  3143. static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
  3144. {
  3145. wlc_hw->shortslot = shortslot;
  3146. if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
  3147. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  3148. brcms_b_update_slot_timing(wlc_hw, shortslot);
  3149. brcms_c_enable_mac(wlc_hw->wlc);
  3150. }
  3151. }
  3152. /*
  3153. * Suspend the the MAC and update the slot timing
  3154. * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
  3155. */
  3156. static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
  3157. {
  3158. /* use the override if it is set */
  3159. if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
  3160. shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
  3161. if (wlc->shortslot == shortslot)
  3162. return;
  3163. wlc->shortslot = shortslot;
  3164. brcms_b_set_shortslot(wlc->hw, shortslot);
  3165. }
  3166. static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3167. {
  3168. if (wlc->home_chanspec != chanspec) {
  3169. wlc->home_chanspec = chanspec;
  3170. if (wlc->pub->associated)
  3171. wlc->bsscfg->current_bss->chanspec = chanspec;
  3172. }
  3173. }
  3174. void
  3175. brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
  3176. bool mute_tx, struct txpwr_limits *txpwr)
  3177. {
  3178. uint bandunit;
  3179. brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
  3180. chanspec);
  3181. wlc_hw->chanspec = chanspec;
  3182. /* Switch bands if necessary */
  3183. if (wlc_hw->_nbands > 1) {
  3184. bandunit = chspec_bandunit(chanspec);
  3185. if (wlc_hw->band->bandunit != bandunit) {
  3186. /* brcms_b_setband disables other bandunit,
  3187. * use light band switch if not up yet
  3188. */
  3189. if (wlc_hw->up) {
  3190. wlc_phy_chanspec_radio_set(wlc_hw->
  3191. bandstate[bandunit]->
  3192. pi, chanspec);
  3193. brcms_b_setband(wlc_hw, bandunit, chanspec);
  3194. } else {
  3195. brcms_c_setxband(wlc_hw, bandunit);
  3196. }
  3197. }
  3198. }
  3199. wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
  3200. if (!wlc_hw->up) {
  3201. if (wlc_hw->clk)
  3202. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
  3203. chanspec);
  3204. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  3205. } else {
  3206. wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
  3207. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
  3208. /* Update muting of the channel */
  3209. brcms_b_mute(wlc_hw, mute_tx);
  3210. }
  3211. }
  3212. /* switch to and initialize new band */
  3213. static void brcms_c_setband(struct brcms_c_info *wlc,
  3214. uint bandunit)
  3215. {
  3216. wlc->band = wlc->bandstate[bandunit];
  3217. if (!wlc->pub->up)
  3218. return;
  3219. /* wait for at least one beacon before entering sleeping state */
  3220. brcms_c_set_ps_ctrl(wlc);
  3221. /* band-specific initializations */
  3222. brcms_c_bsinit(wlc);
  3223. }
  3224. static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3225. {
  3226. uint bandunit;
  3227. bool switchband = false;
  3228. u16 old_chanspec = wlc->chanspec;
  3229. if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
  3230. brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
  3231. wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
  3232. return;
  3233. }
  3234. /* Switch bands if necessary */
  3235. if (wlc->pub->_nbands > 1) {
  3236. bandunit = chspec_bandunit(chanspec);
  3237. if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
  3238. switchband = true;
  3239. if (wlc->bandlocked) {
  3240. brcms_err(wlc->hw->d11core,
  3241. "wl%d: %s: chspec %d band is locked!\n",
  3242. wlc->pub->unit, __func__,
  3243. CHSPEC_CHANNEL(chanspec));
  3244. return;
  3245. }
  3246. /*
  3247. * should the setband call come after the
  3248. * brcms_b_chanspec() ? if the setband updates
  3249. * (brcms_c_bsinit) use low level calls to inspect and
  3250. * set state, the state inspected may be from the wrong
  3251. * band, or the following brcms_b_set_chanspec() may
  3252. * undo the work.
  3253. */
  3254. brcms_c_setband(wlc, bandunit);
  3255. }
  3256. }
  3257. /* sync up phy/radio chanspec */
  3258. brcms_c_set_phy_chanspec(wlc, chanspec);
  3259. /* init antenna selection */
  3260. if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
  3261. brcms_c_antsel_init(wlc->asi);
  3262. /* Fix the hardware rateset based on bw.
  3263. * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
  3264. */
  3265. brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
  3266. wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
  3267. }
  3268. /* update some mac configuration since chanspec changed */
  3269. brcms_c_ucode_mac_upd(wlc);
  3270. }
  3271. /*
  3272. * This function changes the phytxctl for beacon based on current
  3273. * beacon ratespec AND txant setting as per this table:
  3274. * ratespec CCK ant = wlc->stf->txant
  3275. * OFDM ant = 3
  3276. */
  3277. void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
  3278. u32 bcn_rspec)
  3279. {
  3280. u16 phyctl;
  3281. u16 phytxant = wlc->stf->phytxant;
  3282. u16 mask = PHY_TXC_ANT_MASK;
  3283. /* for non-siso rates or default setting, use the available chains */
  3284. if (BRCMS_PHY_11N_CAP(wlc->band))
  3285. phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
  3286. phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
  3287. phyctl = (phyctl & ~mask) | phytxant;
  3288. brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
  3289. }
  3290. /*
  3291. * centralized protection config change function to simplify debugging, no
  3292. * consistency checking this should be called only on changes to avoid overhead
  3293. * in periodic function
  3294. */
  3295. void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
  3296. {
  3297. /*
  3298. * Cannot use brcms_dbg_* here because this function is called
  3299. * before wlc is sufficiently initialized.
  3300. */
  3301. BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
  3302. switch (idx) {
  3303. case BRCMS_PROT_G_SPEC:
  3304. wlc->protection->_g = (bool) val;
  3305. break;
  3306. case BRCMS_PROT_G_OVR:
  3307. wlc->protection->g_override = (s8) val;
  3308. break;
  3309. case BRCMS_PROT_G_USER:
  3310. wlc->protection->gmode_user = (u8) val;
  3311. break;
  3312. case BRCMS_PROT_OVERLAP:
  3313. wlc->protection->overlap = (s8) val;
  3314. break;
  3315. case BRCMS_PROT_N_USER:
  3316. wlc->protection->nmode_user = (s8) val;
  3317. break;
  3318. case BRCMS_PROT_N_CFG:
  3319. wlc->protection->n_cfg = (s8) val;
  3320. break;
  3321. case BRCMS_PROT_N_CFG_OVR:
  3322. wlc->protection->n_cfg_override = (s8) val;
  3323. break;
  3324. case BRCMS_PROT_N_NONGF:
  3325. wlc->protection->nongf = (bool) val;
  3326. break;
  3327. case BRCMS_PROT_N_NONGF_OVR:
  3328. wlc->protection->nongf_override = (s8) val;
  3329. break;
  3330. case BRCMS_PROT_N_PAM_OVR:
  3331. wlc->protection->n_pam_override = (s8) val;
  3332. break;
  3333. case BRCMS_PROT_N_OBSS:
  3334. wlc->protection->n_obss = (bool) val;
  3335. break;
  3336. default:
  3337. break;
  3338. }
  3339. }
  3340. static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
  3341. {
  3342. if (wlc->pub->up) {
  3343. brcms_c_update_beacon(wlc);
  3344. brcms_c_update_probe_resp(wlc, true);
  3345. }
  3346. }
  3347. static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
  3348. {
  3349. wlc->stf->ldpc = val;
  3350. if (wlc->pub->up) {
  3351. brcms_c_update_beacon(wlc);
  3352. brcms_c_update_probe_resp(wlc, true);
  3353. wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
  3354. }
  3355. }
  3356. void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
  3357. const struct ieee80211_tx_queue_params *params,
  3358. bool suspend)
  3359. {
  3360. int i;
  3361. struct shm_acparams acp_shm;
  3362. u16 *shm_entry;
  3363. /* Only apply params if the core is out of reset and has clocks */
  3364. if (!wlc->clk) {
  3365. brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
  3366. wlc->pub->unit, __func__);
  3367. return;
  3368. }
  3369. memset(&acp_shm, 0, sizeof(struct shm_acparams));
  3370. /* fill in shm ac params struct */
  3371. acp_shm.txop = params->txop;
  3372. /* convert from units of 32us to us for ucode */
  3373. wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
  3374. EDCF_TXOP2USEC(acp_shm.txop);
  3375. acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
  3376. if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
  3377. && acp_shm.aifs < EDCF_AIFSN_MAX)
  3378. acp_shm.aifs++;
  3379. if (acp_shm.aifs < EDCF_AIFSN_MIN
  3380. || acp_shm.aifs > EDCF_AIFSN_MAX) {
  3381. brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
  3382. "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
  3383. } else {
  3384. acp_shm.cwmin = params->cw_min;
  3385. acp_shm.cwmax = params->cw_max;
  3386. acp_shm.cwcur = acp_shm.cwmin;
  3387. acp_shm.bslots =
  3388. bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
  3389. acp_shm.cwcur;
  3390. acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
  3391. /* Indicate the new params to the ucode */
  3392. acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
  3393. wme_ac2fifo[aci] *
  3394. M_EDCF_QLEN +
  3395. M_EDCF_STATUS_OFF));
  3396. acp_shm.status |= WME_STATUS_NEWAC;
  3397. /* Fill in shm acparam table */
  3398. shm_entry = (u16 *) &acp_shm;
  3399. for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
  3400. brcms_b_write_shm(wlc->hw,
  3401. M_EDCF_QINFO +
  3402. wme_ac2fifo[aci] * M_EDCF_QLEN + i,
  3403. *shm_entry++);
  3404. }
  3405. if (suspend) {
  3406. brcms_c_suspend_mac_and_wait(wlc);
  3407. brcms_c_enable_mac(wlc);
  3408. }
  3409. }
  3410. static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
  3411. {
  3412. u16 aci;
  3413. int i_ac;
  3414. struct ieee80211_tx_queue_params txq_pars;
  3415. static const struct edcf_acparam default_edcf_acparams[] = {
  3416. {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
  3417. {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
  3418. {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
  3419. {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
  3420. }; /* ucode needs these parameters during its initialization */
  3421. const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
  3422. for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
  3423. /* find out which ac this set of params applies to */
  3424. aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
  3425. /* fill in shm ac params struct */
  3426. txq_pars.txop = edcf_acp->TXOP;
  3427. txq_pars.aifs = edcf_acp->ACI;
  3428. /* CWmin = 2^(ECWmin) - 1 */
  3429. txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
  3430. /* CWmax = 2^(ECWmax) - 1 */
  3431. txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
  3432. >> EDCF_ECWMAX_SHIFT);
  3433. brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
  3434. }
  3435. if (suspend) {
  3436. brcms_c_suspend_mac_and_wait(wlc);
  3437. brcms_c_enable_mac(wlc);
  3438. }
  3439. }
  3440. static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
  3441. {
  3442. /* Don't start the timer if HWRADIO feature is disabled */
  3443. if (wlc->radio_monitor)
  3444. return;
  3445. wlc->radio_monitor = true;
  3446. brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
  3447. brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
  3448. }
  3449. static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
  3450. {
  3451. if (!wlc->radio_monitor)
  3452. return true;
  3453. wlc->radio_monitor = false;
  3454. brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
  3455. return brcms_del_timer(wlc->radio_timer);
  3456. }
  3457. /* read hwdisable state and propagate to wlc flag */
  3458. static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
  3459. {
  3460. if (wlc->pub->hw_off)
  3461. return;
  3462. if (brcms_b_radio_read_hwdisabled(wlc->hw))
  3463. mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3464. else
  3465. mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3466. }
  3467. /* update hwradio status and return it */
  3468. bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
  3469. {
  3470. brcms_c_radio_hwdisable_upd(wlc);
  3471. return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
  3472. true : false;
  3473. }
  3474. /* periodical query hw radio button while driver is "down" */
  3475. static void brcms_c_radio_timer(void *arg)
  3476. {
  3477. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3478. if (brcms_deviceremoved(wlc)) {
  3479. brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
  3480. wlc->pub->unit, __func__);
  3481. brcms_down(wlc->wl);
  3482. return;
  3483. }
  3484. brcms_c_radio_hwdisable_upd(wlc);
  3485. }
  3486. /* common low-level watchdog code */
  3487. static void brcms_b_watchdog(struct brcms_c_info *wlc)
  3488. {
  3489. struct brcms_hardware *wlc_hw = wlc->hw;
  3490. if (!wlc_hw->up)
  3491. return;
  3492. /* increment second count */
  3493. wlc_hw->now++;
  3494. /* Check for FIFO error interrupts */
  3495. brcms_b_fifoerrors(wlc_hw);
  3496. /* make sure RX dma has buffers */
  3497. dma_rxfill(wlc->hw->di[RX_FIFO]);
  3498. wlc_phy_watchdog(wlc_hw->band->pi);
  3499. }
  3500. /* common watchdog code */
  3501. static void brcms_c_watchdog(struct brcms_c_info *wlc)
  3502. {
  3503. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  3504. if (!wlc->pub->up)
  3505. return;
  3506. if (brcms_deviceremoved(wlc)) {
  3507. brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
  3508. wlc->pub->unit, __func__);
  3509. brcms_down(wlc->wl);
  3510. return;
  3511. }
  3512. /* increment second count */
  3513. wlc->pub->now++;
  3514. brcms_c_radio_hwdisable_upd(wlc);
  3515. /* if radio is disable, driver may be down, quit here */
  3516. if (wlc->pub->radio_disabled)
  3517. return;
  3518. brcms_b_watchdog(wlc);
  3519. /*
  3520. * occasionally sample mac stat counters to
  3521. * detect 16-bit counter wrap
  3522. */
  3523. if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
  3524. brcms_c_statsupd(wlc);
  3525. if (BRCMS_ISNPHY(wlc->band) &&
  3526. ((wlc->pub->now - wlc->tempsense_lasttime) >=
  3527. BRCMS_TEMPSENSE_PERIOD)) {
  3528. wlc->tempsense_lasttime = wlc->pub->now;
  3529. brcms_c_tempsense_upd(wlc);
  3530. }
  3531. }
  3532. static void brcms_c_watchdog_by_timer(void *arg)
  3533. {
  3534. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3535. brcms_c_watchdog(wlc);
  3536. }
  3537. static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
  3538. {
  3539. wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
  3540. wlc, "watchdog");
  3541. if (!wlc->wdtimer) {
  3542. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
  3543. "failed\n", unit);
  3544. goto fail;
  3545. }
  3546. wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
  3547. wlc, "radio");
  3548. if (!wlc->radio_timer) {
  3549. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
  3550. "failed\n", unit);
  3551. goto fail;
  3552. }
  3553. return true;
  3554. fail:
  3555. return false;
  3556. }
  3557. /*
  3558. * Initialize brcms_c_info default values ...
  3559. * may get overrides later in this function
  3560. */
  3561. static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
  3562. {
  3563. int i;
  3564. /* Save our copy of the chanspec */
  3565. wlc->chanspec = ch20mhz_chspec(1);
  3566. /* various 802.11g modes */
  3567. wlc->shortslot = false;
  3568. wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
  3569. brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
  3570. brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
  3571. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
  3572. BRCMS_PROTECTION_AUTO);
  3573. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
  3574. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
  3575. BRCMS_PROTECTION_AUTO);
  3576. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
  3577. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
  3578. brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
  3579. BRCMS_PROTECTION_CTL_OVERLAP);
  3580. /* 802.11g draft 4.0 NonERP elt advertisement */
  3581. wlc->include_legacy_erp = true;
  3582. wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
  3583. wlc->stf->txant = ANT_TX_DEF;
  3584. wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
  3585. wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
  3586. for (i = 0; i < NFIFO; i++)
  3587. wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
  3588. wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
  3589. /* default rate fallback retry limits */
  3590. wlc->SFBL = RETRY_SHORT_FB;
  3591. wlc->LFBL = RETRY_LONG_FB;
  3592. /* default mac retry limits */
  3593. wlc->SRL = RETRY_SHORT_DEF;
  3594. wlc->LRL = RETRY_LONG_DEF;
  3595. /* WME QoS mode is Auto by default */
  3596. wlc->pub->_ampdu = AMPDU_AGG_HOST;
  3597. wlc->pub->bcmerror = 0;
  3598. }
  3599. static uint brcms_c_attach_module(struct brcms_c_info *wlc)
  3600. {
  3601. uint err = 0;
  3602. uint unit;
  3603. unit = wlc->pub->unit;
  3604. wlc->asi = brcms_c_antsel_attach(wlc);
  3605. if (wlc->asi == NULL) {
  3606. wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
  3607. "failed\n", unit);
  3608. err = 44;
  3609. goto fail;
  3610. }
  3611. wlc->ampdu = brcms_c_ampdu_attach(wlc);
  3612. if (wlc->ampdu == NULL) {
  3613. wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
  3614. "failed\n", unit);
  3615. err = 50;
  3616. goto fail;
  3617. }
  3618. if ((brcms_c_stf_attach(wlc) != 0)) {
  3619. wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
  3620. "failed\n", unit);
  3621. err = 68;
  3622. goto fail;
  3623. }
  3624. fail:
  3625. return err;
  3626. }
  3627. struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
  3628. {
  3629. return wlc->pub;
  3630. }
  3631. /* low level attach
  3632. * run backplane attach, init nvram
  3633. * run phy attach
  3634. * initialize software state for each core and band
  3635. * put the whole chip in reset(driver down state), no clock
  3636. */
  3637. static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
  3638. uint unit, bool piomode)
  3639. {
  3640. struct brcms_hardware *wlc_hw;
  3641. uint err = 0;
  3642. uint j;
  3643. bool wme = false;
  3644. struct shared_phy_params sha_params;
  3645. struct wiphy *wiphy = wlc->wiphy;
  3646. struct pci_dev *pcidev = core->bus->host_pci;
  3647. struct ssb_sprom *sprom = &core->bus->sprom;
  3648. if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
  3649. brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
  3650. pcidev->vendor,
  3651. pcidev->device);
  3652. else
  3653. brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
  3654. core->bus->boardinfo.vendor,
  3655. core->bus->boardinfo.type);
  3656. wme = true;
  3657. wlc_hw = wlc->hw;
  3658. wlc_hw->wlc = wlc;
  3659. wlc_hw->unit = unit;
  3660. wlc_hw->band = wlc_hw->bandstate[0];
  3661. wlc_hw->_piomode = piomode;
  3662. /* populate struct brcms_hardware with default values */
  3663. brcms_b_info_init(wlc_hw);
  3664. /*
  3665. * Do the hardware portion of the attach. Also initialize software
  3666. * state that depends on the particular hardware we are running.
  3667. */
  3668. wlc_hw->sih = ai_attach(core->bus);
  3669. if (wlc_hw->sih == NULL) {
  3670. wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
  3671. unit);
  3672. err = 11;
  3673. goto fail;
  3674. }
  3675. /* verify again the device is supported */
  3676. if (!brcms_c_chipmatch(core)) {
  3677. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
  3678. unit);
  3679. err = 12;
  3680. goto fail;
  3681. }
  3682. if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
  3683. wlc_hw->vendorid = pcidev->vendor;
  3684. wlc_hw->deviceid = pcidev->device;
  3685. } else {
  3686. wlc_hw->vendorid = core->bus->boardinfo.vendor;
  3687. wlc_hw->deviceid = core->bus->boardinfo.type;
  3688. }
  3689. wlc_hw->d11core = core;
  3690. wlc_hw->corerev = core->id.rev;
  3691. /* validate chip, chiprev and corerev */
  3692. if (!brcms_c_isgoodchip(wlc_hw)) {
  3693. err = 13;
  3694. goto fail;
  3695. }
  3696. /* initialize power control registers */
  3697. ai_clkctl_init(wlc_hw->sih);
  3698. /* request fastclock and force fastclock for the rest of attach
  3699. * bring the d11 core out of reset.
  3700. * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
  3701. * is still false; But it will be called again inside wlc_corereset,
  3702. * after d11 is out of reset.
  3703. */
  3704. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  3705. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  3706. if (!brcms_b_validate_chip_access(wlc_hw)) {
  3707. wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
  3708. "failed\n", unit);
  3709. err = 14;
  3710. goto fail;
  3711. }
  3712. /* get the board rev, used just below */
  3713. j = sprom->board_rev;
  3714. /* promote srom boardrev of 0xFF to 1 */
  3715. if (j == BOARDREV_PROMOTABLE)
  3716. j = BOARDREV_PROMOTED;
  3717. wlc_hw->boardrev = (u16) j;
  3718. if (!brcms_c_validboardtype(wlc_hw)) {
  3719. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
  3720. "board type (0x%x)" " or revision level (0x%x)\n",
  3721. unit, ai_get_boardtype(wlc_hw->sih),
  3722. wlc_hw->boardrev);
  3723. err = 15;
  3724. goto fail;
  3725. }
  3726. wlc_hw->sromrev = sprom->revision;
  3727. wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
  3728. wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
  3729. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  3730. brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
  3731. /* check device id(srom, nvram etc.) to set bands */
  3732. if (wlc_hw->deviceid == BCM43224_D11N_ID ||
  3733. wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
  3734. wlc_hw->deviceid == BCM43224_CHIP_ID)
  3735. /* Dualband boards */
  3736. wlc_hw->_nbands = 2;
  3737. else
  3738. wlc_hw->_nbands = 1;
  3739. if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
  3740. wlc_hw->_nbands = 1;
  3741. /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
  3742. * unconditionally does the init of these values
  3743. */
  3744. wlc->vendorid = wlc_hw->vendorid;
  3745. wlc->deviceid = wlc_hw->deviceid;
  3746. wlc->pub->sih = wlc_hw->sih;
  3747. wlc->pub->corerev = wlc_hw->corerev;
  3748. wlc->pub->sromrev = wlc_hw->sromrev;
  3749. wlc->pub->boardrev = wlc_hw->boardrev;
  3750. wlc->pub->boardflags = wlc_hw->boardflags;
  3751. wlc->pub->boardflags2 = wlc_hw->boardflags2;
  3752. wlc->pub->_nbands = wlc_hw->_nbands;
  3753. wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
  3754. if (wlc_hw->physhim == NULL) {
  3755. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
  3756. "failed\n", unit);
  3757. err = 25;
  3758. goto fail;
  3759. }
  3760. /* pass all the parameters to wlc_phy_shared_attach in one struct */
  3761. sha_params.sih = wlc_hw->sih;
  3762. sha_params.physhim = wlc_hw->physhim;
  3763. sha_params.unit = unit;
  3764. sha_params.corerev = wlc_hw->corerev;
  3765. sha_params.vid = wlc_hw->vendorid;
  3766. sha_params.did = wlc_hw->deviceid;
  3767. sha_params.chip = ai_get_chip_id(wlc_hw->sih);
  3768. sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
  3769. sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
  3770. sha_params.sromrev = wlc_hw->sromrev;
  3771. sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
  3772. sha_params.boardrev = wlc_hw->boardrev;
  3773. sha_params.boardflags = wlc_hw->boardflags;
  3774. sha_params.boardflags2 = wlc_hw->boardflags2;
  3775. /* alloc and save pointer to shared phy state area */
  3776. wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
  3777. if (!wlc_hw->phy_sh) {
  3778. err = 16;
  3779. goto fail;
  3780. }
  3781. /* initialize software state for each core and band */
  3782. for (j = 0; j < wlc_hw->_nbands; j++) {
  3783. /*
  3784. * band0 is always 2.4Ghz
  3785. * band1, if present, is 5Ghz
  3786. */
  3787. brcms_c_setxband(wlc_hw, j);
  3788. wlc_hw->band->bandunit = j;
  3789. wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3790. wlc->band->bandunit = j;
  3791. wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3792. wlc->core->coreidx = core->core_index;
  3793. wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
  3794. wlc_hw->machwcap_backup = wlc_hw->machwcap;
  3795. /* init tx fifo size */
  3796. WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
  3797. (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
  3798. ARRAY_SIZE(xmtfifo_sz));
  3799. wlc_hw->xmtfifo_sz =
  3800. xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
  3801. WARN_ON(!wlc_hw->xmtfifo_sz[0]);
  3802. /* Get a phy for this band */
  3803. wlc_hw->band->pi =
  3804. wlc_phy_attach(wlc_hw->phy_sh, core,
  3805. wlc_hw->band->bandtype,
  3806. wlc->wiphy);
  3807. if (wlc_hw->band->pi == NULL) {
  3808. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
  3809. "attach failed\n", unit);
  3810. err = 17;
  3811. goto fail;
  3812. }
  3813. wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
  3814. wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
  3815. &wlc_hw->band->phyrev,
  3816. &wlc_hw->band->radioid,
  3817. &wlc_hw->band->radiorev);
  3818. wlc_hw->band->abgphy_encore =
  3819. wlc_phy_get_encore(wlc_hw->band->pi);
  3820. wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
  3821. wlc_hw->band->core_flags =
  3822. wlc_phy_get_coreflags(wlc_hw->band->pi);
  3823. /* verify good phy_type & supported phy revision */
  3824. if (BRCMS_ISNPHY(wlc_hw->band)) {
  3825. if (NCONF_HAS(wlc_hw->band->phyrev))
  3826. goto good_phy;
  3827. else
  3828. goto bad_phy;
  3829. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  3830. if (LCNCONF_HAS(wlc_hw->band->phyrev))
  3831. goto good_phy;
  3832. else
  3833. goto bad_phy;
  3834. } else {
  3835. bad_phy:
  3836. wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
  3837. "phy type/rev (%d/%d)\n", unit,
  3838. wlc_hw->band->phytype, wlc_hw->band->phyrev);
  3839. err = 18;
  3840. goto fail;
  3841. }
  3842. good_phy:
  3843. /*
  3844. * BMAC_NOTE: wlc->band->pi should not be set below and should
  3845. * be done in the high level attach. However we can not make
  3846. * that change until all low level access is changed to
  3847. * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
  3848. * keeping wlc_hw->band->pi as well for incremental update of
  3849. * low level fns, and cut over low only init when all fns
  3850. * updated.
  3851. */
  3852. wlc->band->pi = wlc_hw->band->pi;
  3853. wlc->band->phytype = wlc_hw->band->phytype;
  3854. wlc->band->phyrev = wlc_hw->band->phyrev;
  3855. wlc->band->radioid = wlc_hw->band->radioid;
  3856. wlc->band->radiorev = wlc_hw->band->radiorev;
  3857. /* default contention windows size limits */
  3858. wlc_hw->band->CWmin = APHY_CWMIN;
  3859. wlc_hw->band->CWmax = PHY_CWMAX;
  3860. if (!brcms_b_attach_dmapio(wlc, j, wme)) {
  3861. err = 19;
  3862. goto fail;
  3863. }
  3864. }
  3865. /* disable core to match driver "down" state */
  3866. brcms_c_coredisable(wlc_hw);
  3867. /* Match driver "down" state */
  3868. ai_pci_down(wlc_hw->sih);
  3869. /* turn off pll and xtal to match driver "down" state */
  3870. brcms_b_xtal(wlc_hw, OFF);
  3871. /* *******************************************************************
  3872. * The hardware is in the DOWN state at this point. D11 core
  3873. * or cores are in reset with clocks off, and the board PLLs
  3874. * are off if possible.
  3875. *
  3876. * Beyond this point, wlc->sbclk == false and chip registers
  3877. * should not be touched.
  3878. *********************************************************************
  3879. */
  3880. /* init etheraddr state variables */
  3881. brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
  3882. if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
  3883. is_zero_ether_addr(wlc_hw->etheraddr)) {
  3884. wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
  3885. unit);
  3886. err = 22;
  3887. goto fail;
  3888. }
  3889. brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
  3890. wlc_hw->deviceid, wlc_hw->_nbands,
  3891. ai_get_boardtype(wlc_hw->sih));
  3892. return err;
  3893. fail:
  3894. wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
  3895. err);
  3896. return err;
  3897. }
  3898. static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
  3899. {
  3900. uint unit;
  3901. unit = wlc->pub->unit;
  3902. if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
  3903. /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
  3904. wlc->band->antgain = 8;
  3905. } else if (wlc->band->antgain == -1) {
  3906. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3907. " srom, using 2dB\n", unit, __func__);
  3908. wlc->band->antgain = 8;
  3909. } else {
  3910. s8 gain, fract;
  3911. /* Older sroms specified gain in whole dbm only. In order
  3912. * be able to specify qdbm granularity and remain backward
  3913. * compatible the whole dbms are now encoded in only
  3914. * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
  3915. * 6 bit signed number ranges from -32 - 31.
  3916. *
  3917. * Examples:
  3918. * 0x1 = 1 db,
  3919. * 0xc1 = 1.75 db (1 + 3 quarters),
  3920. * 0x3f = -1 (-1 + 0 quarters),
  3921. * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
  3922. * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
  3923. */
  3924. gain = wlc->band->antgain & 0x3f;
  3925. gain <<= 2; /* Sign extend */
  3926. gain >>= 2;
  3927. fract = (wlc->band->antgain & 0xc0) >> 6;
  3928. wlc->band->antgain = 4 * gain + fract;
  3929. }
  3930. }
  3931. static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
  3932. {
  3933. int aa;
  3934. uint unit;
  3935. int bandtype;
  3936. struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
  3937. unit = wlc->pub->unit;
  3938. bandtype = wlc->band->bandtype;
  3939. /* get antennas available */
  3940. if (bandtype == BRCM_BAND_5G)
  3941. aa = sprom->ant_available_a;
  3942. else
  3943. aa = sprom->ant_available_bg;
  3944. if ((aa < 1) || (aa > 15)) {
  3945. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3946. " srom (0x%x), using 3\n", unit, __func__, aa);
  3947. aa = 3;
  3948. }
  3949. /* reset the defaults if we have a single antenna */
  3950. if (aa == 1) {
  3951. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
  3952. wlc->stf->txant = ANT_TX_FORCE_0;
  3953. } else if (aa == 2) {
  3954. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
  3955. wlc->stf->txant = ANT_TX_FORCE_1;
  3956. } else {
  3957. }
  3958. /* Compute Antenna Gain */
  3959. if (bandtype == BRCM_BAND_5G)
  3960. wlc->band->antgain = sprom->antenna_gain.a1;
  3961. else
  3962. wlc->band->antgain = sprom->antenna_gain.a0;
  3963. brcms_c_attach_antgain_init(wlc);
  3964. return true;
  3965. }
  3966. static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
  3967. {
  3968. u16 chanspec;
  3969. struct brcms_band *band;
  3970. struct brcms_bss_info *bi = wlc->default_bss;
  3971. /* init default and target BSS with some sane initial values */
  3972. memset(bi, 0, sizeof(*bi));
  3973. bi->beacon_period = BEACON_INTERVAL_DEFAULT;
  3974. /* fill the default channel as the first valid channel
  3975. * starting from the 2G channels
  3976. */
  3977. chanspec = ch20mhz_chspec(1);
  3978. wlc->home_chanspec = bi->chanspec = chanspec;
  3979. /* find the band of our default channel */
  3980. band = wlc->band;
  3981. if (wlc->pub->_nbands > 1 &&
  3982. band->bandunit != chspec_bandunit(chanspec))
  3983. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  3984. /* init bss rates to the band specific default rate set */
  3985. brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
  3986. band->bandtype, false, BRCMS_RATE_MASK_FULL,
  3987. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  3988. brcms_chspec_bw(chanspec), wlc->stf->txstreams);
  3989. if (wlc->pub->_n_enab & SUPPORT_11N)
  3990. bi->flags |= BRCMS_BSS_HT;
  3991. }
  3992. static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
  3993. {
  3994. uint i;
  3995. struct brcms_band *band;
  3996. for (i = 0; i < wlc->pub->_nbands; i++) {
  3997. band = wlc->bandstate[i];
  3998. if (band->bandtype == BRCM_BAND_5G) {
  3999. if ((bwcap == BRCMS_N_BW_40ALL)
  4000. || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
  4001. band->mimo_cap_40 = true;
  4002. else
  4003. band->mimo_cap_40 = false;
  4004. } else {
  4005. if (bwcap == BRCMS_N_BW_40ALL)
  4006. band->mimo_cap_40 = true;
  4007. else
  4008. band->mimo_cap_40 = false;
  4009. }
  4010. }
  4011. }
  4012. static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
  4013. {
  4014. /* free timer state */
  4015. if (wlc->wdtimer) {
  4016. brcms_free_timer(wlc->wdtimer);
  4017. wlc->wdtimer = NULL;
  4018. }
  4019. if (wlc->radio_timer) {
  4020. brcms_free_timer(wlc->radio_timer);
  4021. wlc->radio_timer = NULL;
  4022. }
  4023. }
  4024. static void brcms_c_detach_module(struct brcms_c_info *wlc)
  4025. {
  4026. if (wlc->asi) {
  4027. brcms_c_antsel_detach(wlc->asi);
  4028. wlc->asi = NULL;
  4029. }
  4030. if (wlc->ampdu) {
  4031. brcms_c_ampdu_detach(wlc->ampdu);
  4032. wlc->ampdu = NULL;
  4033. }
  4034. brcms_c_stf_detach(wlc);
  4035. }
  4036. /*
  4037. * low level detach
  4038. */
  4039. static int brcms_b_detach(struct brcms_c_info *wlc)
  4040. {
  4041. uint i;
  4042. struct brcms_hw_band *band;
  4043. struct brcms_hardware *wlc_hw = wlc->hw;
  4044. int callbacks;
  4045. callbacks = 0;
  4046. brcms_b_detach_dmapio(wlc_hw);
  4047. band = wlc_hw->band;
  4048. for (i = 0; i < wlc_hw->_nbands; i++) {
  4049. if (band->pi) {
  4050. /* Detach this band's phy */
  4051. wlc_phy_detach(band->pi);
  4052. band->pi = NULL;
  4053. }
  4054. band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
  4055. }
  4056. /* Free shared phy state */
  4057. kfree(wlc_hw->phy_sh);
  4058. wlc_phy_shim_detach(wlc_hw->physhim);
  4059. if (wlc_hw->sih) {
  4060. ai_detach(wlc_hw->sih);
  4061. wlc_hw->sih = NULL;
  4062. }
  4063. return callbacks;
  4064. }
  4065. /*
  4066. * Return a count of the number of driver callbacks still pending.
  4067. *
  4068. * General policy is that brcms_c_detach can only dealloc/free software states.
  4069. * It can NOT touch hardware registers since the d11core may be in reset and
  4070. * clock may not be available.
  4071. * One exception is sb register access, which is possible if crystal is turned
  4072. * on after "down" state, driver should avoid software timer with the exception
  4073. * of radio_monitor.
  4074. */
  4075. uint brcms_c_detach(struct brcms_c_info *wlc)
  4076. {
  4077. uint callbacks = 0;
  4078. if (wlc == NULL)
  4079. return 0;
  4080. callbacks += brcms_b_detach(wlc);
  4081. /* delete software timers */
  4082. if (!brcms_c_radio_monitor_stop(wlc))
  4083. callbacks++;
  4084. brcms_c_channel_mgr_detach(wlc->cmi);
  4085. brcms_c_timers_deinit(wlc);
  4086. brcms_c_detach_module(wlc);
  4087. brcms_c_detach_mfree(wlc);
  4088. return callbacks;
  4089. }
  4090. /* update state that depends on the current value of "ap" */
  4091. static void brcms_c_ap_upd(struct brcms_c_info *wlc)
  4092. {
  4093. /* STA-BSS; short capable */
  4094. wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
  4095. }
  4096. /* Initialize just the hardware when coming out of POR or S3/S5 system states */
  4097. static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
  4098. {
  4099. if (wlc_hw->wlc->pub->hw_up)
  4100. return;
  4101. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  4102. /*
  4103. * Enable pll and xtal, initialize the power control registers,
  4104. * and force fastclock for the remainder of brcms_c_up().
  4105. */
  4106. brcms_b_xtal(wlc_hw, ON);
  4107. ai_clkctl_init(wlc_hw->sih);
  4108. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  4109. /*
  4110. * TODO: test suspend/resume
  4111. *
  4112. * AI chip doesn't restore bar0win2 on
  4113. * hibernation/resume, need sw fixup
  4114. */
  4115. /*
  4116. * Inform phy that a POR reset has occurred so
  4117. * it does a complete phy init
  4118. */
  4119. wlc_phy_por_inform(wlc_hw->band->pi);
  4120. wlc_hw->ucode_loaded = false;
  4121. wlc_hw->wlc->pub->hw_up = true;
  4122. if ((wlc_hw->boardflags & BFL_FEM)
  4123. && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
  4124. if (!
  4125. (wlc_hw->boardrev >= 0x1250
  4126. && (wlc_hw->boardflags & BFL_FEM_BT)))
  4127. ai_epa_4313war(wlc_hw->sih);
  4128. }
  4129. }
  4130. static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
  4131. {
  4132. brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
  4133. /*
  4134. * Enable pll and xtal, initialize the power control registers,
  4135. * and force fastclock for the remainder of brcms_c_up().
  4136. */
  4137. brcms_b_xtal(wlc_hw, ON);
  4138. ai_clkctl_init(wlc_hw->sih);
  4139. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  4140. /*
  4141. * Configure pci/pcmcia here instead of in brcms_c_attach()
  4142. * to allow mfg hotswap: down, hotswap (chip power cycle), up.
  4143. */
  4144. bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
  4145. true);
  4146. /*
  4147. * Need to read the hwradio status here to cover the case where the
  4148. * system is loaded with the hw radio disabled. We do not want to
  4149. * bring the driver up in this case.
  4150. */
  4151. if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
  4152. /* put SB PCI in down state again */
  4153. ai_pci_down(wlc_hw->sih);
  4154. brcms_b_xtal(wlc_hw, OFF);
  4155. return -ENOMEDIUM;
  4156. }
  4157. ai_pci_up(wlc_hw->sih);
  4158. /* reset the d11 core */
  4159. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  4160. return 0;
  4161. }
  4162. static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
  4163. {
  4164. wlc_hw->up = true;
  4165. wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
  4166. /* FULLY enable dynamic power control and d11 core interrupt */
  4167. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
  4168. brcms_intrson(wlc_hw->wlc->wl);
  4169. return 0;
  4170. }
  4171. /*
  4172. * Write WME tunable parameters for retransmit/max rate
  4173. * from wlc struct to ucode
  4174. */
  4175. static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
  4176. {
  4177. int ac;
  4178. /* Need clock to do this */
  4179. if (!wlc->clk)
  4180. return;
  4181. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  4182. brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
  4183. wlc->wme_retries[ac]);
  4184. }
  4185. /* make interface operational */
  4186. int brcms_c_up(struct brcms_c_info *wlc)
  4187. {
  4188. struct ieee80211_channel *ch;
  4189. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  4190. /* HW is turned off so don't try to access it */
  4191. if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
  4192. return -ENOMEDIUM;
  4193. if (!wlc->pub->hw_up) {
  4194. brcms_b_hw_up(wlc->hw);
  4195. wlc->pub->hw_up = true;
  4196. }
  4197. if ((wlc->pub->boardflags & BFL_FEM)
  4198. && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
  4199. if (wlc->pub->boardrev >= 0x1250
  4200. && (wlc->pub->boardflags & BFL_FEM_BT))
  4201. brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
  4202. MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
  4203. else
  4204. brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
  4205. MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
  4206. }
  4207. /*
  4208. * Need to read the hwradio status here to cover the case where the
  4209. * system is loaded with the hw radio disabled. We do not want to bring
  4210. * the driver up in this case. If radio is disabled, abort up, lower
  4211. * power, start radio timer and return 0(for NDIS) don't call
  4212. * radio_update to avoid looping brcms_c_up.
  4213. *
  4214. * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
  4215. */
  4216. if (!wlc->pub->radio_disabled) {
  4217. int status = brcms_b_up_prep(wlc->hw);
  4218. if (status == -ENOMEDIUM) {
  4219. if (!mboolisset
  4220. (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
  4221. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  4222. mboolset(wlc->pub->radio_disabled,
  4223. WL_RADIO_HW_DISABLE);
  4224. if (bsscfg->enable &&
  4225. (bsscfg->type == BRCMS_TYPE_STATION ||
  4226. bsscfg->type == BRCMS_TYPE_ADHOC))
  4227. brcms_err(wlc->hw->d11core,
  4228. "wl%d: up: rfdisable -> "
  4229. "bsscfg_disable()\n",
  4230. wlc->pub->unit);
  4231. }
  4232. }
  4233. }
  4234. if (wlc->pub->radio_disabled) {
  4235. brcms_c_radio_monitor_start(wlc);
  4236. return 0;
  4237. }
  4238. /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
  4239. wlc->clk = true;
  4240. brcms_c_radio_monitor_stop(wlc);
  4241. /* Set EDCF hostflags */
  4242. brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
  4243. brcms_init(wlc->wl);
  4244. wlc->pub->up = true;
  4245. if (wlc->bandinit_pending) {
  4246. ch = wlc->pub->ieee_hw->conf.channel;
  4247. brcms_c_suspend_mac_and_wait(wlc);
  4248. brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
  4249. wlc->bandinit_pending = false;
  4250. brcms_c_enable_mac(wlc);
  4251. }
  4252. brcms_b_up_finish(wlc->hw);
  4253. /* Program the TX wme params with the current settings */
  4254. brcms_c_wme_retries_write(wlc);
  4255. /* start one second watchdog timer */
  4256. brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
  4257. wlc->WDarmed = true;
  4258. /* ensure antenna config is up to date */
  4259. brcms_c_stf_phy_txant_upd(wlc);
  4260. /* ensure LDPC config is in sync */
  4261. brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
  4262. return 0;
  4263. }
  4264. static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
  4265. {
  4266. uint callbacks = 0;
  4267. return callbacks;
  4268. }
  4269. static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
  4270. {
  4271. bool dev_gone;
  4272. uint callbacks = 0;
  4273. if (!wlc_hw->up)
  4274. return callbacks;
  4275. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4276. /* disable interrupts */
  4277. if (dev_gone)
  4278. wlc_hw->wlc->macintmask = 0;
  4279. else {
  4280. /* now disable interrupts */
  4281. brcms_intrsoff(wlc_hw->wlc->wl);
  4282. /* ensure we're running on the pll clock again */
  4283. brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
  4284. }
  4285. /* down phy at the last of this stage */
  4286. callbacks += wlc_phy_down(wlc_hw->band->pi);
  4287. return callbacks;
  4288. }
  4289. static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
  4290. {
  4291. uint callbacks = 0;
  4292. bool dev_gone;
  4293. if (!wlc_hw->up)
  4294. return callbacks;
  4295. wlc_hw->up = false;
  4296. wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
  4297. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4298. if (dev_gone) {
  4299. wlc_hw->sbclk = false;
  4300. wlc_hw->clk = false;
  4301. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  4302. /* reclaim any posted packets */
  4303. brcms_c_flushqueues(wlc_hw->wlc);
  4304. } else {
  4305. /* Reset and disable the core */
  4306. if (bcma_core_is_enabled(wlc_hw->d11core)) {
  4307. if (bcma_read32(wlc_hw->d11core,
  4308. D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
  4309. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  4310. callbacks += brcms_reset(wlc_hw->wlc->wl);
  4311. brcms_c_coredisable(wlc_hw);
  4312. }
  4313. /* turn off primary xtal and pll */
  4314. if (!wlc_hw->noreset) {
  4315. ai_pci_down(wlc_hw->sih);
  4316. brcms_b_xtal(wlc_hw, OFF);
  4317. }
  4318. }
  4319. return callbacks;
  4320. }
  4321. /*
  4322. * Mark the interface nonoperational, stop the software mechanisms,
  4323. * disable the hardware, free any transient buffer state.
  4324. * Return a count of the number of driver callbacks still pending.
  4325. */
  4326. uint brcms_c_down(struct brcms_c_info *wlc)
  4327. {
  4328. uint callbacks = 0;
  4329. int i;
  4330. bool dev_gone = false;
  4331. brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
  4332. /* check if we are already in the going down path */
  4333. if (wlc->going_down) {
  4334. brcms_err(wlc->hw->d11core,
  4335. "wl%d: %s: Driver going down so return\n",
  4336. wlc->pub->unit, __func__);
  4337. return 0;
  4338. }
  4339. if (!wlc->pub->up)
  4340. return callbacks;
  4341. wlc->going_down = true;
  4342. callbacks += brcms_b_bmac_down_prep(wlc->hw);
  4343. dev_gone = brcms_deviceremoved(wlc);
  4344. /* Call any registered down handlers */
  4345. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4346. if (wlc->modulecb[i].down_fn)
  4347. callbacks +=
  4348. wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
  4349. }
  4350. /* cancel the watchdog timer */
  4351. if (wlc->WDarmed) {
  4352. if (!brcms_del_timer(wlc->wdtimer))
  4353. callbacks++;
  4354. wlc->WDarmed = false;
  4355. }
  4356. /* cancel all other timers */
  4357. callbacks += brcms_c_down_del_timer(wlc);
  4358. wlc->pub->up = false;
  4359. wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
  4360. callbacks += brcms_b_down_finish(wlc->hw);
  4361. /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
  4362. wlc->clk = false;
  4363. wlc->going_down = false;
  4364. return callbacks;
  4365. }
  4366. /* Set the current gmode configuration */
  4367. int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
  4368. {
  4369. int ret = 0;
  4370. uint i;
  4371. struct brcms_c_rateset rs;
  4372. /* Default to 54g Auto */
  4373. /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
  4374. s8 shortslot = BRCMS_SHORTSLOT_AUTO;
  4375. bool shortslot_restrict = false; /* Restrict association to stations
  4376. * that support shortslot
  4377. */
  4378. bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
  4379. /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
  4380. int preamble = BRCMS_PLCP_LONG;
  4381. bool preamble_restrict = false; /* Restrict association to stations
  4382. * that support short preambles
  4383. */
  4384. struct brcms_band *band;
  4385. /* if N-support is enabled, allow Gmode set as long as requested
  4386. * Gmode is not GMODE_LEGACY_B
  4387. */
  4388. if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
  4389. return -ENOTSUPP;
  4390. /* verify that we are dealing with 2G band and grab the band pointer */
  4391. if (wlc->band->bandtype == BRCM_BAND_2G)
  4392. band = wlc->band;
  4393. else if ((wlc->pub->_nbands > 1) &&
  4394. (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
  4395. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  4396. else
  4397. return -EINVAL;
  4398. /* update configuration value */
  4399. if (config)
  4400. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
  4401. /* Clear rateset override */
  4402. memset(&rs, 0, sizeof(rs));
  4403. switch (gmode) {
  4404. case GMODE_LEGACY_B:
  4405. shortslot = BRCMS_SHORTSLOT_OFF;
  4406. brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
  4407. break;
  4408. case GMODE_LRS:
  4409. break;
  4410. case GMODE_AUTO:
  4411. /* Accept defaults */
  4412. break;
  4413. case GMODE_ONLY:
  4414. ofdm_basic = true;
  4415. preamble = BRCMS_PLCP_SHORT;
  4416. preamble_restrict = true;
  4417. break;
  4418. case GMODE_PERFORMANCE:
  4419. shortslot = BRCMS_SHORTSLOT_ON;
  4420. shortslot_restrict = true;
  4421. ofdm_basic = true;
  4422. preamble = BRCMS_PLCP_SHORT;
  4423. preamble_restrict = true;
  4424. break;
  4425. default:
  4426. /* Error */
  4427. brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
  4428. wlc->pub->unit, __func__, gmode);
  4429. return -ENOTSUPP;
  4430. }
  4431. band->gmode = gmode;
  4432. wlc->shortslot_override = shortslot;
  4433. /* Use the default 11g rateset */
  4434. if (!rs.count)
  4435. brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
  4436. if (ofdm_basic) {
  4437. for (i = 0; i < rs.count; i++) {
  4438. if (rs.rates[i] == BRCM_RATE_6M
  4439. || rs.rates[i] == BRCM_RATE_12M
  4440. || rs.rates[i] == BRCM_RATE_24M)
  4441. rs.rates[i] |= BRCMS_RATE_FLAG;
  4442. }
  4443. }
  4444. /* Set default bss rateset */
  4445. wlc->default_bss->rateset.count = rs.count;
  4446. memcpy(wlc->default_bss->rateset.rates, rs.rates,
  4447. sizeof(wlc->default_bss->rateset.rates));
  4448. return ret;
  4449. }
  4450. int brcms_c_set_nmode(struct brcms_c_info *wlc)
  4451. {
  4452. uint i;
  4453. s32 nmode = AUTO;
  4454. if (wlc->stf->txstreams == WL_11N_3x3)
  4455. nmode = WL_11N_3x3;
  4456. else
  4457. nmode = WL_11N_2x2;
  4458. /* force GMODE_AUTO if NMODE is ON */
  4459. brcms_c_set_gmode(wlc, GMODE_AUTO, true);
  4460. if (nmode == WL_11N_3x3)
  4461. wlc->pub->_n_enab = SUPPORT_HT;
  4462. else
  4463. wlc->pub->_n_enab = SUPPORT_11N;
  4464. wlc->default_bss->flags |= BRCMS_BSS_HT;
  4465. /* add the mcs rates to the default and hw ratesets */
  4466. brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
  4467. wlc->stf->txstreams);
  4468. for (i = 0; i < wlc->pub->_nbands; i++)
  4469. memcpy(wlc->bandstate[i]->hw_rateset.mcs,
  4470. wlc->default_bss->rateset.mcs, MCSSET_LEN);
  4471. return 0;
  4472. }
  4473. static int
  4474. brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
  4475. struct brcms_c_rateset *rs_arg)
  4476. {
  4477. struct brcms_c_rateset rs, new;
  4478. uint bandunit;
  4479. memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
  4480. /* check for bad count value */
  4481. if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
  4482. return -EINVAL;
  4483. /* try the current band */
  4484. bandunit = wlc->band->bandunit;
  4485. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4486. if (brcms_c_rate_hwrs_filter_sort_validate
  4487. (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
  4488. wlc->stf->txstreams))
  4489. goto good;
  4490. /* try the other band */
  4491. if (brcms_is_mband_unlocked(wlc)) {
  4492. bandunit = OTHERBANDUNIT(wlc);
  4493. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4494. if (brcms_c_rate_hwrs_filter_sort_validate(&new,
  4495. &wlc->
  4496. bandstate[bandunit]->
  4497. hw_rateset, true,
  4498. wlc->stf->txstreams))
  4499. goto good;
  4500. }
  4501. return -EBADE;
  4502. good:
  4503. /* apply new rateset */
  4504. memcpy(&wlc->default_bss->rateset, &new,
  4505. sizeof(struct brcms_c_rateset));
  4506. memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
  4507. sizeof(struct brcms_c_rateset));
  4508. return 0;
  4509. }
  4510. static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
  4511. {
  4512. u8 r;
  4513. bool war = false;
  4514. if (wlc->pub->associated)
  4515. r = wlc->bsscfg->current_bss->rateset.rates[0];
  4516. else
  4517. r = wlc->default_bss->rateset.rates[0];
  4518. wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
  4519. }
  4520. int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
  4521. {
  4522. u16 chspec = ch20mhz_chspec(channel);
  4523. if (channel < 0 || channel > MAXCHANNEL)
  4524. return -EINVAL;
  4525. if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
  4526. return -EINVAL;
  4527. if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
  4528. if (wlc->band->bandunit != chspec_bandunit(chspec))
  4529. wlc->bandinit_pending = true;
  4530. else
  4531. wlc->bandinit_pending = false;
  4532. }
  4533. wlc->default_bss->chanspec = chspec;
  4534. /* brcms_c_BSSinit() will sanitize the rateset before
  4535. * using it.. */
  4536. if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
  4537. brcms_c_set_home_chanspec(wlc, chspec);
  4538. brcms_c_suspend_mac_and_wait(wlc);
  4539. brcms_c_set_chanspec(wlc, chspec);
  4540. brcms_c_enable_mac(wlc);
  4541. }
  4542. return 0;
  4543. }
  4544. int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
  4545. {
  4546. int ac;
  4547. if (srl < 1 || srl > RETRY_SHORT_MAX ||
  4548. lrl < 1 || lrl > RETRY_SHORT_MAX)
  4549. return -EINVAL;
  4550. wlc->SRL = srl;
  4551. wlc->LRL = lrl;
  4552. brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
  4553. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
  4554. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4555. EDCF_SHORT, wlc->SRL);
  4556. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4557. EDCF_LONG, wlc->LRL);
  4558. }
  4559. brcms_c_wme_retries_write(wlc);
  4560. return 0;
  4561. }
  4562. void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
  4563. struct brcm_rateset *currs)
  4564. {
  4565. struct brcms_c_rateset *rs;
  4566. if (wlc->pub->associated)
  4567. rs = &wlc->bsscfg->current_bss->rateset;
  4568. else
  4569. rs = &wlc->default_bss->rateset;
  4570. /* Copy only legacy rateset section */
  4571. currs->count = rs->count;
  4572. memcpy(&currs->rates, &rs->rates, rs->count);
  4573. }
  4574. int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
  4575. {
  4576. struct brcms_c_rateset internal_rs;
  4577. int bcmerror;
  4578. if (rs->count > BRCMS_NUMRATES)
  4579. return -ENOBUFS;
  4580. memset(&internal_rs, 0, sizeof(internal_rs));
  4581. /* Copy only legacy rateset section */
  4582. internal_rs.count = rs->count;
  4583. memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
  4584. /* merge rateset coming in with the current mcsset */
  4585. if (wlc->pub->_n_enab & SUPPORT_11N) {
  4586. struct brcms_bss_info *mcsset_bss;
  4587. if (wlc->pub->associated)
  4588. mcsset_bss = wlc->bsscfg->current_bss;
  4589. else
  4590. mcsset_bss = wlc->default_bss;
  4591. memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
  4592. MCSSET_LEN);
  4593. }
  4594. bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
  4595. if (!bcmerror)
  4596. brcms_c_ofdm_rateset_war(wlc);
  4597. return bcmerror;
  4598. }
  4599. static void brcms_c_time_lock(struct brcms_c_info *wlc)
  4600. {
  4601. bcma_set32(wlc->hw->d11core, D11REGOFFS(maccontrol), MCTL_TBTTHOLD);
  4602. /* Commit the write */
  4603. bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
  4604. }
  4605. static void brcms_c_time_unlock(struct brcms_c_info *wlc)
  4606. {
  4607. bcma_mask32(wlc->hw->d11core, D11REGOFFS(maccontrol), ~MCTL_TBTTHOLD);
  4608. /* Commit the write */
  4609. bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
  4610. }
  4611. int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
  4612. {
  4613. if (period == 0)
  4614. return -EINVAL;
  4615. wlc->default_bss->beacon_period = period;
  4616. return 0;
  4617. }
  4618. u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
  4619. {
  4620. return wlc->band->phytype;
  4621. }
  4622. void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
  4623. {
  4624. wlc->shortslot_override = sslot_override;
  4625. /*
  4626. * shortslot is an 11g feature, so no more work if we are
  4627. * currently on the 5G band
  4628. */
  4629. if (wlc->band->bandtype == BRCM_BAND_5G)
  4630. return;
  4631. if (wlc->pub->up && wlc->pub->associated) {
  4632. /* let watchdog or beacon processing update shortslot */
  4633. } else if (wlc->pub->up) {
  4634. /* unassociated shortslot is off */
  4635. brcms_c_switch_shortslot(wlc, false);
  4636. } else {
  4637. /* driver is down, so just update the brcms_c_info
  4638. * value */
  4639. if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
  4640. wlc->shortslot = false;
  4641. else
  4642. wlc->shortslot =
  4643. (wlc->shortslot_override ==
  4644. BRCMS_SHORTSLOT_ON);
  4645. }
  4646. }
  4647. /*
  4648. * register watchdog and down handlers.
  4649. */
  4650. int brcms_c_module_register(struct brcms_pub *pub,
  4651. const char *name, struct brcms_info *hdl,
  4652. int (*d_fn)(void *handle))
  4653. {
  4654. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4655. int i;
  4656. /* find an empty entry and just add, no duplication check! */
  4657. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4658. if (wlc->modulecb[i].name[0] == '\0') {
  4659. strncpy(wlc->modulecb[i].name, name,
  4660. sizeof(wlc->modulecb[i].name) - 1);
  4661. wlc->modulecb[i].hdl = hdl;
  4662. wlc->modulecb[i].down_fn = d_fn;
  4663. return 0;
  4664. }
  4665. }
  4666. return -ENOSR;
  4667. }
  4668. /* unregister module callbacks */
  4669. int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
  4670. struct brcms_info *hdl)
  4671. {
  4672. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4673. int i;
  4674. if (wlc == NULL)
  4675. return -ENODATA;
  4676. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4677. if (!strcmp(wlc->modulecb[i].name, name) &&
  4678. (wlc->modulecb[i].hdl == hdl)) {
  4679. memset(&wlc->modulecb[i], 0, sizeof(wlc->modulecb[i]));
  4680. return 0;
  4681. }
  4682. }
  4683. /* table not found! */
  4684. return -ENODATA;
  4685. }
  4686. static bool brcms_c_chipmatch_pci(struct bcma_device *core)
  4687. {
  4688. struct pci_dev *pcidev = core->bus->host_pci;
  4689. u16 vendor = pcidev->vendor;
  4690. u16 device = pcidev->device;
  4691. if (vendor != PCI_VENDOR_ID_BROADCOM) {
  4692. pr_err("unknown vendor id %04x\n", vendor);
  4693. return false;
  4694. }
  4695. if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
  4696. return true;
  4697. if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
  4698. return true;
  4699. if (device == BCM4313_D11N2G_ID)
  4700. return true;
  4701. if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
  4702. return true;
  4703. pr_err("unknown device id %04x\n", device);
  4704. return false;
  4705. }
  4706. static bool brcms_c_chipmatch_soc(struct bcma_device *core)
  4707. {
  4708. struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
  4709. if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
  4710. return true;
  4711. pr_err("unknown chip id %04x\n", chipinfo->id);
  4712. return false;
  4713. }
  4714. bool brcms_c_chipmatch(struct bcma_device *core)
  4715. {
  4716. switch (core->bus->hosttype) {
  4717. case BCMA_HOSTTYPE_PCI:
  4718. return brcms_c_chipmatch_pci(core);
  4719. case BCMA_HOSTTYPE_SOC:
  4720. return brcms_c_chipmatch_soc(core);
  4721. default:
  4722. pr_err("unknown host type: %i\n", core->bus->hosttype);
  4723. return false;
  4724. }
  4725. }
  4726. u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
  4727. {
  4728. u16 table_ptr;
  4729. u8 phy_rate, index;
  4730. /* get the phy specific rate encoding for the PLCP SIGNAL field */
  4731. if (is_ofdm_rate(rate))
  4732. table_ptr = M_RT_DIRMAP_A;
  4733. else
  4734. table_ptr = M_RT_DIRMAP_B;
  4735. /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
  4736. * the index into the rate table.
  4737. */
  4738. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  4739. index = phy_rate & 0xf;
  4740. /* Find the SHM pointer to the rate table entry by looking in the
  4741. * Direct-map Table
  4742. */
  4743. return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
  4744. }
  4745. /*
  4746. * bcmc_fid_generate:
  4747. * Generate frame ID for a BCMC packet. The frag field is not used
  4748. * for MC frames so is used as part of the sequence number.
  4749. */
  4750. static inline u16
  4751. bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
  4752. struct d11txh *txh)
  4753. {
  4754. u16 frameid;
  4755. frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
  4756. TXFID_QUEUE_MASK);
  4757. frameid |=
  4758. (((wlc->
  4759. mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  4760. TX_BCMC_FIFO;
  4761. return frameid;
  4762. }
  4763. static uint
  4764. brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
  4765. u8 preamble_type)
  4766. {
  4767. uint dur = 0;
  4768. /*
  4769. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  4770. * is less than or equal to the rate of the immediately previous
  4771. * frame in the FES
  4772. */
  4773. rspec = brcms_basic_rate(wlc, rspec);
  4774. /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
  4775. dur =
  4776. brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  4777. (DOT11_ACK_LEN + FCS_LEN));
  4778. return dur;
  4779. }
  4780. static uint
  4781. brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
  4782. u8 preamble_type)
  4783. {
  4784. return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
  4785. }
  4786. static uint
  4787. brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
  4788. u8 preamble_type)
  4789. {
  4790. /*
  4791. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  4792. * is less than or equal to the rate of the immediately previous
  4793. * frame in the FES
  4794. */
  4795. rspec = brcms_basic_rate(wlc, rspec);
  4796. /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
  4797. return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  4798. (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
  4799. FCS_LEN));
  4800. }
  4801. /* brcms_c_compute_frame_dur()
  4802. *
  4803. * Calculate the 802.11 MAC header DUR field for MPDU
  4804. * DUR for a single frame = 1 SIFS + 1 ACK
  4805. * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
  4806. *
  4807. * rate MPDU rate in unit of 500kbps
  4808. * next_frag_len next MPDU length in bytes
  4809. * preamble_type use short/GF or long/MM PLCP header
  4810. */
  4811. static u16
  4812. brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
  4813. u8 preamble_type, uint next_frag_len)
  4814. {
  4815. u16 dur, sifs;
  4816. sifs = get_sifs(wlc->band);
  4817. dur = sifs;
  4818. dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
  4819. if (next_frag_len) {
  4820. /* Double the current DUR to get 2 SIFS + 2 ACKs */
  4821. dur *= 2;
  4822. /* add another SIFS and the frag time */
  4823. dur += sifs;
  4824. dur +=
  4825. (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
  4826. next_frag_len);
  4827. }
  4828. return dur;
  4829. }
  4830. /* The opposite of brcms_c_calc_frame_time */
  4831. static uint
  4832. brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
  4833. u8 preamble_type, uint dur)
  4834. {
  4835. uint nsyms, mac_len, Ndps, kNdps;
  4836. uint rate = rspec2rate(ratespec);
  4837. if (is_mcs_rate(ratespec)) {
  4838. uint mcs = ratespec & RSPEC_RATE_MASK;
  4839. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  4840. dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  4841. /* payload calculation matches that of regular ofdm */
  4842. if (wlc->band->bandtype == BRCM_BAND_2G)
  4843. dur -= DOT11_OFDM_SIGNAL_EXTENSION;
  4844. /* kNdbps = kbps * 4 */
  4845. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  4846. rspec_issgi(ratespec)) * 4;
  4847. nsyms = dur / APHY_SYMBOL_TIME;
  4848. mac_len =
  4849. ((nsyms * kNdps) -
  4850. ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
  4851. } else if (is_ofdm_rate(ratespec)) {
  4852. dur -= APHY_PREAMBLE_TIME;
  4853. dur -= APHY_SIGNAL_TIME;
  4854. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  4855. Ndps = rate * 2;
  4856. nsyms = dur / APHY_SYMBOL_TIME;
  4857. mac_len =
  4858. ((nsyms * Ndps) -
  4859. (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
  4860. } else {
  4861. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  4862. dur -= BPHY_PLCP_SHORT_TIME;
  4863. else
  4864. dur -= BPHY_PLCP_TIME;
  4865. mac_len = dur * rate;
  4866. /* divide out factor of 2 in rate (1/2 mbps) */
  4867. mac_len = mac_len / 8 / 2;
  4868. }
  4869. return mac_len;
  4870. }
  4871. /*
  4872. * Return true if the specified rate is supported by the specified band.
  4873. * BRCM_BAND_AUTO indicates the current band.
  4874. */
  4875. static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
  4876. bool verbose)
  4877. {
  4878. struct brcms_c_rateset *hw_rateset;
  4879. uint i;
  4880. if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
  4881. hw_rateset = &wlc->band->hw_rateset;
  4882. else if (wlc->pub->_nbands > 1)
  4883. hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
  4884. else
  4885. /* other band specified and we are a single band device */
  4886. return false;
  4887. /* check if this is a mimo rate */
  4888. if (is_mcs_rate(rspec)) {
  4889. if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
  4890. goto error;
  4891. return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
  4892. }
  4893. for (i = 0; i < hw_rateset->count; i++)
  4894. if (hw_rateset->rates[i] == rspec2rate(rspec))
  4895. return true;
  4896. error:
  4897. if (verbose)
  4898. brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
  4899. "not in hw_rateset\n", wlc->pub->unit, rspec);
  4900. return false;
  4901. }
  4902. static u32
  4903. mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
  4904. u32 int_val)
  4905. {
  4906. struct bcma_device *core = wlc->hw->d11core;
  4907. u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
  4908. u8 rate = int_val & NRATE_RATE_MASK;
  4909. u32 rspec;
  4910. bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
  4911. bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
  4912. bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
  4913. == NRATE_OVERRIDE_MCS_ONLY);
  4914. int bcmerror = 0;
  4915. if (!ismcs)
  4916. return (u32) rate;
  4917. /* validate the combination of rate/mcs/stf is allowed */
  4918. if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
  4919. /* mcs only allowed when nmode */
  4920. if (stf > PHY_TXC1_MODE_SDM) {
  4921. brcms_err(core, "wl%d: %s: Invalid stf\n",
  4922. wlc->pub->unit, __func__);
  4923. bcmerror = -EINVAL;
  4924. goto done;
  4925. }
  4926. /* mcs 32 is a special case, DUP mode 40 only */
  4927. if (rate == 32) {
  4928. if (!CHSPEC_IS40(wlc->home_chanspec) ||
  4929. ((stf != PHY_TXC1_MODE_SISO)
  4930. && (stf != PHY_TXC1_MODE_CDD))) {
  4931. brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
  4932. wlc->pub->unit, __func__);
  4933. bcmerror = -EINVAL;
  4934. goto done;
  4935. }
  4936. /* mcs > 7 must use stf SDM */
  4937. } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
  4938. /* mcs > 7 must use stf SDM */
  4939. if (stf != PHY_TXC1_MODE_SDM) {
  4940. brcms_dbg_mac80211(core, "wl%d: enabling "
  4941. "SDM mode for mcs %d\n",
  4942. wlc->pub->unit, rate);
  4943. stf = PHY_TXC1_MODE_SDM;
  4944. }
  4945. } else {
  4946. /*
  4947. * MCS 0-7 may use SISO, CDD, and for
  4948. * phy_rev >= 3 STBC
  4949. */
  4950. if ((stf > PHY_TXC1_MODE_STBC) ||
  4951. (!BRCMS_STBC_CAP_PHY(wlc)
  4952. && (stf == PHY_TXC1_MODE_STBC))) {
  4953. brcms_err(core, "wl%d: %s: Invalid STBC\n",
  4954. wlc->pub->unit, __func__);
  4955. bcmerror = -EINVAL;
  4956. goto done;
  4957. }
  4958. }
  4959. } else if (is_ofdm_rate(rate)) {
  4960. if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
  4961. brcms_err(core, "wl%d: %s: Invalid OFDM\n",
  4962. wlc->pub->unit, __func__);
  4963. bcmerror = -EINVAL;
  4964. goto done;
  4965. }
  4966. } else if (is_cck_rate(rate)) {
  4967. if ((cur_band->bandtype != BRCM_BAND_2G)
  4968. || (stf != PHY_TXC1_MODE_SISO)) {
  4969. brcms_err(core, "wl%d: %s: Invalid CCK\n",
  4970. wlc->pub->unit, __func__);
  4971. bcmerror = -EINVAL;
  4972. goto done;
  4973. }
  4974. } else {
  4975. brcms_err(core, "wl%d: %s: Unknown rate type\n",
  4976. wlc->pub->unit, __func__);
  4977. bcmerror = -EINVAL;
  4978. goto done;
  4979. }
  4980. /* make sure multiple antennae are available for non-siso rates */
  4981. if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
  4982. brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
  4983. "request\n", wlc->pub->unit, __func__);
  4984. bcmerror = -EINVAL;
  4985. goto done;
  4986. }
  4987. rspec = rate;
  4988. if (ismcs) {
  4989. rspec |= RSPEC_MIMORATE;
  4990. /* For STBC populate the STC field of the ratespec */
  4991. if (stf == PHY_TXC1_MODE_STBC) {
  4992. u8 stc;
  4993. stc = 1; /* Nss for single stream is always 1 */
  4994. rspec |= (stc << RSPEC_STC_SHIFT);
  4995. }
  4996. }
  4997. rspec |= (stf << RSPEC_STF_SHIFT);
  4998. if (override_mcs_only)
  4999. rspec |= RSPEC_OVERRIDE_MCS_ONLY;
  5000. if (issgi)
  5001. rspec |= RSPEC_SHORT_GI;
  5002. if ((rate != 0)
  5003. && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
  5004. return rate;
  5005. return rspec;
  5006. done:
  5007. return rate;
  5008. }
  5009. /*
  5010. * Compute PLCP, but only requires actual rate and length of pkt.
  5011. * Rate is given in the driver standard multiple of 500 kbps.
  5012. * le is set for 11 Mbps rate if necessary.
  5013. * Broken out for PRQ.
  5014. */
  5015. static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
  5016. uint length, u8 *plcp)
  5017. {
  5018. u16 usec = 0;
  5019. u8 le = 0;
  5020. switch (rate_500) {
  5021. case BRCM_RATE_1M:
  5022. usec = length << 3;
  5023. break;
  5024. case BRCM_RATE_2M:
  5025. usec = length << 2;
  5026. break;
  5027. case BRCM_RATE_5M5:
  5028. usec = (length << 4) / 11;
  5029. if ((length << 4) - (usec * 11) > 0)
  5030. usec++;
  5031. break;
  5032. case BRCM_RATE_11M:
  5033. usec = (length << 3) / 11;
  5034. if ((length << 3) - (usec * 11) > 0) {
  5035. usec++;
  5036. if ((usec * 11) - (length << 3) >= 8)
  5037. le = D11B_PLCP_SIGNAL_LE;
  5038. }
  5039. break;
  5040. default:
  5041. brcms_err(wlc->hw->d11core,
  5042. "brcms_c_cck_plcp_set: unsupported rate %d\n",
  5043. rate_500);
  5044. rate_500 = BRCM_RATE_1M;
  5045. usec = length << 3;
  5046. break;
  5047. }
  5048. /* PLCP signal byte */
  5049. plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
  5050. /* PLCP service byte */
  5051. plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
  5052. /* PLCP length u16, little endian */
  5053. plcp[2] = usec & 0xff;
  5054. plcp[3] = (usec >> 8) & 0xff;
  5055. /* PLCP CRC16 */
  5056. plcp[4] = 0;
  5057. plcp[5] = 0;
  5058. }
  5059. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5060. static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
  5061. {
  5062. u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
  5063. plcp[0] = mcs;
  5064. if (rspec_is40mhz(rspec) || (mcs == 32))
  5065. plcp[0] |= MIMO_PLCP_40MHZ;
  5066. BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
  5067. plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
  5068. plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
  5069. plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
  5070. plcp[5] = 0;
  5071. }
  5072. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5073. static void
  5074. brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
  5075. {
  5076. u8 rate_signal;
  5077. u32 tmp = 0;
  5078. int rate = rspec2rate(rspec);
  5079. /*
  5080. * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
  5081. * transmitted first
  5082. */
  5083. rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
  5084. memset(plcp, 0, D11_PHY_HDR_LEN);
  5085. D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
  5086. tmp = (length & 0xfff) << 5;
  5087. plcp[2] |= (tmp >> 16) & 0xff;
  5088. plcp[1] |= (tmp >> 8) & 0xff;
  5089. plcp[0] |= tmp & 0xff;
  5090. }
  5091. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5092. static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
  5093. uint length, u8 *plcp)
  5094. {
  5095. int rate = rspec2rate(rspec);
  5096. brcms_c_cck_plcp_set(wlc, rate, length, plcp);
  5097. }
  5098. static void
  5099. brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
  5100. uint length, u8 *plcp)
  5101. {
  5102. if (is_mcs_rate(rspec))
  5103. brcms_c_compute_mimo_plcp(rspec, length, plcp);
  5104. else if (is_ofdm_rate(rspec))
  5105. brcms_c_compute_ofdm_plcp(rspec, length, plcp);
  5106. else
  5107. brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
  5108. }
  5109. /* brcms_c_compute_rtscts_dur()
  5110. *
  5111. * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
  5112. * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
  5113. * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
  5114. *
  5115. * cts cts-to-self or rts/cts
  5116. * rts_rate rts or cts rate in unit of 500kbps
  5117. * rate next MPDU rate in unit of 500kbps
  5118. * frame_len next MPDU frame length in bytes
  5119. */
  5120. u16
  5121. brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
  5122. u32 rts_rate,
  5123. u32 frame_rate, u8 rts_preamble_type,
  5124. u8 frame_preamble_type, uint frame_len, bool ba)
  5125. {
  5126. u16 dur, sifs;
  5127. sifs = get_sifs(wlc->band);
  5128. if (!cts_only) {
  5129. /* RTS/CTS */
  5130. dur = 3 * sifs;
  5131. dur +=
  5132. (u16) brcms_c_calc_cts_time(wlc, rts_rate,
  5133. rts_preamble_type);
  5134. } else {
  5135. /* CTS-TO-SELF */
  5136. dur = 2 * sifs;
  5137. }
  5138. dur +=
  5139. (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
  5140. frame_len);
  5141. if (ba)
  5142. dur +=
  5143. (u16) brcms_c_calc_ba_time(wlc, frame_rate,
  5144. BRCMS_SHORT_PREAMBLE);
  5145. else
  5146. dur +=
  5147. (u16) brcms_c_calc_ack_time(wlc, frame_rate,
  5148. frame_preamble_type);
  5149. return dur;
  5150. }
  5151. static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
  5152. {
  5153. u16 phyctl1 = 0;
  5154. u16 bw;
  5155. if (BRCMS_ISLCNPHY(wlc->band)) {
  5156. bw = PHY_TXC1_BW_20MHZ;
  5157. } else {
  5158. bw = rspec_get_bw(rspec);
  5159. /* 10Mhz is not supported yet */
  5160. if (bw < PHY_TXC1_BW_20MHZ) {
  5161. brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
  5162. "not supported yet, set to 20L\n", bw);
  5163. bw = PHY_TXC1_BW_20MHZ;
  5164. }
  5165. }
  5166. if (is_mcs_rate(rspec)) {
  5167. uint mcs = rspec & RSPEC_RATE_MASK;
  5168. /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
  5169. phyctl1 = rspec_phytxbyte2(rspec);
  5170. /* set the upper byte of phyctl1 */
  5171. phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
  5172. } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
  5173. && !BRCMS_ISSSLPNPHY(wlc->band)) {
  5174. /*
  5175. * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
  5176. * Data Rate. Eventually MIMOPHY would also be converted to
  5177. * this format
  5178. */
  5179. /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
  5180. phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5181. } else { /* legacy OFDM/CCK */
  5182. s16 phycfg;
  5183. /* get the phyctl byte from rate phycfg table */
  5184. phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
  5185. if (phycfg == -1) {
  5186. brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
  5187. "legacy OFDM/CCK rate\n");
  5188. phycfg = 0;
  5189. }
  5190. /* set the upper byte of phyctl1 */
  5191. phyctl1 =
  5192. (bw | (phycfg << 8) |
  5193. (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5194. }
  5195. return phyctl1;
  5196. }
  5197. /*
  5198. * Add struct d11txh, struct cck_phy_hdr.
  5199. *
  5200. * 'p' data must start with 802.11 MAC header
  5201. * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
  5202. *
  5203. * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
  5204. *
  5205. */
  5206. static u16
  5207. brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
  5208. struct sk_buff *p, struct scb *scb, uint frag,
  5209. uint nfrags, uint queue, uint next_frag_len)
  5210. {
  5211. struct ieee80211_hdr *h;
  5212. struct d11txh *txh;
  5213. u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
  5214. int len, phylen, rts_phylen;
  5215. u16 mch, phyctl, xfts, mainrates;
  5216. u16 seq = 0, mcl = 0, status = 0, frameid = 0;
  5217. u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5218. u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5219. bool use_rts = false;
  5220. bool use_cts = false;
  5221. bool use_rifs = false;
  5222. bool short_preamble[2] = { false, false };
  5223. u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5224. u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5225. u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
  5226. struct ieee80211_rts *rts = NULL;
  5227. bool qos;
  5228. uint ac;
  5229. bool hwtkmic = false;
  5230. u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
  5231. #define ANTCFG_NONE 0xFF
  5232. u8 antcfg = ANTCFG_NONE;
  5233. u8 fbantcfg = ANTCFG_NONE;
  5234. uint phyctl1_stf = 0;
  5235. u16 durid = 0;
  5236. struct ieee80211_tx_rate *txrate[2];
  5237. int k;
  5238. struct ieee80211_tx_info *tx_info;
  5239. bool is_mcs;
  5240. u16 mimo_txbw;
  5241. u8 mimo_preamble_type;
  5242. /* locate 802.11 MAC header */
  5243. h = (struct ieee80211_hdr *)(p->data);
  5244. qos = ieee80211_is_data_qos(h->frame_control);
  5245. /* compute length of frame in bytes for use in PLCP computations */
  5246. len = p->len;
  5247. phylen = len + FCS_LEN;
  5248. /* Get tx_info */
  5249. tx_info = IEEE80211_SKB_CB(p);
  5250. /* add PLCP */
  5251. plcp = skb_push(p, D11_PHY_HDR_LEN);
  5252. /* add Broadcom tx descriptor header */
  5253. txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
  5254. memset(txh, 0, D11_TXH_LEN);
  5255. /* setup frameid */
  5256. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  5257. /* non-AP STA should never use BCMC queue */
  5258. if (queue == TX_BCMC_FIFO) {
  5259. brcms_err(wlc->hw->d11core,
  5260. "wl%d: %s: ASSERT queue == TX_BCMC!\n",
  5261. wlc->pub->unit, __func__);
  5262. frameid = bcmc_fid_generate(wlc, NULL, txh);
  5263. } else {
  5264. /* Increment the counter for first fragment */
  5265. if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  5266. scb->seqnum[p->priority]++;
  5267. /* extract fragment number from frame first */
  5268. seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
  5269. seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
  5270. h->seq_ctrl = cpu_to_le16(seq);
  5271. frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  5272. (queue & TXFID_QUEUE_MASK);
  5273. }
  5274. }
  5275. frameid |= queue & TXFID_QUEUE_MASK;
  5276. /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
  5277. if (ieee80211_is_beacon(h->frame_control))
  5278. mcl |= TXC_IGNOREPMQ;
  5279. txrate[0] = tx_info->control.rates;
  5280. txrate[1] = txrate[0] + 1;
  5281. /*
  5282. * if rate control algorithm didn't give us a fallback
  5283. * rate, use the primary rate
  5284. */
  5285. if (txrate[1]->idx < 0)
  5286. txrate[1] = txrate[0];
  5287. for (k = 0; k < hw->max_rates; k++) {
  5288. is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
  5289. if (!is_mcs) {
  5290. if ((txrate[k]->idx >= 0)
  5291. && (txrate[k]->idx <
  5292. hw->wiphy->bands[tx_info->band]->n_bitrates)) {
  5293. rspec[k] =
  5294. hw->wiphy->bands[tx_info->band]->
  5295. bitrates[txrate[k]->idx].hw_value;
  5296. short_preamble[k] =
  5297. txrate[k]->
  5298. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
  5299. true : false;
  5300. } else {
  5301. rspec[k] = BRCM_RATE_1M;
  5302. }
  5303. } else {
  5304. rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
  5305. NRATE_MCS_INUSE | txrate[k]->idx);
  5306. }
  5307. /*
  5308. * Currently only support same setting for primay and
  5309. * fallback rates. Unify flags for each rate into a
  5310. * single value for the frame
  5311. */
  5312. use_rts |=
  5313. txrate[k]->
  5314. flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
  5315. use_cts |=
  5316. txrate[k]->
  5317. flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
  5318. /*
  5319. * (1) RATE:
  5320. * determine and validate primary rate
  5321. * and fallback rates
  5322. */
  5323. if (!rspec_active(rspec[k])) {
  5324. rspec[k] = BRCM_RATE_1M;
  5325. } else {
  5326. if (!is_multicast_ether_addr(h->addr1)) {
  5327. /* set tx antenna config */
  5328. brcms_c_antsel_antcfg_get(wlc->asi, false,
  5329. false, 0, 0, &antcfg, &fbantcfg);
  5330. }
  5331. }
  5332. }
  5333. phyctl1_stf = wlc->stf->ss_opmode;
  5334. if (wlc->pub->_n_enab & SUPPORT_11N) {
  5335. for (k = 0; k < hw->max_rates; k++) {
  5336. /*
  5337. * apply siso/cdd to single stream mcs's or ofdm
  5338. * if rspec is auto selected
  5339. */
  5340. if (((is_mcs_rate(rspec[k]) &&
  5341. is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
  5342. is_ofdm_rate(rspec[k]))
  5343. && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
  5344. || !(rspec[k] & RSPEC_OVERRIDE))) {
  5345. rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
  5346. /* For SISO MCS use STBC if possible */
  5347. if (is_mcs_rate(rspec[k])
  5348. && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
  5349. u8 stc;
  5350. /* Nss for single stream is always 1 */
  5351. stc = 1;
  5352. rspec[k] |= (PHY_TXC1_MODE_STBC <<
  5353. RSPEC_STF_SHIFT) |
  5354. (stc << RSPEC_STC_SHIFT);
  5355. } else
  5356. rspec[k] |=
  5357. (phyctl1_stf << RSPEC_STF_SHIFT);
  5358. }
  5359. /*
  5360. * Is the phy configured to use 40MHZ frames? If
  5361. * so then pick the desired txbw
  5362. */
  5363. if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
  5364. /* default txbw is 20in40 SB */
  5365. mimo_ctlchbw = mimo_txbw =
  5366. CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
  5367. wlc->band->pi))
  5368. ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
  5369. if (is_mcs_rate(rspec[k])) {
  5370. /* mcs 32 must be 40b/w DUP */
  5371. if ((rspec[k] & RSPEC_RATE_MASK)
  5372. == 32) {
  5373. mimo_txbw =
  5374. PHY_TXC1_BW_40MHZ_DUP;
  5375. /* use override */
  5376. } else if (wlc->mimo_40txbw != AUTO)
  5377. mimo_txbw = wlc->mimo_40txbw;
  5378. /* else check if dst is using 40 Mhz */
  5379. else if (scb->flags & SCB_IS40)
  5380. mimo_txbw = PHY_TXC1_BW_40MHZ;
  5381. } else if (is_ofdm_rate(rspec[k])) {
  5382. if (wlc->ofdm_40txbw != AUTO)
  5383. mimo_txbw = wlc->ofdm_40txbw;
  5384. } else if (wlc->cck_40txbw != AUTO) {
  5385. mimo_txbw = wlc->cck_40txbw;
  5386. }
  5387. } else {
  5388. /*
  5389. * mcs32 is 40 b/w only.
  5390. * This is possible for probe packets on
  5391. * a STA during SCAN
  5392. */
  5393. if ((rspec[k] & RSPEC_RATE_MASK) == 32)
  5394. /* mcs 0 */
  5395. rspec[k] = RSPEC_MIMORATE;
  5396. mimo_txbw = PHY_TXC1_BW_20MHZ;
  5397. }
  5398. /* Set channel width */
  5399. rspec[k] &= ~RSPEC_BW_MASK;
  5400. if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
  5401. rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
  5402. else
  5403. rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  5404. /* Disable short GI, not supported yet */
  5405. rspec[k] &= ~RSPEC_SHORT_GI;
  5406. mimo_preamble_type = BRCMS_MM_PREAMBLE;
  5407. if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
  5408. mimo_preamble_type = BRCMS_GF_PREAMBLE;
  5409. if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
  5410. && (!is_mcs_rate(rspec[k]))) {
  5411. brcms_warn(wlc->hw->d11core,
  5412. "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n",
  5413. wlc->pub->unit, __func__);
  5414. }
  5415. if (is_mcs_rate(rspec[k])) {
  5416. preamble_type[k] = mimo_preamble_type;
  5417. /*
  5418. * if SGI is selected, then forced mm
  5419. * for single stream
  5420. */
  5421. if ((rspec[k] & RSPEC_SHORT_GI)
  5422. && is_single_stream(rspec[k] &
  5423. RSPEC_RATE_MASK))
  5424. preamble_type[k] = BRCMS_MM_PREAMBLE;
  5425. }
  5426. /* should be better conditionalized */
  5427. if (!is_mcs_rate(rspec[0])
  5428. && (tx_info->control.rates[0].
  5429. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
  5430. preamble_type[k] = BRCMS_SHORT_PREAMBLE;
  5431. }
  5432. } else {
  5433. for (k = 0; k < hw->max_rates; k++) {
  5434. /* Set ctrlchbw as 20Mhz */
  5435. rspec[k] &= ~RSPEC_BW_MASK;
  5436. rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
  5437. /* for nphy, stf of ofdm frames must follow policies */
  5438. if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
  5439. rspec[k] &= ~RSPEC_STF_MASK;
  5440. rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
  5441. }
  5442. }
  5443. }
  5444. /* Reset these for use with AMPDU's */
  5445. txrate[0]->count = 0;
  5446. txrate[1]->count = 0;
  5447. /* (2) PROTECTION, may change rspec */
  5448. if ((ieee80211_is_data(h->frame_control) ||
  5449. ieee80211_is_mgmt(h->frame_control)) &&
  5450. (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
  5451. use_rts = true;
  5452. /* (3) PLCP: determine PLCP header and MAC duration,
  5453. * fill struct d11txh */
  5454. brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
  5455. brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
  5456. memcpy(&txh->FragPLCPFallback,
  5457. plcp_fallback, sizeof(txh->FragPLCPFallback));
  5458. /* Length field now put in CCK FBR CRC field */
  5459. if (is_cck_rate(rspec[1])) {
  5460. txh->FragPLCPFallback[4] = phylen & 0xff;
  5461. txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
  5462. }
  5463. /* MIMO-RATE: need validation ?? */
  5464. mainrates = is_ofdm_rate(rspec[0]) ?
  5465. D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
  5466. plcp[0];
  5467. /* DUR field for main rate */
  5468. if (!ieee80211_is_pspoll(h->frame_control) &&
  5469. !is_multicast_ether_addr(h->addr1) && !use_rifs) {
  5470. durid =
  5471. brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
  5472. next_frag_len);
  5473. h->duration_id = cpu_to_le16(durid);
  5474. } else if (use_rifs) {
  5475. /* NAV protect to end of next max packet size */
  5476. durid =
  5477. (u16) brcms_c_calc_frame_time(wlc, rspec[0],
  5478. preamble_type[0],
  5479. DOT11_MAX_FRAG_LEN);
  5480. durid += RIFS_11N_TIME;
  5481. h->duration_id = cpu_to_le16(durid);
  5482. }
  5483. /* DUR field for fallback rate */
  5484. if (ieee80211_is_pspoll(h->frame_control))
  5485. txh->FragDurFallback = h->duration_id;
  5486. else if (is_multicast_ether_addr(h->addr1) || use_rifs)
  5487. txh->FragDurFallback = 0;
  5488. else {
  5489. durid = brcms_c_compute_frame_dur(wlc, rspec[1],
  5490. preamble_type[1], next_frag_len);
  5491. txh->FragDurFallback = cpu_to_le16(durid);
  5492. }
  5493. /* (4) MAC-HDR: MacTxControlLow */
  5494. if (frag == 0)
  5495. mcl |= TXC_STARTMSDU;
  5496. if (!is_multicast_ether_addr(h->addr1))
  5497. mcl |= TXC_IMMEDACK;
  5498. if (wlc->band->bandtype == BRCM_BAND_5G)
  5499. mcl |= TXC_FREQBAND_5G;
  5500. if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
  5501. mcl |= TXC_BW_40;
  5502. /* set AMIC bit if using hardware TKIP MIC */
  5503. if (hwtkmic)
  5504. mcl |= TXC_AMIC;
  5505. txh->MacTxControlLow = cpu_to_le16(mcl);
  5506. /* MacTxControlHigh */
  5507. mch = 0;
  5508. /* Set fallback rate preamble type */
  5509. if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
  5510. (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
  5511. if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
  5512. mch |= TXC_PREAMBLE_DATA_FB_SHORT;
  5513. }
  5514. /* MacFrameControl */
  5515. memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
  5516. txh->TxFesTimeNormal = cpu_to_le16(0);
  5517. txh->TxFesTimeFallback = cpu_to_le16(0);
  5518. /* TxFrameRA */
  5519. memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
  5520. /* TxFrameID */
  5521. txh->TxFrameID = cpu_to_le16(frameid);
  5522. /*
  5523. * TxStatus, Note the case of recreating the first frag of a suppressed
  5524. * frame then we may need to reset the retry cnt's via the status reg
  5525. */
  5526. txh->TxStatus = cpu_to_le16(status);
  5527. /*
  5528. * extra fields for ucode AMPDU aggregation, the new fields are added to
  5529. * the END of previous structure so that it's compatible in driver.
  5530. */
  5531. txh->MaxNMpdus = cpu_to_le16(0);
  5532. txh->MaxABytes_MRT = cpu_to_le16(0);
  5533. txh->MaxABytes_FBR = cpu_to_le16(0);
  5534. txh->MinMBytes = cpu_to_le16(0);
  5535. /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
  5536. * furnish struct d11txh */
  5537. /* RTS PLCP header and RTS frame */
  5538. if (use_rts || use_cts) {
  5539. if (use_rts && use_cts)
  5540. use_cts = false;
  5541. for (k = 0; k < 2; k++) {
  5542. rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
  5543. false,
  5544. mimo_ctlchbw);
  5545. }
  5546. if (!is_ofdm_rate(rts_rspec[0]) &&
  5547. !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
  5548. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5549. rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
  5550. mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
  5551. }
  5552. if (!is_ofdm_rate(rts_rspec[1]) &&
  5553. !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
  5554. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5555. rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
  5556. mch |= TXC_PREAMBLE_RTS_FB_SHORT;
  5557. }
  5558. /* RTS/CTS additions to MacTxControlLow */
  5559. if (use_cts) {
  5560. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
  5561. } else {
  5562. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
  5563. txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
  5564. }
  5565. /* RTS PLCP header */
  5566. rts_plcp = txh->RTSPhyHeader;
  5567. if (use_cts)
  5568. rts_phylen = DOT11_CTS_LEN + FCS_LEN;
  5569. else
  5570. rts_phylen = DOT11_RTS_LEN + FCS_LEN;
  5571. brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
  5572. /* fallback rate version of RTS PLCP header */
  5573. brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
  5574. rts_plcp_fallback);
  5575. memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
  5576. sizeof(txh->RTSPLCPFallback));
  5577. /* RTS frame fields... */
  5578. rts = (struct ieee80211_rts *)&txh->rts_frame;
  5579. durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
  5580. rspec[0], rts_preamble_type[0],
  5581. preamble_type[0], phylen, false);
  5582. rts->duration = cpu_to_le16(durid);
  5583. /* fallback rate version of RTS DUR field */
  5584. durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
  5585. rts_rspec[1], rspec[1],
  5586. rts_preamble_type[1],
  5587. preamble_type[1], phylen, false);
  5588. txh->RTSDurFallback = cpu_to_le16(durid);
  5589. if (use_cts) {
  5590. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5591. IEEE80211_STYPE_CTS);
  5592. memcpy(&rts->ra, &h->addr2, ETH_ALEN);
  5593. } else {
  5594. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5595. IEEE80211_STYPE_RTS);
  5596. memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
  5597. }
  5598. /* mainrate
  5599. * low 8 bits: main frag rate/mcs,
  5600. * high 8 bits: rts/cts rate/mcs
  5601. */
  5602. mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
  5603. D11A_PHY_HDR_GRATE(
  5604. (struct ofdm_phy_hdr *) rts_plcp) :
  5605. rts_plcp[0]) << 8;
  5606. } else {
  5607. memset(txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
  5608. memset(&txh->rts_frame, 0, sizeof(struct ieee80211_rts));
  5609. memset(txh->RTSPLCPFallback, 0, sizeof(txh->RTSPLCPFallback));
  5610. txh->RTSDurFallback = 0;
  5611. }
  5612. #ifdef SUPPORT_40MHZ
  5613. /* add null delimiter count */
  5614. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
  5615. txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
  5616. brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
  5617. #endif
  5618. /*
  5619. * Now that RTS/RTS FB preamble types are updated, write
  5620. * the final value
  5621. */
  5622. txh->MacTxControlHigh = cpu_to_le16(mch);
  5623. /*
  5624. * MainRates (both the rts and frag plcp rates have
  5625. * been calculated now)
  5626. */
  5627. txh->MainRates = cpu_to_le16(mainrates);
  5628. /* XtraFrameTypes */
  5629. xfts = frametype(rspec[1], wlc->mimoft);
  5630. xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
  5631. xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
  5632. xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
  5633. XFTS_CHANNEL_SHIFT;
  5634. txh->XtraFrameTypes = cpu_to_le16(xfts);
  5635. /* PhyTxControlWord */
  5636. phyctl = frametype(rspec[0], wlc->mimoft);
  5637. if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
  5638. (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
  5639. if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
  5640. phyctl |= PHY_TXC_SHORT_HDR;
  5641. }
  5642. /* phytxant is properly bit shifted */
  5643. phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
  5644. txh->PhyTxControlWord = cpu_to_le16(phyctl);
  5645. /* PhyTxControlWord_1 */
  5646. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  5647. u16 phyctl1 = 0;
  5648. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
  5649. txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
  5650. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
  5651. txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
  5652. if (use_rts || use_cts) {
  5653. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
  5654. txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
  5655. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
  5656. txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
  5657. }
  5658. /*
  5659. * For mcs frames, if mixedmode(overloaded with long preamble)
  5660. * is going to be set, fill in non-zero MModeLen and/or
  5661. * MModeFbrLen it will be unnecessary if they are separated
  5662. */
  5663. if (is_mcs_rate(rspec[0]) &&
  5664. (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
  5665. u16 mmodelen =
  5666. brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
  5667. txh->MModeLen = cpu_to_le16(mmodelen);
  5668. }
  5669. if (is_mcs_rate(rspec[1]) &&
  5670. (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
  5671. u16 mmodefbrlen =
  5672. brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
  5673. txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
  5674. }
  5675. }
  5676. ac = skb_get_queue_mapping(p);
  5677. if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
  5678. uint frag_dur, dur, dur_fallback;
  5679. /* WME: Update TXOP threshold */
  5680. if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
  5681. frag_dur =
  5682. brcms_c_calc_frame_time(wlc, rspec[0],
  5683. preamble_type[0], phylen);
  5684. if (rts) {
  5685. /* 1 RTS or CTS-to-self frame */
  5686. dur =
  5687. brcms_c_calc_cts_time(wlc, rts_rspec[0],
  5688. rts_preamble_type[0]);
  5689. dur_fallback =
  5690. brcms_c_calc_cts_time(wlc, rts_rspec[1],
  5691. rts_preamble_type[1]);
  5692. /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
  5693. dur += le16_to_cpu(rts->duration);
  5694. dur_fallback +=
  5695. le16_to_cpu(txh->RTSDurFallback);
  5696. } else if (use_rifs) {
  5697. dur = frag_dur;
  5698. dur_fallback = 0;
  5699. } else {
  5700. /* frame + SIFS + ACK */
  5701. dur = frag_dur;
  5702. dur +=
  5703. brcms_c_compute_frame_dur(wlc, rspec[0],
  5704. preamble_type[0], 0);
  5705. dur_fallback =
  5706. brcms_c_calc_frame_time(wlc, rspec[1],
  5707. preamble_type[1],
  5708. phylen);
  5709. dur_fallback +=
  5710. brcms_c_compute_frame_dur(wlc, rspec[1],
  5711. preamble_type[1], 0);
  5712. }
  5713. /* NEED to set TxFesTimeNormal (hard) */
  5714. txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
  5715. /*
  5716. * NEED to set fallback rate version of
  5717. * TxFesTimeNormal (hard)
  5718. */
  5719. txh->TxFesTimeFallback =
  5720. cpu_to_le16((u16) dur_fallback);
  5721. /*
  5722. * update txop byte threshold (txop minus intraframe
  5723. * overhead)
  5724. */
  5725. if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
  5726. uint newfragthresh;
  5727. newfragthresh =
  5728. brcms_c_calc_frame_len(wlc,
  5729. rspec[0], preamble_type[0],
  5730. (wlc->edcf_txop[ac] -
  5731. (dur - frag_dur)));
  5732. /* range bound the fragthreshold */
  5733. if (newfragthresh < DOT11_MIN_FRAG_LEN)
  5734. newfragthresh =
  5735. DOT11_MIN_FRAG_LEN;
  5736. else if (newfragthresh >
  5737. wlc->usr_fragthresh)
  5738. newfragthresh =
  5739. wlc->usr_fragthresh;
  5740. /* update the fragthresh and do txc update */
  5741. if (wlc->fragthresh[queue] !=
  5742. (u16) newfragthresh)
  5743. wlc->fragthresh[queue] =
  5744. (u16) newfragthresh;
  5745. } else {
  5746. brcms_warn(wlc->hw->d11core,
  5747. "wl%d: %s txop invalid for rate %d\n",
  5748. wlc->pub->unit, fifo_names[queue],
  5749. rspec2rate(rspec[0]));
  5750. }
  5751. if (dur > wlc->edcf_txop[ac])
  5752. brcms_warn(wlc->hw->d11core,
  5753. "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
  5754. wlc->pub->unit, __func__,
  5755. fifo_names[queue],
  5756. phylen, wlc->fragthresh[queue],
  5757. dur, wlc->edcf_txop[ac]);
  5758. }
  5759. }
  5760. return 0;
  5761. }
  5762. static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
  5763. {
  5764. struct dma_pub *dma;
  5765. int fifo, ret = -ENOSPC;
  5766. struct d11txh *txh;
  5767. u16 frameid = INVALIDFID;
  5768. fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
  5769. dma = wlc->hw->di[fifo];
  5770. txh = (struct d11txh *)(skb->data);
  5771. if (dma->txavail == 0) {
  5772. /*
  5773. * We sometimes get a frame from mac80211 after stopping
  5774. * the queues. This only ever seems to be a single frame
  5775. * and is seems likely to be a race. TX_HEADROOM should
  5776. * ensure that we have enough space to handle these stray
  5777. * packets, so warn if there isn't. If we're out of space
  5778. * in the tx ring and the tx queue isn't stopped then
  5779. * we've really got a bug; warn loudly if that happens.
  5780. */
  5781. brcms_warn(wlc->hw->d11core,
  5782. "Received frame for tx with no space in DMA ring\n");
  5783. WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
  5784. skb_get_queue_mapping(skb)));
  5785. return -ENOSPC;
  5786. }
  5787. /* When a BC/MC frame is being committed to the BCMC fifo
  5788. * via DMA (NOT PIO), update ucode or BSS info as appropriate.
  5789. */
  5790. if (fifo == TX_BCMC_FIFO)
  5791. frameid = le16_to_cpu(txh->TxFrameID);
  5792. /* Commit BCMC sequence number in the SHM frame ID location */
  5793. if (frameid != INVALIDFID) {
  5794. /*
  5795. * To inform the ucode of the last mcast frame posted
  5796. * so that it can clear moredata bit
  5797. */
  5798. brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
  5799. }
  5800. ret = brcms_c_txfifo(wlc, fifo, skb);
  5801. /*
  5802. * The only reason for brcms_c_txfifo to fail is because
  5803. * there weren't any DMA descriptors, but we've already
  5804. * checked for that. So if it does fail yell loudly.
  5805. */
  5806. WARN_ON_ONCE(ret);
  5807. return ret;
  5808. }
  5809. bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
  5810. struct ieee80211_hw *hw)
  5811. {
  5812. uint fifo;
  5813. struct scb *scb = &wlc->pri_scb;
  5814. fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
  5815. brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
  5816. if (!brcms_c_tx(wlc, sdu))
  5817. return true;
  5818. /* packet discarded */
  5819. dev_kfree_skb_any(sdu);
  5820. return false;
  5821. }
  5822. int
  5823. brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
  5824. {
  5825. struct dma_pub *dma = wlc->hw->di[fifo];
  5826. int ret;
  5827. u16 queue;
  5828. ret = dma_txfast(wlc, dma, p);
  5829. if (ret < 0)
  5830. wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
  5831. /*
  5832. * Stop queue if DMA ring is full. Reserve some free descriptors,
  5833. * as we sometimes receive a frame from mac80211 after the queues
  5834. * are stopped.
  5835. */
  5836. queue = skb_get_queue_mapping(p);
  5837. if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
  5838. !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
  5839. ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
  5840. return ret;
  5841. }
  5842. u32
  5843. brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
  5844. bool use_rspec, u16 mimo_ctlchbw)
  5845. {
  5846. u32 rts_rspec = 0;
  5847. if (use_rspec)
  5848. /* use frame rate as rts rate */
  5849. rts_rspec = rspec;
  5850. else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
  5851. /* Use 11Mbps as the g protection RTS target rate and fallback.
  5852. * Use the brcms_basic_rate() lookup to find the best basic rate
  5853. * under the target in case 11 Mbps is not Basic.
  5854. * 6 and 9 Mbps are not usually selected by rate selection, but
  5855. * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
  5856. * is more robust.
  5857. */
  5858. rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
  5859. else
  5860. /* calculate RTS rate and fallback rate based on the frame rate
  5861. * RTS must be sent at a basic rate since it is a
  5862. * control frame, sec 9.6 of 802.11 spec
  5863. */
  5864. rts_rspec = brcms_basic_rate(wlc, rspec);
  5865. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  5866. /* set rts txbw to correct side band */
  5867. rts_rspec &= ~RSPEC_BW_MASK;
  5868. /*
  5869. * if rspec/rspec_fallback is 40MHz, then send RTS on both
  5870. * 20MHz channel (DUP), otherwise send RTS on control channel
  5871. */
  5872. if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
  5873. rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
  5874. else
  5875. rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  5876. /* pick siso/cdd as default for ofdm */
  5877. if (is_ofdm_rate(rts_rspec)) {
  5878. rts_rspec &= ~RSPEC_STF_MASK;
  5879. rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
  5880. }
  5881. }
  5882. return rts_rspec;
  5883. }
  5884. /* Update beacon listen interval in shared memory */
  5885. static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
  5886. {
  5887. /* wake up every DTIM is the default */
  5888. if (wlc->bcn_li_dtim == 1)
  5889. brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
  5890. else
  5891. brcms_b_write_shm(wlc->hw, M_BCN_LI,
  5892. (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
  5893. }
  5894. static void
  5895. brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
  5896. u32 *tsf_h_ptr)
  5897. {
  5898. struct bcma_device *core = wlc_hw->d11core;
  5899. /* read the tsf timer low, then high to get an atomic read */
  5900. *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
  5901. *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
  5902. }
  5903. /*
  5904. * recover 64bit TSF value from the 16bit TSF value in the rx header
  5905. * given the assumption that the TSF passed in header is within 65ms
  5906. * of the current tsf.
  5907. *
  5908. * 6 5 4 4 3 2 1
  5909. * 3.......6.......8.......0.......2.......4.......6.......8......0
  5910. * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
  5911. *
  5912. * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
  5913. * tsf_l is filled in by brcms_b_recv, which is done earlier in the
  5914. * receive call sequence after rx interrupt. Only the higher 16 bits
  5915. * are used. Finally, the tsf_h is read from the tsf register.
  5916. */
  5917. static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
  5918. struct d11rxhdr *rxh)
  5919. {
  5920. u32 tsf_h, tsf_l;
  5921. u16 rx_tsf_0_15, rx_tsf_16_31;
  5922. brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
  5923. rx_tsf_16_31 = (u16)(tsf_l >> 16);
  5924. rx_tsf_0_15 = rxh->RxTSFTime;
  5925. /*
  5926. * a greater tsf time indicates the low 16 bits of
  5927. * tsf_l wrapped, so decrement the high 16 bits.
  5928. */
  5929. if ((u16)tsf_l < rx_tsf_0_15) {
  5930. rx_tsf_16_31 -= 1;
  5931. if (rx_tsf_16_31 == 0xffff)
  5932. tsf_h -= 1;
  5933. }
  5934. return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
  5935. }
  5936. static void
  5937. prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  5938. struct sk_buff *p,
  5939. struct ieee80211_rx_status *rx_status)
  5940. {
  5941. int preamble;
  5942. int channel;
  5943. u32 rspec;
  5944. unsigned char *plcp;
  5945. /* fill in TSF and flag its presence */
  5946. rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
  5947. rx_status->flag |= RX_FLAG_MACTIME_START;
  5948. channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
  5949. rx_status->band =
  5950. channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
  5951. rx_status->freq =
  5952. ieee80211_channel_to_frequency(channel, rx_status->band);
  5953. rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
  5954. /* noise */
  5955. /* qual */
  5956. rx_status->antenna =
  5957. (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
  5958. plcp = p->data;
  5959. rspec = brcms_c_compute_rspec(rxh, plcp);
  5960. if (is_mcs_rate(rspec)) {
  5961. rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
  5962. rx_status->flag |= RX_FLAG_HT;
  5963. if (rspec_is40mhz(rspec))
  5964. rx_status->flag |= RX_FLAG_40MHZ;
  5965. } else {
  5966. switch (rspec2rate(rspec)) {
  5967. case BRCM_RATE_1M:
  5968. rx_status->rate_idx = 0;
  5969. break;
  5970. case BRCM_RATE_2M:
  5971. rx_status->rate_idx = 1;
  5972. break;
  5973. case BRCM_RATE_5M5:
  5974. rx_status->rate_idx = 2;
  5975. break;
  5976. case BRCM_RATE_11M:
  5977. rx_status->rate_idx = 3;
  5978. break;
  5979. case BRCM_RATE_6M:
  5980. rx_status->rate_idx = 4;
  5981. break;
  5982. case BRCM_RATE_9M:
  5983. rx_status->rate_idx = 5;
  5984. break;
  5985. case BRCM_RATE_12M:
  5986. rx_status->rate_idx = 6;
  5987. break;
  5988. case BRCM_RATE_18M:
  5989. rx_status->rate_idx = 7;
  5990. break;
  5991. case BRCM_RATE_24M:
  5992. rx_status->rate_idx = 8;
  5993. break;
  5994. case BRCM_RATE_36M:
  5995. rx_status->rate_idx = 9;
  5996. break;
  5997. case BRCM_RATE_48M:
  5998. rx_status->rate_idx = 10;
  5999. break;
  6000. case BRCM_RATE_54M:
  6001. rx_status->rate_idx = 11;
  6002. break;
  6003. default:
  6004. brcms_err(wlc->hw->d11core,
  6005. "%s: Unknown rate\n", __func__);
  6006. }
  6007. /*
  6008. * For 5GHz, we should decrease the index as it is
  6009. * a subset of the 2.4G rates. See bitrates field
  6010. * of brcms_band_5GHz_nphy (in mac80211_if.c).
  6011. */
  6012. if (rx_status->band == IEEE80211_BAND_5GHZ)
  6013. rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
  6014. /* Determine short preamble and rate_idx */
  6015. preamble = 0;
  6016. if (is_cck_rate(rspec)) {
  6017. if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
  6018. rx_status->flag |= RX_FLAG_SHORTPRE;
  6019. } else if (is_ofdm_rate(rspec)) {
  6020. rx_status->flag |= RX_FLAG_SHORTPRE;
  6021. } else {
  6022. brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
  6023. __func__);
  6024. }
  6025. }
  6026. if (plcp3_issgi(plcp[3]))
  6027. rx_status->flag |= RX_FLAG_SHORT_GI;
  6028. if (rxh->RxStatus1 & RXS_DECERR) {
  6029. rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
  6030. brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
  6031. __func__);
  6032. }
  6033. if (rxh->RxStatus1 & RXS_FCSERR) {
  6034. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  6035. brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n",
  6036. __func__);
  6037. }
  6038. }
  6039. static void
  6040. brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  6041. struct sk_buff *p)
  6042. {
  6043. int len_mpdu;
  6044. struct ieee80211_rx_status rx_status;
  6045. struct ieee80211_hdr *hdr;
  6046. memset(&rx_status, 0, sizeof(rx_status));
  6047. prep_mac80211_status(wlc, rxh, p, &rx_status);
  6048. /* mac header+body length, exclude CRC and plcp header */
  6049. len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
  6050. skb_pull(p, D11_PHY_HDR_LEN);
  6051. __skb_trim(p, len_mpdu);
  6052. /* unmute transmit */
  6053. if (wlc->hw->suspended_fifos) {
  6054. hdr = (struct ieee80211_hdr *)p->data;
  6055. if (ieee80211_is_beacon(hdr->frame_control))
  6056. brcms_b_mute(wlc->hw, false);
  6057. }
  6058. memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
  6059. ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
  6060. }
  6061. /* calculate frame duration for Mixed-mode L-SIG spoofing, return
  6062. * number of bytes goes in the length field
  6063. *
  6064. * Formula given by HT PHY Spec v 1.13
  6065. * len = 3(nsyms + nstream + 3) - 3
  6066. */
  6067. u16
  6068. brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
  6069. uint mac_len)
  6070. {
  6071. uint nsyms, len = 0, kNdps;
  6072. if (is_mcs_rate(ratespec)) {
  6073. uint mcs = ratespec & RSPEC_RATE_MASK;
  6074. int tot_streams = (mcs_2_txstreams(mcs) + 1) +
  6075. rspec_stc(ratespec);
  6076. /*
  6077. * the payload duration calculation matches that
  6078. * of regular ofdm
  6079. */
  6080. /* 1000Ndbps = kbps * 4 */
  6081. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  6082. rspec_issgi(ratespec)) * 4;
  6083. if (rspec_stc(ratespec) == 0)
  6084. nsyms =
  6085. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6086. APHY_TAIL_NBITS) * 1000, kNdps);
  6087. else
  6088. /* STBC needs to have even number of symbols */
  6089. nsyms =
  6090. 2 *
  6091. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6092. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  6093. /* (+3) account for HT-SIG(2) and HT-STF(1) */
  6094. nsyms += (tot_streams + 3);
  6095. /*
  6096. * 3 bytes/symbol @ legacy 6Mbps rate
  6097. * (-3) excluding service bits and tail bits
  6098. */
  6099. len = (3 * nsyms) - 3;
  6100. }
  6101. return (u16) len;
  6102. }
  6103. static void
  6104. brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
  6105. {
  6106. const struct brcms_c_rateset *rs_dflt;
  6107. struct brcms_c_rateset rs;
  6108. u8 rate;
  6109. u16 entry_ptr;
  6110. u8 plcp[D11_PHY_HDR_LEN];
  6111. u16 dur, sifs;
  6112. uint i;
  6113. sifs = get_sifs(wlc->band);
  6114. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  6115. brcms_c_rateset_copy(rs_dflt, &rs);
  6116. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  6117. /*
  6118. * walk the phy rate table and update MAC core SHM
  6119. * basic rate table entries
  6120. */
  6121. for (i = 0; i < rs.count; i++) {
  6122. rate = rs.rates[i] & BRCMS_RATE_MASK;
  6123. entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
  6124. /* Calculate the Probe Response PLCP for the given rate */
  6125. brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
  6126. /*
  6127. * Calculate the duration of the Probe Response
  6128. * frame plus SIFS for the MAC
  6129. */
  6130. dur = (u16) brcms_c_calc_frame_time(wlc, rate,
  6131. BRCMS_LONG_PREAMBLE, frame_len);
  6132. dur += sifs;
  6133. /* Update the SHM Rate Table entry Probe Response values */
  6134. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
  6135. (u16) (plcp[0] + (plcp[1] << 8)));
  6136. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
  6137. (u16) (plcp[2] + (plcp[3] << 8)));
  6138. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
  6139. }
  6140. }
  6141. /* Max buffering needed for beacon template/prb resp template is 142 bytes.
  6142. *
  6143. * PLCP header is 6 bytes.
  6144. * 802.11 A3 header is 24 bytes.
  6145. * Max beacon frame body template length is 112 bytes.
  6146. * Max probe resp frame body template length is 110 bytes.
  6147. *
  6148. * *len on input contains the max length of the packet available.
  6149. *
  6150. * The *len value is set to the number of bytes in buf used, and starts
  6151. * with the PLCP and included up to, but not including, the 4 byte FCS.
  6152. */
  6153. static void
  6154. brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
  6155. u32 bcn_rspec,
  6156. struct brcms_bss_cfg *cfg, u16 *buf, int *len)
  6157. {
  6158. static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
  6159. struct cck_phy_hdr *plcp;
  6160. struct ieee80211_mgmt *h;
  6161. int hdr_len, body_len;
  6162. hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
  6163. /* calc buffer size provided for frame body */
  6164. body_len = *len - hdr_len;
  6165. /* return actual size */
  6166. *len = hdr_len + body_len;
  6167. /* format PHY and MAC headers */
  6168. memset(buf, 0, hdr_len);
  6169. plcp = (struct cck_phy_hdr *) buf;
  6170. /*
  6171. * PLCP for Probe Response frames are filled in from
  6172. * core's rate table
  6173. */
  6174. if (type == IEEE80211_STYPE_BEACON)
  6175. /* fill in PLCP */
  6176. brcms_c_compute_plcp(wlc, bcn_rspec,
  6177. (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
  6178. (u8 *) plcp);
  6179. /* "Regular" and 16 MBSS but not for 4 MBSS */
  6180. /* Update the phytxctl for the beacon based on the rspec */
  6181. brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
  6182. h = (struct ieee80211_mgmt *)&plcp[1];
  6183. /* fill in 802.11 header */
  6184. h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
  6185. /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
  6186. /* A1 filled in by MAC for prb resp, broadcast for bcn */
  6187. if (type == IEEE80211_STYPE_BEACON)
  6188. memcpy(&h->da, &ether_bcast, ETH_ALEN);
  6189. memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
  6190. memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
  6191. /* SEQ filled in by MAC */
  6192. }
  6193. int brcms_c_get_header_len(void)
  6194. {
  6195. return TXOFF;
  6196. }
  6197. /*
  6198. * Update all beacons for the system.
  6199. */
  6200. void brcms_c_update_beacon(struct brcms_c_info *wlc)
  6201. {
  6202. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6203. if (bsscfg->up && (bsscfg->type == BRCMS_TYPE_AP ||
  6204. bsscfg->type == BRCMS_TYPE_ADHOC))
  6205. /* Clear the soft intmask */
  6206. wlc->defmacintmask &= ~MI_BCNTPL;
  6207. }
  6208. /* Write ssid into shared memory */
  6209. static void
  6210. brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
  6211. {
  6212. u8 *ssidptr = cfg->SSID;
  6213. u16 base = M_SSID;
  6214. u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
  6215. /* padding the ssid with zero and copy it into shm */
  6216. memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
  6217. memcpy(ssidbuf, ssidptr, cfg->SSID_len);
  6218. brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
  6219. brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
  6220. }
  6221. static void
  6222. brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
  6223. struct brcms_bss_cfg *cfg,
  6224. bool suspend)
  6225. {
  6226. u16 *prb_resp;
  6227. int len = BCN_TMPL_LEN;
  6228. prb_resp = kmalloc(BCN_TMPL_LEN, GFP_ATOMIC);
  6229. if (!prb_resp)
  6230. return;
  6231. /*
  6232. * write the probe response to hardware, or save in
  6233. * the config structure
  6234. */
  6235. /* create the probe response template */
  6236. brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
  6237. cfg, prb_resp, &len);
  6238. if (suspend)
  6239. brcms_c_suspend_mac_and_wait(wlc);
  6240. /* write the probe response into the template region */
  6241. brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
  6242. (len + 3) & ~3, prb_resp);
  6243. /* write the length of the probe response frame (+PLCP/-FCS) */
  6244. brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
  6245. /* write the SSID and SSID length */
  6246. brcms_c_shm_ssid_upd(wlc, cfg);
  6247. /*
  6248. * Write PLCP headers and durations for probe response frames
  6249. * at all rates. Use the actual frame length covered by the
  6250. * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
  6251. * by subtracting the PLCP len and adding the FCS.
  6252. */
  6253. len += (-D11_PHY_HDR_LEN + FCS_LEN);
  6254. brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
  6255. if (suspend)
  6256. brcms_c_enable_mac(wlc);
  6257. kfree(prb_resp);
  6258. }
  6259. void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
  6260. {
  6261. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6262. /* update AP or IBSS probe responses */
  6263. if (bsscfg->up && (bsscfg->type == BRCMS_TYPE_AP ||
  6264. bsscfg->type == BRCMS_TYPE_ADHOC))
  6265. brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
  6266. }
  6267. int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
  6268. uint *blocks)
  6269. {
  6270. if (fifo >= NFIFO)
  6271. return -EINVAL;
  6272. *blocks = wlc_hw->xmtfifo_sz[fifo];
  6273. return 0;
  6274. }
  6275. void
  6276. brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
  6277. const u8 *addr)
  6278. {
  6279. brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
  6280. if (match_reg_offset == RCM_BSSID_OFFSET)
  6281. memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
  6282. }
  6283. /*
  6284. * Flag 'scan in progress' to withhold dynamic phy calibration
  6285. */
  6286. void brcms_c_scan_start(struct brcms_c_info *wlc)
  6287. {
  6288. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
  6289. }
  6290. void brcms_c_scan_stop(struct brcms_c_info *wlc)
  6291. {
  6292. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
  6293. }
  6294. void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
  6295. {
  6296. wlc->pub->associated = state;
  6297. }
  6298. /*
  6299. * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
  6300. * AMPDU traffic, packets pending in hardware have to be invalidated so that
  6301. * when later on hardware releases them, they can be handled appropriately.
  6302. */
  6303. void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
  6304. struct ieee80211_sta *sta,
  6305. void (*dma_callback_fn))
  6306. {
  6307. struct dma_pub *dmah;
  6308. int i;
  6309. for (i = 0; i < NFIFO; i++) {
  6310. dmah = hw->di[i];
  6311. if (dmah != NULL)
  6312. dma_walk_packets(dmah, dma_callback_fn, sta);
  6313. }
  6314. }
  6315. int brcms_c_get_curband(struct brcms_c_info *wlc)
  6316. {
  6317. return wlc->band->bandunit;
  6318. }
  6319. bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc)
  6320. {
  6321. int i;
  6322. /* Kick DMA to send any pending AMPDU */
  6323. for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
  6324. if (wlc->hw->di[i])
  6325. dma_kick_tx(wlc->hw->di[i]);
  6326. return !brcms_txpktpendtot(wlc);
  6327. }
  6328. void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
  6329. {
  6330. wlc->bcn_li_bcn = interval;
  6331. if (wlc->pub->up)
  6332. brcms_c_bcn_li_upd(wlc);
  6333. }
  6334. u64 brcms_c_tsf_get(struct brcms_c_info *wlc)
  6335. {
  6336. u32 tsf_h, tsf_l;
  6337. u64 tsf;
  6338. brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
  6339. tsf = tsf_h;
  6340. tsf <<= 32;
  6341. tsf |= tsf_l;
  6342. return tsf;
  6343. }
  6344. void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf)
  6345. {
  6346. u32 tsf_h, tsf_l;
  6347. brcms_c_time_lock(wlc);
  6348. tsf_l = tsf;
  6349. tsf_h = (tsf >> 32);
  6350. /* read the tsf timer low, then high to get an atomic read */
  6351. bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerlow), tsf_l);
  6352. bcma_write32(wlc->hw->d11core, D11REGOFFS(tsf_timerhigh), tsf_h);
  6353. brcms_c_time_unlock(wlc);
  6354. }
  6355. int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
  6356. {
  6357. uint qdbm;
  6358. /* Remove override bit and clip to max qdbm value */
  6359. qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
  6360. return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
  6361. }
  6362. int brcms_c_get_tx_power(struct brcms_c_info *wlc)
  6363. {
  6364. uint qdbm;
  6365. bool override;
  6366. wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
  6367. /* Return qdbm units */
  6368. return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
  6369. }
  6370. /* Process received frames */
  6371. /*
  6372. * Return true if more frames need to be processed. false otherwise.
  6373. * Param 'bound' indicates max. # frames to process before break out.
  6374. */
  6375. static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
  6376. {
  6377. struct d11rxhdr *rxh;
  6378. struct ieee80211_hdr *h;
  6379. uint len;
  6380. bool is_amsdu;
  6381. /* frame starts with rxhdr */
  6382. rxh = (struct d11rxhdr *) (p->data);
  6383. /* strip off rxhdr */
  6384. skb_pull(p, BRCMS_HWRXOFF);
  6385. /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
  6386. if (rxh->RxStatus1 & RXS_PBPRES) {
  6387. if (p->len < 2) {
  6388. brcms_err(wlc->hw->d11core,
  6389. "wl%d: recv: rcvd runt of len %d\n",
  6390. wlc->pub->unit, p->len);
  6391. goto toss;
  6392. }
  6393. skb_pull(p, 2);
  6394. }
  6395. h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
  6396. len = p->len;
  6397. if (rxh->RxStatus1 & RXS_FCSERR) {
  6398. if (!(wlc->filter_flags & FIF_FCSFAIL))
  6399. goto toss;
  6400. }
  6401. /* check received pkt has at least frame control field */
  6402. if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
  6403. goto toss;
  6404. /* not supporting A-MSDU */
  6405. is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
  6406. if (is_amsdu)
  6407. goto toss;
  6408. brcms_c_recvctl(wlc, rxh, p);
  6409. return;
  6410. toss:
  6411. brcmu_pkt_buf_free_skb(p);
  6412. }
  6413. /* Process received frames */
  6414. /*
  6415. * Return true if more frames need to be processed. false otherwise.
  6416. * Param 'bound' indicates max. # frames to process before break out.
  6417. */
  6418. static bool
  6419. brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
  6420. {
  6421. struct sk_buff *p;
  6422. struct sk_buff *next = NULL;
  6423. struct sk_buff_head recv_frames;
  6424. uint n = 0;
  6425. uint bound_limit = bound ? RXBND : -1;
  6426. bool morepending = false;
  6427. skb_queue_head_init(&recv_frames);
  6428. /* gather received frames */
  6429. do {
  6430. /* !give others some time to run! */
  6431. if (n >= bound_limit)
  6432. break;
  6433. morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
  6434. n++;
  6435. } while (morepending);
  6436. /* post more rbufs */
  6437. dma_rxfill(wlc_hw->di[fifo]);
  6438. /* process each frame */
  6439. skb_queue_walk_safe(&recv_frames, p, next) {
  6440. struct d11rxhdr_le *rxh_le;
  6441. struct d11rxhdr *rxh;
  6442. skb_unlink(p, &recv_frames);
  6443. rxh_le = (struct d11rxhdr_le *)p->data;
  6444. rxh = (struct d11rxhdr *)p->data;
  6445. /* fixup rx header endianness */
  6446. rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
  6447. rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
  6448. rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
  6449. rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
  6450. rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
  6451. rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
  6452. rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
  6453. rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
  6454. rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
  6455. rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
  6456. rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
  6457. brcms_c_recv(wlc_hw->wlc, p);
  6458. }
  6459. return morepending;
  6460. }
  6461. /* second-level interrupt processing
  6462. * Return true if another dpc needs to be re-scheduled. false otherwise.
  6463. * Param 'bounded' indicates if applicable loops should be bounded.
  6464. */
  6465. bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
  6466. {
  6467. u32 macintstatus;
  6468. struct brcms_hardware *wlc_hw = wlc->hw;
  6469. struct bcma_device *core = wlc_hw->d11core;
  6470. if (brcms_deviceremoved(wlc)) {
  6471. brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
  6472. __func__);
  6473. brcms_down(wlc->wl);
  6474. return false;
  6475. }
  6476. /* grab and clear the saved software intstatus bits */
  6477. macintstatus = wlc->macintstatus;
  6478. wlc->macintstatus = 0;
  6479. brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
  6480. wlc_hw->unit, macintstatus);
  6481. WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
  6482. /* tx status */
  6483. if (macintstatus & MI_TFS) {
  6484. bool fatal;
  6485. if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
  6486. wlc->macintstatus |= MI_TFS;
  6487. if (fatal) {
  6488. brcms_err(core, "MI_TFS: fatal\n");
  6489. goto fatal;
  6490. }
  6491. }
  6492. if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
  6493. brcms_c_tbtt(wlc);
  6494. /* ATIM window end */
  6495. if (macintstatus & MI_ATIMWINEND) {
  6496. brcms_dbg_info(core, "end of ATIM window\n");
  6497. bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
  6498. wlc->qvalid = 0;
  6499. }
  6500. /*
  6501. * received data or control frame, MI_DMAINT is
  6502. * indication of RX_FIFO interrupt
  6503. */
  6504. if (macintstatus & MI_DMAINT)
  6505. if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
  6506. wlc->macintstatus |= MI_DMAINT;
  6507. /* noise sample collected */
  6508. if (macintstatus & MI_BG_NOISE)
  6509. wlc_phy_noise_sample_intr(wlc_hw->band->pi);
  6510. if (macintstatus & MI_GP0) {
  6511. brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
  6512. "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
  6513. printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
  6514. __func__, ai_get_chip_id(wlc_hw->sih),
  6515. ai_get_chiprev(wlc_hw->sih));
  6516. brcms_fatal_error(wlc_hw->wlc->wl);
  6517. }
  6518. /* gptimer timeout */
  6519. if (macintstatus & MI_TO)
  6520. bcma_write32(core, D11REGOFFS(gptimer), 0);
  6521. if (macintstatus & MI_RFDISABLE) {
  6522. brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
  6523. " RF Disable Input\n", wlc_hw->unit);
  6524. brcms_rfkill_set_hw_state(wlc->wl);
  6525. }
  6526. /* it isn't done and needs to be resched if macintstatus is non-zero */
  6527. return wlc->macintstatus != 0;
  6528. fatal:
  6529. brcms_fatal_error(wlc_hw->wlc->wl);
  6530. return wlc->macintstatus != 0;
  6531. }
  6532. void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
  6533. {
  6534. struct bcma_device *core = wlc->hw->d11core;
  6535. struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
  6536. u16 chanspec;
  6537. brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
  6538. chanspec = ch20mhz_chspec(ch->hw_value);
  6539. brcms_b_init(wlc->hw, chanspec);
  6540. /* update beacon listen interval */
  6541. brcms_c_bcn_li_upd(wlc);
  6542. /* write ethernet address to core */
  6543. brcms_c_set_mac(wlc->bsscfg);
  6544. brcms_c_set_bssid(wlc->bsscfg);
  6545. /* Update tsf_cfprep if associated and up */
  6546. if (wlc->pub->associated && wlc->bsscfg->up) {
  6547. u32 bi;
  6548. /* get beacon period and convert to uS */
  6549. bi = wlc->bsscfg->current_bss->beacon_period << 10;
  6550. /*
  6551. * update since init path would reset
  6552. * to default value
  6553. */
  6554. bcma_write32(core, D11REGOFFS(tsf_cfprep),
  6555. bi << CFPREP_CBI_SHIFT);
  6556. /* Update maccontrol PM related bits */
  6557. brcms_c_set_ps_ctrl(wlc);
  6558. }
  6559. brcms_c_bandinit_ordered(wlc, chanspec);
  6560. /* init probe response timeout */
  6561. brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
  6562. /* init max burst txop (framebursting) */
  6563. brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
  6564. (wlc->
  6565. _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
  6566. /* initialize maximum allowed duty cycle */
  6567. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
  6568. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
  6569. /*
  6570. * Update some shared memory locations related to
  6571. * max AMPDU size allowed to received
  6572. */
  6573. brcms_c_ampdu_shm_upd(wlc->ampdu);
  6574. /* band-specific inits */
  6575. brcms_c_bsinit(wlc);
  6576. /* Enable EDCF mode (while the MAC is suspended) */
  6577. bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
  6578. brcms_c_edcf_setparams(wlc, false);
  6579. /* read the ucode version if we have not yet done so */
  6580. if (wlc->ucode_rev == 0) {
  6581. u16 rev;
  6582. u16 patch;
  6583. rev = brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR);
  6584. patch = brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
  6585. wlc->ucode_rev = (rev << NBITS(u16)) | patch;
  6586. snprintf(wlc->wiphy->fw_version,
  6587. sizeof(wlc->wiphy->fw_version), "%u.%u", rev, patch);
  6588. }
  6589. /* ..now really unleash hell (allow the MAC out of suspend) */
  6590. brcms_c_enable_mac(wlc);
  6591. /* suspend the tx fifos and mute the phy for preism cac time */
  6592. if (mute_tx)
  6593. brcms_b_mute(wlc->hw, true);
  6594. /* enable the RF Disable Delay timer */
  6595. bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
  6596. /*
  6597. * Initialize WME parameters; if they haven't been set by some other
  6598. * mechanism (IOVar, etc) then read them from the hardware.
  6599. */
  6600. if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
  6601. /* Uninitialized; read from HW */
  6602. int ac;
  6603. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  6604. wlc->wme_retries[ac] =
  6605. brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
  6606. }
  6607. }
  6608. /*
  6609. * The common driver entry routine. Error codes should be unique
  6610. */
  6611. struct brcms_c_info *
  6612. brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
  6613. bool piomode, uint *perr)
  6614. {
  6615. struct brcms_c_info *wlc;
  6616. uint err = 0;
  6617. uint i, j;
  6618. struct brcms_pub *pub;
  6619. /* allocate struct brcms_c_info state and its substructures */
  6620. wlc = brcms_c_attach_malloc(unit, &err, 0);
  6621. if (wlc == NULL)
  6622. goto fail;
  6623. wlc->wiphy = wl->wiphy;
  6624. pub = wlc->pub;
  6625. #if defined(DEBUG)
  6626. wlc_info_dbg = wlc;
  6627. #endif
  6628. wlc->band = wlc->bandstate[0];
  6629. wlc->core = wlc->corestate;
  6630. wlc->wl = wl;
  6631. pub->unit = unit;
  6632. pub->_piomode = piomode;
  6633. wlc->bandinit_pending = false;
  6634. /* populate struct brcms_c_info with default values */
  6635. brcms_c_info_init(wlc, unit);
  6636. /* update sta/ap related parameters */
  6637. brcms_c_ap_upd(wlc);
  6638. /*
  6639. * low level attach steps(all hw accesses go
  6640. * inside, no more in rest of the attach)
  6641. */
  6642. err = brcms_b_attach(wlc, core, unit, piomode);
  6643. if (err)
  6644. goto fail;
  6645. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
  6646. pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
  6647. /* disable allowed duty cycle */
  6648. wlc->tx_duty_cycle_ofdm = 0;
  6649. wlc->tx_duty_cycle_cck = 0;
  6650. brcms_c_stf_phy_chain_calc(wlc);
  6651. /* txchain 1: txant 0, txchain 2: txant 1 */
  6652. if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
  6653. wlc->stf->txant = wlc->stf->hw_txchain - 1;
  6654. /* push to BMAC driver */
  6655. wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
  6656. wlc->stf->hw_rxchain);
  6657. /* pull up some info resulting from the low attach */
  6658. for (i = 0; i < NFIFO; i++)
  6659. wlc->core->txavail[i] = wlc->hw->txavail[i];
  6660. memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  6661. memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  6662. for (j = 0; j < wlc->pub->_nbands; j++) {
  6663. wlc->band = wlc->bandstate[j];
  6664. if (!brcms_c_attach_stf_ant_init(wlc)) {
  6665. err = 24;
  6666. goto fail;
  6667. }
  6668. /* default contention windows size limits */
  6669. wlc->band->CWmin = APHY_CWMIN;
  6670. wlc->band->CWmax = PHY_CWMAX;
  6671. /* init gmode value */
  6672. if (wlc->band->bandtype == BRCM_BAND_2G) {
  6673. wlc->band->gmode = GMODE_AUTO;
  6674. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
  6675. wlc->band->gmode);
  6676. }
  6677. /* init _n_enab supported mode */
  6678. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  6679. pub->_n_enab = SUPPORT_11N;
  6680. brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
  6681. ((pub->_n_enab ==
  6682. SUPPORT_11N) ? WL_11N_2x2 :
  6683. WL_11N_3x3));
  6684. }
  6685. /* init per-band default rateset, depend on band->gmode */
  6686. brcms_default_rateset(wlc, &wlc->band->defrateset);
  6687. /* fill in hw_rateset */
  6688. brcms_c_rateset_filter(&wlc->band->defrateset,
  6689. &wlc->band->hw_rateset, false,
  6690. BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  6691. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  6692. }
  6693. /*
  6694. * update antenna config due to
  6695. * wlc->stf->txant/txchain/ant_rx_ovr change
  6696. */
  6697. brcms_c_stf_phy_txant_upd(wlc);
  6698. /* attach each modules */
  6699. err = brcms_c_attach_module(wlc);
  6700. if (err != 0)
  6701. goto fail;
  6702. if (!brcms_c_timers_init(wlc, unit)) {
  6703. wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
  6704. __func__);
  6705. err = 32;
  6706. goto fail;
  6707. }
  6708. /* depend on rateset, gmode */
  6709. wlc->cmi = brcms_c_channel_mgr_attach(wlc);
  6710. if (!wlc->cmi) {
  6711. wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
  6712. "\n", unit, __func__);
  6713. err = 33;
  6714. goto fail;
  6715. }
  6716. /* init default when all parameters are ready, i.e. ->rateset */
  6717. brcms_c_bss_default_init(wlc);
  6718. /*
  6719. * Complete the wlc default state initializations..
  6720. */
  6721. wlc->bsscfg->wlc = wlc;
  6722. wlc->mimoft = FT_HT;
  6723. wlc->mimo_40txbw = AUTO;
  6724. wlc->ofdm_40txbw = AUTO;
  6725. wlc->cck_40txbw = AUTO;
  6726. brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
  6727. /* Set default values of SGI */
  6728. if (BRCMS_SGI_CAP_PHY(wlc)) {
  6729. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  6730. BRCMS_N_SGI_40));
  6731. } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
  6732. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  6733. BRCMS_N_SGI_40));
  6734. } else {
  6735. brcms_c_ht_update_sgi_rx(wlc, 0);
  6736. }
  6737. brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
  6738. if (perr)
  6739. *perr = 0;
  6740. return wlc;
  6741. fail:
  6742. wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
  6743. unit, __func__, err);
  6744. if (wlc)
  6745. brcms_c_detach(wlc);
  6746. if (perr)
  6747. *perr = err;
  6748. return NULL;
  6749. }