11n.c 25 KB

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  1. /*
  2. * Marvell Wireless LAN device driver: 802.11n
  3. *
  4. * Copyright (C) 2011, Marvell International Ltd.
  5. *
  6. * This software file (the "File") is distributed by Marvell International
  7. * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  8. * (the "License"). You may use, redistribute and/or modify this File in
  9. * accordance with the terms and conditions of the License, a copy of which
  10. * is available by writing to the Free Software Foundation, Inc.,
  11. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12. * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13. *
  14. * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16. * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
  17. * this warranty disclaimer.
  18. */
  19. #include "decl.h"
  20. #include "ioctl.h"
  21. #include "util.h"
  22. #include "fw.h"
  23. #include "main.h"
  24. #include "wmm.h"
  25. #include "11n.h"
  26. /*
  27. * Fills HT capability information field, AMPDU Parameters field, HT extended
  28. * capability field, and supported MCS set fields.
  29. *
  30. * Only the following HT capability information fields are used, all other
  31. * fields are always turned off.
  32. *
  33. * Bit 1 : Supported channel width (0: 20MHz, 1: Both 20 and 40 MHz)
  34. * Bit 4 : Greenfield support (0: Not supported, 1: Supported)
  35. * Bit 5 : Short GI for 20 MHz support (0: Not supported, 1: Supported)
  36. * Bit 6 : Short GI for 40 MHz support (0: Not supported, 1: Supported)
  37. * Bit 7 : Tx STBC (0: Not supported, 1: Supported)
  38. * Bit 8-9 : Rx STBC (0: Not supported, X: Support for up to X spatial streams)
  39. * Bit 10 : Delayed BA support (0: Not supported, 1: Supported)
  40. * Bit 11 : Maximum AMSDU length (0: 3839 octets, 1: 7935 octets)
  41. * Bit 14 : 40-Mhz intolerant support (0: Not supported, 1: Supported)
  42. *
  43. * In addition, the following AMPDU Parameters are set -
  44. * - Maximum AMPDU length exponent (set to 3)
  45. * - Minimum AMPDU start spacing (set to 0 - No restrictions)
  46. *
  47. * MCS is set for 1x1, with MSC32 for infra mode or ad-hoc mode with 40 MHz
  48. * support.
  49. *
  50. * RD responder bit to set to clear in the extended capability header.
  51. */
  52. void
  53. mwifiex_fill_cap_info(struct mwifiex_private *priv,
  54. struct mwifiex_ie_types_htcap *ht_cap)
  55. {
  56. struct mwifiex_adapter *adapter = priv->adapter;
  57. u8 *mcs;
  58. int rx_mcs_supp;
  59. uint16_t ht_cap_info = le16_to_cpu(ht_cap->ht_cap.cap_info);
  60. uint16_t ht_ext_cap = le16_to_cpu(ht_cap->ht_cap.extended_ht_cap_info);
  61. /* Convert dev_cap to IEEE80211_HT_CAP */
  62. if (ISSUPP_CHANWIDTH40(adapter->hw_dot_11n_dev_cap))
  63. ht_cap_info |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  64. else
  65. ht_cap_info &= ~IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  66. if (ISSUPP_SHORTGI20(adapter->hw_dot_11n_dev_cap))
  67. ht_cap_info |= IEEE80211_HT_CAP_SGI_20;
  68. else
  69. ht_cap_info &= ~IEEE80211_HT_CAP_SGI_20;
  70. if (ISSUPP_SHORTGI40(adapter->hw_dot_11n_dev_cap))
  71. ht_cap_info |= IEEE80211_HT_CAP_SGI_40;
  72. else
  73. ht_cap_info &= ~IEEE80211_HT_CAP_SGI_40;
  74. if (ISSUPP_TXSTBC(adapter->hw_dot_11n_dev_cap))
  75. ht_cap_info |= IEEE80211_HT_CAP_TX_STBC;
  76. else
  77. ht_cap_info &= ~IEEE80211_HT_CAP_TX_STBC;
  78. if (ISSUPP_RXSTBC(adapter->hw_dot_11n_dev_cap))
  79. ht_cap_info |= 1 << IEEE80211_HT_CAP_RX_STBC_SHIFT;
  80. else
  81. ht_cap_info &= ~(3 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  82. if (ISSUPP_GREENFIELD(adapter->hw_dot_11n_dev_cap))
  83. ht_cap_info |= IEEE80211_HT_CAP_GRN_FLD;
  84. else
  85. ht_cap_info &= ~IEEE80211_HT_CAP_GRN_FLD;
  86. ht_cap_info &= ~IEEE80211_HT_CAP_MAX_AMSDU;
  87. ht_cap_info |= IEEE80211_HT_CAP_SM_PS;
  88. ht_cap->ht_cap.ampdu_params_info |= IEEE80211_HT_AMPDU_PARM_FACTOR;
  89. ht_cap->ht_cap.ampdu_params_info &= ~IEEE80211_HT_AMPDU_PARM_DENSITY;
  90. rx_mcs_supp = GET_RXMCSSUPP(adapter->hw_dev_mcs_support);
  91. mcs = (u8 *)&ht_cap->ht_cap.mcs;
  92. /* Set MCS for 1x1 */
  93. memset(mcs, 0xff, rx_mcs_supp);
  94. /* Clear all the other values */
  95. memset(&mcs[rx_mcs_supp], 0,
  96. sizeof(struct ieee80211_mcs_info) - rx_mcs_supp);
  97. if (priv->bss_mode == MWIFIEX_BSS_MODE_INFRA ||
  98. (ht_cap_info & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
  99. /* Set MCS32 for infra mode or ad-hoc mode with 40MHz support */
  100. SETHT_MCS32(ht_cap->ht_cap.mcs.rx_mask);
  101. /* Clear RD responder bit */
  102. RESETHT_EXTCAP_RDG(ht_ext_cap);
  103. ht_cap->ht_cap.cap_info = cpu_to_le16(ht_cap_info);
  104. ht_cap->ht_cap.extended_ht_cap_info = cpu_to_le16(ht_ext_cap);
  105. }
  106. /*
  107. * This function returns the pointer to an entry in BA Stream
  108. * table which matches the requested BA status.
  109. */
  110. static struct mwifiex_tx_ba_stream_tbl *
  111. mwifiex_11n_get_tx_ba_stream_status(struct mwifiex_private *priv,
  112. enum mwifiex_ba_status ba_status)
  113. {
  114. struct mwifiex_tx_ba_stream_tbl *tx_ba_tsr_tbl;
  115. unsigned long flags;
  116. spin_lock_irqsave(&priv->tx_ba_stream_tbl_lock, flags);
  117. list_for_each_entry(tx_ba_tsr_tbl, &priv->tx_ba_stream_tbl_ptr, list) {
  118. if (tx_ba_tsr_tbl->ba_status == ba_status) {
  119. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock,
  120. flags);
  121. return tx_ba_tsr_tbl;
  122. }
  123. }
  124. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock, flags);
  125. return NULL;
  126. }
  127. /*
  128. * This function handles the command response of delete a block
  129. * ack request.
  130. *
  131. * The function checks the response success status and takes action
  132. * accordingly (send an add BA request in case of success, or recreate
  133. * the deleted stream in case of failure, if the add BA was also
  134. * initiated by us).
  135. */
  136. int mwifiex_ret_11n_delba(struct mwifiex_private *priv,
  137. struct host_cmd_ds_command *resp)
  138. {
  139. int tid;
  140. struct mwifiex_tx_ba_stream_tbl *tx_ba_tbl;
  141. struct host_cmd_ds_11n_delba *del_ba =
  142. (struct host_cmd_ds_11n_delba *) &resp->params.del_ba;
  143. uint16_t del_ba_param_set = le16_to_cpu(del_ba->del_ba_param_set);
  144. tid = del_ba_param_set >> DELBA_TID_POS;
  145. if (del_ba->del_result == BA_RESULT_SUCCESS) {
  146. mwifiex_11n_delete_ba_stream_tbl(priv, tid,
  147. del_ba->peer_mac_addr, TYPE_DELBA_SENT,
  148. INITIATOR_BIT(del_ba_param_set));
  149. tx_ba_tbl = mwifiex_11n_get_tx_ba_stream_status(priv,
  150. BA_STREAM_SETUP_INPROGRESS);
  151. if (tx_ba_tbl)
  152. mwifiex_send_addba(priv, tx_ba_tbl->tid,
  153. tx_ba_tbl->ra);
  154. } else { /*
  155. * In case of failure, recreate the deleted stream in case
  156. * we initiated the ADDBA
  157. */
  158. if (INITIATOR_BIT(del_ba_param_set)) {
  159. mwifiex_11n_create_tx_ba_stream_tbl(priv,
  160. del_ba->peer_mac_addr, tid,
  161. BA_STREAM_SETUP_INPROGRESS);
  162. tx_ba_tbl = mwifiex_11n_get_tx_ba_stream_status(priv,
  163. BA_STREAM_SETUP_INPROGRESS);
  164. if (tx_ba_tbl)
  165. mwifiex_11n_delete_ba_stream_tbl(priv,
  166. tx_ba_tbl->tid, tx_ba_tbl->ra,
  167. TYPE_DELBA_SENT, true);
  168. }
  169. }
  170. return 0;
  171. }
  172. /*
  173. * This function handles the command response of add a block
  174. * ack request.
  175. *
  176. * Handling includes changing the header fields to CPU formats, checking
  177. * the response success status and taking actions accordingly (delete the
  178. * BA stream table in case of failure).
  179. */
  180. int mwifiex_ret_11n_addba_req(struct mwifiex_private *priv,
  181. struct host_cmd_ds_command *resp)
  182. {
  183. int tid;
  184. struct host_cmd_ds_11n_addba_rsp *add_ba_rsp =
  185. (struct host_cmd_ds_11n_addba_rsp *) &resp->params.add_ba_rsp;
  186. struct mwifiex_tx_ba_stream_tbl *tx_ba_tbl;
  187. add_ba_rsp->ssn = cpu_to_le16((le16_to_cpu(add_ba_rsp->ssn))
  188. & SSN_MASK);
  189. tid = (le16_to_cpu(add_ba_rsp->block_ack_param_set)
  190. & IEEE80211_ADDBA_PARAM_TID_MASK)
  191. >> BLOCKACKPARAM_TID_POS;
  192. if (le16_to_cpu(add_ba_rsp->status_code) == BA_RESULT_SUCCESS) {
  193. tx_ba_tbl = mwifiex_11n_get_tx_ba_stream_tbl(priv, tid,
  194. add_ba_rsp->peer_mac_addr);
  195. if (tx_ba_tbl) {
  196. dev_dbg(priv->adapter->dev, "info: BA stream complete\n");
  197. tx_ba_tbl->ba_status = BA_STREAM_SETUP_COMPLETE;
  198. } else {
  199. dev_err(priv->adapter->dev, "BA stream not created\n");
  200. }
  201. } else {
  202. mwifiex_11n_delete_ba_stream_tbl(priv, tid,
  203. add_ba_rsp->peer_mac_addr,
  204. TYPE_DELBA_SENT, true);
  205. if (add_ba_rsp->add_rsp_result != BA_RESULT_TIMEOUT)
  206. priv->aggr_prio_tbl[tid].ampdu_ap =
  207. BA_STREAM_NOT_ALLOWED;
  208. }
  209. return 0;
  210. }
  211. /*
  212. * This function handles the command response of 11n configuration request.
  213. *
  214. * Handling includes changing the header fields into CPU format.
  215. */
  216. int mwifiex_ret_11n_cfg(struct mwifiex_private *priv,
  217. struct host_cmd_ds_command *resp,
  218. void *data_buf)
  219. {
  220. struct mwifiex_ds_11n_tx_cfg *tx_cfg = NULL;
  221. struct host_cmd_ds_11n_cfg *htcfg = &resp->params.htcfg;
  222. if (data_buf) {
  223. tx_cfg = (struct mwifiex_ds_11n_tx_cfg *) data_buf;
  224. tx_cfg->tx_htcap = le16_to_cpu(htcfg->ht_tx_cap);
  225. tx_cfg->tx_htinfo = le16_to_cpu(htcfg->ht_tx_info);
  226. }
  227. return 0;
  228. }
  229. /*
  230. * This function prepares command of reconfigure Tx buffer.
  231. *
  232. * Preparation includes -
  233. * - Setting command ID, action and proper size
  234. * - Setting Tx buffer size (for SET only)
  235. * - Ensuring correct endian-ness
  236. */
  237. int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv,
  238. struct host_cmd_ds_command *cmd, int cmd_action,
  239. void *data_buf)
  240. {
  241. struct host_cmd_ds_txbuf_cfg *tx_buf = &cmd->params.tx_buf;
  242. u16 action = (u16) cmd_action;
  243. u16 buf_size = *((u16 *) data_buf);
  244. cmd->command = cpu_to_le16(HostCmd_CMD_RECONFIGURE_TX_BUFF);
  245. cmd->size =
  246. cpu_to_le16(sizeof(struct host_cmd_ds_txbuf_cfg) + S_DS_GEN);
  247. tx_buf->action = cpu_to_le16(action);
  248. switch (action) {
  249. case HostCmd_ACT_GEN_SET:
  250. dev_dbg(priv->adapter->dev, "cmd: set tx_buf=%d\n", buf_size);
  251. tx_buf->buff_size = cpu_to_le16(buf_size);
  252. break;
  253. case HostCmd_ACT_GEN_GET:
  254. default:
  255. tx_buf->buff_size = 0;
  256. break;
  257. }
  258. return 0;
  259. }
  260. /*
  261. * This function prepares command of AMSDU aggregation control.
  262. *
  263. * Preparation includes -
  264. * - Setting command ID, action and proper size
  265. * - Setting AMSDU control parameters (for SET only)
  266. * - Ensuring correct endian-ness
  267. */
  268. int mwifiex_cmd_amsdu_aggr_ctrl(struct mwifiex_private *priv,
  269. struct host_cmd_ds_command *cmd,
  270. int cmd_action, void *data_buf)
  271. {
  272. struct host_cmd_ds_amsdu_aggr_ctrl *amsdu_ctrl =
  273. &cmd->params.amsdu_aggr_ctrl;
  274. u16 action = (u16) cmd_action;
  275. struct mwifiex_ds_11n_amsdu_aggr_ctrl *aa_ctrl =
  276. (struct mwifiex_ds_11n_amsdu_aggr_ctrl *) data_buf;
  277. cmd->command = cpu_to_le16(HostCmd_CMD_AMSDU_AGGR_CTRL);
  278. cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_amsdu_aggr_ctrl)
  279. + S_DS_GEN);
  280. amsdu_ctrl->action = cpu_to_le16(action);
  281. switch (action) {
  282. case HostCmd_ACT_GEN_SET:
  283. amsdu_ctrl->enable = cpu_to_le16(aa_ctrl->enable);
  284. amsdu_ctrl->curr_buf_size = 0;
  285. break;
  286. case HostCmd_ACT_GEN_GET:
  287. default:
  288. amsdu_ctrl->curr_buf_size = 0;
  289. break;
  290. }
  291. return 0;
  292. }
  293. /*
  294. * This function handles the command response of AMSDU aggregation
  295. * control request.
  296. *
  297. * Handling includes changing the header fields into CPU format.
  298. */
  299. int mwifiex_ret_amsdu_aggr_ctrl(struct mwifiex_private *priv,
  300. struct host_cmd_ds_command *resp,
  301. void *data_buf)
  302. {
  303. struct mwifiex_ds_11n_amsdu_aggr_ctrl *amsdu_aggr_ctrl = NULL;
  304. struct host_cmd_ds_amsdu_aggr_ctrl *amsdu_ctrl =
  305. &resp->params.amsdu_aggr_ctrl;
  306. if (data_buf) {
  307. amsdu_aggr_ctrl =
  308. (struct mwifiex_ds_11n_amsdu_aggr_ctrl *) data_buf;
  309. amsdu_aggr_ctrl->enable = le16_to_cpu(amsdu_ctrl->enable);
  310. amsdu_aggr_ctrl->curr_buf_size =
  311. le16_to_cpu(amsdu_ctrl->curr_buf_size);
  312. }
  313. return 0;
  314. }
  315. /*
  316. * This function prepares 11n configuration command.
  317. *
  318. * Preparation includes -
  319. * - Setting command ID, action and proper size
  320. * - Setting HT Tx capability and HT Tx information fields
  321. * - Ensuring correct endian-ness
  322. */
  323. int mwifiex_cmd_11n_cfg(struct mwifiex_private *priv,
  324. struct host_cmd_ds_command *cmd,
  325. u16 cmd_action, void *data_buf)
  326. {
  327. struct host_cmd_ds_11n_cfg *htcfg = &cmd->params.htcfg;
  328. struct mwifiex_ds_11n_tx_cfg *txcfg =
  329. (struct mwifiex_ds_11n_tx_cfg *) data_buf;
  330. cmd->command = cpu_to_le16(HostCmd_CMD_11N_CFG);
  331. cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_11n_cfg) + S_DS_GEN);
  332. htcfg->action = cpu_to_le16(cmd_action);
  333. htcfg->ht_tx_cap = cpu_to_le16(txcfg->tx_htcap);
  334. htcfg->ht_tx_info = cpu_to_le16(txcfg->tx_htinfo);
  335. return 0;
  336. }
  337. /*
  338. * This function appends an 11n TLV to a buffer.
  339. *
  340. * Buffer allocation is responsibility of the calling
  341. * function. No size validation is made here.
  342. *
  343. * The function fills up the following sections, if applicable -
  344. * - HT capability IE
  345. * - HT information IE (with channel list)
  346. * - 20/40 BSS Coexistence IE
  347. * - HT Extended Capabilities IE
  348. */
  349. int
  350. mwifiex_cmd_append_11n_tlv(struct mwifiex_private *priv,
  351. struct mwifiex_bssdescriptor *bss_desc,
  352. u8 **buffer)
  353. {
  354. struct mwifiex_ie_types_htcap *ht_cap;
  355. struct mwifiex_ie_types_htinfo *ht_info;
  356. struct mwifiex_ie_types_chan_list_param_set *chan_list;
  357. struct mwifiex_ie_types_2040bssco *bss_co_2040;
  358. struct mwifiex_ie_types_extcap *ext_cap;
  359. int ret_len = 0;
  360. if (!buffer || !*buffer)
  361. return ret_len;
  362. if (bss_desc->bcn_ht_cap) {
  363. ht_cap = (struct mwifiex_ie_types_htcap *) *buffer;
  364. memset(ht_cap, 0, sizeof(struct mwifiex_ie_types_htcap));
  365. ht_cap->header.type = cpu_to_le16(WLAN_EID_HT_CAPABILITY);
  366. ht_cap->header.len =
  367. cpu_to_le16(sizeof(struct ieee80211_ht_cap));
  368. memcpy((u8 *) ht_cap + sizeof(struct mwifiex_ie_types_header),
  369. (u8 *) bss_desc->bcn_ht_cap +
  370. sizeof(struct ieee_types_header),
  371. le16_to_cpu(ht_cap->header.len));
  372. mwifiex_fill_cap_info(priv, ht_cap);
  373. *buffer += sizeof(struct mwifiex_ie_types_htcap);
  374. ret_len += sizeof(struct mwifiex_ie_types_htcap);
  375. }
  376. if (bss_desc->bcn_ht_info) {
  377. if (priv->bss_mode == MWIFIEX_BSS_MODE_IBSS) {
  378. ht_info = (struct mwifiex_ie_types_htinfo *) *buffer;
  379. memset(ht_info, 0,
  380. sizeof(struct mwifiex_ie_types_htinfo));
  381. ht_info->header.type =
  382. cpu_to_le16(WLAN_EID_HT_INFORMATION);
  383. ht_info->header.len =
  384. cpu_to_le16(sizeof(struct ieee80211_ht_info));
  385. memcpy((u8 *) ht_info +
  386. sizeof(struct mwifiex_ie_types_header),
  387. (u8 *) bss_desc->bcn_ht_info +
  388. sizeof(struct ieee_types_header),
  389. le16_to_cpu(ht_info->header.len));
  390. if (!ISSUPP_CHANWIDTH40
  391. (priv->adapter->hw_dot_11n_dev_cap))
  392. ht_info->ht_info.ht_param &=
  393. ~(IEEE80211_HT_PARAM_CHAN_WIDTH_ANY |
  394. IEEE80211_HT_PARAM_CHA_SEC_OFFSET);
  395. *buffer += sizeof(struct mwifiex_ie_types_htinfo);
  396. ret_len += sizeof(struct mwifiex_ie_types_htinfo);
  397. }
  398. chan_list =
  399. (struct mwifiex_ie_types_chan_list_param_set *) *buffer;
  400. memset(chan_list, 0,
  401. sizeof(struct mwifiex_ie_types_chan_list_param_set));
  402. chan_list->header.type = cpu_to_le16(TLV_TYPE_CHANLIST);
  403. chan_list->header.len = cpu_to_le16(
  404. sizeof(struct mwifiex_ie_types_chan_list_param_set) -
  405. sizeof(struct mwifiex_ie_types_header));
  406. chan_list->chan_scan_param[0].chan_number =
  407. bss_desc->bcn_ht_info->control_chan;
  408. chan_list->chan_scan_param[0].radio_type =
  409. mwifiex_band_to_radio_type((u8) bss_desc->bss_band);
  410. if (ISSUPP_CHANWIDTH40(priv->adapter->hw_dot_11n_dev_cap)
  411. && (bss_desc->bcn_ht_info->ht_param &
  412. IEEE80211_HT_PARAM_CHAN_WIDTH_ANY))
  413. SET_SECONDARYCHAN(chan_list->chan_scan_param[0].
  414. radio_type,
  415. (bss_desc->bcn_ht_info->ht_param &
  416. IEEE80211_HT_PARAM_CHA_SEC_OFFSET));
  417. *buffer += sizeof(struct mwifiex_ie_types_chan_list_param_set);
  418. ret_len += sizeof(struct mwifiex_ie_types_chan_list_param_set);
  419. }
  420. if (bss_desc->bcn_bss_co_2040) {
  421. bss_co_2040 = (struct mwifiex_ie_types_2040bssco *) *buffer;
  422. memset(bss_co_2040, 0,
  423. sizeof(struct mwifiex_ie_types_2040bssco));
  424. bss_co_2040->header.type = cpu_to_le16(WLAN_EID_BSS_COEX_2040);
  425. bss_co_2040->header.len =
  426. cpu_to_le16(sizeof(bss_co_2040->bss_co_2040));
  427. memcpy((u8 *) bss_co_2040 +
  428. sizeof(struct mwifiex_ie_types_header),
  429. (u8 *) bss_desc->bcn_bss_co_2040 +
  430. sizeof(struct ieee_types_header),
  431. le16_to_cpu(bss_co_2040->header.len));
  432. *buffer += sizeof(struct mwifiex_ie_types_2040bssco);
  433. ret_len += sizeof(struct mwifiex_ie_types_2040bssco);
  434. }
  435. if (bss_desc->bcn_ext_cap) {
  436. ext_cap = (struct mwifiex_ie_types_extcap *) *buffer;
  437. memset(ext_cap, 0, sizeof(struct mwifiex_ie_types_extcap));
  438. ext_cap->header.type = cpu_to_le16(WLAN_EID_EXT_CAPABILITY);
  439. ext_cap->header.len = cpu_to_le16(sizeof(ext_cap->ext_cap));
  440. memcpy((u8 *) ext_cap +
  441. sizeof(struct mwifiex_ie_types_header),
  442. (u8 *) bss_desc->bcn_ext_cap +
  443. sizeof(struct ieee_types_header),
  444. le16_to_cpu(ext_cap->header.len));
  445. *buffer += sizeof(struct mwifiex_ie_types_extcap);
  446. ret_len += sizeof(struct mwifiex_ie_types_extcap);
  447. }
  448. return ret_len;
  449. }
  450. /*
  451. * This function reconfigures the Tx buffer size in firmware.
  452. *
  453. * This function prepares a firmware command and issues it, if
  454. * the current Tx buffer size is different from the one requested.
  455. * Maximum configurable Tx buffer size is limited by the HT capability
  456. * field value.
  457. */
  458. void
  459. mwifiex_cfg_tx_buf(struct mwifiex_private *priv,
  460. struct mwifiex_bssdescriptor *bss_desc)
  461. {
  462. u16 max_amsdu = MWIFIEX_TX_DATA_BUF_SIZE_2K;
  463. u16 tx_buf = 0;
  464. u16 curr_tx_buf_size = 0;
  465. if (bss_desc->bcn_ht_cap) {
  466. if (le16_to_cpu(bss_desc->bcn_ht_cap->cap_info) &
  467. IEEE80211_HT_CAP_MAX_AMSDU)
  468. max_amsdu = MWIFIEX_TX_DATA_BUF_SIZE_8K;
  469. else
  470. max_amsdu = MWIFIEX_TX_DATA_BUF_SIZE_4K;
  471. }
  472. tx_buf = min(priv->adapter->max_tx_buf_size, max_amsdu);
  473. dev_dbg(priv->adapter->dev, "info: max_amsdu=%d, max_tx_buf=%d\n",
  474. max_amsdu, priv->adapter->max_tx_buf_size);
  475. if (priv->adapter->curr_tx_buf_size <= MWIFIEX_TX_DATA_BUF_SIZE_2K)
  476. curr_tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K;
  477. else if (priv->adapter->curr_tx_buf_size <= MWIFIEX_TX_DATA_BUF_SIZE_4K)
  478. curr_tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K;
  479. else if (priv->adapter->curr_tx_buf_size <= MWIFIEX_TX_DATA_BUF_SIZE_8K)
  480. curr_tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_8K;
  481. if (curr_tx_buf_size != tx_buf)
  482. mwifiex_prepare_cmd(priv, HostCmd_CMD_RECONFIGURE_TX_BUFF,
  483. HostCmd_ACT_GEN_SET, 0,
  484. NULL, &tx_buf);
  485. return;
  486. }
  487. /*
  488. * This function checks if the given pointer is valid entry of
  489. * Tx BA Stream table.
  490. */
  491. static int mwifiex_is_tx_ba_stream_ptr_valid(struct mwifiex_private *priv,
  492. struct mwifiex_tx_ba_stream_tbl *tx_tbl_ptr)
  493. {
  494. struct mwifiex_tx_ba_stream_tbl *tx_ba_tsr_tbl;
  495. list_for_each_entry(tx_ba_tsr_tbl, &priv->tx_ba_stream_tbl_ptr, list) {
  496. if (tx_ba_tsr_tbl == tx_tbl_ptr)
  497. return true;
  498. }
  499. return false;
  500. }
  501. /*
  502. * This function deletes the given entry in Tx BA Stream table.
  503. *
  504. * The function also performs a validity check on the supplied
  505. * pointer before trying to delete.
  506. */
  507. void mwifiex_11n_delete_tx_ba_stream_tbl_entry(struct mwifiex_private *priv,
  508. struct mwifiex_tx_ba_stream_tbl *tx_ba_tsr_tbl)
  509. {
  510. if (!tx_ba_tsr_tbl &&
  511. mwifiex_is_tx_ba_stream_ptr_valid(priv, tx_ba_tsr_tbl))
  512. return;
  513. dev_dbg(priv->adapter->dev, "info: tx_ba_tsr_tbl %p\n", tx_ba_tsr_tbl);
  514. list_del(&tx_ba_tsr_tbl->list);
  515. kfree(tx_ba_tsr_tbl);
  516. return;
  517. }
  518. /*
  519. * This function deletes all the entries in Tx BA Stream table.
  520. */
  521. void mwifiex_11n_delete_all_tx_ba_stream_tbl(struct mwifiex_private *priv)
  522. {
  523. int i;
  524. struct mwifiex_tx_ba_stream_tbl *del_tbl_ptr, *tmp_node;
  525. unsigned long flags;
  526. spin_lock_irqsave(&priv->tx_ba_stream_tbl_lock, flags);
  527. list_for_each_entry_safe(del_tbl_ptr, tmp_node,
  528. &priv->tx_ba_stream_tbl_ptr, list)
  529. mwifiex_11n_delete_tx_ba_stream_tbl_entry(priv, del_tbl_ptr);
  530. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock, flags);
  531. INIT_LIST_HEAD(&priv->tx_ba_stream_tbl_ptr);
  532. for (i = 0; i < MAX_NUM_TID; ++i)
  533. priv->aggr_prio_tbl[i].ampdu_ap =
  534. priv->aggr_prio_tbl[i].ampdu_user;
  535. }
  536. /*
  537. * This function returns the pointer to an entry in BA Stream
  538. * table which matches the given RA/TID pair.
  539. */
  540. struct mwifiex_tx_ba_stream_tbl *
  541. mwifiex_11n_get_tx_ba_stream_tbl(struct mwifiex_private *priv,
  542. int tid, u8 *ra)
  543. {
  544. struct mwifiex_tx_ba_stream_tbl *tx_ba_tsr_tbl;
  545. unsigned long flags;
  546. spin_lock_irqsave(&priv->tx_ba_stream_tbl_lock, flags);
  547. list_for_each_entry(tx_ba_tsr_tbl, &priv->tx_ba_stream_tbl_ptr, list) {
  548. if ((!memcmp(tx_ba_tsr_tbl->ra, ra, ETH_ALEN))
  549. && (tx_ba_tsr_tbl->tid == tid)) {
  550. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock,
  551. flags);
  552. return tx_ba_tsr_tbl;
  553. }
  554. }
  555. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock, flags);
  556. return NULL;
  557. }
  558. /*
  559. * This function creates an entry in Tx BA stream table for the
  560. * given RA/TID pair.
  561. */
  562. void mwifiex_11n_create_tx_ba_stream_tbl(struct mwifiex_private *priv,
  563. u8 *ra, int tid,
  564. enum mwifiex_ba_status ba_status)
  565. {
  566. struct mwifiex_tx_ba_stream_tbl *new_node;
  567. unsigned long flags;
  568. if (!mwifiex_11n_get_tx_ba_stream_tbl(priv, tid, ra)) {
  569. new_node = kzalloc(sizeof(struct mwifiex_tx_ba_stream_tbl),
  570. GFP_ATOMIC);
  571. if (!new_node) {
  572. dev_err(priv->adapter->dev,
  573. "%s: failed to alloc new_node\n", __func__);
  574. return;
  575. }
  576. INIT_LIST_HEAD(&new_node->list);
  577. new_node->tid = tid;
  578. new_node->ba_status = ba_status;
  579. memcpy(new_node->ra, ra, ETH_ALEN);
  580. spin_lock_irqsave(&priv->tx_ba_stream_tbl_lock, flags);
  581. list_add_tail(&new_node->list, &priv->tx_ba_stream_tbl_ptr);
  582. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock, flags);
  583. }
  584. return;
  585. }
  586. /*
  587. * This function sends an add BA request to the given TID/RA pair.
  588. */
  589. int mwifiex_send_addba(struct mwifiex_private *priv, int tid, u8 *peer_mac)
  590. {
  591. struct host_cmd_ds_11n_addba_req add_ba_req;
  592. static u8 dialog_tok;
  593. int ret;
  594. dev_dbg(priv->adapter->dev, "cmd: %s: tid %d\n", __func__, tid);
  595. add_ba_req.block_ack_param_set = cpu_to_le16(
  596. (u16) ((tid << BLOCKACKPARAM_TID_POS) |
  597. (priv->add_ba_param.
  598. tx_win_size << BLOCKACKPARAM_WINSIZE_POS) |
  599. IMMEDIATE_BLOCK_ACK));
  600. add_ba_req.block_ack_tmo = cpu_to_le16((u16)priv->add_ba_param.timeout);
  601. ++dialog_tok;
  602. if (dialog_tok == 0)
  603. dialog_tok = 1;
  604. add_ba_req.dialog_token = dialog_tok;
  605. memcpy(&add_ba_req.peer_mac_addr, peer_mac, ETH_ALEN);
  606. /* We don't wait for the response of this command */
  607. ret = mwifiex_prepare_cmd(priv, HostCmd_CMD_11N_ADDBA_REQ,
  608. 0, 0, NULL, &add_ba_req);
  609. return ret;
  610. }
  611. /*
  612. * This function sends a delete BA request to the given TID/RA pair.
  613. */
  614. int mwifiex_send_delba(struct mwifiex_private *priv, int tid, u8 *peer_mac,
  615. int initiator)
  616. {
  617. struct host_cmd_ds_11n_delba delba;
  618. int ret;
  619. uint16_t del_ba_param_set;
  620. memset(&delba, 0, sizeof(delba));
  621. delba.del_ba_param_set = cpu_to_le16(tid << DELBA_TID_POS);
  622. del_ba_param_set = le16_to_cpu(delba.del_ba_param_set);
  623. if (initiator)
  624. del_ba_param_set |= IEEE80211_DELBA_PARAM_INITIATOR_MASK;
  625. else
  626. del_ba_param_set &= ~IEEE80211_DELBA_PARAM_INITIATOR_MASK;
  627. memcpy(&delba.peer_mac_addr, peer_mac, ETH_ALEN);
  628. /* We don't wait for the response of this command */
  629. ret = mwifiex_prepare_cmd(priv, HostCmd_CMD_11N_DELBA,
  630. HostCmd_ACT_GEN_SET, 0, NULL, &delba);
  631. return ret;
  632. }
  633. /*
  634. * This function handles the command response of a delete BA request.
  635. */
  636. void mwifiex_11n_delete_ba_stream(struct mwifiex_private *priv, u8 *del_ba)
  637. {
  638. struct host_cmd_ds_11n_delba *cmd_del_ba =
  639. (struct host_cmd_ds_11n_delba *) del_ba;
  640. uint16_t del_ba_param_set = le16_to_cpu(cmd_del_ba->del_ba_param_set);
  641. int tid;
  642. tid = del_ba_param_set >> DELBA_TID_POS;
  643. mwifiex_11n_delete_ba_stream_tbl(priv, tid, cmd_del_ba->peer_mac_addr,
  644. TYPE_DELBA_RECEIVE,
  645. INITIATOR_BIT(del_ba_param_set));
  646. }
  647. /*
  648. * This function retrieves the Rx reordering table.
  649. */
  650. int mwifiex_get_rx_reorder_tbl(struct mwifiex_private *priv,
  651. struct mwifiex_ds_rx_reorder_tbl *buf)
  652. {
  653. int i;
  654. struct mwifiex_ds_rx_reorder_tbl *rx_reo_tbl = buf;
  655. struct mwifiex_rx_reorder_tbl *rx_reorder_tbl_ptr;
  656. int count = 0;
  657. unsigned long flags;
  658. spin_lock_irqsave(&priv->rx_reorder_tbl_lock, flags);
  659. list_for_each_entry(rx_reorder_tbl_ptr, &priv->rx_reorder_tbl_ptr,
  660. list) {
  661. rx_reo_tbl->tid = (u16) rx_reorder_tbl_ptr->tid;
  662. memcpy(rx_reo_tbl->ta, rx_reorder_tbl_ptr->ta, ETH_ALEN);
  663. rx_reo_tbl->start_win = rx_reorder_tbl_ptr->start_win;
  664. rx_reo_tbl->win_size = rx_reorder_tbl_ptr->win_size;
  665. for (i = 0; i < rx_reorder_tbl_ptr->win_size; ++i) {
  666. if (rx_reorder_tbl_ptr->rx_reorder_ptr[i])
  667. rx_reo_tbl->buffer[i] = true;
  668. else
  669. rx_reo_tbl->buffer[i] = false;
  670. }
  671. rx_reo_tbl++;
  672. count++;
  673. if (count >= MWIFIEX_MAX_RX_BASTREAM_SUPPORTED)
  674. break;
  675. }
  676. spin_unlock_irqrestore(&priv->rx_reorder_tbl_lock, flags);
  677. return count;
  678. }
  679. /*
  680. * This function retrieves the Tx BA stream table.
  681. */
  682. int mwifiex_get_tx_ba_stream_tbl(struct mwifiex_private *priv,
  683. struct mwifiex_ds_tx_ba_stream_tbl *buf)
  684. {
  685. struct mwifiex_tx_ba_stream_tbl *tx_ba_tsr_tbl;
  686. struct mwifiex_ds_tx_ba_stream_tbl *rx_reo_tbl = buf;
  687. int count = 0;
  688. unsigned long flags;
  689. spin_lock_irqsave(&priv->tx_ba_stream_tbl_lock, flags);
  690. list_for_each_entry(tx_ba_tsr_tbl, &priv->tx_ba_stream_tbl_ptr, list) {
  691. rx_reo_tbl->tid = (u16) tx_ba_tsr_tbl->tid;
  692. dev_dbg(priv->adapter->dev, "data: %s tid=%d\n",
  693. __func__, rx_reo_tbl->tid);
  694. memcpy(rx_reo_tbl->ra, tx_ba_tsr_tbl->ra, ETH_ALEN);
  695. rx_reo_tbl++;
  696. count++;
  697. if (count >= MWIFIEX_MAX_TX_BASTREAM_SUPPORTED)
  698. break;
  699. }
  700. spin_unlock_irqrestore(&priv->tx_ba_stream_tbl_lock, flags);
  701. return count;
  702. }