pm-debug.c 15 KB

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  1. /*
  2. * OMAP Power Management debug routines
  3. *
  4. * Copyright (C) 2005 Texas Instruments, Inc.
  5. * Copyright (C) 2006-2008 Nokia Corporation
  6. *
  7. * Written by:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Tony Lindgren
  10. * Juha Yrjola
  11. * Amit Kucheria <amit.kucheria@nokia.com>
  12. * Igor Stoppa <igor.stoppa@nokia.com>
  13. * Jouni Hogander
  14. *
  15. * Based on pm.c for omap2
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/sched.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/io.h>
  26. #include <linux/module.h>
  27. #include <linux/slab.h>
  28. #include <plat/clock.h>
  29. #include <plat/board.h>
  30. #include <plat/powerdomain.h>
  31. #include <plat/clockdomain.h>
  32. #include "prm.h"
  33. #include "cm.h"
  34. #include "pm.h"
  35. int omap2_pm_debug;
  36. u32 enable_off_mode;
  37. u32 sleep_while_idle;
  38. u32 wakeup_timer_seconds;
  39. u32 wakeup_timer_milliseconds;
  40. #define DUMP_PRM_MOD_REG(mod, reg) \
  41. regs[reg_count].name = #mod "." #reg; \
  42. regs[reg_count++].val = prm_read_mod_reg(mod, reg)
  43. #define DUMP_CM_MOD_REG(mod, reg) \
  44. regs[reg_count].name = #mod "." #reg; \
  45. regs[reg_count++].val = cm_read_mod_reg(mod, reg)
  46. #define DUMP_PRM_REG(reg) \
  47. regs[reg_count].name = #reg; \
  48. regs[reg_count++].val = __raw_readl(reg)
  49. #define DUMP_CM_REG(reg) \
  50. regs[reg_count].name = #reg; \
  51. regs[reg_count++].val = __raw_readl(reg)
  52. #define DUMP_INTC_REG(reg, off) \
  53. regs[reg_count].name = #reg; \
  54. regs[reg_count++].val = \
  55. __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
  56. void omap2_pm_dump(int mode, int resume, unsigned int us)
  57. {
  58. struct reg {
  59. const char *name;
  60. u32 val;
  61. } regs[32];
  62. int reg_count = 0, i;
  63. const char *s1 = NULL, *s2 = NULL;
  64. if (!resume) {
  65. #if 0
  66. /* MPU */
  67. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
  68. DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
  69. DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
  70. DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
  71. DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
  72. #endif
  73. #if 0
  74. /* INTC */
  75. DUMP_INTC_REG(INTC_MIR0, 0x0084);
  76. DUMP_INTC_REG(INTC_MIR1, 0x00a4);
  77. DUMP_INTC_REG(INTC_MIR2, 0x00c4);
  78. #endif
  79. #if 0
  80. DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
  81. if (cpu_is_omap24xx()) {
  82. DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  83. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  84. OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
  85. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  86. OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
  87. }
  88. DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
  89. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
  90. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
  91. DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
  92. DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
  93. DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
  94. DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
  95. #endif
  96. #if 0
  97. /* DSP */
  98. if (cpu_is_omap24xx()) {
  99. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
  100. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
  101. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
  102. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
  103. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
  104. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
  105. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
  106. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
  107. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
  108. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
  109. }
  110. #endif
  111. } else {
  112. DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
  113. if (cpu_is_omap24xx())
  114. DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
  115. DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
  116. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  117. #if 1
  118. DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
  119. DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
  120. DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
  121. #endif
  122. }
  123. switch (mode) {
  124. case 0:
  125. s1 = "full";
  126. s2 = "retention";
  127. break;
  128. case 1:
  129. s1 = "MPU";
  130. s2 = "retention";
  131. break;
  132. case 2:
  133. s1 = "MPU";
  134. s2 = "idle";
  135. break;
  136. }
  137. if (!resume)
  138. #ifdef CONFIG_NO_HZ
  139. printk(KERN_INFO
  140. "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
  141. jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
  142. jiffies));
  143. #else
  144. printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
  145. #endif
  146. else
  147. printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
  148. us / 1000, us % 1000);
  149. for (i = 0; i < reg_count; i++)
  150. printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
  151. }
  152. #ifdef CONFIG_DEBUG_FS
  153. #include <linux/debugfs.h>
  154. #include <linux/seq_file.h>
  155. static void pm_dbg_regset_store(u32 *ptr);
  156. struct dentry *pm_dbg_dir;
  157. static int pm_dbg_init_done;
  158. static int __init pm_dbg_init(void);
  159. enum {
  160. DEBUG_FILE_COUNTERS = 0,
  161. DEBUG_FILE_TIMERS,
  162. };
  163. struct pm_module_def {
  164. char name[8]; /* Name of the module */
  165. short type; /* CM or PRM */
  166. unsigned short offset;
  167. int low; /* First register address on this module */
  168. int high; /* Last register address on this module */
  169. };
  170. #define MOD_CM 0
  171. #define MOD_PRM 1
  172. static const struct pm_module_def *pm_dbg_reg_modules;
  173. static const struct pm_module_def omap3_pm_reg_modules[] = {
  174. { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
  175. { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
  176. { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
  177. { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
  178. { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
  179. { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
  180. { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
  181. { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
  182. { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
  183. { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
  184. { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
  185. { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
  186. { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
  187. { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
  188. { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
  189. { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
  190. { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
  191. { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
  192. { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
  193. { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
  194. { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
  195. { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
  196. { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
  197. { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
  198. { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
  199. { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
  200. { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
  201. { "", 0, 0, 0, 0 },
  202. };
  203. #define PM_DBG_MAX_REG_SETS 4
  204. static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
  205. static int pm_dbg_get_regset_size(void)
  206. {
  207. static int regset_size;
  208. if (regset_size == 0) {
  209. int i = 0;
  210. while (pm_dbg_reg_modules[i].name[0] != 0) {
  211. regset_size += pm_dbg_reg_modules[i].high +
  212. 4 - pm_dbg_reg_modules[i].low;
  213. i++;
  214. }
  215. }
  216. return regset_size;
  217. }
  218. static int pm_dbg_show_regs(struct seq_file *s, void *unused)
  219. {
  220. int i, j;
  221. unsigned long val;
  222. int reg_set = (int)s->private;
  223. u32 *ptr;
  224. void *store = NULL;
  225. int regs;
  226. int linefeed;
  227. if (reg_set == 0) {
  228. store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  229. ptr = store;
  230. pm_dbg_regset_store(ptr);
  231. } else {
  232. ptr = pm_dbg_reg_set[reg_set - 1];
  233. }
  234. i = 0;
  235. while (pm_dbg_reg_modules[i].name[0] != 0) {
  236. regs = 0;
  237. linefeed = 0;
  238. if (pm_dbg_reg_modules[i].type == MOD_CM)
  239. seq_printf(s, "MOD: CM_%s (%08x)\n",
  240. pm_dbg_reg_modules[i].name,
  241. (u32)(OMAP3430_CM_BASE +
  242. pm_dbg_reg_modules[i].offset));
  243. else
  244. seq_printf(s, "MOD: PRM_%s (%08x)\n",
  245. pm_dbg_reg_modules[i].name,
  246. (u32)(OMAP3430_PRM_BASE +
  247. pm_dbg_reg_modules[i].offset));
  248. for (j = pm_dbg_reg_modules[i].low;
  249. j <= pm_dbg_reg_modules[i].high; j += 4) {
  250. val = *(ptr++);
  251. if (val != 0) {
  252. regs++;
  253. if (linefeed) {
  254. seq_printf(s, "\n");
  255. linefeed = 0;
  256. }
  257. seq_printf(s, " %02x => %08lx", j, val);
  258. if (regs % 4 == 0)
  259. linefeed = 1;
  260. }
  261. }
  262. seq_printf(s, "\n");
  263. i++;
  264. }
  265. if (store != NULL)
  266. kfree(store);
  267. return 0;
  268. }
  269. static void pm_dbg_regset_store(u32 *ptr)
  270. {
  271. int i, j;
  272. u32 val;
  273. i = 0;
  274. while (pm_dbg_reg_modules[i].name[0] != 0) {
  275. for (j = pm_dbg_reg_modules[i].low;
  276. j <= pm_dbg_reg_modules[i].high; j += 4) {
  277. if (pm_dbg_reg_modules[i].type == MOD_CM)
  278. val = cm_read_mod_reg(
  279. pm_dbg_reg_modules[i].offset, j);
  280. else
  281. val = prm_read_mod_reg(
  282. pm_dbg_reg_modules[i].offset, j);
  283. *(ptr++) = val;
  284. }
  285. i++;
  286. }
  287. }
  288. int pm_dbg_regset_save(int reg_set)
  289. {
  290. if (pm_dbg_reg_set[reg_set-1] == NULL)
  291. return -EINVAL;
  292. pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
  293. return 0;
  294. }
  295. static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
  296. "OFF",
  297. "RET",
  298. "INA",
  299. "ON"
  300. };
  301. void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
  302. {
  303. s64 t;
  304. if (!pm_dbg_init_done)
  305. return ;
  306. /* Update timer for previous state */
  307. t = sched_clock();
  308. pwrdm->state_timer[prev] += t - pwrdm->timer;
  309. pwrdm->timer = t;
  310. }
  311. static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
  312. {
  313. struct seq_file *s = (struct seq_file *)user;
  314. if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
  315. strcmp(clkdm->name, "wkup_clkdm") == 0 ||
  316. strncmp(clkdm->name, "dpll", 4) == 0)
  317. return 0;
  318. seq_printf(s, "%s->%s (%d)", clkdm->name,
  319. clkdm->pwrdm.ptr->name,
  320. atomic_read(&clkdm->usecount));
  321. seq_printf(s, "\n");
  322. return 0;
  323. }
  324. static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
  325. {
  326. struct seq_file *s = (struct seq_file *)user;
  327. int i;
  328. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  329. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  330. strncmp(pwrdm->name, "dpll", 4) == 0)
  331. return 0;
  332. if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
  333. printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
  334. pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
  335. seq_printf(s, "%s (%s)", pwrdm->name,
  336. pwrdm_state_names[pwrdm->state]);
  337. for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
  338. seq_printf(s, ",%s:%d", pwrdm_state_names[i],
  339. pwrdm->state_counter[i]);
  340. seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
  341. for (i = 0; i < pwrdm->banks; i++)
  342. seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
  343. pwrdm->ret_mem_off_counter[i]);
  344. seq_printf(s, "\n");
  345. return 0;
  346. }
  347. static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
  348. {
  349. struct seq_file *s = (struct seq_file *)user;
  350. int i;
  351. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  352. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  353. strncmp(pwrdm->name, "dpll", 4) == 0)
  354. return 0;
  355. pwrdm_state_switch(pwrdm);
  356. seq_printf(s, "%s (%s)", pwrdm->name,
  357. pwrdm_state_names[pwrdm->state]);
  358. for (i = 0; i < 4; i++)
  359. seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
  360. pwrdm->state_timer[i]);
  361. seq_printf(s, "\n");
  362. return 0;
  363. }
  364. static int pm_dbg_show_counters(struct seq_file *s, void *unused)
  365. {
  366. pwrdm_for_each(pwrdm_dbg_show_counter, s);
  367. clkdm_for_each(clkdm_dbg_show_counter, s);
  368. return 0;
  369. }
  370. static int pm_dbg_show_timers(struct seq_file *s, void *unused)
  371. {
  372. pwrdm_for_each(pwrdm_dbg_show_timer, s);
  373. return 0;
  374. }
  375. static int pm_dbg_open(struct inode *inode, struct file *file)
  376. {
  377. switch ((int)inode->i_private) {
  378. case DEBUG_FILE_COUNTERS:
  379. return single_open(file, pm_dbg_show_counters,
  380. &inode->i_private);
  381. case DEBUG_FILE_TIMERS:
  382. default:
  383. return single_open(file, pm_dbg_show_timers,
  384. &inode->i_private);
  385. };
  386. }
  387. static int pm_dbg_reg_open(struct inode *inode, struct file *file)
  388. {
  389. return single_open(file, pm_dbg_show_regs, inode->i_private);
  390. }
  391. static const struct file_operations debug_fops = {
  392. .open = pm_dbg_open,
  393. .read = seq_read,
  394. .llseek = seq_lseek,
  395. .release = single_release,
  396. };
  397. static const struct file_operations debug_reg_fops = {
  398. .open = pm_dbg_reg_open,
  399. .read = seq_read,
  400. .llseek = seq_lseek,
  401. .release = single_release,
  402. };
  403. int pm_dbg_regset_init(int reg_set)
  404. {
  405. char name[2];
  406. if (!pm_dbg_init_done)
  407. pm_dbg_init();
  408. if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
  409. pm_dbg_reg_set[reg_set-1] != NULL)
  410. return -EINVAL;
  411. pm_dbg_reg_set[reg_set-1] =
  412. kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  413. if (pm_dbg_reg_set[reg_set-1] == NULL)
  414. return -ENOMEM;
  415. if (pm_dbg_dir != NULL) {
  416. sprintf(name, "%d", reg_set);
  417. (void) debugfs_create_file(name, S_IRUGO,
  418. pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
  419. }
  420. return 0;
  421. }
  422. static int pwrdm_suspend_get(void *data, u64 *val)
  423. {
  424. int ret = -EINVAL;
  425. if (cpu_is_omap34xx())
  426. ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
  427. *val = ret;
  428. if (ret >= 0)
  429. return 0;
  430. return *val;
  431. }
  432. static int pwrdm_suspend_set(void *data, u64 val)
  433. {
  434. if (cpu_is_omap34xx())
  435. return omap3_pm_set_suspend_state(
  436. (struct powerdomain *)data, (int)val);
  437. return -EINVAL;
  438. }
  439. DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
  440. pwrdm_suspend_set, "%llu\n");
  441. static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
  442. {
  443. int i;
  444. s64 t;
  445. struct dentry *d;
  446. t = sched_clock();
  447. for (i = 0; i < 4; i++)
  448. pwrdm->state_timer[i] = 0;
  449. pwrdm->timer = t;
  450. if (strncmp(pwrdm->name, "dpll", 4) == 0)
  451. return 0;
  452. d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
  453. (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
  454. (void *)pwrdm, &pwrdm_suspend_fops);
  455. return 0;
  456. }
  457. static int option_get(void *data, u64 *val)
  458. {
  459. u32 *option = data;
  460. *val = *option;
  461. return 0;
  462. }
  463. static int option_set(void *data, u64 val)
  464. {
  465. u32 *option = data;
  466. if (option == &wakeup_timer_milliseconds && val >= 1000)
  467. return -EINVAL;
  468. *option = val;
  469. if (option == &enable_off_mode) {
  470. if (cpu_is_omap34xx())
  471. omap3_pm_off_mode_enable(val);
  472. }
  473. return 0;
  474. }
  475. DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
  476. static int __init pm_dbg_init(void)
  477. {
  478. int i;
  479. struct dentry *d;
  480. char name[2];
  481. if (pm_dbg_init_done)
  482. return 0;
  483. if (cpu_is_omap34xx())
  484. pm_dbg_reg_modules = omap3_pm_reg_modules;
  485. else {
  486. printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
  487. return -ENODEV;
  488. }
  489. d = debugfs_create_dir("pm_debug", NULL);
  490. if (IS_ERR(d))
  491. return PTR_ERR(d);
  492. (void) debugfs_create_file("count", S_IRUGO,
  493. d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
  494. (void) debugfs_create_file("time", S_IRUGO,
  495. d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
  496. pwrdm_for_each(pwrdms_setup, (void *)d);
  497. pm_dbg_dir = debugfs_create_dir("registers", d);
  498. if (IS_ERR(pm_dbg_dir))
  499. return PTR_ERR(pm_dbg_dir);
  500. (void) debugfs_create_file("current", S_IRUGO,
  501. pm_dbg_dir, (void *)0, &debug_reg_fops);
  502. for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
  503. if (pm_dbg_reg_set[i] != NULL) {
  504. sprintf(name, "%d", i+1);
  505. (void) debugfs_create_file(name, S_IRUGO,
  506. pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
  507. }
  508. (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
  509. &enable_off_mode, &pm_dbg_option_fops);
  510. (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
  511. &sleep_while_idle, &pm_dbg_option_fops);
  512. (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
  513. &wakeup_timer_seconds, &pm_dbg_option_fops);
  514. pm_dbg_init_done = 1;
  515. return 0;
  516. }
  517. arch_initcall(pm_dbg_init);
  518. #endif