aaci.c 25 KB

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  1. /*
  2. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Documentation: ARM DDI 0173B
  11. */
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <linux/amba/bus.h>
  21. #include <linux/io.h>
  22. #include <sound/core.h>
  23. #include <sound/initval.h>
  24. #include <sound/ac97_codec.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "aaci.h"
  28. #define DRIVER_NAME "aaci-pl041"
  29. /*
  30. * PM support is not complete. Turn it off.
  31. */
  32. #undef CONFIG_PM
  33. static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  34. {
  35. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  36. /*
  37. * Ensure that the slot 1/2 RX registers are empty.
  38. */
  39. v = readl(aaci->base + AACI_SLFR);
  40. if (v & SLFR_2RXV)
  41. readl(aaci->base + AACI_SL2RX);
  42. if (v & SLFR_1RXV)
  43. readl(aaci->base + AACI_SL1RX);
  44. writel(maincr, aaci->base + AACI_MAINCR);
  45. }
  46. /*
  47. * P29:
  48. * The recommended use of programming the external codec through slot 1
  49. * and slot 2 data is to use the channels during setup routines and the
  50. * slot register at any other time. The data written into slot 1, slot 2
  51. * and slot 12 registers is transmitted only when their corresponding
  52. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  53. * register.
  54. */
  55. static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  56. unsigned short val)
  57. {
  58. struct aaci *aaci = ac97->private_data;
  59. u32 v;
  60. int timeout = 5000;
  61. if (ac97->num >= 4)
  62. return;
  63. mutex_lock(&aaci->ac97_sem);
  64. aaci_ac97_select_codec(aaci, ac97);
  65. /*
  66. * P54: You must ensure that AACI_SL2TX is always written
  67. * to, if required, before data is written to AACI_SL1TX.
  68. */
  69. writel(val << 4, aaci->base + AACI_SL2TX);
  70. writel(reg << 12, aaci->base + AACI_SL1TX);
  71. /*
  72. * Wait for the transmission of both slots to complete.
  73. */
  74. do {
  75. v = readl(aaci->base + AACI_SLFR);
  76. } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
  77. if (!timeout)
  78. dev_err(&aaci->dev->dev,
  79. "timeout waiting for write to complete\n");
  80. mutex_unlock(&aaci->ac97_sem);
  81. }
  82. /*
  83. * Read an AC'97 register.
  84. */
  85. static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  86. {
  87. struct aaci *aaci = ac97->private_data;
  88. u32 v;
  89. int timeout = 5000;
  90. int retries = 10;
  91. if (ac97->num >= 4)
  92. return ~0;
  93. mutex_lock(&aaci->ac97_sem);
  94. aaci_ac97_select_codec(aaci, ac97);
  95. /*
  96. * Write the register address to slot 1.
  97. */
  98. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  99. /*
  100. * Wait for the transmission to complete.
  101. */
  102. do {
  103. v = readl(aaci->base + AACI_SLFR);
  104. } while ((v & SLFR_1TXB) && --timeout);
  105. if (!timeout) {
  106. dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
  107. v = ~0;
  108. goto out;
  109. }
  110. /*
  111. * Give the AC'97 codec more than enough time
  112. * to respond. (42us = ~2 frames at 48kHz.)
  113. */
  114. udelay(42);
  115. /*
  116. * Wait for slot 2 to indicate data.
  117. */
  118. timeout = 5000;
  119. do {
  120. cond_resched();
  121. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  122. } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
  123. if (!timeout) {
  124. dev_err(&aaci->dev->dev, "timeout on RX valid\n");
  125. v = ~0;
  126. goto out;
  127. }
  128. do {
  129. v = readl(aaci->base + AACI_SL1RX) >> 12;
  130. if (v == reg) {
  131. v = readl(aaci->base + AACI_SL2RX) >> 4;
  132. break;
  133. } else if (--retries) {
  134. dev_warn(&aaci->dev->dev,
  135. "ac97 read back fail. retry\n");
  136. continue;
  137. } else {
  138. dev_warn(&aaci->dev->dev,
  139. "wrong ac97 register read back (%x != %x)\n",
  140. v, reg);
  141. v = ~0;
  142. }
  143. } while (retries);
  144. out:
  145. mutex_unlock(&aaci->ac97_sem);
  146. return v;
  147. }
  148. static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
  149. {
  150. u32 val;
  151. int timeout = 5000;
  152. do {
  153. val = readl(aacirun->base + AACI_SR);
  154. } while (val & (SR_TXB|SR_RXB) && timeout--);
  155. }
  156. /*
  157. * Interrupt support.
  158. */
  159. static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
  160. {
  161. if (mask & ISR_ORINTR) {
  162. dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
  163. writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
  164. }
  165. if (mask & ISR_RXTOINTR) {
  166. dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
  167. writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
  168. }
  169. if (mask & ISR_RXINTR) {
  170. struct aaci_runtime *aacirun = &aaci->capture;
  171. void *ptr;
  172. if (!aacirun->substream || !aacirun->start) {
  173. dev_warn(&aaci->dev->dev, "RX interrupt???\n");
  174. writel(0, aacirun->base + AACI_IE);
  175. return;
  176. }
  177. ptr = aacirun->ptr;
  178. do {
  179. unsigned int len = aacirun->fifosz;
  180. u32 val;
  181. if (aacirun->bytes <= 0) {
  182. aacirun->bytes += aacirun->period;
  183. aacirun->ptr = ptr;
  184. spin_unlock(&aaci->lock);
  185. snd_pcm_period_elapsed(aacirun->substream);
  186. spin_lock(&aaci->lock);
  187. }
  188. if (!(aacirun->cr & CR_EN))
  189. break;
  190. val = readl(aacirun->base + AACI_SR);
  191. if (!(val & SR_RXHF))
  192. break;
  193. if (!(val & SR_RXFF))
  194. len >>= 1;
  195. aacirun->bytes -= len;
  196. /* reading 16 bytes at a time */
  197. for( ; len > 0; len -= 16) {
  198. asm(
  199. "ldmia %1, {r0, r1, r2, r3}\n\t"
  200. "stmia %0!, {r0, r1, r2, r3}"
  201. : "+r" (ptr)
  202. : "r" (aacirun->fifo)
  203. : "r0", "r1", "r2", "r3", "cc");
  204. if (ptr >= aacirun->end)
  205. ptr = aacirun->start;
  206. }
  207. } while(1);
  208. aacirun->ptr = ptr;
  209. }
  210. if (mask & ISR_URINTR) {
  211. dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
  212. writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
  213. }
  214. if (mask & ISR_TXINTR) {
  215. struct aaci_runtime *aacirun = &aaci->playback;
  216. void *ptr;
  217. if (!aacirun->substream || !aacirun->start) {
  218. dev_warn(&aaci->dev->dev, "TX interrupt???\n");
  219. writel(0, aacirun->base + AACI_IE);
  220. return;
  221. }
  222. ptr = aacirun->ptr;
  223. do {
  224. unsigned int len = aacirun->fifosz;
  225. u32 val;
  226. if (aacirun->bytes <= 0) {
  227. aacirun->bytes += aacirun->period;
  228. aacirun->ptr = ptr;
  229. spin_unlock(&aaci->lock);
  230. snd_pcm_period_elapsed(aacirun->substream);
  231. spin_lock(&aaci->lock);
  232. }
  233. if (!(aacirun->cr & CR_EN))
  234. break;
  235. val = readl(aacirun->base + AACI_SR);
  236. if (!(val & SR_TXHE))
  237. break;
  238. if (!(val & SR_TXFE))
  239. len >>= 1;
  240. aacirun->bytes -= len;
  241. /* writing 16 bytes at a time */
  242. for ( ; len > 0; len -= 16) {
  243. asm(
  244. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  245. "stmia %1, {r0, r1, r2, r3}"
  246. : "+r" (ptr)
  247. : "r" (aacirun->fifo)
  248. : "r0", "r1", "r2", "r3", "cc");
  249. if (ptr >= aacirun->end)
  250. ptr = aacirun->start;
  251. }
  252. } while (1);
  253. aacirun->ptr = ptr;
  254. }
  255. }
  256. static irqreturn_t aaci_irq(int irq, void *devid)
  257. {
  258. struct aaci *aaci = devid;
  259. u32 mask;
  260. int i;
  261. spin_lock(&aaci->lock);
  262. mask = readl(aaci->base + AACI_ALLINTS);
  263. if (mask) {
  264. u32 m = mask;
  265. for (i = 0; i < 4; i++, m >>= 7) {
  266. if (m & 0x7f) {
  267. aaci_fifo_irq(aaci, i, m);
  268. }
  269. }
  270. }
  271. spin_unlock(&aaci->lock);
  272. return mask ? IRQ_HANDLED : IRQ_NONE;
  273. }
  274. /*
  275. * ALSA support.
  276. */
  277. static struct snd_pcm_hardware aaci_hw_info = {
  278. .info = SNDRV_PCM_INFO_MMAP |
  279. SNDRV_PCM_INFO_MMAP_VALID |
  280. SNDRV_PCM_INFO_INTERLEAVED |
  281. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  282. SNDRV_PCM_INFO_RESUME,
  283. /*
  284. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  285. * words. It also doesn't support 12-bit at all.
  286. */
  287. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  288. /* rates are setup from the AC'97 codec */
  289. .channels_min = 2,
  290. .channels_max = 6,
  291. .buffer_bytes_max = 64 * 1024,
  292. .period_bytes_min = 256,
  293. .period_bytes_max = PAGE_SIZE,
  294. .periods_min = 4,
  295. .periods_max = PAGE_SIZE / 16,
  296. };
  297. static int __aaci_pcm_open(struct aaci *aaci,
  298. struct snd_pcm_substream *substream,
  299. struct aaci_runtime *aacirun)
  300. {
  301. struct snd_pcm_runtime *runtime = substream->runtime;
  302. int ret;
  303. aacirun->substream = substream;
  304. runtime->private_data = aacirun;
  305. runtime->hw = aaci_hw_info;
  306. runtime->hw.rates = aacirun->pcm->rates;
  307. snd_pcm_limit_hw_rates(runtime);
  308. /*
  309. * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
  310. * mode, each 32-bit word contains one sample. If we're in
  311. * compact mode, each 32-bit word contains two samples, effectively
  312. * halving the FIFO size. However, we don't know for sure which
  313. * we'll be using at this point. We set this to the lower limit.
  314. */
  315. runtime->hw.fifo_size = aaci->fifosize * 2;
  316. ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
  317. DRIVER_NAME, aaci);
  318. if (ret)
  319. goto out;
  320. return 0;
  321. out:
  322. return ret;
  323. }
  324. /*
  325. * Common ALSA stuff
  326. */
  327. static int aaci_pcm_close(struct snd_pcm_substream *substream)
  328. {
  329. struct aaci *aaci = substream->private_data;
  330. struct aaci_runtime *aacirun = substream->runtime->private_data;
  331. WARN_ON(aacirun->cr & CR_EN);
  332. aacirun->substream = NULL;
  333. free_irq(aaci->dev->irq[0], aaci);
  334. return 0;
  335. }
  336. static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
  337. {
  338. struct aaci_runtime *aacirun = substream->runtime->private_data;
  339. /*
  340. * This must not be called with the device enabled.
  341. */
  342. WARN_ON(aacirun->cr & CR_EN);
  343. if (aacirun->pcm_open)
  344. snd_ac97_pcm_close(aacirun->pcm);
  345. aacirun->pcm_open = 0;
  346. /*
  347. * Clear out the DMA and any allocated buffers.
  348. */
  349. snd_pcm_lib_free_pages(substream);
  350. return 0;
  351. }
  352. static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
  353. struct aaci_runtime *aacirun,
  354. struct snd_pcm_hw_params *params)
  355. {
  356. int err;
  357. aaci_pcm_hw_free(substream);
  358. if (aacirun->pcm_open) {
  359. snd_ac97_pcm_close(aacirun->pcm);
  360. aacirun->pcm_open = 0;
  361. }
  362. err = snd_pcm_lib_malloc_pages(substream,
  363. params_buffer_bytes(params));
  364. if (err < 0)
  365. goto out;
  366. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  367. params_channels(params),
  368. aacirun->pcm->r[0].slots);
  369. if (err)
  370. goto out;
  371. aacirun->pcm_open = 1;
  372. out:
  373. return err;
  374. }
  375. static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
  376. {
  377. struct snd_pcm_runtime *runtime = substream->runtime;
  378. struct aaci_runtime *aacirun = runtime->private_data;
  379. aacirun->start = (void *)runtime->dma_area;
  380. aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
  381. aacirun->ptr = aacirun->start;
  382. aacirun->period =
  383. aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
  384. return 0;
  385. }
  386. static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
  387. {
  388. struct snd_pcm_runtime *runtime = substream->runtime;
  389. struct aaci_runtime *aacirun = runtime->private_data;
  390. ssize_t bytes = aacirun->ptr - aacirun->start;
  391. return bytes_to_frames(runtime, bytes);
  392. }
  393. /*
  394. * Playback specific ALSA stuff
  395. */
  396. static const u32 channels_to_txmask[] = {
  397. [2] = CR_SL3 | CR_SL4,
  398. [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
  399. [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
  400. };
  401. /*
  402. * We can support two and four channel audio. Unfortunately
  403. * six channel audio requires a non-standard channel ordering:
  404. * 2 -> FL(3), FR(4)
  405. * 4 -> FL(3), FR(4), SL(7), SR(8)
  406. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  407. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  408. * This requires an ALSA configuration file to correct.
  409. */
  410. static unsigned int channel_list[] = { 2, 4, 6 };
  411. static int
  412. aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  413. {
  414. struct aaci *aaci = rule->private;
  415. unsigned int chan_mask = 1 << 0, slots;
  416. /*
  417. * pcms[0] is the our 5.1 PCM instance.
  418. */
  419. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  420. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  421. chan_mask |= 1 << 1;
  422. if (slots & (1 << AC97_SLOT_LFE))
  423. chan_mask |= 1 << 2;
  424. }
  425. return snd_interval_list(hw_param_interval(p, rule->var),
  426. ARRAY_SIZE(channel_list), channel_list,
  427. chan_mask);
  428. }
  429. static int aaci_pcm_open(struct snd_pcm_substream *substream)
  430. {
  431. struct aaci *aaci = substream->private_data;
  432. int ret;
  433. /*
  434. * Add rule describing channel dependency.
  435. */
  436. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  437. SNDRV_PCM_HW_PARAM_CHANNELS,
  438. aaci_rule_channels, aaci,
  439. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  440. if (ret)
  441. return ret;
  442. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  443. ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
  444. } else {
  445. ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
  446. }
  447. return ret;
  448. }
  449. static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
  450. struct snd_pcm_hw_params *params)
  451. {
  452. struct aaci *aaci = substream->private_data;
  453. struct aaci_runtime *aacirun = substream->runtime->private_data;
  454. unsigned int channels = params_channels(params);
  455. int ret;
  456. WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
  457. !channels_to_txmask[channels]);
  458. ret = aaci_pcm_hw_params(substream, aacirun, params);
  459. /*
  460. * Enable FIFO, compact mode, 16 bits per sample.
  461. * FIXME: double rate slots?
  462. */
  463. if (ret >= 0) {
  464. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  465. aacirun->cr |= channels_to_txmask[channels];
  466. aacirun->fifosz = aaci->fifosize * 4;
  467. if (aacirun->cr & CR_COMPACT)
  468. aacirun->fifosz >>= 1;
  469. }
  470. return ret;
  471. }
  472. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  473. {
  474. u32 ie;
  475. ie = readl(aacirun->base + AACI_IE);
  476. ie &= ~(IE_URIE|IE_TXIE);
  477. writel(ie, aacirun->base + AACI_IE);
  478. aacirun->cr &= ~CR_EN;
  479. aaci_chan_wait_ready(aacirun);
  480. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  481. }
  482. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  483. {
  484. u32 ie;
  485. aaci_chan_wait_ready(aacirun);
  486. aacirun->cr |= CR_EN;
  487. ie = readl(aacirun->base + AACI_IE);
  488. ie |= IE_URIE | IE_TXIE;
  489. writel(ie, aacirun->base + AACI_IE);
  490. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  491. }
  492. static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  493. {
  494. struct aaci *aaci = substream->private_data;
  495. struct aaci_runtime *aacirun = substream->runtime->private_data;
  496. unsigned long flags;
  497. int ret = 0;
  498. spin_lock_irqsave(&aaci->lock, flags);
  499. switch (cmd) {
  500. case SNDRV_PCM_TRIGGER_START:
  501. aaci_pcm_playback_start(aacirun);
  502. break;
  503. case SNDRV_PCM_TRIGGER_RESUME:
  504. aaci_pcm_playback_start(aacirun);
  505. break;
  506. case SNDRV_PCM_TRIGGER_STOP:
  507. aaci_pcm_playback_stop(aacirun);
  508. break;
  509. case SNDRV_PCM_TRIGGER_SUSPEND:
  510. aaci_pcm_playback_stop(aacirun);
  511. break;
  512. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  513. break;
  514. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  515. break;
  516. default:
  517. ret = -EINVAL;
  518. }
  519. spin_unlock_irqrestore(&aaci->lock, flags);
  520. return ret;
  521. }
  522. static struct snd_pcm_ops aaci_playback_ops = {
  523. .open = aaci_pcm_open,
  524. .close = aaci_pcm_close,
  525. .ioctl = snd_pcm_lib_ioctl,
  526. .hw_params = aaci_pcm_playback_hw_params,
  527. .hw_free = aaci_pcm_hw_free,
  528. .prepare = aaci_pcm_prepare,
  529. .trigger = aaci_pcm_playback_trigger,
  530. .pointer = aaci_pcm_pointer,
  531. };
  532. static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
  533. struct snd_pcm_hw_params *params)
  534. {
  535. struct aaci *aaci = substream->private_data;
  536. struct aaci_runtime *aacirun = substream->runtime->private_data;
  537. int ret;
  538. ret = aaci_pcm_hw_params(substream, aacirun, params);
  539. if (ret >= 0) {
  540. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  541. /* Line in record: slot 3 and 4 */
  542. aacirun->cr |= CR_SL3 | CR_SL4;
  543. aacirun->fifosz = aaci->fifosize * 4;
  544. if (aacirun->cr & CR_COMPACT)
  545. aacirun->fifosz >>= 1;
  546. }
  547. return ret;
  548. }
  549. static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
  550. {
  551. u32 ie;
  552. aaci_chan_wait_ready(aacirun);
  553. ie = readl(aacirun->base + AACI_IE);
  554. ie &= ~(IE_ORIE | IE_RXIE);
  555. writel(ie, aacirun->base+AACI_IE);
  556. aacirun->cr &= ~CR_EN;
  557. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  558. }
  559. static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
  560. {
  561. u32 ie;
  562. aaci_chan_wait_ready(aacirun);
  563. #ifdef DEBUG
  564. /* RX Timeout value: bits 28:17 in RXCR */
  565. aacirun->cr |= 0xf << 17;
  566. #endif
  567. aacirun->cr |= CR_EN;
  568. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  569. ie = readl(aacirun->base + AACI_IE);
  570. ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
  571. writel(ie, aacirun->base + AACI_IE);
  572. }
  573. static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  574. {
  575. struct aaci *aaci = substream->private_data;
  576. struct aaci_runtime *aacirun = substream->runtime->private_data;
  577. unsigned long flags;
  578. int ret = 0;
  579. spin_lock_irqsave(&aaci->lock, flags);
  580. switch (cmd) {
  581. case SNDRV_PCM_TRIGGER_START:
  582. aaci_pcm_capture_start(aacirun);
  583. break;
  584. case SNDRV_PCM_TRIGGER_RESUME:
  585. aaci_pcm_capture_start(aacirun);
  586. break;
  587. case SNDRV_PCM_TRIGGER_STOP:
  588. aaci_pcm_capture_stop(aacirun);
  589. break;
  590. case SNDRV_PCM_TRIGGER_SUSPEND:
  591. aaci_pcm_capture_stop(aacirun);
  592. break;
  593. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  594. break;
  595. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  596. break;
  597. default:
  598. ret = -EINVAL;
  599. }
  600. spin_unlock_irqrestore(&aaci->lock, flags);
  601. return ret;
  602. }
  603. static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
  604. {
  605. struct snd_pcm_runtime *runtime = substream->runtime;
  606. struct aaci *aaci = substream->private_data;
  607. aaci_pcm_prepare(substream);
  608. /* allow changing of sample rate */
  609. aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
  610. aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  611. aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
  612. /* Record select: Mic: 0, Aux: 3, Line: 4 */
  613. aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
  614. return 0;
  615. }
  616. static struct snd_pcm_ops aaci_capture_ops = {
  617. .open = aaci_pcm_open,
  618. .close = aaci_pcm_close,
  619. .ioctl = snd_pcm_lib_ioctl,
  620. .hw_params = aaci_pcm_capture_hw_params,
  621. .hw_free = aaci_pcm_hw_free,
  622. .prepare = aaci_pcm_capture_prepare,
  623. .trigger = aaci_pcm_capture_trigger,
  624. .pointer = aaci_pcm_pointer,
  625. };
  626. /*
  627. * Power Management.
  628. */
  629. #ifdef CONFIG_PM
  630. static int aaci_do_suspend(struct snd_card *card, unsigned int state)
  631. {
  632. struct aaci *aaci = card->private_data;
  633. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  634. snd_pcm_suspend_all(aaci->pcm);
  635. return 0;
  636. }
  637. static int aaci_do_resume(struct snd_card *card, unsigned int state)
  638. {
  639. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  640. return 0;
  641. }
  642. static int aaci_suspend(struct amba_device *dev, pm_message_t state)
  643. {
  644. struct snd_card *card = amba_get_drvdata(dev);
  645. return card ? aaci_do_suspend(card) : 0;
  646. }
  647. static int aaci_resume(struct amba_device *dev)
  648. {
  649. struct snd_card *card = amba_get_drvdata(dev);
  650. return card ? aaci_do_resume(card) : 0;
  651. }
  652. #else
  653. #define aaci_do_suspend NULL
  654. #define aaci_do_resume NULL
  655. #define aaci_suspend NULL
  656. #define aaci_resume NULL
  657. #endif
  658. static struct ac97_pcm ac97_defs[] __devinitdata = {
  659. [0] = { /* Front PCM */
  660. .exclusive = 1,
  661. .r = {
  662. [0] = {
  663. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  664. (1 << AC97_SLOT_PCM_RIGHT) |
  665. (1 << AC97_SLOT_PCM_CENTER) |
  666. (1 << AC97_SLOT_PCM_SLEFT) |
  667. (1 << AC97_SLOT_PCM_SRIGHT) |
  668. (1 << AC97_SLOT_LFE),
  669. },
  670. },
  671. },
  672. [1] = { /* PCM in */
  673. .stream = 1,
  674. .exclusive = 1,
  675. .r = {
  676. [0] = {
  677. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  678. (1 << AC97_SLOT_PCM_RIGHT),
  679. },
  680. },
  681. },
  682. [2] = { /* Mic in */
  683. .stream = 1,
  684. .exclusive = 1,
  685. .r = {
  686. [0] = {
  687. .slots = (1 << AC97_SLOT_MIC),
  688. },
  689. },
  690. }
  691. };
  692. static struct snd_ac97_bus_ops aaci_bus_ops = {
  693. .write = aaci_ac97_write,
  694. .read = aaci_ac97_read,
  695. };
  696. static int __devinit aaci_probe_ac97(struct aaci *aaci)
  697. {
  698. struct snd_ac97_template ac97_template;
  699. struct snd_ac97_bus *ac97_bus;
  700. struct snd_ac97 *ac97;
  701. int ret;
  702. writel(0, aaci->base + AC97_POWERDOWN);
  703. /*
  704. * Assert AACIRESET for 2us
  705. */
  706. writel(0, aaci->base + AACI_RESET);
  707. udelay(2);
  708. writel(RESET_NRST, aaci->base + AACI_RESET);
  709. /*
  710. * Give the AC'97 codec more than enough time
  711. * to wake up. (42us = ~2 frames at 48kHz.)
  712. */
  713. udelay(42);
  714. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  715. if (ret)
  716. goto out;
  717. ac97_bus->clock = 48000;
  718. aaci->ac97_bus = ac97_bus;
  719. memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
  720. ac97_template.private_data = aaci;
  721. ac97_template.num = 0;
  722. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  723. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  724. if (ret)
  725. goto out;
  726. aaci->ac97 = ac97;
  727. /*
  728. * Disable AC97 PC Beep input on audio codecs.
  729. */
  730. if (ac97_is_audio(ac97))
  731. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  732. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  733. if (ret)
  734. goto out;
  735. aaci->playback.pcm = &ac97_bus->pcms[0];
  736. aaci->capture.pcm = &ac97_bus->pcms[1];
  737. out:
  738. return ret;
  739. }
  740. static void aaci_free_card(struct snd_card *card)
  741. {
  742. struct aaci *aaci = card->private_data;
  743. if (aaci->base)
  744. iounmap(aaci->base);
  745. }
  746. static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
  747. {
  748. struct aaci *aaci;
  749. struct snd_card *card;
  750. int err;
  751. err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  752. THIS_MODULE, sizeof(struct aaci), &card);
  753. if (err < 0)
  754. return NULL;
  755. card->private_free = aaci_free_card;
  756. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  757. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  758. snprintf(card->longname, sizeof(card->longname),
  759. "%s at 0x%016llx, irq %d",
  760. card->shortname, (unsigned long long)dev->res.start,
  761. dev->irq[0]);
  762. aaci = card->private_data;
  763. mutex_init(&aaci->ac97_sem);
  764. spin_lock_init(&aaci->lock);
  765. aaci->card = card;
  766. aaci->dev = dev;
  767. /* Set MAINCR to allow slot 1 and 2 data IO */
  768. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  769. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  770. return aaci;
  771. }
  772. static int __devinit aaci_init_pcm(struct aaci *aaci)
  773. {
  774. struct snd_pcm *pcm;
  775. int ret;
  776. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
  777. if (ret == 0) {
  778. aaci->pcm = pcm;
  779. pcm->private_data = aaci;
  780. pcm->info_flags = 0;
  781. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  782. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  783. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
  784. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  785. NULL, 0, 64 * 1024);
  786. }
  787. return ret;
  788. }
  789. static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
  790. {
  791. struct aaci_runtime *aacirun = &aaci->playback;
  792. int i;
  793. writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
  794. for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  795. writel(0, aacirun->fifo);
  796. writel(0, aacirun->base + AACI_TXCR);
  797. /*
  798. * Re-initialise the AACI after the FIFO depth test, to
  799. * ensure that the FIFOs are empty. Unfortunately, merely
  800. * disabling the channel doesn't clear the FIFO.
  801. */
  802. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  803. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  804. /*
  805. * If we hit 4096, we failed. Go back to the specified
  806. * fifo depth.
  807. */
  808. if (i == 4096)
  809. i = 8;
  810. return i;
  811. }
  812. static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
  813. {
  814. struct aaci *aaci;
  815. int ret, i;
  816. ret = amba_request_regions(dev, NULL);
  817. if (ret)
  818. return ret;
  819. aaci = aaci_init_card(dev);
  820. if (!aaci) {
  821. ret = -ENOMEM;
  822. goto out;
  823. }
  824. aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
  825. if (!aaci->base) {
  826. ret = -ENOMEM;
  827. goto out;
  828. }
  829. /*
  830. * Playback uses AACI channel 0
  831. */
  832. aaci->playback.base = aaci->base + AACI_CSCH1;
  833. aaci->playback.fifo = aaci->base + AACI_DR1;
  834. /*
  835. * Capture uses AACI channel 0
  836. */
  837. aaci->capture.base = aaci->base + AACI_CSCH1;
  838. aaci->capture.fifo = aaci->base + AACI_DR1;
  839. for (i = 0; i < 4; i++) {
  840. void __iomem *base = aaci->base + i * 0x14;
  841. writel(0, base + AACI_IE);
  842. writel(0, base + AACI_TXCR);
  843. writel(0, base + AACI_RXCR);
  844. }
  845. writel(0x1fff, aaci->base + AACI_INTCLR);
  846. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  847. ret = aaci_probe_ac97(aaci);
  848. if (ret)
  849. goto out;
  850. /*
  851. * Size the FIFOs (must be multiple of 16).
  852. */
  853. aaci->fifosize = aaci_size_fifo(aaci);
  854. if (aaci->fifosize & 15) {
  855. printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
  856. aaci->fifosize);
  857. ret = -ENODEV;
  858. goto out;
  859. }
  860. ret = aaci_init_pcm(aaci);
  861. if (ret)
  862. goto out;
  863. snd_card_set_dev(aaci->card, &dev->dev);
  864. ret = snd_card_register(aaci->card);
  865. if (ret == 0) {
  866. dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
  867. aaci->fifosize);
  868. amba_set_drvdata(dev, aaci->card);
  869. return ret;
  870. }
  871. out:
  872. if (aaci)
  873. snd_card_free(aaci->card);
  874. amba_release_regions(dev);
  875. return ret;
  876. }
  877. static int __devexit aaci_remove(struct amba_device *dev)
  878. {
  879. struct snd_card *card = amba_get_drvdata(dev);
  880. amba_set_drvdata(dev, NULL);
  881. if (card) {
  882. struct aaci *aaci = card->private_data;
  883. writel(0, aaci->base + AACI_MAINCR);
  884. snd_card_free(card);
  885. amba_release_regions(dev);
  886. }
  887. return 0;
  888. }
  889. static struct amba_id aaci_ids[] = {
  890. {
  891. .id = 0x00041041,
  892. .mask = 0x000fffff,
  893. },
  894. { 0, 0 },
  895. };
  896. static struct amba_driver aaci_driver = {
  897. .drv = {
  898. .name = DRIVER_NAME,
  899. },
  900. .probe = aaci_probe,
  901. .remove = __devexit_p(aaci_remove),
  902. .suspend = aaci_suspend,
  903. .resume = aaci_resume,
  904. .id_table = aaci_ids,
  905. };
  906. static int __init aaci_init(void)
  907. {
  908. return amba_driver_register(&aaci_driver);
  909. }
  910. static void __exit aaci_exit(void)
  911. {
  912. amba_driver_unregister(&aaci_driver);
  913. }
  914. module_init(aaci_init);
  915. module_exit(aaci_exit);
  916. MODULE_LICENSE("GPL");
  917. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");