netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. unsigned long last_schedule_time;
  43. #define NETXEN_MAX_CRB_XFORM 60
  44. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  45. #define NETXEN_ADDR_ERROR (0xffffffff)
  46. #define crb_addr_transform(name) \
  47. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  48. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  49. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  50. static inline void
  51. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  52. unsigned long off, int *data)
  53. {
  54. void __iomem *addr = pci_base_offset(adapter, off);
  55. writel(*data, addr);
  56. }
  57. static void crb_addr_transform_setup(void)
  58. {
  59. crb_addr_transform(XDMA);
  60. crb_addr_transform(TIMR);
  61. crb_addr_transform(SRE);
  62. crb_addr_transform(SQN3);
  63. crb_addr_transform(SQN2);
  64. crb_addr_transform(SQN1);
  65. crb_addr_transform(SQN0);
  66. crb_addr_transform(SQS3);
  67. crb_addr_transform(SQS2);
  68. crb_addr_transform(SQS1);
  69. crb_addr_transform(SQS0);
  70. crb_addr_transform(RPMX7);
  71. crb_addr_transform(RPMX6);
  72. crb_addr_transform(RPMX5);
  73. crb_addr_transform(RPMX4);
  74. crb_addr_transform(RPMX3);
  75. crb_addr_transform(RPMX2);
  76. crb_addr_transform(RPMX1);
  77. crb_addr_transform(RPMX0);
  78. crb_addr_transform(ROMUSB);
  79. crb_addr_transform(SN);
  80. crb_addr_transform(QMN);
  81. crb_addr_transform(QMS);
  82. crb_addr_transform(PGNI);
  83. crb_addr_transform(PGND);
  84. crb_addr_transform(PGN3);
  85. crb_addr_transform(PGN2);
  86. crb_addr_transform(PGN1);
  87. crb_addr_transform(PGN0);
  88. crb_addr_transform(PGSI);
  89. crb_addr_transform(PGSD);
  90. crb_addr_transform(PGS3);
  91. crb_addr_transform(PGS2);
  92. crb_addr_transform(PGS1);
  93. crb_addr_transform(PGS0);
  94. crb_addr_transform(PS);
  95. crb_addr_transform(PH);
  96. crb_addr_transform(NIU);
  97. crb_addr_transform(I2Q);
  98. crb_addr_transform(EG);
  99. crb_addr_transform(MN);
  100. crb_addr_transform(MS);
  101. crb_addr_transform(CAS2);
  102. crb_addr_transform(CAS1);
  103. crb_addr_transform(CAS0);
  104. crb_addr_transform(CAM);
  105. crb_addr_transform(C2C1);
  106. crb_addr_transform(C2C0);
  107. crb_addr_transform(SMB);
  108. }
  109. int netxen_init_firmware(struct netxen_adapter *adapter)
  110. {
  111. u32 state = 0, loops = 0, err = 0;
  112. /* Window 1 call */
  113. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  114. if (state == PHAN_INITIALIZE_ACK)
  115. return 0;
  116. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  117. udelay(100);
  118. /* Window 1 call */
  119. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  120. loops++;
  121. }
  122. if (loops >= 2000) {
  123. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  124. state);
  125. err = -EIO;
  126. return err;
  127. }
  128. /* Window 1 call */
  129. writel(MPORT_MULTI_FUNCTION_MODE,
  130. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  131. writel(PHAN_INITIALIZE_ACK,
  132. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  133. return err;
  134. }
  135. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  136. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  137. struct pci_dev **used_dev)
  138. {
  139. void *addr;
  140. addr = pci_alloc_consistent(pdev, sz, ptr);
  141. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  142. *used_dev = pdev;
  143. return addr;
  144. }
  145. pci_free_consistent(pdev, sz, addr, *ptr);
  146. addr = pci_alloc_consistent(NULL, sz, ptr);
  147. *used_dev = NULL;
  148. return addr;
  149. }
  150. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  151. {
  152. int ctxid, ring;
  153. u32 i;
  154. u32 num_rx_bufs = 0;
  155. struct netxen_rcv_desc_ctx *rcv_desc;
  156. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  157. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  158. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  159. struct netxen_rx_buffer *rx_buf;
  160. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  161. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  162. rcv_desc->begin_alloc = 0;
  163. rx_buf = rcv_desc->rx_buf_arr;
  164. num_rx_bufs = rcv_desc->max_rx_desc_count;
  165. /*
  166. * Now go through all of them, set reference handles
  167. * and put them in the queues.
  168. */
  169. for (i = 0; i < num_rx_bufs; i++) {
  170. rx_buf->ref_handle = i;
  171. rx_buf->state = NETXEN_BUFFER_FREE;
  172. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  173. "%p\n", ctxid, i, rx_buf);
  174. rx_buf++;
  175. }
  176. }
  177. }
  178. }
  179. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  180. {
  181. int ports = 0;
  182. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  183. if (netxen_nic_get_board_info(adapter) != 0)
  184. printk("%s: Error getting board config info.\n",
  185. netxen_nic_driver_name);
  186. get_brd_port_by_type(board_info->board_type, &ports);
  187. if (ports == 0)
  188. printk(KERN_ERR "%s: Unknown board type\n",
  189. netxen_nic_driver_name);
  190. adapter->ahw.max_ports = ports;
  191. }
  192. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  193. {
  194. switch (adapter->ahw.board_type) {
  195. case NETXEN_NIC_GBE:
  196. adapter->enable_phy_interrupts =
  197. netxen_niu_gbe_enable_phy_interrupts;
  198. adapter->disable_phy_interrupts =
  199. netxen_niu_gbe_disable_phy_interrupts;
  200. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  201. adapter->macaddr_set = netxen_niu_macaddr_set;
  202. adapter->set_mtu = netxen_nic_set_mtu_gb;
  203. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  204. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  205. adapter->phy_read = netxen_niu_gbe_phy_read;
  206. adapter->phy_write = netxen_niu_gbe_phy_write;
  207. adapter->init_niu = netxen_nic_init_niu_gb;
  208. adapter->stop_port = netxen_niu_disable_gbe_port;
  209. break;
  210. case NETXEN_NIC_XGBE:
  211. adapter->enable_phy_interrupts =
  212. netxen_niu_xgbe_enable_phy_interrupts;
  213. adapter->disable_phy_interrupts =
  214. netxen_niu_xgbe_disable_phy_interrupts;
  215. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  216. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  217. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  218. adapter->init_port = netxen_niu_xg_init_port;
  219. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  220. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  221. adapter->stop_port = netxen_niu_disable_xg_port;
  222. break;
  223. default:
  224. break;
  225. }
  226. }
  227. /*
  228. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  229. * address to external PCI CRB address.
  230. */
  231. u32 netxen_decode_crb_addr(u32 addr)
  232. {
  233. int i;
  234. u32 base_addr, offset, pci_base;
  235. crb_addr_transform_setup();
  236. pci_base = NETXEN_ADDR_ERROR;
  237. base_addr = addr & 0xfff00000;
  238. offset = addr & 0x000fffff;
  239. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  240. if (crb_addr_xform[i] == base_addr) {
  241. pci_base = i << 20;
  242. break;
  243. }
  244. }
  245. if (pci_base == NETXEN_ADDR_ERROR)
  246. return pci_base;
  247. else
  248. return (pci_base + offset);
  249. }
  250. static long rom_max_timeout = 100;
  251. static long rom_lock_timeout = 10000;
  252. static long rom_write_timeout = 700;
  253. static inline int rom_lock(struct netxen_adapter *adapter)
  254. {
  255. int iter;
  256. u32 done = 0;
  257. int timeout = 0;
  258. while (!done) {
  259. /* acquire semaphore2 from PCI HW block */
  260. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  261. &done);
  262. if (done == 1)
  263. break;
  264. if (timeout >= rom_lock_timeout)
  265. return -EIO;
  266. timeout++;
  267. /*
  268. * Yield CPU
  269. */
  270. if (!in_atomic())
  271. schedule();
  272. else {
  273. for (iter = 0; iter < 20; iter++)
  274. cpu_relax(); /*This a nop instr on i386 */
  275. }
  276. }
  277. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  278. return 0;
  279. }
  280. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  281. {
  282. long timeout = 0;
  283. long done = 0;
  284. while (done == 0) {
  285. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  286. done &= 2;
  287. timeout++;
  288. if (timeout >= rom_max_timeout) {
  289. printk("Timeout reached waiting for rom done");
  290. return -EIO;
  291. }
  292. }
  293. return 0;
  294. }
  295. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  296. {
  297. /* Set write enable latch in ROM status register */
  298. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  299. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  300. M25P_INSTR_WREN);
  301. if (netxen_wait_rom_done(adapter)) {
  302. return -1;
  303. }
  304. return 0;
  305. }
  306. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  307. unsigned int addr)
  308. {
  309. unsigned int data = 0xdeaddead;
  310. data = netxen_nic_reg_read(adapter, addr);
  311. return data;
  312. }
  313. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  314. {
  315. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  316. M25P_INSTR_RDSR);
  317. if (netxen_wait_rom_done(adapter)) {
  318. return -1;
  319. }
  320. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  321. }
  322. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  323. {
  324. u32 val;
  325. /* release semaphore2 */
  326. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  327. }
  328. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  329. {
  330. long timeout = 0;
  331. long wip = 1;
  332. int val;
  333. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  334. while (wip != 0) {
  335. val = netxen_do_rom_rdsr(adapter);
  336. wip = val & 1;
  337. timeout++;
  338. if (timeout > rom_max_timeout) {
  339. return -1;
  340. }
  341. }
  342. return 0;
  343. }
  344. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  345. int data)
  346. {
  347. if (netxen_rom_wren(adapter)) {
  348. return -1;
  349. }
  350. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  351. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  354. M25P_INSTR_PP);
  355. if (netxen_wait_rom_done(adapter)) {
  356. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  357. return -1;
  358. }
  359. return netxen_rom_wip_poll(adapter);
  360. }
  361. static inline int
  362. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  363. {
  364. if (jiffies > (last_schedule_time + (8 * HZ))) {
  365. last_schedule_time = jiffies;
  366. schedule();
  367. }
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  369. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  370. udelay(100); /* prevent bursting on CRB */
  371. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  372. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  373. if (netxen_wait_rom_done(adapter)) {
  374. printk("Error waiting for rom done\n");
  375. return -EIO;
  376. }
  377. /* reset abyte_cnt and dummy_byte_cnt */
  378. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  379. udelay(100); /* prevent bursting on CRB */
  380. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  381. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  382. return 0;
  383. }
  384. static inline int
  385. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  386. u8 *bytes, size_t size)
  387. {
  388. int addridx;
  389. int ret = 0;
  390. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  391. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  392. if (ret != 0)
  393. break;
  394. bytes += 4;
  395. }
  396. return ret;
  397. }
  398. int
  399. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  400. u8 *bytes, size_t size)
  401. {
  402. int ret;
  403. ret = rom_lock(adapter);
  404. if (ret < 0)
  405. return ret;
  406. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  407. netxen_rom_unlock(adapter);
  408. return ret;
  409. }
  410. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  411. {
  412. int ret;
  413. if (rom_lock(adapter) != 0)
  414. return -EIO;
  415. ret = do_rom_fast_read(adapter, addr, valp);
  416. netxen_rom_unlock(adapter);
  417. return ret;
  418. }
  419. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  420. {
  421. int ret = 0;
  422. if (rom_lock(adapter) != 0) {
  423. return -1;
  424. }
  425. ret = do_rom_fast_write(adapter, addr, data);
  426. netxen_rom_unlock(adapter);
  427. return ret;
  428. }
  429. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  430. int addr, u8 *bytes, size_t size)
  431. {
  432. int addridx = addr;
  433. int ret = 0;
  434. while (addridx < (addr + size)) {
  435. int last_attempt = 0;
  436. int timeout = 0;
  437. int data;
  438. data = *(u32*)bytes;
  439. ret = do_rom_fast_write(adapter, addridx, data);
  440. if (ret < 0)
  441. return ret;
  442. while(1) {
  443. int data1;
  444. ret = do_rom_fast_read(adapter, addridx, &data1);
  445. if (ret < 0)
  446. return ret;
  447. if (data1 == data)
  448. break;
  449. if (timeout++ >= rom_write_timeout) {
  450. if (last_attempt++ < 4) {
  451. ret = do_rom_fast_write(adapter,
  452. addridx, data);
  453. if (ret < 0)
  454. return ret;
  455. }
  456. else {
  457. printk(KERN_INFO "Data write did not "
  458. "succeed at address 0x%x\n", addridx);
  459. break;
  460. }
  461. }
  462. }
  463. bytes += 4;
  464. addridx += 4;
  465. }
  466. return ret;
  467. }
  468. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  469. u8 *bytes, size_t size)
  470. {
  471. int ret = 0;
  472. ret = rom_lock(adapter);
  473. if (ret < 0)
  474. return ret;
  475. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  476. netxen_rom_unlock(adapter);
  477. return ret;
  478. }
  479. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  480. {
  481. int ret;
  482. ret = netxen_rom_wren(adapter);
  483. if (ret < 0)
  484. return ret;
  485. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  486. netxen_crb_writelit_adapter(adapter,
  487. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  488. ret = netxen_wait_rom_done(adapter);
  489. if (ret < 0)
  490. return ret;
  491. return netxen_rom_wip_poll(adapter);
  492. }
  493. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  494. {
  495. int ret;
  496. ret = rom_lock(adapter);
  497. if (ret < 0)
  498. return ret;
  499. ret = netxen_do_rom_rdsr(adapter);
  500. netxen_rom_unlock(adapter);
  501. return ret;
  502. }
  503. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  504. {
  505. int ret = FLASH_SUCCESS;
  506. int val;
  507. char *buffer = kmalloc(FLASH_SECTOR_SIZE, GFP_KERNEL);
  508. if (!buffer)
  509. return -ENOMEM;
  510. /* unlock sector 63 */
  511. val = netxen_rom_rdsr(adapter);
  512. val = val & 0xe3;
  513. ret = netxen_rom_wrsr(adapter, val);
  514. if (ret != FLASH_SUCCESS)
  515. goto out_kfree;
  516. ret = netxen_rom_wip_poll(adapter);
  517. if (ret != FLASH_SUCCESS)
  518. goto out_kfree;
  519. /* copy sector 0 to sector 63 */
  520. ret = netxen_rom_fast_read_words(adapter, CRBINIT_START,
  521. buffer, FLASH_SECTOR_SIZE);
  522. if (ret != FLASH_SUCCESS)
  523. goto out_kfree;
  524. ret = netxen_rom_fast_write_words(adapter, FIXED_START,
  525. buffer, FLASH_SECTOR_SIZE);
  526. if (ret != FLASH_SUCCESS)
  527. goto out_kfree;
  528. /* lock sector 63 */
  529. val = netxen_rom_rdsr(adapter);
  530. if (!(val & 0x8)) {
  531. val |= (0x1 << 2);
  532. /* lock sector 63 */
  533. if (netxen_rom_wrsr(adapter, val) == 0) {
  534. ret = netxen_rom_wip_poll(adapter);
  535. if (ret != FLASH_SUCCESS)
  536. goto out_kfree;
  537. /* lock SR writes */
  538. ret = netxen_rom_wip_poll(adapter);
  539. if (ret != FLASH_SUCCESS)
  540. goto out_kfree;
  541. }
  542. }
  543. out_kfree:
  544. kfree(buffer);
  545. return ret;
  546. }
  547. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  548. {
  549. netxen_rom_wren(adapter);
  550. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  551. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  552. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  553. M25P_INSTR_SE);
  554. if (netxen_wait_rom_done(adapter)) {
  555. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  556. return -1;
  557. }
  558. return netxen_rom_wip_poll(adapter);
  559. }
  560. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  561. {
  562. int i;
  563. int val;
  564. int count = 0, erased_errors = 0;
  565. int range;
  566. range = (addr == USER_START) ? FIXED_START : addr + FLASH_SECTOR_SIZE;
  567. for (i = addr; i < range; i += 4) {
  568. netxen_rom_fast_read(adapter, i, &val);
  569. if (val != 0xffffffff)
  570. erased_errors++;
  571. count++;
  572. }
  573. if (erased_errors)
  574. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  575. "for sector address: %x\n", erased_errors, count, addr);
  576. }
  577. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  578. {
  579. int ret = 0;
  580. if (rom_lock(adapter) != 0) {
  581. return -1;
  582. }
  583. ret = netxen_do_rom_se(adapter, addr);
  584. netxen_rom_unlock(adapter);
  585. msleep(30);
  586. check_erased_flash(adapter, addr);
  587. return ret;
  588. }
  589. int
  590. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  591. {
  592. int ret = FLASH_SUCCESS;
  593. int i;
  594. for (i = start; i < end; i++) {
  595. ret = netxen_rom_se(adapter, i * FLASH_SECTOR_SIZE);
  596. if (ret)
  597. break;
  598. ret = netxen_rom_wip_poll(adapter);
  599. if (ret < 0)
  600. return ret;
  601. }
  602. return ret;
  603. }
  604. int
  605. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  606. {
  607. int ret = FLASH_SUCCESS;
  608. int start, end;
  609. start = SECONDARY_START / FLASH_SECTOR_SIZE;
  610. end = USER_START / FLASH_SECTOR_SIZE;
  611. ret = netxen_flash_erase_sections(adapter, start, end);
  612. return ret;
  613. }
  614. int
  615. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  616. {
  617. int ret = FLASH_SUCCESS;
  618. int start, end;
  619. start = PRIMARY_START / FLASH_SECTOR_SIZE;
  620. end = SECONDARY_START / FLASH_SECTOR_SIZE;
  621. ret = netxen_flash_erase_sections(adapter, start, end);
  622. return ret;
  623. }
  624. void netxen_halt_pegs(struct netxen_adapter *adapter)
  625. {
  626. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  627. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  628. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  629. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  630. }
  631. int netxen_flash_unlock(struct netxen_adapter *adapter)
  632. {
  633. int ret = 0;
  634. ret = netxen_rom_wrsr(adapter, 0);
  635. if (ret < 0)
  636. return ret;
  637. ret = netxen_rom_wren(adapter);
  638. if (ret < 0)
  639. return ret;
  640. return ret;
  641. }
  642. #define NETXEN_BOARDTYPE 0x4008
  643. #define NETXEN_BOARDNUM 0x400c
  644. #define NETXEN_CHIPNUM 0x4010
  645. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  646. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  647. #define NETXEN_ROM_FOUND_INIT 0x400
  648. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  649. {
  650. int addr, val, status;
  651. int n, i;
  652. int init_delay = 0;
  653. struct crb_addr_pair *buf;
  654. u32 off;
  655. /* resetall */
  656. status = netxen_nic_get_board_info(adapter);
  657. if (status)
  658. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  659. netxen_nic_driver_name);
  660. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  661. NETXEN_ROMBUS_RESET);
  662. if (verbose) {
  663. int val;
  664. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  665. printk("P2 ROM board type: 0x%08x\n", val);
  666. else
  667. printk("Could not read board type\n");
  668. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  669. printk("P2 ROM board num: 0x%08x\n", val);
  670. else
  671. printk("Could not read board number\n");
  672. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  673. printk("P2 ROM chip num: 0x%08x\n", val);
  674. else
  675. printk("Could not read chip number\n");
  676. }
  677. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  678. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  679. n &= ~NETXEN_ROM_ROUNDUP;
  680. if (n < NETXEN_ROM_FOUND_INIT) {
  681. if (verbose)
  682. printk("%s: %d CRB init values found"
  683. " in ROM.\n", netxen_nic_driver_name, n);
  684. } else {
  685. printk("%s:n=0x%x Error! NetXen card flash not"
  686. " initialized.\n", __FUNCTION__, n);
  687. return -EIO;
  688. }
  689. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  690. if (buf == NULL) {
  691. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  692. "memory.\n", netxen_nic_driver_name);
  693. return -ENOMEM;
  694. }
  695. for (i = 0; i < n; i++) {
  696. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  697. || netxen_rom_fast_read(adapter, 8 * i + 8,
  698. &addr) != 0)
  699. return -EIO;
  700. buf[i].addr = addr;
  701. buf[i].data = val;
  702. if (verbose)
  703. printk("%s: PCI: 0x%08x == 0x%08x\n",
  704. netxen_nic_driver_name, (unsigned int)
  705. netxen_decode_crb_addr(addr), val);
  706. }
  707. for (i = 0; i < n; i++) {
  708. off = netxen_decode_crb_addr(buf[i].addr);
  709. if (off == NETXEN_ADDR_ERROR) {
  710. printk(KERN_ERR"CRB init value out of range %x\n",
  711. buf[i].addr);
  712. continue;
  713. }
  714. off += NETXEN_PCI_CRBSPACE;
  715. /* skipping cold reboot MAGIC */
  716. if (off == NETXEN_CAM_RAM(0x1fc))
  717. continue;
  718. /* After writing this register, HW needs time for CRB */
  719. /* to quiet down (else crb_window returns 0xffffffff) */
  720. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  721. init_delay = 1;
  722. /* hold xdma in reset also */
  723. buf[i].data = NETXEN_NIC_XDMA_RESET;
  724. }
  725. if (ADDR_IN_WINDOW1(off)) {
  726. writel(buf[i].data,
  727. NETXEN_CRB_NORMALIZE(adapter, off));
  728. } else {
  729. netxen_nic_pci_change_crbwindow(adapter, 0);
  730. writel(buf[i].data,
  731. pci_base_offset(adapter, off));
  732. netxen_nic_pci_change_crbwindow(adapter, 1);
  733. }
  734. if (init_delay == 1) {
  735. ssleep(1);
  736. init_delay = 0;
  737. }
  738. msleep(1);
  739. }
  740. kfree(buf);
  741. /* disable_peg_cache_all */
  742. /* unreset_net_cache */
  743. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  744. 4);
  745. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  746. (val & 0xffffff0f));
  747. /* p2dn replyCount */
  748. netxen_crb_writelit_adapter(adapter,
  749. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  750. /* disable_peg_cache 0 */
  751. netxen_crb_writelit_adapter(adapter,
  752. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  753. /* disable_peg_cache 1 */
  754. netxen_crb_writelit_adapter(adapter,
  755. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  756. /* peg_clr_all */
  757. /* peg_clr 0 */
  758. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  759. 0);
  760. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  761. 0);
  762. /* peg_clr 1 */
  763. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  764. 0);
  765. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  766. 0);
  767. /* peg_clr 2 */
  768. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  769. 0);
  770. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  771. 0);
  772. /* peg_clr 3 */
  773. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  774. 0);
  775. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  776. 0);
  777. }
  778. return 0;
  779. }
  780. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  781. {
  782. uint64_t addr;
  783. uint32_t hi;
  784. uint32_t lo;
  785. adapter->dummy_dma.addr =
  786. pci_alloc_consistent(adapter->ahw.pdev,
  787. NETXEN_HOST_DUMMY_DMA_SIZE,
  788. &adapter->dummy_dma.phys_addr);
  789. if (adapter->dummy_dma.addr == NULL) {
  790. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  791. __FUNCTION__);
  792. return -ENOMEM;
  793. }
  794. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  795. hi = (addr >> 32) & 0xffffffff;
  796. lo = addr & 0xffffffff;
  797. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  798. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  799. return 0;
  800. }
  801. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  802. {
  803. if (adapter->dummy_dma.addr) {
  804. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  805. CRB_HOST_DUMMY_BUF_ADDR_HI));
  806. writel(0, NETXEN_CRB_NORMALIZE(adapter,
  807. CRB_HOST_DUMMY_BUF_ADDR_LO));
  808. pci_free_consistent(adapter->ahw.pdev,
  809. NETXEN_HOST_DUMMY_DMA_SIZE,
  810. adapter->dummy_dma.addr,
  811. adapter->dummy_dma.phys_addr);
  812. adapter->dummy_dma.addr = NULL;
  813. }
  814. }
  815. void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  816. {
  817. u32 val = 0;
  818. int loops = 0;
  819. if (!pegtune_val) {
  820. val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  821. while (val != PHAN_INITIALIZE_COMPLETE &&
  822. val != PHAN_INITIALIZE_ACK && loops < 200000) {
  823. udelay(100);
  824. schedule();
  825. val =
  826. readl(NETXEN_CRB_NORMALIZE
  827. (adapter, CRB_CMDPEG_STATE));
  828. loops++;
  829. }
  830. if (val != PHAN_INITIALIZE_COMPLETE)
  831. printk("WARNING: Initial boot wait loop failed...\n");
  832. }
  833. }
  834. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  835. {
  836. int ctx;
  837. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  838. struct netxen_recv_context *recv_ctx =
  839. &(adapter->recv_ctx[ctx]);
  840. u32 consumer;
  841. struct status_desc *desc_head;
  842. struct status_desc *desc;
  843. consumer = recv_ctx->status_rx_consumer;
  844. desc_head = recv_ctx->rcv_status_desc_head;
  845. desc = &desc_head[consumer];
  846. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  847. return 1;
  848. }
  849. return 0;
  850. }
  851. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  852. {
  853. struct net_device *netdev = adapter->netdev;
  854. uint32_t temp, temp_state, temp_val;
  855. int rv = 0;
  856. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  857. temp_state = nx_get_temp_state(temp);
  858. temp_val = nx_get_temp_val(temp);
  859. if (temp_state == NX_TEMP_PANIC) {
  860. printk(KERN_ALERT
  861. "%s: Device temperature %d degrees C exceeds"
  862. " maximum allowed. Hardware has been shut down.\n",
  863. netxen_nic_driver_name, temp_val);
  864. netif_carrier_off(netdev);
  865. netif_stop_queue(netdev);
  866. rv = 1;
  867. } else if (temp_state == NX_TEMP_WARN) {
  868. if (adapter->temp == NX_TEMP_NORMAL) {
  869. printk(KERN_ALERT
  870. "%s: Device temperature %d degrees C "
  871. "exceeds operating range."
  872. " Immediate action needed.\n",
  873. netxen_nic_driver_name, temp_val);
  874. }
  875. } else {
  876. if (adapter->temp == NX_TEMP_WARN) {
  877. printk(KERN_INFO
  878. "%s: Device temperature is now %d degrees C"
  879. " in normal range.\n", netxen_nic_driver_name,
  880. temp_val);
  881. }
  882. }
  883. adapter->temp = temp_state;
  884. return rv;
  885. }
  886. void netxen_watchdog_task(struct work_struct *work)
  887. {
  888. struct net_device *netdev;
  889. struct netxen_adapter *adapter =
  890. container_of(work, struct netxen_adapter, watchdog_task);
  891. if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
  892. return;
  893. netdev = adapter->netdev;
  894. if ((netif_running(netdev)) && !netif_carrier_ok(netdev)) {
  895. printk(KERN_INFO "%s port %d, %s carrier is now ok\n",
  896. netxen_nic_driver_name, adapter->portnum, netdev->name);
  897. netif_carrier_on(netdev);
  898. }
  899. if (netif_queue_stopped(netdev))
  900. netif_wake_queue(netdev);
  901. if (adapter->handle_phy_intr)
  902. adapter->handle_phy_intr(adapter);
  903. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  904. }
  905. /*
  906. * netxen_process_rcv() send the received packet to the protocol stack.
  907. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  908. * invoke the routine to send more rx buffers to the Phantom...
  909. */
  910. void
  911. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  912. struct status_desc *desc)
  913. {
  914. struct pci_dev *pdev = adapter->pdev;
  915. struct net_device *netdev = adapter->netdev;
  916. int index = netxen_get_sts_refhandle(desc);
  917. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  918. struct netxen_rx_buffer *buffer;
  919. struct sk_buff *skb;
  920. u32 length = netxen_get_sts_totallength(desc);
  921. u32 desc_ctx;
  922. struct netxen_rcv_desc_ctx *rcv_desc;
  923. int ret;
  924. desc_ctx = netxen_get_sts_type(desc);
  925. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  926. printk("%s: %s Bad Rcv descriptor ring\n",
  927. netxen_nic_driver_name, netdev->name);
  928. return;
  929. }
  930. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  931. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  932. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  933. index, rcv_desc->max_rx_desc_count);
  934. return;
  935. }
  936. buffer = &rcv_desc->rx_buf_arr[index];
  937. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  938. buffer->lro_current_frags++;
  939. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  940. buffer->lro_expected_frags =
  941. netxen_get_sts_desc_lro_cnt(desc);
  942. buffer->lro_length = length;
  943. }
  944. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  945. if (buffer->lro_expected_frags != 0) {
  946. printk("LRO: (refhandle:%x) recv frag."
  947. "wait for last. flags: %x expected:%d"
  948. "have:%d\n", index,
  949. netxen_get_sts_desc_lro_last_frag(desc),
  950. buffer->lro_expected_frags,
  951. buffer->lro_current_frags);
  952. }
  953. return;
  954. }
  955. }
  956. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  957. PCI_DMA_FROMDEVICE);
  958. skb = (struct sk_buff *)buffer->skb;
  959. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  960. adapter->stats.csummed++;
  961. skb->ip_summed = CHECKSUM_UNNECESSARY;
  962. }
  963. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  964. /* True length was only available on the last pkt */
  965. skb_put(skb, buffer->lro_length);
  966. } else {
  967. skb_put(skb, length);
  968. }
  969. skb->protocol = eth_type_trans(skb, netdev);
  970. ret = netif_receive_skb(skb);
  971. /*
  972. * RH: Do we need these stats on a regular basis. Can we get it from
  973. * Linux stats.
  974. */
  975. switch (ret) {
  976. case NET_RX_SUCCESS:
  977. adapter->stats.uphappy++;
  978. break;
  979. case NET_RX_CN_LOW:
  980. adapter->stats.uplcong++;
  981. break;
  982. case NET_RX_CN_MOD:
  983. adapter->stats.upmcong++;
  984. break;
  985. case NET_RX_CN_HIGH:
  986. adapter->stats.uphcong++;
  987. break;
  988. case NET_RX_DROP:
  989. adapter->stats.updropped++;
  990. break;
  991. default:
  992. adapter->stats.updunno++;
  993. break;
  994. }
  995. netdev->last_rx = jiffies;
  996. rcv_desc->rcv_free++;
  997. rcv_desc->rcv_pending--;
  998. /*
  999. * We just consumed one buffer so post a buffer.
  1000. */
  1001. buffer->skb = NULL;
  1002. buffer->state = NETXEN_BUFFER_FREE;
  1003. buffer->lro_current_frags = 0;
  1004. buffer->lro_expected_frags = 0;
  1005. adapter->stats.no_rcv++;
  1006. adapter->stats.rxbytes += length;
  1007. }
  1008. /* Process Receive status ring */
  1009. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1010. {
  1011. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1012. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1013. struct status_desc *desc; /* used to read status desc here */
  1014. u32 consumer = recv_ctx->status_rx_consumer;
  1015. u32 producer = 0;
  1016. int count = 0, ring;
  1017. DPRINTK(INFO, "procesing receive\n");
  1018. /*
  1019. * we assume in this case that there is only one port and that is
  1020. * port #1...changes need to be done in firmware to indicate port
  1021. * number as part of the descriptor. This way we will be able to get
  1022. * the netdev which is associated with that device.
  1023. */
  1024. while (count < max) {
  1025. desc = &desc_head[consumer];
  1026. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1027. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1028. netxen_get_sts_owner(desc));
  1029. break;
  1030. }
  1031. netxen_process_rcv(adapter, ctxid, desc);
  1032. netxen_clear_sts_owner(desc);
  1033. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1034. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1035. count++;
  1036. }
  1037. if (count) {
  1038. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1039. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1040. }
  1041. }
  1042. /* update the consumer index in phantom */
  1043. if (count) {
  1044. recv_ctx->status_rx_consumer = consumer;
  1045. recv_ctx->status_rx_producer = producer;
  1046. /* Window = 1 */
  1047. writel(consumer,
  1048. NETXEN_CRB_NORMALIZE(adapter,
  1049. recv_crb_registers[ctxid].
  1050. crb_rcv_status_consumer));
  1051. }
  1052. return count;
  1053. }
  1054. /* Process Command status ring */
  1055. int netxen_process_cmd_ring(unsigned long data)
  1056. {
  1057. u32 last_consumer;
  1058. u32 consumer;
  1059. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1060. int count1 = 0;
  1061. int count2 = 0;
  1062. struct netxen_cmd_buffer *buffer;
  1063. struct pci_dev *pdev;
  1064. struct netxen_skb_frag *frag;
  1065. u32 i;
  1066. struct sk_buff *skb = NULL;
  1067. int done;
  1068. spin_lock(&adapter->tx_lock);
  1069. last_consumer = adapter->last_cmd_consumer;
  1070. DPRINTK(INFO, "procesing xmit complete\n");
  1071. /* we assume in this case that there is only one port and that is
  1072. * port #1...changes need to be done in firmware to indicate port
  1073. * number as part of the descriptor. This way we will be able to get
  1074. * the netdev which is associated with that device.
  1075. */
  1076. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1077. if (last_consumer == consumer) { /* Ring is empty */
  1078. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1079. last_consumer, consumer);
  1080. spin_unlock(&adapter->tx_lock);
  1081. return 1;
  1082. }
  1083. adapter->proc_cmd_buf_counter++;
  1084. /*
  1085. * Not needed - does not seem to be used anywhere.
  1086. * adapter->cmd_consumer = consumer;
  1087. */
  1088. spin_unlock(&adapter->tx_lock);
  1089. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1090. buffer = &adapter->cmd_buf_arr[last_consumer];
  1091. pdev = adapter->pdev;
  1092. frag = &buffer->frag_array[0];
  1093. skb = buffer->skb;
  1094. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1095. pci_unmap_single(pdev, frag->dma, frag->length,
  1096. PCI_DMA_TODEVICE);
  1097. for (i = 1; i < buffer->frag_count; i++) {
  1098. DPRINTK(INFO, "getting fragment no %d\n", i);
  1099. frag++; /* Get the next frag */
  1100. pci_unmap_page(pdev, frag->dma, frag->length,
  1101. PCI_DMA_TODEVICE);
  1102. }
  1103. adapter->stats.skbfreed++;
  1104. dev_kfree_skb_any(skb);
  1105. skb = NULL;
  1106. } else if (adapter->proc_cmd_buf_counter == 1) {
  1107. adapter->stats.txnullskb++;
  1108. }
  1109. if (unlikely(netif_queue_stopped(adapter->netdev)
  1110. && netif_carrier_ok(adapter->netdev))
  1111. && ((jiffies - adapter->netdev->trans_start) >
  1112. adapter->netdev->watchdog_timeo)) {
  1113. SCHEDULE_WORK(&adapter->tx_timeout_task);
  1114. }
  1115. last_consumer = get_next_index(last_consumer,
  1116. adapter->max_tx_desc_count);
  1117. count1++;
  1118. }
  1119. count2 = 0;
  1120. spin_lock(&adapter->tx_lock);
  1121. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1122. adapter->last_cmd_consumer = last_consumer;
  1123. while ((adapter->last_cmd_consumer != consumer)
  1124. && (count2 < MAX_STATUS_HANDLE)) {
  1125. buffer =
  1126. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1127. count2++;
  1128. if (buffer->skb)
  1129. break;
  1130. else
  1131. adapter->last_cmd_consumer =
  1132. get_next_index(adapter->last_cmd_consumer,
  1133. adapter->max_tx_desc_count);
  1134. }
  1135. }
  1136. if (count1 || count2) {
  1137. if (netif_queue_stopped(adapter->netdev)
  1138. && (adapter->flags & NETXEN_NETDEV_STATUS)) {
  1139. netif_wake_queue(adapter->netdev);
  1140. adapter->flags &= ~NETXEN_NETDEV_STATUS;
  1141. }
  1142. }
  1143. /*
  1144. * If everything is freed up to consumer then check if the ring is full
  1145. * If the ring is full then check if more needs to be freed and
  1146. * schedule the call back again.
  1147. *
  1148. * This happens when there are 2 CPUs. One could be freeing and the
  1149. * other filling it. If the ring is full when we get out of here and
  1150. * the card has already interrupted the host then the host can miss the
  1151. * interrupt.
  1152. *
  1153. * There is still a possible race condition and the host could miss an
  1154. * interrupt. The card has to take care of this.
  1155. */
  1156. if (adapter->last_cmd_consumer == consumer &&
  1157. (((adapter->cmd_producer + 1) %
  1158. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1159. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1160. }
  1161. done = (adapter->last_cmd_consumer == consumer);
  1162. spin_unlock(&adapter->tx_lock);
  1163. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1164. __FUNCTION__);
  1165. return (done);
  1166. }
  1167. /*
  1168. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1169. */
  1170. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1171. {
  1172. struct pci_dev *pdev = adapter->ahw.pdev;
  1173. struct sk_buff *skb;
  1174. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1175. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1176. uint producer;
  1177. struct rcv_desc *pdesc;
  1178. struct netxen_rx_buffer *buffer;
  1179. int count = 0;
  1180. int index = 0;
  1181. netxen_ctx_msg msg = 0;
  1182. dma_addr_t dma;
  1183. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1184. producer = rcv_desc->producer;
  1185. index = rcv_desc->begin_alloc;
  1186. buffer = &rcv_desc->rx_buf_arr[index];
  1187. /* We can start writing rx descriptors into the phantom memory. */
  1188. while (buffer->state == NETXEN_BUFFER_FREE) {
  1189. skb = dev_alloc_skb(rcv_desc->skb_size);
  1190. if (unlikely(!skb)) {
  1191. /*
  1192. * TODO
  1193. * We need to schedule the posting of buffers to the pegs.
  1194. */
  1195. rcv_desc->begin_alloc = index;
  1196. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1197. " allocated only %d buffers\n", count);
  1198. break;
  1199. }
  1200. count++; /* now there should be no failure */
  1201. pdesc = &rcv_desc->desc_head[producer];
  1202. #if defined(XGB_DEBUG)
  1203. *(unsigned long *)(skb->head) = 0xc0debabe;
  1204. if (skb_is_nonlinear(skb)) {
  1205. printk("Allocated SKB @%p is nonlinear\n");
  1206. }
  1207. #endif
  1208. skb_reserve(skb, 2);
  1209. /* This will be setup when we receive the
  1210. * buffer after it has been filled FSL TBD TBD
  1211. * skb->dev = netdev;
  1212. */
  1213. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1214. PCI_DMA_FROMDEVICE);
  1215. pdesc->addr_buffer = cpu_to_le64(dma);
  1216. buffer->skb = skb;
  1217. buffer->state = NETXEN_BUFFER_BUSY;
  1218. buffer->dma = dma;
  1219. /* make a rcv descriptor */
  1220. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1221. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1222. DPRINTK(INFO, "done writing descripter\n");
  1223. producer =
  1224. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1225. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1226. buffer = &rcv_desc->rx_buf_arr[index];
  1227. }
  1228. /* if we did allocate buffers, then write the count to Phantom */
  1229. if (count) {
  1230. rcv_desc->begin_alloc = index;
  1231. rcv_desc->rcv_pending += count;
  1232. rcv_desc->producer = producer;
  1233. if (rcv_desc->rcv_free >= 32) {
  1234. rcv_desc->rcv_free = 0;
  1235. /* Window = 1 */
  1236. writel((producer - 1) &
  1237. (rcv_desc->max_rx_desc_count - 1),
  1238. NETXEN_CRB_NORMALIZE(adapter,
  1239. recv_crb_registers[
  1240. adapter->portnum].
  1241. rcv_desc_crb[ringid].
  1242. crb_rcv_producer_offset));
  1243. /*
  1244. * Write a doorbell msg to tell phanmon of change in
  1245. * receive ring producer
  1246. */
  1247. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1248. netxen_set_msg_privid(msg);
  1249. netxen_set_msg_count(msg,
  1250. ((producer -
  1251. 1) & (rcv_desc->
  1252. max_rx_desc_count - 1)));
  1253. netxen_set_msg_ctxid(msg, adapter->portnum);
  1254. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1255. writel(msg,
  1256. DB_NORMALIZE(adapter,
  1257. NETXEN_RCV_PRODUCER_OFFSET));
  1258. }
  1259. }
  1260. }
  1261. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1262. uint32_t ringid)
  1263. {
  1264. struct pci_dev *pdev = adapter->ahw.pdev;
  1265. struct sk_buff *skb;
  1266. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1267. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1268. u32 producer;
  1269. struct rcv_desc *pdesc;
  1270. struct netxen_rx_buffer *buffer;
  1271. int count = 0;
  1272. int index = 0;
  1273. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1274. producer = rcv_desc->producer;
  1275. index = rcv_desc->begin_alloc;
  1276. buffer = &rcv_desc->rx_buf_arr[index];
  1277. /* We can start writing rx descriptors into the phantom memory. */
  1278. while (buffer->state == NETXEN_BUFFER_FREE) {
  1279. skb = dev_alloc_skb(rcv_desc->skb_size);
  1280. if (unlikely(!skb)) {
  1281. /*
  1282. * We need to schedule the posting of buffers to the pegs.
  1283. */
  1284. rcv_desc->begin_alloc = index;
  1285. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1286. " allocated only %d buffers\n", count);
  1287. break;
  1288. }
  1289. count++; /* now there should be no failure */
  1290. pdesc = &rcv_desc->desc_head[producer];
  1291. skb_reserve(skb, 2);
  1292. /*
  1293. * This will be setup when we receive the
  1294. * buffer after it has been filled
  1295. * skb->dev = netdev;
  1296. */
  1297. buffer->skb = skb;
  1298. buffer->state = NETXEN_BUFFER_BUSY;
  1299. buffer->dma = pci_map_single(pdev, skb->data,
  1300. rcv_desc->dma_size,
  1301. PCI_DMA_FROMDEVICE);
  1302. /* make a rcv descriptor */
  1303. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1304. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1305. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1306. DPRINTK(INFO, "done writing descripter\n");
  1307. producer =
  1308. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1309. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1310. buffer = &rcv_desc->rx_buf_arr[index];
  1311. }
  1312. /* if we did allocate buffers, then write the count to Phantom */
  1313. if (count) {
  1314. rcv_desc->begin_alloc = index;
  1315. rcv_desc->rcv_pending += count;
  1316. rcv_desc->producer = producer;
  1317. if (rcv_desc->rcv_free >= 32) {
  1318. rcv_desc->rcv_free = 0;
  1319. /* Window = 1 */
  1320. writel((producer - 1) &
  1321. (rcv_desc->max_rx_desc_count - 1),
  1322. NETXEN_CRB_NORMALIZE(adapter,
  1323. recv_crb_registers[
  1324. adapter->portnum].
  1325. rcv_desc_crb[ringid].
  1326. crb_rcv_producer_offset));
  1327. wmb();
  1328. }
  1329. }
  1330. }
  1331. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1332. {
  1333. if (find_diff_among(adapter->last_cmd_consumer,
  1334. adapter->cmd_producer,
  1335. adapter->max_tx_desc_count) > 0)
  1336. return 1;
  1337. return 0;
  1338. }
  1339. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1340. {
  1341. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1342. return;
  1343. }