radeon_fence.c 14 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  43. {
  44. if (rdev->wb.enabled) {
  45. *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
  46. } else {
  47. WREG32(rdev->fence_drv[ring].scratch_reg, seq);
  48. }
  49. }
  50. static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  51. {
  52. u32 seq = 0;
  53. if (rdev->wb.enabled) {
  54. seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
  55. } else {
  56. seq = RREG32(rdev->fence_drv[ring].scratch_reg);
  57. }
  58. return seq;
  59. }
  60. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  61. {
  62. unsigned long irq_flags;
  63. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  64. if (fence->emitted) {
  65. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  66. return 0;
  67. }
  68. fence->seq = atomic_add_return(1, &rdev->fence_drv[fence->ring].seq);
  69. radeon_fence_ring_emit(rdev, fence->ring, fence);
  70. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  71. fence->emitted = true;
  72. /* are we the first fence on a previusly idle ring? */
  73. if (list_empty(&rdev->fence_drv[fence->ring].emitted)) {
  74. rdev->fence_drv[fence->ring].last_activity = jiffies;
  75. }
  76. list_move_tail(&fence->list, &rdev->fence_drv[fence->ring].emitted);
  77. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  78. return 0;
  79. }
  80. static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
  81. {
  82. struct radeon_fence *fence;
  83. struct list_head *i, *n;
  84. uint32_t seq;
  85. bool wake = false;
  86. seq = radeon_fence_read(rdev, ring);
  87. if (seq == rdev->fence_drv[ring].last_seq)
  88. return false;
  89. rdev->fence_drv[ring].last_seq = seq;
  90. rdev->fence_drv[ring].last_activity = jiffies;
  91. n = NULL;
  92. list_for_each(i, &rdev->fence_drv[ring].emitted) {
  93. fence = list_entry(i, struct radeon_fence, list);
  94. if (fence->seq == seq) {
  95. n = i;
  96. break;
  97. }
  98. }
  99. /* all fence previous to this one are considered as signaled */
  100. if (n) {
  101. i = n;
  102. do {
  103. n = i->prev;
  104. list_move_tail(i, &rdev->fence_drv[ring].signaled);
  105. fence = list_entry(i, struct radeon_fence, list);
  106. fence->signaled = true;
  107. i = n;
  108. } while (i != &rdev->fence_drv[ring].emitted);
  109. wake = true;
  110. }
  111. return wake;
  112. }
  113. static void radeon_fence_destroy(struct kref *kref)
  114. {
  115. unsigned long irq_flags;
  116. struct radeon_fence *fence;
  117. fence = container_of(kref, struct radeon_fence, kref);
  118. write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
  119. list_del(&fence->list);
  120. fence->emitted = false;
  121. write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
  122. if (fence->semaphore)
  123. radeon_semaphore_free(fence->rdev, fence->semaphore);
  124. kfree(fence);
  125. }
  126. int radeon_fence_create(struct radeon_device *rdev,
  127. struct radeon_fence **fence,
  128. int ring)
  129. {
  130. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  131. if ((*fence) == NULL) {
  132. return -ENOMEM;
  133. }
  134. kref_init(&((*fence)->kref));
  135. (*fence)->rdev = rdev;
  136. (*fence)->emitted = false;
  137. (*fence)->signaled = false;
  138. (*fence)->seq = 0;
  139. (*fence)->ring = ring;
  140. (*fence)->semaphore = NULL;
  141. INIT_LIST_HEAD(&(*fence)->list);
  142. return 0;
  143. }
  144. bool radeon_fence_signaled(struct radeon_fence *fence)
  145. {
  146. unsigned long irq_flags;
  147. bool signaled = false;
  148. if (!fence)
  149. return true;
  150. write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
  151. signaled = fence->signaled;
  152. /* if we are shuting down report all fence as signaled */
  153. if (fence->rdev->shutdown) {
  154. signaled = true;
  155. }
  156. if (!fence->emitted) {
  157. WARN(1, "Querying an unemitted fence : %p !\n", fence);
  158. signaled = true;
  159. }
  160. if (!signaled) {
  161. radeon_fence_poll_locked(fence->rdev, fence->ring);
  162. signaled = fence->signaled;
  163. }
  164. write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
  165. return signaled;
  166. }
  167. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  168. {
  169. struct radeon_device *rdev;
  170. unsigned long irq_flags, timeout;
  171. u32 seq;
  172. int i, r;
  173. bool signaled;
  174. if (fence == NULL) {
  175. WARN(1, "Querying an invalid fence : %p !\n", fence);
  176. return -EINVAL;
  177. }
  178. rdev = fence->rdev;
  179. signaled = radeon_fence_signaled(fence);
  180. while (!signaled) {
  181. read_lock_irqsave(&rdev->fence_lock, irq_flags);
  182. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  183. if (time_after(rdev->fence_drv[fence->ring].last_activity, timeout)) {
  184. /* the normal case, timeout is somewhere before last_activity */
  185. timeout = rdev->fence_drv[fence->ring].last_activity - timeout;
  186. } else {
  187. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  188. * anyway we will just wait for the minimum amount and then check for a lockup */
  189. timeout = 1;
  190. }
  191. /* save current sequence value used to check for GPU lockups */
  192. seq = rdev->fence_drv[fence->ring].last_seq;
  193. read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  194. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  195. radeon_irq_kms_sw_irq_get(rdev, fence->ring);
  196. if (intr) {
  197. r = wait_event_interruptible_timeout(
  198. rdev->fence_drv[fence->ring].queue,
  199. (signaled = radeon_fence_signaled(fence)), timeout);
  200. } else {
  201. r = wait_event_timeout(
  202. rdev->fence_drv[fence->ring].queue,
  203. (signaled = radeon_fence_signaled(fence)), timeout);
  204. }
  205. radeon_irq_kms_sw_irq_put(rdev, fence->ring);
  206. if (unlikely(r < 0)) {
  207. return r;
  208. }
  209. trace_radeon_fence_wait_end(rdev->ddev, seq);
  210. if (unlikely(!signaled)) {
  211. /* we were interrupted for some reason and fence
  212. * isn't signaled yet, resume waiting */
  213. if (r) {
  214. continue;
  215. }
  216. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  217. /* check if sequence value has changed since last_activity */
  218. if (seq != rdev->fence_drv[fence->ring].last_seq) {
  219. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  220. continue;
  221. }
  222. /* change sequence value on all rings, so nobody else things there is a lockup */
  223. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  224. rdev->fence_drv[i].last_seq -= 0x10000;
  225. rdev->fence_drv[fence->ring].last_activity = jiffies;
  226. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  227. if (radeon_ring_is_lockup(rdev, fence->ring, &rdev->ring[fence->ring])) {
  228. /* good news we believe it's a lockup */
  229. printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
  230. fence->seq, seq);
  231. /* mark the ring as not ready any more */
  232. rdev->ring[fence->ring].ready = false;
  233. return -EDEADLK;
  234. }
  235. }
  236. }
  237. return 0;
  238. }
  239. int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
  240. {
  241. unsigned long irq_flags;
  242. struct radeon_fence *fence;
  243. int r;
  244. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  245. if (!rdev->ring[ring].ready) {
  246. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  247. return -EBUSY;
  248. }
  249. if (list_empty(&rdev->fence_drv[ring].emitted)) {
  250. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  251. return -ENOENT;
  252. }
  253. fence = list_entry(rdev->fence_drv[ring].emitted.next,
  254. struct radeon_fence, list);
  255. radeon_fence_ref(fence);
  256. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  257. r = radeon_fence_wait(fence, false);
  258. radeon_fence_unref(&fence);
  259. return r;
  260. }
  261. int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
  262. {
  263. unsigned long irq_flags;
  264. struct radeon_fence *fence;
  265. int r;
  266. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  267. if (!rdev->ring[ring].ready) {
  268. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  269. return -EBUSY;
  270. }
  271. if (list_empty(&rdev->fence_drv[ring].emitted)) {
  272. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  273. return 0;
  274. }
  275. fence = list_entry(rdev->fence_drv[ring].emitted.prev,
  276. struct radeon_fence, list);
  277. radeon_fence_ref(fence);
  278. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  279. r = radeon_fence_wait(fence, false);
  280. radeon_fence_unref(&fence);
  281. return r;
  282. }
  283. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  284. {
  285. kref_get(&fence->kref);
  286. return fence;
  287. }
  288. void radeon_fence_unref(struct radeon_fence **fence)
  289. {
  290. struct radeon_fence *tmp = *fence;
  291. *fence = NULL;
  292. if (tmp) {
  293. kref_put(&tmp->kref, radeon_fence_destroy);
  294. }
  295. }
  296. void radeon_fence_process(struct radeon_device *rdev, int ring)
  297. {
  298. unsigned long irq_flags;
  299. bool wake;
  300. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  301. wake = radeon_fence_poll_locked(rdev, ring);
  302. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  303. if (wake) {
  304. wake_up_all(&rdev->fence_drv[ring].queue);
  305. }
  306. }
  307. int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
  308. {
  309. unsigned long irq_flags;
  310. int not_processed = 0;
  311. read_lock_irqsave(&rdev->fence_lock, irq_flags);
  312. if (!rdev->fence_drv[ring].initialized) {
  313. read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  314. return 0;
  315. }
  316. if (!list_empty(&rdev->fence_drv[ring].emitted)) {
  317. struct list_head *ptr;
  318. list_for_each(ptr, &rdev->fence_drv[ring].emitted) {
  319. /* count up to 3, that's enought info */
  320. if (++not_processed >= 3)
  321. break;
  322. }
  323. }
  324. read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  325. return not_processed;
  326. }
  327. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  328. {
  329. unsigned long irq_flags;
  330. uint64_t index;
  331. int r;
  332. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  333. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  334. if (rdev->wb.use_event) {
  335. rdev->fence_drv[ring].scratch_reg = 0;
  336. index = R600_WB_EVENT_OFFSET + ring * 4;
  337. } else {
  338. r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
  339. if (r) {
  340. dev_err(rdev->dev, "fence failed to get scratch register\n");
  341. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  342. return r;
  343. }
  344. index = RADEON_WB_SCRATCH_OFFSET +
  345. rdev->fence_drv[ring].scratch_reg -
  346. rdev->scratch.reg_base;
  347. }
  348. rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
  349. rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
  350. radeon_fence_write(rdev, atomic_read(&rdev->fence_drv[ring].seq), ring);
  351. rdev->fence_drv[ring].initialized = true;
  352. DRM_INFO("fence driver on ring %d use gpu addr 0x%08Lx and cpu addr 0x%p\n",
  353. ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
  354. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  355. return 0;
  356. }
  357. static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
  358. {
  359. rdev->fence_drv[ring].scratch_reg = -1;
  360. rdev->fence_drv[ring].cpu_addr = NULL;
  361. rdev->fence_drv[ring].gpu_addr = 0;
  362. atomic_set(&rdev->fence_drv[ring].seq, 0);
  363. INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
  364. INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
  365. init_waitqueue_head(&rdev->fence_drv[ring].queue);
  366. rdev->fence_drv[ring].initialized = false;
  367. }
  368. int radeon_fence_driver_init(struct radeon_device *rdev)
  369. {
  370. unsigned long irq_flags;
  371. int ring;
  372. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  373. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  374. radeon_fence_driver_init_ring(rdev, ring);
  375. }
  376. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  377. if (radeon_debugfs_fence_init(rdev)) {
  378. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  379. }
  380. return 0;
  381. }
  382. void radeon_fence_driver_fini(struct radeon_device *rdev)
  383. {
  384. unsigned long irq_flags;
  385. int ring;
  386. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  387. if (!rdev->fence_drv[ring].initialized)
  388. continue;
  389. radeon_fence_wait_empty(rdev, ring);
  390. wake_up_all(&rdev->fence_drv[ring].queue);
  391. write_lock_irqsave(&rdev->fence_lock, irq_flags);
  392. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  393. write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
  394. rdev->fence_drv[ring].initialized = false;
  395. }
  396. }
  397. /*
  398. * Fence debugfs
  399. */
  400. #if defined(CONFIG_DEBUG_FS)
  401. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  402. {
  403. struct drm_info_node *node = (struct drm_info_node *)m->private;
  404. struct drm_device *dev = node->minor->dev;
  405. struct radeon_device *rdev = dev->dev_private;
  406. struct radeon_fence *fence;
  407. int i;
  408. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  409. if (!rdev->fence_drv[i].initialized)
  410. continue;
  411. seq_printf(m, "--- ring %d ---\n", i);
  412. seq_printf(m, "Last signaled fence 0x%08X\n",
  413. radeon_fence_read(rdev, i));
  414. if (!list_empty(&rdev->fence_drv[i].emitted)) {
  415. fence = list_entry(rdev->fence_drv[i].emitted.prev,
  416. struct radeon_fence, list);
  417. seq_printf(m, "Last emitted fence %p with 0x%08X\n",
  418. fence, fence->seq);
  419. }
  420. }
  421. return 0;
  422. }
  423. static struct drm_info_list radeon_debugfs_fence_list[] = {
  424. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  425. };
  426. #endif
  427. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  428. {
  429. #if defined(CONFIG_DEBUG_FS)
  430. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  431. #else
  432. return 0;
  433. #endif
  434. }