radeon_cs.c 17 KB

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  1. /*
  2. * Copyright 2008 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Jerome Glisse <glisse@freedesktop.org>
  26. */
  27. #include "drmP.h"
  28. #include "radeon_drm.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  32. struct radeon_cs_packet *pkt);
  33. int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  34. {
  35. struct drm_device *ddev = p->rdev->ddev;
  36. struct radeon_cs_chunk *chunk;
  37. unsigned i, j;
  38. bool duplicate;
  39. if (p->chunk_relocs_idx == -1) {
  40. return 0;
  41. }
  42. chunk = &p->chunks[p->chunk_relocs_idx];
  43. /* FIXME: we assume that each relocs use 4 dwords */
  44. p->nrelocs = chunk->length_dw / 4;
  45. p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  46. if (p->relocs_ptr == NULL) {
  47. return -ENOMEM;
  48. }
  49. p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  50. if (p->relocs == NULL) {
  51. return -ENOMEM;
  52. }
  53. for (i = 0; i < p->nrelocs; i++) {
  54. struct drm_radeon_cs_reloc *r;
  55. duplicate = false;
  56. r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  57. for (j = 0; j < i; j++) {
  58. if (r->handle == p->relocs[j].handle) {
  59. p->relocs_ptr[i] = &p->relocs[j];
  60. duplicate = true;
  61. break;
  62. }
  63. }
  64. if (!duplicate) {
  65. p->relocs[i].gobj = drm_gem_object_lookup(ddev,
  66. p->filp,
  67. r->handle);
  68. if (p->relocs[i].gobj == NULL) {
  69. DRM_ERROR("gem object lookup failed 0x%x\n",
  70. r->handle);
  71. return -ENOENT;
  72. }
  73. p->relocs_ptr[i] = &p->relocs[i];
  74. p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  75. p->relocs[i].lobj.bo = p->relocs[i].robj;
  76. p->relocs[i].lobj.wdomain = r->write_domain;
  77. p->relocs[i].lobj.rdomain = r->read_domains;
  78. p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
  79. p->relocs[i].handle = r->handle;
  80. p->relocs[i].flags = r->flags;
  81. radeon_bo_list_add_object(&p->relocs[i].lobj,
  82. &p->validated);
  83. } else
  84. p->relocs[i].handle = 0;
  85. }
  86. return radeon_bo_list_validate(&p->validated);
  87. }
  88. static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
  89. {
  90. p->priority = priority;
  91. switch (ring) {
  92. default:
  93. DRM_ERROR("unknown ring id: %d\n", ring);
  94. return -EINVAL;
  95. case RADEON_CS_RING_GFX:
  96. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  97. break;
  98. case RADEON_CS_RING_COMPUTE:
  99. if (p->rdev->family >= CHIP_TAHITI) {
  100. if (p->priority > 0)
  101. p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
  102. else
  103. p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
  104. } else
  105. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  106. break;
  107. }
  108. return 0;
  109. }
  110. static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
  111. {
  112. bool sync_to_ring[RADEON_NUM_RINGS] = { };
  113. bool need_sync = false;
  114. int i, r;
  115. for (i = 0; i < p->nrelocs; i++) {
  116. if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
  117. continue;
  118. if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
  119. struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
  120. if (fence->ring != p->ring && !radeon_fence_signaled(fence)) {
  121. sync_to_ring[fence->ring] = true;
  122. need_sync = true;
  123. }
  124. }
  125. }
  126. if (!need_sync) {
  127. return 0;
  128. }
  129. r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
  130. if (r) {
  131. return r;
  132. }
  133. return radeon_semaphore_sync_rings(p->rdev, p->ib->fence->semaphore,
  134. sync_to_ring, p->ring);
  135. }
  136. int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
  137. {
  138. struct drm_radeon_cs *cs = data;
  139. uint64_t *chunk_array_ptr;
  140. unsigned size, i;
  141. u32 ring = RADEON_CS_RING_GFX;
  142. s32 priority = 0;
  143. if (!cs->num_chunks) {
  144. return 0;
  145. }
  146. /* get chunks */
  147. INIT_LIST_HEAD(&p->validated);
  148. p->idx = 0;
  149. p->chunk_ib_idx = -1;
  150. p->chunk_relocs_idx = -1;
  151. p->chunk_flags_idx = -1;
  152. p->chunk_const_ib_idx = -1;
  153. p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
  154. if (p->chunks_array == NULL) {
  155. return -ENOMEM;
  156. }
  157. chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
  158. if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
  159. sizeof(uint64_t)*cs->num_chunks)) {
  160. return -EFAULT;
  161. }
  162. p->cs_flags = 0;
  163. p->nchunks = cs->num_chunks;
  164. p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
  165. if (p->chunks == NULL) {
  166. return -ENOMEM;
  167. }
  168. for (i = 0; i < p->nchunks; i++) {
  169. struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
  170. struct drm_radeon_cs_chunk user_chunk;
  171. uint32_t __user *cdata;
  172. chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
  173. if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
  174. sizeof(struct drm_radeon_cs_chunk))) {
  175. return -EFAULT;
  176. }
  177. p->chunks[i].length_dw = user_chunk.length_dw;
  178. p->chunks[i].kdata = NULL;
  179. p->chunks[i].chunk_id = user_chunk.chunk_id;
  180. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
  181. p->chunk_relocs_idx = i;
  182. }
  183. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
  184. p->chunk_ib_idx = i;
  185. /* zero length IB isn't useful */
  186. if (p->chunks[i].length_dw == 0)
  187. return -EINVAL;
  188. }
  189. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
  190. p->chunk_const_ib_idx = i;
  191. /* zero length CONST IB isn't useful */
  192. if (p->chunks[i].length_dw == 0)
  193. return -EINVAL;
  194. }
  195. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  196. p->chunk_flags_idx = i;
  197. /* zero length flags aren't useful */
  198. if (p->chunks[i].length_dw == 0)
  199. return -EINVAL;
  200. }
  201. p->chunks[i].length_dw = user_chunk.length_dw;
  202. p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
  203. cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
  204. if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
  205. (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
  206. size = p->chunks[i].length_dw * sizeof(uint32_t);
  207. p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
  208. if (p->chunks[i].kdata == NULL) {
  209. return -ENOMEM;
  210. }
  211. if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
  212. p->chunks[i].user_ptr, size)) {
  213. return -EFAULT;
  214. }
  215. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  216. p->cs_flags = p->chunks[i].kdata[0];
  217. if (p->chunks[i].length_dw > 1)
  218. ring = p->chunks[i].kdata[1];
  219. if (p->chunks[i].length_dw > 2)
  220. priority = (s32)p->chunks[i].kdata[2];
  221. }
  222. }
  223. }
  224. if ((p->cs_flags & RADEON_CS_USE_VM) &&
  225. !p->rdev->vm_manager.enabled) {
  226. DRM_ERROR("VM not active on asic!\n");
  227. return -EINVAL;
  228. }
  229. /* we only support VM on SI+ */
  230. if ((p->rdev->family >= CHIP_TAHITI) &&
  231. ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
  232. DRM_ERROR("VM required on SI+!\n");
  233. return -EINVAL;
  234. }
  235. if (radeon_cs_get_ring(p, ring, priority))
  236. return -EINVAL;
  237. /* deal with non-vm */
  238. if ((p->chunk_ib_idx != -1) &&
  239. ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
  240. (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
  241. if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
  242. DRM_ERROR("cs IB too big: %d\n",
  243. p->chunks[p->chunk_ib_idx].length_dw);
  244. return -EINVAL;
  245. }
  246. if ((p->rdev->flags & RADEON_IS_AGP)) {
  247. p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  248. p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  249. if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
  250. p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
  251. kfree(p->chunks[i].kpage[0]);
  252. kfree(p->chunks[i].kpage[1]);
  253. return -ENOMEM;
  254. }
  255. }
  256. p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
  257. p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
  258. p->chunks[p->chunk_ib_idx].last_copied_page = -1;
  259. p->chunks[p->chunk_ib_idx].last_page_index =
  260. ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
  261. }
  262. return 0;
  263. }
  264. /**
  265. * cs_parser_fini() - clean parser states
  266. * @parser: parser structure holding parsing context.
  267. * @error: error number
  268. *
  269. * If error is set than unvalidate buffer, otherwise just free memory
  270. * used by parsing context.
  271. **/
  272. static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
  273. {
  274. unsigned i;
  275. if (!error && parser->ib)
  276. ttm_eu_fence_buffer_objects(&parser->validated,
  277. parser->ib->fence);
  278. else
  279. ttm_eu_backoff_reservation(&parser->validated);
  280. if (parser->relocs != NULL) {
  281. for (i = 0; i < parser->nrelocs; i++) {
  282. if (parser->relocs[i].gobj)
  283. drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
  284. }
  285. }
  286. kfree(parser->track);
  287. kfree(parser->relocs);
  288. kfree(parser->relocs_ptr);
  289. for (i = 0; i < parser->nchunks; i++) {
  290. kfree(parser->chunks[i].kdata);
  291. if ((parser->rdev->flags & RADEON_IS_AGP)) {
  292. kfree(parser->chunks[i].kpage[0]);
  293. kfree(parser->chunks[i].kpage[1]);
  294. }
  295. }
  296. kfree(parser->chunks);
  297. kfree(parser->chunks_array);
  298. radeon_ib_free(parser->rdev, &parser->ib);
  299. }
  300. static int radeon_cs_ib_chunk(struct radeon_device *rdev,
  301. struct radeon_cs_parser *parser)
  302. {
  303. struct radeon_cs_chunk *ib_chunk;
  304. int r;
  305. if (parser->chunk_ib_idx == -1)
  306. return 0;
  307. if (parser->cs_flags & RADEON_CS_USE_VM)
  308. return 0;
  309. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  310. /* Copy the packet into the IB, the parser will read from the
  311. * input memory (cached) and write to the IB (which can be
  312. * uncached).
  313. */
  314. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  315. ib_chunk->length_dw * 4);
  316. if (r) {
  317. DRM_ERROR("Failed to get ib !\n");
  318. return r;
  319. }
  320. parser->ib->length_dw = ib_chunk->length_dw;
  321. r = radeon_cs_parse(rdev, parser->ring, parser);
  322. if (r || parser->parser_error) {
  323. DRM_ERROR("Invalid command stream !\n");
  324. return r;
  325. }
  326. r = radeon_cs_finish_pages(parser);
  327. if (r) {
  328. DRM_ERROR("Invalid command stream !\n");
  329. return r;
  330. }
  331. r = radeon_cs_sync_rings(parser);
  332. if (r) {
  333. DRM_ERROR("Failed to synchronize rings !\n");
  334. }
  335. parser->ib->vm_id = 0;
  336. r = radeon_ib_schedule(rdev, parser->ib);
  337. if (r) {
  338. DRM_ERROR("Failed to schedule IB !\n");
  339. }
  340. return 0;
  341. }
  342. static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
  343. struct radeon_vm *vm)
  344. {
  345. struct radeon_bo_list *lobj;
  346. struct radeon_bo *bo;
  347. int r;
  348. list_for_each_entry(lobj, &parser->validated, tv.head) {
  349. bo = lobj->bo;
  350. r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
  351. if (r) {
  352. return r;
  353. }
  354. }
  355. return 0;
  356. }
  357. static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
  358. struct radeon_cs_parser *parser)
  359. {
  360. struct radeon_cs_chunk *ib_chunk;
  361. struct radeon_fpriv *fpriv = parser->filp->driver_priv;
  362. struct radeon_vm *vm = &fpriv->vm;
  363. int r;
  364. if (parser->chunk_ib_idx == -1)
  365. return 0;
  366. if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
  367. return 0;
  368. if ((rdev->family >= CHIP_TAHITI) &&
  369. (parser->chunk_const_ib_idx != -1)) {
  370. ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
  371. if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
  372. DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
  373. return -EINVAL;
  374. }
  375. r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
  376. ib_chunk->length_dw * 4);
  377. if (r) {
  378. DRM_ERROR("Failed to get const ib !\n");
  379. return r;
  380. }
  381. parser->const_ib->is_const_ib = true;
  382. parser->const_ib->length_dw = ib_chunk->length_dw;
  383. /* Copy the packet into the IB */
  384. if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
  385. ib_chunk->length_dw * 4)) {
  386. return -EFAULT;
  387. }
  388. r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
  389. if (r) {
  390. return r;
  391. }
  392. }
  393. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  394. if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
  395. DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
  396. return -EINVAL;
  397. }
  398. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  399. ib_chunk->length_dw * 4);
  400. if (r) {
  401. DRM_ERROR("Failed to get ib !\n");
  402. return r;
  403. }
  404. parser->ib->length_dw = ib_chunk->length_dw;
  405. /* Copy the packet into the IB */
  406. if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
  407. ib_chunk->length_dw * 4)) {
  408. return -EFAULT;
  409. }
  410. r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
  411. if (r) {
  412. return r;
  413. }
  414. mutex_lock(&vm->mutex);
  415. r = radeon_vm_bind(rdev, vm);
  416. if (r) {
  417. goto out;
  418. }
  419. r = radeon_bo_vm_update_pte(parser, vm);
  420. if (r) {
  421. goto out;
  422. }
  423. r = radeon_cs_sync_rings(parser);
  424. if (r) {
  425. DRM_ERROR("Failed to synchronize rings !\n");
  426. }
  427. if ((rdev->family >= CHIP_TAHITI) &&
  428. (parser->chunk_const_ib_idx != -1)) {
  429. parser->const_ib->vm_id = vm->id;
  430. /* ib pool is bind at 0 in virtual address space to gpu_addr is the
  431. * offset inside the pool bo
  432. */
  433. parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
  434. r = radeon_ib_schedule(rdev, parser->const_ib);
  435. if (r)
  436. goto out;
  437. }
  438. parser->ib->vm_id = vm->id;
  439. /* ib pool is bind at 0 in virtual address space to gpu_addr is the
  440. * offset inside the pool bo
  441. */
  442. parser->ib->gpu_addr = parser->ib->sa_bo.offset;
  443. parser->ib->is_const_ib = false;
  444. r = radeon_ib_schedule(rdev, parser->ib);
  445. out:
  446. if (!r) {
  447. if (vm->fence) {
  448. radeon_fence_unref(&vm->fence);
  449. }
  450. vm->fence = radeon_fence_ref(parser->ib->fence);
  451. }
  452. mutex_unlock(&fpriv->vm.mutex);
  453. return r;
  454. }
  455. static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
  456. {
  457. if (r == -EDEADLK) {
  458. r = radeon_gpu_reset(rdev);
  459. if (!r)
  460. r = -EAGAIN;
  461. }
  462. return r;
  463. }
  464. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  465. {
  466. struct radeon_device *rdev = dev->dev_private;
  467. struct radeon_cs_parser parser;
  468. int r;
  469. radeon_mutex_lock(&rdev->cs_mutex);
  470. if (!rdev->accel_working) {
  471. radeon_mutex_unlock(&rdev->cs_mutex);
  472. return -EBUSY;
  473. }
  474. /* initialize parser */
  475. memset(&parser, 0, sizeof(struct radeon_cs_parser));
  476. parser.filp = filp;
  477. parser.rdev = rdev;
  478. parser.dev = rdev->dev;
  479. parser.family = rdev->family;
  480. r = radeon_cs_parser_init(&parser, data);
  481. if (r) {
  482. DRM_ERROR("Failed to initialize parser !\n");
  483. radeon_cs_parser_fini(&parser, r);
  484. r = radeon_cs_handle_lockup(rdev, r);
  485. radeon_mutex_unlock(&rdev->cs_mutex);
  486. return r;
  487. }
  488. r = radeon_cs_parser_relocs(&parser);
  489. if (r) {
  490. if (r != -ERESTARTSYS)
  491. DRM_ERROR("Failed to parse relocation %d!\n", r);
  492. radeon_cs_parser_fini(&parser, r);
  493. r = radeon_cs_handle_lockup(rdev, r);
  494. radeon_mutex_unlock(&rdev->cs_mutex);
  495. return r;
  496. }
  497. r = radeon_cs_ib_chunk(rdev, &parser);
  498. if (r) {
  499. goto out;
  500. }
  501. r = radeon_cs_ib_vm_chunk(rdev, &parser);
  502. if (r) {
  503. goto out;
  504. }
  505. out:
  506. radeon_cs_parser_fini(&parser, r);
  507. r = radeon_cs_handle_lockup(rdev, r);
  508. radeon_mutex_unlock(&rdev->cs_mutex);
  509. return r;
  510. }
  511. int radeon_cs_finish_pages(struct radeon_cs_parser *p)
  512. {
  513. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  514. int i;
  515. int size = PAGE_SIZE;
  516. for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
  517. if (i == ibc->last_page_index) {
  518. size = (ibc->length_dw * 4) % PAGE_SIZE;
  519. if (size == 0)
  520. size = PAGE_SIZE;
  521. }
  522. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  523. ibc->user_ptr + (i * PAGE_SIZE),
  524. size))
  525. return -EFAULT;
  526. }
  527. return 0;
  528. }
  529. int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
  530. {
  531. int new_page;
  532. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  533. int i;
  534. int size = PAGE_SIZE;
  535. bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
  536. for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
  537. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  538. ibc->user_ptr + (i * PAGE_SIZE),
  539. PAGE_SIZE)) {
  540. p->parser_error = -EFAULT;
  541. return 0;
  542. }
  543. }
  544. if (pg_idx == ibc->last_page_index) {
  545. size = (ibc->length_dw * 4) % PAGE_SIZE;
  546. if (size == 0)
  547. size = PAGE_SIZE;
  548. }
  549. new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
  550. if (copy1)
  551. ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));
  552. if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
  553. ibc->user_ptr + (pg_idx * PAGE_SIZE),
  554. size)) {
  555. p->parser_error = -EFAULT;
  556. return 0;
  557. }
  558. /* copy to IB for non single case */
  559. if (!copy1)
  560. memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
  561. ibc->last_copied_page = pg_idx;
  562. ibc->kpage_idx[new_page] = pg_idx;
  563. return new_page;
  564. }