bnx2fc_hwi.c 58 KB

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  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2010 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *destroy_kcqe);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  87. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  88. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  89. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  90. ((u64) hba->hash_tbl_pbl_dma >> 32);
  91. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  92. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  93. ((u64) hba->t2_hash_tbl_dma >> 32);
  94. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  95. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  96. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  97. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  98. /* fill init3 KWQE */
  99. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  100. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  101. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  102. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  103. fcoe_init3.error_bit_map_lo = 0xffffffff;
  104. fcoe_init3.error_bit_map_hi = 0xffffffff;
  105. fcoe_init3.perf_config = 1;
  106. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  107. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  108. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  109. if (hba->cnic && hba->cnic->submit_kwqes)
  110. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  111. return rc;
  112. }
  113. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  114. {
  115. struct fcoe_kwqe_destroy fcoe_destroy;
  116. struct kwqe *kwqe_arr[2];
  117. int num_kwqes = 1;
  118. int rc = -1;
  119. /* fill destroy KWQE */
  120. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  121. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  122. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  123. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  124. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  125. if (hba->cnic && hba->cnic->submit_kwqes)
  126. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  127. return rc;
  128. }
  129. /**
  130. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  131. *
  132. * @port: port structure pointer
  133. * @tgt: bnx2fc_rport structure pointer
  134. */
  135. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  136. struct bnx2fc_rport *tgt)
  137. {
  138. struct fc_lport *lport = port->lport;
  139. struct bnx2fc_interface *interface = port->priv;
  140. struct bnx2fc_hba *hba = interface->hba;
  141. struct kwqe *kwqe_arr[4];
  142. struct fcoe_kwqe_conn_offload1 ofld_req1;
  143. struct fcoe_kwqe_conn_offload2 ofld_req2;
  144. struct fcoe_kwqe_conn_offload3 ofld_req3;
  145. struct fcoe_kwqe_conn_offload4 ofld_req4;
  146. struct fc_rport_priv *rdata = tgt->rdata;
  147. struct fc_rport *rport = tgt->rport;
  148. int num_kwqes = 4;
  149. u32 port_id;
  150. int rc = 0;
  151. u16 conn_id;
  152. /* Initialize offload request 1 structure */
  153. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  154. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  155. ofld_req1.hdr.flags =
  156. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  157. conn_id = (u16)tgt->fcoe_conn_id;
  158. ofld_req1.fcoe_conn_id = conn_id;
  159. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  160. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  161. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  162. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  163. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  164. ofld_req1.rq_first_pbe_addr_hi =
  165. (u32)((u64) tgt->rq_dma >> 32);
  166. ofld_req1.rq_prod = 0x8000;
  167. /* Initialize offload request 2 structure */
  168. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  169. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  170. ofld_req2.hdr.flags =
  171. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  172. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  173. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  174. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  175. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  176. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  177. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  178. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  179. /* Initialize offload request 3 structure */
  180. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  181. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  182. ofld_req3.hdr.flags =
  183. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  184. ofld_req3.vlan_tag = interface->vlan_id <<
  185. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  186. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  187. port_id = fc_host_port_id(lport->host);
  188. if (port_id == 0) {
  189. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  190. return -EINVAL;
  191. }
  192. /*
  193. * Store s_id of the initiator for further reference. This will
  194. * be used during disable/destroy during linkdown processing as
  195. * when the lport is reset, the port_id also is reset to 0
  196. */
  197. tgt->sid = port_id;
  198. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  199. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  200. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  201. port_id = rport->port_id;
  202. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  203. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  204. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  205. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  206. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  207. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  208. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  209. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  210. ofld_req3.rx_open_seqs_exch_c3 = 1;
  211. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  212. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  213. /* set mul_n_port_ids supported flag to 0, until it is supported */
  214. ofld_req3.flags = 0;
  215. /*
  216. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  217. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  218. */
  219. /* Info from PLOGI response */
  220. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  221. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  222. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  223. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  224. /*
  225. * Info from PRLI response, this info is used for sequence level error
  226. * recovery support
  227. */
  228. if (tgt->dev_type == TYPE_TAPE) {
  229. ofld_req3.flags |= 1 <<
  230. FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
  231. ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
  232. ? 1 : 0) <<
  233. FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
  234. }
  235. /* vlan flag */
  236. ofld_req3.flags |= (interface->vlan_enabled <<
  237. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  238. /* C2_VALID and ACK flags are not set as they are not suppported */
  239. /* Initialize offload request 4 structure */
  240. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  241. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  242. ofld_req4.hdr.flags =
  243. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  244. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  245. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  246. /* local mac */
  247. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  248. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  249. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  250. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  251. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  252. ofld_req4.dst_mac_addr_lo[0] = interface->ctlr.dest_addr[5];
  253. /* fcf mac */
  254. ofld_req4.dst_mac_addr_lo[1] = interface->ctlr.dest_addr[4];
  255. ofld_req4.dst_mac_addr_mid[0] = interface->ctlr.dest_addr[3];
  256. ofld_req4.dst_mac_addr_mid[1] = interface->ctlr.dest_addr[2];
  257. ofld_req4.dst_mac_addr_hi[0] = interface->ctlr.dest_addr[1];
  258. ofld_req4.dst_mac_addr_hi[1] = interface->ctlr.dest_addr[0];
  259. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  260. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  261. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  262. ofld_req4.confq_pbl_base_addr_hi =
  263. (u32)((u64) tgt->confq_pbl_dma >> 32);
  264. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  265. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  266. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  267. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  268. if (hba->cnic && hba->cnic->submit_kwqes)
  269. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  270. return rc;
  271. }
  272. /**
  273. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  274. *
  275. * @port: port structure pointer
  276. * @tgt: bnx2fc_rport structure pointer
  277. */
  278. static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  279. struct bnx2fc_rport *tgt)
  280. {
  281. struct kwqe *kwqe_arr[2];
  282. struct bnx2fc_interface *interface = port->priv;
  283. struct bnx2fc_hba *hba = interface->hba;
  284. struct fcoe_kwqe_conn_enable_disable enbl_req;
  285. struct fc_lport *lport = port->lport;
  286. struct fc_rport *rport = tgt->rport;
  287. int num_kwqes = 1;
  288. int rc = 0;
  289. u32 port_id;
  290. memset(&enbl_req, 0x00,
  291. sizeof(struct fcoe_kwqe_conn_enable_disable));
  292. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  293. enbl_req.hdr.flags =
  294. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  295. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  296. /* local mac */
  297. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  298. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  299. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  300. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  301. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  302. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  303. enbl_req.dst_mac_addr_lo[0] = interface->ctlr.dest_addr[5];
  304. enbl_req.dst_mac_addr_lo[1] = interface->ctlr.dest_addr[4];
  305. enbl_req.dst_mac_addr_mid[0] = interface->ctlr.dest_addr[3];
  306. enbl_req.dst_mac_addr_mid[1] = interface->ctlr.dest_addr[2];
  307. enbl_req.dst_mac_addr_hi[0] = interface->ctlr.dest_addr[1];
  308. enbl_req.dst_mac_addr_hi[1] = interface->ctlr.dest_addr[0];
  309. port_id = fc_host_port_id(lport->host);
  310. if (port_id != tgt->sid) {
  311. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  312. "sid = 0x%x\n", port_id, tgt->sid);
  313. port_id = tgt->sid;
  314. }
  315. enbl_req.s_id[0] = (port_id & 0x000000FF);
  316. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  317. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  318. port_id = rport->port_id;
  319. enbl_req.d_id[0] = (port_id & 0x000000FF);
  320. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  321. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  322. enbl_req.vlan_tag = interface->vlan_id <<
  323. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  324. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  325. enbl_req.vlan_flag = interface->vlan_enabled;
  326. enbl_req.context_id = tgt->context_id;
  327. enbl_req.conn_id = tgt->fcoe_conn_id;
  328. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  329. if (hba->cnic && hba->cnic->submit_kwqes)
  330. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  331. return rc;
  332. }
  333. /**
  334. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  335. *
  336. * @port: port structure pointer
  337. * @tgt: bnx2fc_rport structure pointer
  338. */
  339. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  340. struct bnx2fc_rport *tgt)
  341. {
  342. struct bnx2fc_interface *interface = port->priv;
  343. struct bnx2fc_hba *hba = interface->hba;
  344. struct fcoe_kwqe_conn_enable_disable disable_req;
  345. struct kwqe *kwqe_arr[2];
  346. struct fc_rport *rport = tgt->rport;
  347. int num_kwqes = 1;
  348. int rc = 0;
  349. u32 port_id;
  350. memset(&disable_req, 0x00,
  351. sizeof(struct fcoe_kwqe_conn_enable_disable));
  352. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  353. disable_req.hdr.flags =
  354. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  355. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  356. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  357. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  358. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  359. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  360. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  361. disable_req.dst_mac_addr_lo[0] = interface->ctlr.dest_addr[5];
  362. disable_req.dst_mac_addr_lo[1] = interface->ctlr.dest_addr[4];
  363. disable_req.dst_mac_addr_mid[0] = interface->ctlr.dest_addr[3];
  364. disable_req.dst_mac_addr_mid[1] = interface->ctlr.dest_addr[2];
  365. disable_req.dst_mac_addr_hi[0] = interface->ctlr.dest_addr[1];
  366. disable_req.dst_mac_addr_hi[1] = interface->ctlr.dest_addr[0];
  367. port_id = tgt->sid;
  368. disable_req.s_id[0] = (port_id & 0x000000FF);
  369. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  370. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  371. port_id = rport->port_id;
  372. disable_req.d_id[0] = (port_id & 0x000000FF);
  373. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  374. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  375. disable_req.context_id = tgt->context_id;
  376. disable_req.conn_id = tgt->fcoe_conn_id;
  377. disable_req.vlan_tag = interface->vlan_id <<
  378. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  379. disable_req.vlan_tag |=
  380. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  381. disable_req.vlan_flag = interface->vlan_enabled;
  382. kwqe_arr[0] = (struct kwqe *) &disable_req;
  383. if (hba->cnic && hba->cnic->submit_kwqes)
  384. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  385. return rc;
  386. }
  387. /**
  388. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  389. *
  390. * @port: port structure pointer
  391. * @tgt: bnx2fc_rport structure pointer
  392. */
  393. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  394. struct bnx2fc_rport *tgt)
  395. {
  396. struct fcoe_kwqe_conn_destroy destroy_req;
  397. struct kwqe *kwqe_arr[2];
  398. int num_kwqes = 1;
  399. int rc = 0;
  400. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  401. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  402. destroy_req.hdr.flags =
  403. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  404. destroy_req.context_id = tgt->context_id;
  405. destroy_req.conn_id = tgt->fcoe_conn_id;
  406. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  407. if (hba->cnic && hba->cnic->submit_kwqes)
  408. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  409. return rc;
  410. }
  411. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  412. {
  413. struct bnx2fc_lport *blport;
  414. spin_lock_bh(&hba->hba_lock);
  415. list_for_each_entry(blport, &hba->vports, list) {
  416. if (blport->lport == lport) {
  417. spin_unlock_bh(&hba->hba_lock);
  418. return true;
  419. }
  420. }
  421. spin_unlock_bh(&hba->hba_lock);
  422. return false;
  423. }
  424. static void bnx2fc_unsol_els_work(struct work_struct *work)
  425. {
  426. struct bnx2fc_unsol_els *unsol_els;
  427. struct fc_lport *lport;
  428. struct bnx2fc_hba *hba;
  429. struct fc_frame *fp;
  430. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  431. lport = unsol_els->lport;
  432. fp = unsol_els->fp;
  433. hba = unsol_els->hba;
  434. if (is_valid_lport(hba, lport))
  435. fc_exch_recv(lport, fp);
  436. kfree(unsol_els);
  437. }
  438. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  439. unsigned char *buf,
  440. u32 frame_len, u16 l2_oxid)
  441. {
  442. struct fcoe_port *port = tgt->port;
  443. struct fc_lport *lport = port->lport;
  444. struct bnx2fc_interface *interface = port->priv;
  445. struct bnx2fc_unsol_els *unsol_els;
  446. struct fc_frame_header *fh;
  447. struct fc_frame *fp;
  448. struct sk_buff *skb;
  449. u32 payload_len;
  450. u32 crc;
  451. u8 op;
  452. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  453. if (!unsol_els) {
  454. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  455. return;
  456. }
  457. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  458. l2_oxid, frame_len);
  459. payload_len = frame_len - sizeof(struct fc_frame_header);
  460. fp = fc_frame_alloc(lport, payload_len);
  461. if (!fp) {
  462. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  463. kfree(unsol_els);
  464. return;
  465. }
  466. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  467. /* Copy FC Frame header and payload into the frame */
  468. memcpy(fh, buf, frame_len);
  469. if (l2_oxid != FC_XID_UNKNOWN)
  470. fh->fh_ox_id = htons(l2_oxid);
  471. skb = fp_skb(fp);
  472. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  473. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  474. if (fh->fh_type == FC_TYPE_ELS) {
  475. op = fc_frame_payload_op(fp);
  476. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  477. (op == ELS_FAN) || (op == ELS_CSU)) {
  478. /*
  479. * No need to reply for these
  480. * ELS requests
  481. */
  482. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  483. kfree_skb(skb);
  484. kfree(unsol_els);
  485. return;
  486. }
  487. }
  488. crc = fcoe_fc_crc(fp);
  489. fc_frame_init(fp);
  490. fr_dev(fp) = lport;
  491. fr_sof(fp) = FC_SOF_I3;
  492. fr_eof(fp) = FC_EOF_T;
  493. fr_crc(fp) = cpu_to_le32(~crc);
  494. unsol_els->lport = lport;
  495. unsol_els->hba = interface->hba;
  496. unsol_els->fp = fp;
  497. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  498. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  499. } else {
  500. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  501. kfree_skb(skb);
  502. kfree(unsol_els);
  503. }
  504. }
  505. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  506. {
  507. u8 num_rq;
  508. struct fcoe_err_report_entry *err_entry;
  509. unsigned char *rq_data;
  510. unsigned char *buf = NULL, *buf1;
  511. int i;
  512. u16 xid;
  513. u32 frame_len, len;
  514. struct bnx2fc_cmd *io_req = NULL;
  515. struct fcoe_task_ctx_entry *task, *task_page;
  516. struct bnx2fc_interface *interface = tgt->port->priv;
  517. struct bnx2fc_hba *hba = interface->hba;
  518. int task_idx, index;
  519. int rc = 0;
  520. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  521. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  522. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  523. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  524. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  525. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  526. spin_lock_bh(&tgt->tgt_lock);
  527. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  528. spin_unlock_bh(&tgt->tgt_lock);
  529. if (rq_data) {
  530. buf = rq_data;
  531. } else {
  532. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  533. GFP_ATOMIC);
  534. if (!buf1) {
  535. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  536. break;
  537. }
  538. for (i = 0; i < num_rq; i++) {
  539. spin_lock_bh(&tgt->tgt_lock);
  540. rq_data = (unsigned char *)
  541. bnx2fc_get_next_rqe(tgt, 1);
  542. spin_unlock_bh(&tgt->tgt_lock);
  543. len = BNX2FC_RQ_BUF_SZ;
  544. memcpy(buf1, rq_data, len);
  545. buf1 += len;
  546. }
  547. }
  548. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  549. FC_XID_UNKNOWN);
  550. if (buf != rq_data)
  551. kfree(buf);
  552. spin_lock_bh(&tgt->tgt_lock);
  553. bnx2fc_return_rqe(tgt, num_rq);
  554. spin_unlock_bh(&tgt->tgt_lock);
  555. break;
  556. case FCOE_ERROR_DETECTION_CQE_TYPE:
  557. /*
  558. * In case of error reporting CQE a single RQ entry
  559. * is consumed.
  560. */
  561. spin_lock_bh(&tgt->tgt_lock);
  562. num_rq = 1;
  563. err_entry = (struct fcoe_err_report_entry *)
  564. bnx2fc_get_next_rqe(tgt, 1);
  565. xid = err_entry->fc_hdr.ox_id;
  566. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  567. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  568. err_entry->data.err_warn_bitmap_hi,
  569. err_entry->data.err_warn_bitmap_lo);
  570. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  571. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  572. bnx2fc_return_rqe(tgt, 1);
  573. if (xid > BNX2FC_MAX_XID) {
  574. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  575. xid);
  576. spin_unlock_bh(&tgt->tgt_lock);
  577. break;
  578. }
  579. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  580. index = xid % BNX2FC_TASKS_PER_PAGE;
  581. task_page = (struct fcoe_task_ctx_entry *)
  582. hba->task_ctx[task_idx];
  583. task = &(task_page[index]);
  584. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  585. if (!io_req) {
  586. spin_unlock_bh(&tgt->tgt_lock);
  587. break;
  588. }
  589. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  590. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  591. spin_unlock_bh(&tgt->tgt_lock);
  592. break;
  593. }
  594. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  595. &io_req->req_flags)) {
  596. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  597. "progress.. ignore unsol err\n");
  598. spin_unlock_bh(&tgt->tgt_lock);
  599. break;
  600. }
  601. /*
  602. * If ABTS is already in progress, and FW error is
  603. * received after that, do not cancel the timeout_work
  604. * and let the error recovery continue by explicitly
  605. * logging out the target, when the ABTS eventually
  606. * times out.
  607. */
  608. if (!test_and_set_bit(BNX2FC_FLAG_ISSUE_ABTS,
  609. &io_req->req_flags)) {
  610. /*
  611. * Cancel the timeout_work, as we received IO
  612. * completion with FW error.
  613. */
  614. if (cancel_delayed_work(&io_req->timeout_work))
  615. kref_put(&io_req->refcount,
  616. bnx2fc_cmd_release); /* timer hold */
  617. rc = bnx2fc_initiate_abts(io_req);
  618. if (rc != SUCCESS) {
  619. BNX2FC_IO_DBG(io_req, "err_warn: initiate_abts "
  620. "failed. issue cleanup\n");
  621. rc = bnx2fc_initiate_cleanup(io_req);
  622. BUG_ON(rc);
  623. }
  624. } else
  625. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  626. "in ABTS processing\n", xid);
  627. spin_unlock_bh(&tgt->tgt_lock);
  628. break;
  629. case FCOE_WARNING_DETECTION_CQE_TYPE:
  630. /*
  631. *In case of warning reporting CQE a single RQ entry
  632. * is consumes.
  633. */
  634. spin_lock_bh(&tgt->tgt_lock);
  635. num_rq = 1;
  636. err_entry = (struct fcoe_err_report_entry *)
  637. bnx2fc_get_next_rqe(tgt, 1);
  638. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  639. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  640. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  641. err_entry->data.err_warn_bitmap_hi,
  642. err_entry->data.err_warn_bitmap_lo);
  643. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  644. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  645. bnx2fc_return_rqe(tgt, 1);
  646. spin_unlock_bh(&tgt->tgt_lock);
  647. break;
  648. default:
  649. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  650. break;
  651. }
  652. }
  653. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  654. {
  655. struct fcoe_task_ctx_entry *task;
  656. struct fcoe_task_ctx_entry *task_page;
  657. struct fcoe_port *port = tgt->port;
  658. struct bnx2fc_interface *interface = port->priv;
  659. struct bnx2fc_hba *hba = interface->hba;
  660. struct bnx2fc_cmd *io_req;
  661. int task_idx, index;
  662. u16 xid;
  663. u8 cmd_type;
  664. u8 rx_state = 0;
  665. u8 num_rq;
  666. spin_lock_bh(&tgt->tgt_lock);
  667. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  668. if (xid >= BNX2FC_MAX_TASKS) {
  669. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  670. spin_unlock_bh(&tgt->tgt_lock);
  671. return;
  672. }
  673. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  674. index = xid % BNX2FC_TASKS_PER_PAGE;
  675. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  676. task = &(task_page[index]);
  677. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  678. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  679. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  680. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  681. if (io_req == NULL) {
  682. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  683. spin_unlock_bh(&tgt->tgt_lock);
  684. return;
  685. }
  686. /* Timestamp IO completion time */
  687. cmd_type = io_req->cmd_type;
  688. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  689. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  690. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  691. /* Process other IO completion types */
  692. switch (cmd_type) {
  693. case BNX2FC_SCSI_CMD:
  694. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  695. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  696. spin_unlock_bh(&tgt->tgt_lock);
  697. return;
  698. }
  699. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  700. bnx2fc_process_abts_compl(io_req, task, num_rq);
  701. else if (rx_state ==
  702. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  703. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  704. else
  705. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  706. rx_state);
  707. break;
  708. case BNX2FC_TASK_MGMT_CMD:
  709. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  710. bnx2fc_process_tm_compl(io_req, task, num_rq);
  711. break;
  712. case BNX2FC_ABTS:
  713. /*
  714. * ABTS request received by firmware. ABTS response
  715. * will be delivered to the task belonging to the IO
  716. * that was aborted
  717. */
  718. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  719. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  720. break;
  721. case BNX2FC_ELS:
  722. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  723. bnx2fc_process_els_compl(io_req, task, num_rq);
  724. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  725. bnx2fc_process_abts_compl(io_req, task, num_rq);
  726. else if (rx_state ==
  727. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  728. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  729. else
  730. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  731. rx_state);
  732. break;
  733. case BNX2FC_CLEANUP:
  734. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  735. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  736. break;
  737. case BNX2FC_SEQ_CLEANUP:
  738. BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
  739. io_req->xid);
  740. bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
  741. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  742. break;
  743. default:
  744. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  745. break;
  746. }
  747. spin_unlock_bh(&tgt->tgt_lock);
  748. }
  749. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  750. {
  751. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  752. u32 msg;
  753. wmb();
  754. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  755. FCOE_CQE_TOGGLE_BIT_SHIFT);
  756. msg = *((u32 *)rx_db);
  757. writel(cpu_to_le32(msg), tgt->ctx_base);
  758. mmiowb();
  759. }
  760. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  761. {
  762. struct bnx2fc_work *work;
  763. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  764. if (!work)
  765. return NULL;
  766. INIT_LIST_HEAD(&work->list);
  767. work->tgt = tgt;
  768. work->wqe = wqe;
  769. return work;
  770. }
  771. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  772. {
  773. struct fcoe_cqe *cq;
  774. u32 cq_cons;
  775. struct fcoe_cqe *cqe;
  776. u32 num_free_sqes = 0;
  777. u16 wqe;
  778. /*
  779. * cq_lock is a low contention lock used to protect
  780. * the CQ data structure from being freed up during
  781. * the upload operation
  782. */
  783. spin_lock_bh(&tgt->cq_lock);
  784. if (!tgt->cq) {
  785. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  786. spin_unlock_bh(&tgt->cq_lock);
  787. return 0;
  788. }
  789. cq = tgt->cq;
  790. cq_cons = tgt->cq_cons_idx;
  791. cqe = &cq[cq_cons];
  792. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  793. (tgt->cq_curr_toggle_bit <<
  794. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  795. /* new entry on the cq */
  796. if (wqe & FCOE_CQE_CQE_TYPE) {
  797. /* Unsolicited event notification */
  798. bnx2fc_process_unsol_compl(tgt, wqe);
  799. } else {
  800. /* Pending work request completion */
  801. struct bnx2fc_work *work = NULL;
  802. struct bnx2fc_percpu_s *fps = NULL;
  803. unsigned int cpu = wqe % num_possible_cpus();
  804. fps = &per_cpu(bnx2fc_percpu, cpu);
  805. spin_lock_bh(&fps->fp_work_lock);
  806. if (unlikely(!fps->iothread))
  807. goto unlock;
  808. work = bnx2fc_alloc_work(tgt, wqe);
  809. if (work)
  810. list_add_tail(&work->list,
  811. &fps->work_list);
  812. unlock:
  813. spin_unlock_bh(&fps->fp_work_lock);
  814. /* Pending work request completion */
  815. if (fps->iothread && work)
  816. wake_up_process(fps->iothread);
  817. else
  818. bnx2fc_process_cq_compl(tgt, wqe);
  819. }
  820. cqe++;
  821. tgt->cq_cons_idx++;
  822. num_free_sqes++;
  823. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  824. tgt->cq_cons_idx = 0;
  825. cqe = cq;
  826. tgt->cq_curr_toggle_bit =
  827. 1 - tgt->cq_curr_toggle_bit;
  828. }
  829. }
  830. bnx2fc_arm_cq(tgt);
  831. atomic_add(num_free_sqes, &tgt->free_sqes);
  832. spin_unlock_bh(&tgt->cq_lock);
  833. return 0;
  834. }
  835. /**
  836. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  837. *
  838. * @hba: adapter structure pointer
  839. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  840. *
  841. * Fast path event notification handler
  842. */
  843. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  844. struct fcoe_kcqe *new_cqe_kcqe)
  845. {
  846. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  847. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  848. if (!tgt) {
  849. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  850. return;
  851. }
  852. bnx2fc_process_new_cqes(tgt);
  853. }
  854. /**
  855. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  856. *
  857. * @hba: adapter structure pointer
  858. * @ofld_kcqe: connection offload kcqe pointer
  859. *
  860. * handle session offload completion, enable the session if offload is
  861. * successful.
  862. */
  863. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  864. struct fcoe_kcqe *ofld_kcqe)
  865. {
  866. struct bnx2fc_rport *tgt;
  867. struct fcoe_port *port;
  868. struct bnx2fc_interface *interface;
  869. u32 conn_id;
  870. u32 context_id;
  871. int rc;
  872. conn_id = ofld_kcqe->fcoe_conn_id;
  873. context_id = ofld_kcqe->fcoe_conn_context_id;
  874. tgt = hba->tgt_ofld_list[conn_id];
  875. if (!tgt) {
  876. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  877. return;
  878. }
  879. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  880. ofld_kcqe->fcoe_conn_context_id);
  881. port = tgt->port;
  882. interface = tgt->port->priv;
  883. if (hba != interface->hba) {
  884. printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  885. goto ofld_cmpl_err;
  886. }
  887. /*
  888. * cnic has allocated a context_id for this session; use this
  889. * while enabling the session.
  890. */
  891. tgt->context_id = context_id;
  892. if (ofld_kcqe->completion_status) {
  893. if (ofld_kcqe->completion_status ==
  894. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  895. printk(KERN_ERR PFX "unable to allocate FCoE context "
  896. "resources\n");
  897. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  898. }
  899. goto ofld_cmpl_err;
  900. } else {
  901. /* now enable the session */
  902. rc = bnx2fc_send_session_enable_req(port, tgt);
  903. if (rc) {
  904. printk(KERN_ERR PFX "enable session failed\n");
  905. goto ofld_cmpl_err;
  906. }
  907. }
  908. return;
  909. ofld_cmpl_err:
  910. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  911. wake_up_interruptible(&tgt->ofld_wait);
  912. }
  913. /**
  914. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  915. *
  916. * @hba: adapter structure pointer
  917. * @ofld_kcqe: connection offload kcqe pointer
  918. *
  919. * handle session enable completion, mark the rport as ready
  920. */
  921. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  922. struct fcoe_kcqe *ofld_kcqe)
  923. {
  924. struct bnx2fc_rport *tgt;
  925. struct bnx2fc_interface *interface;
  926. u32 conn_id;
  927. u32 context_id;
  928. context_id = ofld_kcqe->fcoe_conn_context_id;
  929. conn_id = ofld_kcqe->fcoe_conn_id;
  930. tgt = hba->tgt_ofld_list[conn_id];
  931. if (!tgt) {
  932. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  933. return;
  934. }
  935. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  936. ofld_kcqe->fcoe_conn_context_id);
  937. /*
  938. * context_id should be the same for this target during offload
  939. * and enable
  940. */
  941. if (tgt->context_id != context_id) {
  942. printk(KERN_ERR PFX "context id mis-match\n");
  943. return;
  944. }
  945. interface = tgt->port->priv;
  946. if (hba != interface->hba) {
  947. printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  948. goto enbl_cmpl_err;
  949. }
  950. if (ofld_kcqe->completion_status)
  951. goto enbl_cmpl_err;
  952. else {
  953. /* enable successful - rport ready for issuing IOs */
  954. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  955. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  956. wake_up_interruptible(&tgt->ofld_wait);
  957. }
  958. return;
  959. enbl_cmpl_err:
  960. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  961. wake_up_interruptible(&tgt->ofld_wait);
  962. }
  963. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  964. struct fcoe_kcqe *disable_kcqe)
  965. {
  966. struct bnx2fc_rport *tgt;
  967. u32 conn_id;
  968. conn_id = disable_kcqe->fcoe_conn_id;
  969. tgt = hba->tgt_ofld_list[conn_id];
  970. if (!tgt) {
  971. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  972. return;
  973. }
  974. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  975. if (disable_kcqe->completion_status) {
  976. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  977. disable_kcqe->completion_status);
  978. return;
  979. } else {
  980. /* disable successful */
  981. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  982. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  983. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  984. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  985. wake_up_interruptible(&tgt->upld_wait);
  986. }
  987. }
  988. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  989. struct fcoe_kcqe *destroy_kcqe)
  990. {
  991. struct bnx2fc_rport *tgt;
  992. u32 conn_id;
  993. conn_id = destroy_kcqe->fcoe_conn_id;
  994. tgt = hba->tgt_ofld_list[conn_id];
  995. if (!tgt) {
  996. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  997. return;
  998. }
  999. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  1000. if (destroy_kcqe->completion_status) {
  1001. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  1002. destroy_kcqe->completion_status);
  1003. return;
  1004. } else {
  1005. /* destroy successful */
  1006. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  1007. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1008. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  1009. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1010. wake_up_interruptible(&tgt->upld_wait);
  1011. }
  1012. }
  1013. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  1014. {
  1015. switch (err_code) {
  1016. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  1017. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  1018. break;
  1019. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  1020. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  1021. break;
  1022. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  1023. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  1024. break;
  1025. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  1026. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1027. break;
  1028. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1029. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1030. break;
  1031. default:
  1032. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1033. }
  1034. }
  1035. /**
  1036. * bnx2fc_indicae_kcqe - process KCQE
  1037. *
  1038. * @hba: adapter structure pointer
  1039. * @kcqe: kcqe pointer
  1040. * @num_cqe: Number of completion queue elements
  1041. *
  1042. * Generic KCQ event handler
  1043. */
  1044. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1045. u32 num_cqe)
  1046. {
  1047. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1048. int i = 0;
  1049. struct fcoe_kcqe *kcqe = NULL;
  1050. while (i < num_cqe) {
  1051. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1052. switch (kcqe->op_code) {
  1053. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1054. bnx2fc_fastpath_notification(hba, kcqe);
  1055. break;
  1056. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1057. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1058. break;
  1059. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1060. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1061. break;
  1062. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1063. if (kcqe->completion_status !=
  1064. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1065. bnx2fc_init_failure(hba,
  1066. kcqe->completion_status);
  1067. } else {
  1068. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1069. bnx2fc_get_link_state(hba);
  1070. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1071. (u8)hba->pcidev->bus->number);
  1072. }
  1073. break;
  1074. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1075. if (kcqe->completion_status !=
  1076. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1077. printk(KERN_ERR PFX "DESTROY failed\n");
  1078. } else {
  1079. printk(KERN_ERR PFX "DESTROY success\n");
  1080. }
  1081. set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
  1082. wake_up_interruptible(&hba->destroy_wait);
  1083. break;
  1084. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1085. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1086. break;
  1087. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1088. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1089. break;
  1090. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1091. if (kcqe->completion_status !=
  1092. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1093. printk(KERN_ERR PFX "STAT failed\n");
  1094. complete(&hba->stat_req_done);
  1095. break;
  1096. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1097. /* fall thru */
  1098. default:
  1099. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1100. kcqe->op_code);
  1101. }
  1102. }
  1103. }
  1104. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1105. {
  1106. struct fcoe_sqe *sqe;
  1107. sqe = &tgt->sq[tgt->sq_prod_idx];
  1108. /* Fill SQ WQE */
  1109. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1110. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1111. /* Advance SQ Prod Idx */
  1112. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1113. tgt->sq_prod_idx = 0;
  1114. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1115. }
  1116. }
  1117. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1118. {
  1119. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1120. u32 msg;
  1121. wmb();
  1122. sq_db->prod = tgt->sq_prod_idx |
  1123. (tgt->sq_curr_toggle_bit << 15);
  1124. msg = *((u32 *)sq_db);
  1125. writel(cpu_to_le32(msg), tgt->ctx_base);
  1126. mmiowb();
  1127. }
  1128. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1129. {
  1130. u32 context_id = tgt->context_id;
  1131. struct fcoe_port *port = tgt->port;
  1132. u32 reg_off;
  1133. resource_size_t reg_base;
  1134. struct bnx2fc_interface *interface = port->priv;
  1135. struct bnx2fc_hba *hba = interface->hba;
  1136. reg_base = pci_resource_start(hba->pcidev,
  1137. BNX2X_DOORBELL_PCI_BAR);
  1138. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1139. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1140. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1141. if (!tgt->ctx_base)
  1142. return -ENOMEM;
  1143. return 0;
  1144. }
  1145. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1146. {
  1147. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1148. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1149. return NULL;
  1150. tgt->rq_cons_idx += num_items;
  1151. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1152. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1153. return buf;
  1154. }
  1155. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1156. {
  1157. /* return the rq buffer */
  1158. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1159. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1160. /* Wrap around RQ */
  1161. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1162. }
  1163. tgt->rq_prod_idx = next_prod_idx;
  1164. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1165. }
  1166. void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
  1167. struct fcoe_task_ctx_entry *task,
  1168. struct bnx2fc_cmd *orig_io_req,
  1169. u32 offset)
  1170. {
  1171. struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
  1172. struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
  1173. struct bnx2fc_interface *interface = tgt->port->priv;
  1174. struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
  1175. struct fcoe_task_ctx_entry *orig_task;
  1176. struct fcoe_task_ctx_entry *task_page;
  1177. struct fcoe_ext_mul_sges_ctx *sgl;
  1178. u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
  1179. u8 orig_task_type;
  1180. u16 orig_xid = orig_io_req->xid;
  1181. u32 context_id = tgt->context_id;
  1182. u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
  1183. u32 orig_offset = offset;
  1184. int bd_count;
  1185. int orig_task_idx, index;
  1186. int i;
  1187. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1188. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1189. orig_task_type = FCOE_TASK_TYPE_WRITE;
  1190. else
  1191. orig_task_type = FCOE_TASK_TYPE_READ;
  1192. /* Tx flags */
  1193. task->txwr_rxrd.const_ctx.tx_flags =
  1194. FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
  1195. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1196. /* init flags */
  1197. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1198. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1199. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1200. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1201. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1202. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1203. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1204. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1205. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1206. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
  1207. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
  1208. bd_count = orig_io_req->bd_tbl->bd_valid;
  1209. /* obtain the appropriate bd entry from relative offset */
  1210. for (i = 0; i < bd_count; i++) {
  1211. if (offset < bd[i].buf_len)
  1212. break;
  1213. offset -= bd[i].buf_len;
  1214. }
  1215. phys_addr += (i * sizeof(struct fcoe_bd_ctx));
  1216. if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
  1217. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1218. (u32)phys_addr;
  1219. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1220. (u32)((u64)phys_addr >> 32);
  1221. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1222. bd_count;
  1223. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
  1224. offset; /* adjusted offset */
  1225. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
  1226. } else {
  1227. orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
  1228. index = orig_xid % BNX2FC_TASKS_PER_PAGE;
  1229. task_page = (struct fcoe_task_ctx_entry *)
  1230. interface->hba->task_ctx[orig_task_idx];
  1231. orig_task = &(task_page[index]);
  1232. /* Multiple SGEs were used for this IO */
  1233. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1234. sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
  1235. sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
  1236. sgl->mul_sgl.sgl_size = bd_count;
  1237. sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
  1238. sgl->mul_sgl.cur_sge_idx = i;
  1239. memset(&task->rxwr_only.rx_seq_ctx, 0,
  1240. sizeof(struct fcoe_rx_seq_ctx));
  1241. task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
  1242. task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
  1243. }
  1244. }
  1245. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1246. struct fcoe_task_ctx_entry *task,
  1247. u16 orig_xid)
  1248. {
  1249. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1250. struct bnx2fc_rport *tgt = io_req->tgt;
  1251. u32 context_id = tgt->context_id;
  1252. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1253. /* Tx Write Rx Read */
  1254. /* init flags */
  1255. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1256. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1257. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1258. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1259. task->txwr_rxrd.const_ctx.init_flags |=
  1260. FCOE_TASK_DEV_TYPE_DISK <<
  1261. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1262. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1263. /* Tx flags */
  1264. task->txwr_rxrd.const_ctx.tx_flags =
  1265. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1266. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1267. /* Rx Read Tx Write */
  1268. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1269. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1270. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1271. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1272. }
  1273. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1274. struct fcoe_task_ctx_entry *task)
  1275. {
  1276. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1277. struct bnx2fc_rport *tgt = io_req->tgt;
  1278. struct fc_frame_header *fc_hdr;
  1279. struct fcoe_ext_mul_sges_ctx *sgl;
  1280. u8 task_type = 0;
  1281. u64 *hdr;
  1282. u64 temp_hdr[3];
  1283. u32 context_id;
  1284. /* Obtain task_type */
  1285. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1286. (io_req->cmd_type == BNX2FC_ELS)) {
  1287. task_type = FCOE_TASK_TYPE_MIDPATH;
  1288. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1289. task_type = FCOE_TASK_TYPE_ABTS;
  1290. }
  1291. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1292. /* Setup the task from io_req for easy reference */
  1293. io_req->task = task;
  1294. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1295. io_req->cmd_type, task_type);
  1296. /* Tx only */
  1297. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1298. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1299. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1300. (u32)mp_req->mp_req_bd_dma;
  1301. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1302. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1303. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1304. }
  1305. /* Tx Write Rx Read */
  1306. /* init flags */
  1307. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1308. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1309. task->txwr_rxrd.const_ctx.init_flags |=
  1310. FCOE_TASK_DEV_TYPE_DISK <<
  1311. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1312. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1313. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1314. /* tx flags */
  1315. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1316. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1317. /* Rx Write Tx Read */
  1318. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1319. /* rx flags */
  1320. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1321. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1322. context_id = tgt->context_id;
  1323. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1324. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1325. fc_hdr = &(mp_req->req_fc_hdr);
  1326. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1327. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1328. fc_hdr->fh_rx_id = htons(0xffff);
  1329. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1330. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1331. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1332. }
  1333. /* Fill FC Header into middle path buffer */
  1334. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1335. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1336. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1337. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1338. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1339. /* Rx Only */
  1340. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1341. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1342. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1343. sgl->mul_sgl.cur_sge_addr.hi =
  1344. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1345. sgl->mul_sgl.sgl_size = 1;
  1346. }
  1347. }
  1348. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1349. struct fcoe_task_ctx_entry *task)
  1350. {
  1351. u8 task_type;
  1352. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1353. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1354. struct bnx2fc_rport *tgt = io_req->tgt;
  1355. struct fcoe_cached_sge_ctx *cached_sge;
  1356. struct fcoe_ext_mul_sges_ctx *sgl;
  1357. u64 *fcp_cmnd;
  1358. u64 tmp_fcp_cmnd[4];
  1359. u32 context_id;
  1360. int cnt, i;
  1361. int bd_count;
  1362. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1363. /* Setup the task from io_req for easy reference */
  1364. io_req->task = task;
  1365. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1366. task_type = FCOE_TASK_TYPE_WRITE;
  1367. else
  1368. task_type = FCOE_TASK_TYPE_READ;
  1369. /* Tx only */
  1370. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1371. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1372. (u32)bd_tbl->bd_tbl_dma;
  1373. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1374. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1375. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1376. bd_tbl->bd_valid;
  1377. }
  1378. /*Tx Write Rx Read */
  1379. /* Init state to NORMAL */
  1380. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1381. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1382. task->txwr_rxrd.const_ctx.init_flags |=
  1383. FCOE_TASK_DEV_TYPE_DISK <<
  1384. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1385. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1386. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1387. /* tx flags */
  1388. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1389. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1390. /* Set initial seq counter */
  1391. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1392. /* Fill FCP_CMND IU */
  1393. fcp_cmnd = (u64 *)
  1394. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1395. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1396. /* swap fcp_cmnd */
  1397. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1398. for (i = 0; i < cnt; i++) {
  1399. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1400. fcp_cmnd++;
  1401. }
  1402. /* Rx Write Tx Read */
  1403. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1404. context_id = tgt->context_id;
  1405. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1406. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1407. /* rx flags */
  1408. /* Set state to "waiting for the first packet" */
  1409. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1410. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1411. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1412. /* Rx Only */
  1413. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1414. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1415. bd_count = bd_tbl->bd_valid;
  1416. if (task_type == FCOE_TASK_TYPE_READ) {
  1417. if (bd_count == 1) {
  1418. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1419. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1420. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1421. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1422. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1423. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1424. } else if (bd_count == 2) {
  1425. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1426. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1427. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1428. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1429. fcoe_bd_tbl++;
  1430. cached_sge->second_buf_addr.lo =
  1431. fcoe_bd_tbl->buf_addr_lo;
  1432. cached_sge->second_buf_addr.hi =
  1433. fcoe_bd_tbl->buf_addr_hi;
  1434. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1435. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1436. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1437. } else {
  1438. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1439. sgl->mul_sgl.cur_sge_addr.hi =
  1440. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1441. sgl->mul_sgl.sgl_size = bd_count;
  1442. }
  1443. }
  1444. }
  1445. /**
  1446. * bnx2fc_setup_task_ctx - allocate and map task context
  1447. *
  1448. * @hba: pointer to adapter structure
  1449. *
  1450. * allocate memory for task context, and associated BD table to be used
  1451. * by firmware
  1452. *
  1453. */
  1454. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1455. {
  1456. int rc = 0;
  1457. struct regpair *task_ctx_bdt;
  1458. dma_addr_t addr;
  1459. int i;
  1460. /*
  1461. * Allocate task context bd table. A page size of bd table
  1462. * can map 256 buffers. Each buffer contains 32 task context
  1463. * entries. Hence the limit with one page is 8192 task context
  1464. * entries.
  1465. */
  1466. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1467. PAGE_SIZE,
  1468. &hba->task_ctx_bd_dma,
  1469. GFP_KERNEL);
  1470. if (!hba->task_ctx_bd_tbl) {
  1471. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1472. rc = -1;
  1473. goto out;
  1474. }
  1475. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1476. /*
  1477. * Allocate task_ctx which is an array of pointers pointing to
  1478. * a page containing 32 task contexts
  1479. */
  1480. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1481. GFP_KERNEL);
  1482. if (!hba->task_ctx) {
  1483. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1484. rc = -1;
  1485. goto out1;
  1486. }
  1487. /*
  1488. * Allocate task_ctx_dma which is an array of dma addresses
  1489. */
  1490. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1491. sizeof(dma_addr_t)), GFP_KERNEL);
  1492. if (!hba->task_ctx_dma) {
  1493. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1494. rc = -1;
  1495. goto out2;
  1496. }
  1497. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1498. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1499. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1500. PAGE_SIZE,
  1501. &hba->task_ctx_dma[i],
  1502. GFP_KERNEL);
  1503. if (!hba->task_ctx[i]) {
  1504. printk(KERN_ERR PFX "unable to alloc task context\n");
  1505. rc = -1;
  1506. goto out3;
  1507. }
  1508. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1509. addr = (u64)hba->task_ctx_dma[i];
  1510. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1511. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1512. task_ctx_bdt++;
  1513. }
  1514. return 0;
  1515. out3:
  1516. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1517. if (hba->task_ctx[i]) {
  1518. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1519. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1520. hba->task_ctx[i] = NULL;
  1521. }
  1522. }
  1523. kfree(hba->task_ctx_dma);
  1524. hba->task_ctx_dma = NULL;
  1525. out2:
  1526. kfree(hba->task_ctx);
  1527. hba->task_ctx = NULL;
  1528. out1:
  1529. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1530. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1531. hba->task_ctx_bd_tbl = NULL;
  1532. out:
  1533. return rc;
  1534. }
  1535. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1536. {
  1537. int i;
  1538. if (hba->task_ctx_bd_tbl) {
  1539. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1540. hba->task_ctx_bd_tbl,
  1541. hba->task_ctx_bd_dma);
  1542. hba->task_ctx_bd_tbl = NULL;
  1543. }
  1544. if (hba->task_ctx) {
  1545. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1546. if (hba->task_ctx[i]) {
  1547. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1548. hba->task_ctx[i],
  1549. hba->task_ctx_dma[i]);
  1550. hba->task_ctx[i] = NULL;
  1551. }
  1552. }
  1553. kfree(hba->task_ctx);
  1554. hba->task_ctx = NULL;
  1555. }
  1556. kfree(hba->task_ctx_dma);
  1557. hba->task_ctx_dma = NULL;
  1558. }
  1559. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1560. {
  1561. int i;
  1562. int segment_count;
  1563. int hash_table_size;
  1564. u32 *pbl;
  1565. segment_count = hba->hash_tbl_segment_count;
  1566. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1567. sizeof(struct fcoe_hash_table_entry);
  1568. pbl = hba->hash_tbl_pbl;
  1569. for (i = 0; i < segment_count; ++i) {
  1570. dma_addr_t dma_address;
  1571. dma_address = le32_to_cpu(*pbl);
  1572. ++pbl;
  1573. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1574. ++pbl;
  1575. dma_free_coherent(&hba->pcidev->dev,
  1576. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1577. hba->hash_tbl_segments[i],
  1578. dma_address);
  1579. }
  1580. if (hba->hash_tbl_pbl) {
  1581. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1582. hba->hash_tbl_pbl,
  1583. hba->hash_tbl_pbl_dma);
  1584. hba->hash_tbl_pbl = NULL;
  1585. }
  1586. }
  1587. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1588. {
  1589. int i;
  1590. int hash_table_size;
  1591. int segment_count;
  1592. int segment_array_size;
  1593. int dma_segment_array_size;
  1594. dma_addr_t *dma_segment_array;
  1595. u32 *pbl;
  1596. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1597. sizeof(struct fcoe_hash_table_entry);
  1598. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1599. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1600. hba->hash_tbl_segment_count = segment_count;
  1601. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1602. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1603. if (!hba->hash_tbl_segments) {
  1604. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1605. return -ENOMEM;
  1606. }
  1607. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1608. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1609. if (!dma_segment_array) {
  1610. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1611. return -ENOMEM;
  1612. }
  1613. for (i = 0; i < segment_count; ++i) {
  1614. hba->hash_tbl_segments[i] =
  1615. dma_alloc_coherent(&hba->pcidev->dev,
  1616. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1617. &dma_segment_array[i],
  1618. GFP_KERNEL);
  1619. if (!hba->hash_tbl_segments[i]) {
  1620. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1621. while (--i >= 0) {
  1622. dma_free_coherent(&hba->pcidev->dev,
  1623. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1624. hba->hash_tbl_segments[i],
  1625. dma_segment_array[i]);
  1626. hba->hash_tbl_segments[i] = NULL;
  1627. }
  1628. kfree(dma_segment_array);
  1629. return -ENOMEM;
  1630. }
  1631. memset(hba->hash_tbl_segments[i], 0,
  1632. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1633. }
  1634. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1635. PAGE_SIZE,
  1636. &hba->hash_tbl_pbl_dma,
  1637. GFP_KERNEL);
  1638. if (!hba->hash_tbl_pbl) {
  1639. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1640. kfree(dma_segment_array);
  1641. return -ENOMEM;
  1642. }
  1643. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1644. pbl = hba->hash_tbl_pbl;
  1645. for (i = 0; i < segment_count; ++i) {
  1646. u64 paddr = dma_segment_array[i];
  1647. *pbl = cpu_to_le32((u32) paddr);
  1648. ++pbl;
  1649. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1650. ++pbl;
  1651. }
  1652. pbl = hba->hash_tbl_pbl;
  1653. i = 0;
  1654. while (*pbl && *(pbl + 1)) {
  1655. u32 lo;
  1656. u32 hi;
  1657. lo = *pbl;
  1658. ++pbl;
  1659. hi = *pbl;
  1660. ++pbl;
  1661. ++i;
  1662. }
  1663. kfree(dma_segment_array);
  1664. return 0;
  1665. }
  1666. /**
  1667. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1668. *
  1669. * @hba: Pointer to adapter structure
  1670. *
  1671. */
  1672. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1673. {
  1674. u64 addr;
  1675. u32 mem_size;
  1676. int i;
  1677. if (bnx2fc_allocate_hash_table(hba))
  1678. return -ENOMEM;
  1679. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1680. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1681. &hba->t2_hash_tbl_ptr_dma,
  1682. GFP_KERNEL);
  1683. if (!hba->t2_hash_tbl_ptr) {
  1684. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1685. bnx2fc_free_fw_resc(hba);
  1686. return -ENOMEM;
  1687. }
  1688. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1689. mem_size = BNX2FC_NUM_MAX_SESS *
  1690. sizeof(struct fcoe_t2_hash_table_entry);
  1691. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1692. &hba->t2_hash_tbl_dma,
  1693. GFP_KERNEL);
  1694. if (!hba->t2_hash_tbl) {
  1695. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1696. bnx2fc_free_fw_resc(hba);
  1697. return -ENOMEM;
  1698. }
  1699. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1700. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1701. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1702. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1703. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1704. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1705. }
  1706. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1707. PAGE_SIZE, &hba->dummy_buf_dma,
  1708. GFP_KERNEL);
  1709. if (!hba->dummy_buffer) {
  1710. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1711. bnx2fc_free_fw_resc(hba);
  1712. return -ENOMEM;
  1713. }
  1714. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1715. PAGE_SIZE,
  1716. &hba->stats_buf_dma,
  1717. GFP_KERNEL);
  1718. if (!hba->stats_buffer) {
  1719. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1720. bnx2fc_free_fw_resc(hba);
  1721. return -ENOMEM;
  1722. }
  1723. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1724. return 0;
  1725. }
  1726. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1727. {
  1728. u32 mem_size;
  1729. if (hba->stats_buffer) {
  1730. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1731. hba->stats_buffer, hba->stats_buf_dma);
  1732. hba->stats_buffer = NULL;
  1733. }
  1734. if (hba->dummy_buffer) {
  1735. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1736. hba->dummy_buffer, hba->dummy_buf_dma);
  1737. hba->dummy_buffer = NULL;
  1738. }
  1739. if (hba->t2_hash_tbl_ptr) {
  1740. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1741. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1742. hba->t2_hash_tbl_ptr,
  1743. hba->t2_hash_tbl_ptr_dma);
  1744. hba->t2_hash_tbl_ptr = NULL;
  1745. }
  1746. if (hba->t2_hash_tbl) {
  1747. mem_size = BNX2FC_NUM_MAX_SESS *
  1748. sizeof(struct fcoe_t2_hash_table_entry);
  1749. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1750. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1751. hba->t2_hash_tbl = NULL;
  1752. }
  1753. bnx2fc_free_hash_table(hba);
  1754. }