i915_debugfs.c 56 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. *
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/slab.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "intel_drv.h"
  35. #include "intel_ringbuffer.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #define DRM_I915_RING_DEBUG 1
  39. #if defined(CONFIG_DEBUG_FS)
  40. enum {
  41. ACTIVE_LIST,
  42. INACTIVE_LIST,
  43. PINNED_LIST,
  44. };
  45. static const char *yesno(int v)
  46. {
  47. return v ? "yes" : "no";
  48. }
  49. static int i915_capabilities(struct seq_file *m, void *data)
  50. {
  51. struct drm_info_node *node = (struct drm_info_node *) m->private;
  52. struct drm_device *dev = node->minor->dev;
  53. const struct intel_device_info *info = INTEL_INFO(dev);
  54. seq_printf(m, "gen: %d\n", info->gen);
  55. seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  56. #define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
  57. #define DEV_INFO_SEP ;
  58. DEV_INFO_FLAGS;
  59. #undef DEV_INFO_FLAG
  60. #undef DEV_INFO_SEP
  61. return 0;
  62. }
  63. static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  64. {
  65. if (obj->user_pin_count > 0)
  66. return "P";
  67. else if (obj->pin_count > 0)
  68. return "p";
  69. else
  70. return " ";
  71. }
  72. static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  73. {
  74. switch (obj->tiling_mode) {
  75. default:
  76. case I915_TILING_NONE: return " ";
  77. case I915_TILING_X: return "X";
  78. case I915_TILING_Y: return "Y";
  79. }
  80. }
  81. static const char *cache_level_str(int type)
  82. {
  83. switch (type) {
  84. case I915_CACHE_NONE: return " uncached";
  85. case I915_CACHE_LLC: return " snooped (LLC)";
  86. case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
  87. default: return "";
  88. }
  89. }
  90. static void
  91. describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
  92. {
  93. seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
  94. &obj->base,
  95. get_pin_flag(obj),
  96. get_tiling_flag(obj),
  97. obj->base.size / 1024,
  98. obj->base.read_domains,
  99. obj->base.write_domain,
  100. obj->last_read_seqno,
  101. obj->last_write_seqno,
  102. obj->last_fenced_seqno,
  103. cache_level_str(obj->cache_level),
  104. obj->dirty ? " dirty" : "",
  105. obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
  106. if (obj->base.name)
  107. seq_printf(m, " (name: %d)", obj->base.name);
  108. if (obj->fence_reg != I915_FENCE_REG_NONE)
  109. seq_printf(m, " (fence: %d)", obj->fence_reg);
  110. if (obj->gtt_space != NULL)
  111. seq_printf(m, " (gtt offset: %08x, size: %08x)",
  112. obj->gtt_offset, (unsigned int)obj->gtt_space->size);
  113. if (obj->pin_mappable || obj->fault_mappable) {
  114. char s[3], *t = s;
  115. if (obj->pin_mappable)
  116. *t++ = 'p';
  117. if (obj->fault_mappable)
  118. *t++ = 'f';
  119. *t = '\0';
  120. seq_printf(m, " (%s mappable)", s);
  121. }
  122. if (obj->ring != NULL)
  123. seq_printf(m, " (%s)", obj->ring->name);
  124. }
  125. static int i915_gem_object_list_info(struct seq_file *m, void *data)
  126. {
  127. struct drm_info_node *node = (struct drm_info_node *) m->private;
  128. uintptr_t list = (uintptr_t) node->info_ent->data;
  129. struct list_head *head;
  130. struct drm_device *dev = node->minor->dev;
  131. drm_i915_private_t *dev_priv = dev->dev_private;
  132. struct drm_i915_gem_object *obj;
  133. size_t total_obj_size, total_gtt_size;
  134. int count, ret;
  135. ret = mutex_lock_interruptible(&dev->struct_mutex);
  136. if (ret)
  137. return ret;
  138. switch (list) {
  139. case ACTIVE_LIST:
  140. seq_printf(m, "Active:\n");
  141. head = &dev_priv->mm.active_list;
  142. break;
  143. case INACTIVE_LIST:
  144. seq_printf(m, "Inactive:\n");
  145. head = &dev_priv->mm.inactive_list;
  146. break;
  147. default:
  148. mutex_unlock(&dev->struct_mutex);
  149. return -EINVAL;
  150. }
  151. total_obj_size = total_gtt_size = count = 0;
  152. list_for_each_entry(obj, head, mm_list) {
  153. seq_printf(m, " ");
  154. describe_obj(m, obj);
  155. seq_printf(m, "\n");
  156. total_obj_size += obj->base.size;
  157. total_gtt_size += obj->gtt_space->size;
  158. count++;
  159. }
  160. mutex_unlock(&dev->struct_mutex);
  161. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  162. count, total_obj_size, total_gtt_size);
  163. return 0;
  164. }
  165. #define count_objects(list, member) do { \
  166. list_for_each_entry(obj, list, member) { \
  167. size += obj->gtt_space->size; \
  168. ++count; \
  169. if (obj->map_and_fenceable) { \
  170. mappable_size += obj->gtt_space->size; \
  171. ++mappable_count; \
  172. } \
  173. } \
  174. } while (0)
  175. static int i915_gem_object_info(struct seq_file *m, void* data)
  176. {
  177. struct drm_info_node *node = (struct drm_info_node *) m->private;
  178. struct drm_device *dev = node->minor->dev;
  179. struct drm_i915_private *dev_priv = dev->dev_private;
  180. u32 count, mappable_count;
  181. size_t size, mappable_size;
  182. struct drm_i915_gem_object *obj;
  183. int ret;
  184. ret = mutex_lock_interruptible(&dev->struct_mutex);
  185. if (ret)
  186. return ret;
  187. seq_printf(m, "%u objects, %zu bytes\n",
  188. dev_priv->mm.object_count,
  189. dev_priv->mm.object_memory);
  190. size = count = mappable_size = mappable_count = 0;
  191. count_objects(&dev_priv->mm.bound_list, gtt_list);
  192. seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
  193. count, mappable_count, size, mappable_size);
  194. size = count = mappable_size = mappable_count = 0;
  195. count_objects(&dev_priv->mm.active_list, mm_list);
  196. seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
  197. count, mappable_count, size, mappable_size);
  198. size = count = mappable_size = mappable_count = 0;
  199. count_objects(&dev_priv->mm.inactive_list, mm_list);
  200. seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
  201. count, mappable_count, size, mappable_size);
  202. size = count = 0;
  203. list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
  204. size += obj->base.size, ++count;
  205. seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
  206. size = count = mappable_size = mappable_count = 0;
  207. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  208. if (obj->fault_mappable) {
  209. size += obj->gtt_space->size;
  210. ++count;
  211. }
  212. if (obj->pin_mappable) {
  213. mappable_size += obj->gtt_space->size;
  214. ++mappable_count;
  215. }
  216. }
  217. seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
  218. mappable_count, mappable_size);
  219. seq_printf(m, "%u fault mappable objects, %zu bytes\n",
  220. count, size);
  221. seq_printf(m, "%zu [%zu] gtt total\n",
  222. dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
  223. mutex_unlock(&dev->struct_mutex);
  224. return 0;
  225. }
  226. static int i915_gem_gtt_info(struct seq_file *m, void* data)
  227. {
  228. struct drm_info_node *node = (struct drm_info_node *) m->private;
  229. struct drm_device *dev = node->minor->dev;
  230. uintptr_t list = (uintptr_t) node->info_ent->data;
  231. struct drm_i915_private *dev_priv = dev->dev_private;
  232. struct drm_i915_gem_object *obj;
  233. size_t total_obj_size, total_gtt_size;
  234. int count, ret;
  235. ret = mutex_lock_interruptible(&dev->struct_mutex);
  236. if (ret)
  237. return ret;
  238. total_obj_size = total_gtt_size = count = 0;
  239. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  240. if (list == PINNED_LIST && obj->pin_count == 0)
  241. continue;
  242. seq_printf(m, " ");
  243. describe_obj(m, obj);
  244. seq_printf(m, "\n");
  245. total_obj_size += obj->base.size;
  246. total_gtt_size += obj->gtt_space->size;
  247. count++;
  248. }
  249. mutex_unlock(&dev->struct_mutex);
  250. seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
  251. count, total_obj_size, total_gtt_size);
  252. return 0;
  253. }
  254. static int i915_gem_pageflip_info(struct seq_file *m, void *data)
  255. {
  256. struct drm_info_node *node = (struct drm_info_node *) m->private;
  257. struct drm_device *dev = node->minor->dev;
  258. unsigned long flags;
  259. struct intel_crtc *crtc;
  260. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  261. const char pipe = pipe_name(crtc->pipe);
  262. const char plane = plane_name(crtc->plane);
  263. struct intel_unpin_work *work;
  264. spin_lock_irqsave(&dev->event_lock, flags);
  265. work = crtc->unpin_work;
  266. if (work == NULL) {
  267. seq_printf(m, "No flip due on pipe %c (plane %c)\n",
  268. pipe, plane);
  269. } else {
  270. if (!work->pending) {
  271. seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
  272. pipe, plane);
  273. } else {
  274. seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
  275. pipe, plane);
  276. }
  277. if (work->enable_stall_check)
  278. seq_printf(m, "Stall check enabled, ");
  279. else
  280. seq_printf(m, "Stall check waiting for page flip ioctl, ");
  281. seq_printf(m, "%d prepares\n", work->pending);
  282. if (work->old_fb_obj) {
  283. struct drm_i915_gem_object *obj = work->old_fb_obj;
  284. if (obj)
  285. seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  286. }
  287. if (work->pending_flip_obj) {
  288. struct drm_i915_gem_object *obj = work->pending_flip_obj;
  289. if (obj)
  290. seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
  291. }
  292. }
  293. spin_unlock_irqrestore(&dev->event_lock, flags);
  294. }
  295. return 0;
  296. }
  297. static int i915_gem_request_info(struct seq_file *m, void *data)
  298. {
  299. struct drm_info_node *node = (struct drm_info_node *) m->private;
  300. struct drm_device *dev = node->minor->dev;
  301. drm_i915_private_t *dev_priv = dev->dev_private;
  302. struct drm_i915_gem_request *gem_request;
  303. int ret, count;
  304. ret = mutex_lock_interruptible(&dev->struct_mutex);
  305. if (ret)
  306. return ret;
  307. count = 0;
  308. if (!list_empty(&dev_priv->ring[RCS].request_list)) {
  309. seq_printf(m, "Render requests:\n");
  310. list_for_each_entry(gem_request,
  311. &dev_priv->ring[RCS].request_list,
  312. list) {
  313. seq_printf(m, " %d @ %d\n",
  314. gem_request->seqno,
  315. (int) (jiffies - gem_request->emitted_jiffies));
  316. }
  317. count++;
  318. }
  319. if (!list_empty(&dev_priv->ring[VCS].request_list)) {
  320. seq_printf(m, "BSD requests:\n");
  321. list_for_each_entry(gem_request,
  322. &dev_priv->ring[VCS].request_list,
  323. list) {
  324. seq_printf(m, " %d @ %d\n",
  325. gem_request->seqno,
  326. (int) (jiffies - gem_request->emitted_jiffies));
  327. }
  328. count++;
  329. }
  330. if (!list_empty(&dev_priv->ring[BCS].request_list)) {
  331. seq_printf(m, "BLT requests:\n");
  332. list_for_each_entry(gem_request,
  333. &dev_priv->ring[BCS].request_list,
  334. list) {
  335. seq_printf(m, " %d @ %d\n",
  336. gem_request->seqno,
  337. (int) (jiffies - gem_request->emitted_jiffies));
  338. }
  339. count++;
  340. }
  341. mutex_unlock(&dev->struct_mutex);
  342. if (count == 0)
  343. seq_printf(m, "No requests\n");
  344. return 0;
  345. }
  346. static void i915_ring_seqno_info(struct seq_file *m,
  347. struct intel_ring_buffer *ring)
  348. {
  349. if (ring->get_seqno) {
  350. seq_printf(m, "Current sequence (%s): %d\n",
  351. ring->name, ring->get_seqno(ring, false));
  352. }
  353. }
  354. static int i915_gem_seqno_info(struct seq_file *m, void *data)
  355. {
  356. struct drm_info_node *node = (struct drm_info_node *) m->private;
  357. struct drm_device *dev = node->minor->dev;
  358. drm_i915_private_t *dev_priv = dev->dev_private;
  359. int ret, i;
  360. ret = mutex_lock_interruptible(&dev->struct_mutex);
  361. if (ret)
  362. return ret;
  363. for (i = 0; i < I915_NUM_RINGS; i++)
  364. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  365. mutex_unlock(&dev->struct_mutex);
  366. return 0;
  367. }
  368. static int i915_interrupt_info(struct seq_file *m, void *data)
  369. {
  370. struct drm_info_node *node = (struct drm_info_node *) m->private;
  371. struct drm_device *dev = node->minor->dev;
  372. drm_i915_private_t *dev_priv = dev->dev_private;
  373. int ret, i, pipe;
  374. ret = mutex_lock_interruptible(&dev->struct_mutex);
  375. if (ret)
  376. return ret;
  377. if (IS_VALLEYVIEW(dev)) {
  378. seq_printf(m, "Display IER:\t%08x\n",
  379. I915_READ(VLV_IER));
  380. seq_printf(m, "Display IIR:\t%08x\n",
  381. I915_READ(VLV_IIR));
  382. seq_printf(m, "Display IIR_RW:\t%08x\n",
  383. I915_READ(VLV_IIR_RW));
  384. seq_printf(m, "Display IMR:\t%08x\n",
  385. I915_READ(VLV_IMR));
  386. for_each_pipe(pipe)
  387. seq_printf(m, "Pipe %c stat:\t%08x\n",
  388. pipe_name(pipe),
  389. I915_READ(PIPESTAT(pipe)));
  390. seq_printf(m, "Master IER:\t%08x\n",
  391. I915_READ(VLV_MASTER_IER));
  392. seq_printf(m, "Render IER:\t%08x\n",
  393. I915_READ(GTIER));
  394. seq_printf(m, "Render IIR:\t%08x\n",
  395. I915_READ(GTIIR));
  396. seq_printf(m, "Render IMR:\t%08x\n",
  397. I915_READ(GTIMR));
  398. seq_printf(m, "PM IER:\t\t%08x\n",
  399. I915_READ(GEN6_PMIER));
  400. seq_printf(m, "PM IIR:\t\t%08x\n",
  401. I915_READ(GEN6_PMIIR));
  402. seq_printf(m, "PM IMR:\t\t%08x\n",
  403. I915_READ(GEN6_PMIMR));
  404. seq_printf(m, "Port hotplug:\t%08x\n",
  405. I915_READ(PORT_HOTPLUG_EN));
  406. seq_printf(m, "DPFLIPSTAT:\t%08x\n",
  407. I915_READ(VLV_DPFLIPSTAT));
  408. seq_printf(m, "DPINVGTT:\t%08x\n",
  409. I915_READ(DPINVGTT));
  410. } else if (!HAS_PCH_SPLIT(dev)) {
  411. seq_printf(m, "Interrupt enable: %08x\n",
  412. I915_READ(IER));
  413. seq_printf(m, "Interrupt identity: %08x\n",
  414. I915_READ(IIR));
  415. seq_printf(m, "Interrupt mask: %08x\n",
  416. I915_READ(IMR));
  417. for_each_pipe(pipe)
  418. seq_printf(m, "Pipe %c stat: %08x\n",
  419. pipe_name(pipe),
  420. I915_READ(PIPESTAT(pipe)));
  421. } else {
  422. seq_printf(m, "North Display Interrupt enable: %08x\n",
  423. I915_READ(DEIER));
  424. seq_printf(m, "North Display Interrupt identity: %08x\n",
  425. I915_READ(DEIIR));
  426. seq_printf(m, "North Display Interrupt mask: %08x\n",
  427. I915_READ(DEIMR));
  428. seq_printf(m, "South Display Interrupt enable: %08x\n",
  429. I915_READ(SDEIER));
  430. seq_printf(m, "South Display Interrupt identity: %08x\n",
  431. I915_READ(SDEIIR));
  432. seq_printf(m, "South Display Interrupt mask: %08x\n",
  433. I915_READ(SDEIMR));
  434. seq_printf(m, "Graphics Interrupt enable: %08x\n",
  435. I915_READ(GTIER));
  436. seq_printf(m, "Graphics Interrupt identity: %08x\n",
  437. I915_READ(GTIIR));
  438. seq_printf(m, "Graphics Interrupt mask: %08x\n",
  439. I915_READ(GTIMR));
  440. }
  441. seq_printf(m, "Interrupts received: %d\n",
  442. atomic_read(&dev_priv->irq_received));
  443. for (i = 0; i < I915_NUM_RINGS; i++) {
  444. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  445. seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
  446. dev_priv->ring[i].name,
  447. I915_READ_IMR(&dev_priv->ring[i]));
  448. }
  449. i915_ring_seqno_info(m, &dev_priv->ring[i]);
  450. }
  451. mutex_unlock(&dev->struct_mutex);
  452. return 0;
  453. }
  454. static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
  455. {
  456. struct drm_info_node *node = (struct drm_info_node *) m->private;
  457. struct drm_device *dev = node->minor->dev;
  458. drm_i915_private_t *dev_priv = dev->dev_private;
  459. int i, ret;
  460. ret = mutex_lock_interruptible(&dev->struct_mutex);
  461. if (ret)
  462. return ret;
  463. seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
  464. seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
  465. for (i = 0; i < dev_priv->num_fence_regs; i++) {
  466. struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
  467. seq_printf(m, "Fence %d, pin count = %d, object = ",
  468. i, dev_priv->fence_regs[i].pin_count);
  469. if (obj == NULL)
  470. seq_printf(m, "unused");
  471. else
  472. describe_obj(m, obj);
  473. seq_printf(m, "\n");
  474. }
  475. mutex_unlock(&dev->struct_mutex);
  476. return 0;
  477. }
  478. static int i915_hws_info(struct seq_file *m, void *data)
  479. {
  480. struct drm_info_node *node = (struct drm_info_node *) m->private;
  481. struct drm_device *dev = node->minor->dev;
  482. drm_i915_private_t *dev_priv = dev->dev_private;
  483. struct intel_ring_buffer *ring;
  484. const volatile u32 __iomem *hws;
  485. int i;
  486. ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
  487. hws = (volatile u32 __iomem *)ring->status_page.page_addr;
  488. if (hws == NULL)
  489. return 0;
  490. for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
  491. seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  492. i * 4,
  493. hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
  494. }
  495. return 0;
  496. }
  497. static const char *ring_str(int ring)
  498. {
  499. switch (ring) {
  500. case RCS: return "render";
  501. case VCS: return "bsd";
  502. case BCS: return "blt";
  503. default: return "";
  504. }
  505. }
  506. static const char *pin_flag(int pinned)
  507. {
  508. if (pinned > 0)
  509. return " P";
  510. else if (pinned < 0)
  511. return " p";
  512. else
  513. return "";
  514. }
  515. static const char *tiling_flag(int tiling)
  516. {
  517. switch (tiling) {
  518. default:
  519. case I915_TILING_NONE: return "";
  520. case I915_TILING_X: return " X";
  521. case I915_TILING_Y: return " Y";
  522. }
  523. }
  524. static const char *dirty_flag(int dirty)
  525. {
  526. return dirty ? " dirty" : "";
  527. }
  528. static const char *purgeable_flag(int purgeable)
  529. {
  530. return purgeable ? " purgeable" : "";
  531. }
  532. static void print_error_buffers(struct seq_file *m,
  533. const char *name,
  534. struct drm_i915_error_buffer *err,
  535. int count)
  536. {
  537. seq_printf(m, "%s [%d]:\n", name, count);
  538. while (count--) {
  539. seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
  540. err->gtt_offset,
  541. err->size,
  542. err->read_domains,
  543. err->write_domain,
  544. err->rseqno, err->wseqno,
  545. pin_flag(err->pinned),
  546. tiling_flag(err->tiling),
  547. dirty_flag(err->dirty),
  548. purgeable_flag(err->purgeable),
  549. err->ring != -1 ? " " : "",
  550. ring_str(err->ring),
  551. cache_level_str(err->cache_level));
  552. if (err->name)
  553. seq_printf(m, " (name: %d)", err->name);
  554. if (err->fence_reg != I915_FENCE_REG_NONE)
  555. seq_printf(m, " (fence: %d)", err->fence_reg);
  556. seq_printf(m, "\n");
  557. err++;
  558. }
  559. }
  560. static void i915_ring_error_state(struct seq_file *m,
  561. struct drm_device *dev,
  562. struct drm_i915_error_state *error,
  563. unsigned ring)
  564. {
  565. BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
  566. seq_printf(m, "%s command stream:\n", ring_str(ring));
  567. seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
  568. seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
  569. seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
  570. seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
  571. seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
  572. seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
  573. if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
  574. seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
  575. seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
  576. }
  577. if (INTEL_INFO(dev)->gen >= 4)
  578. seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
  579. seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
  580. seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
  581. if (INTEL_INFO(dev)->gen >= 6) {
  582. seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
  583. seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
  584. seq_printf(m, " SYNC_0: 0x%08x\n",
  585. error->semaphore_mboxes[ring][0]);
  586. seq_printf(m, " SYNC_1: 0x%08x\n",
  587. error->semaphore_mboxes[ring][1]);
  588. }
  589. seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
  590. seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
  591. seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
  592. seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
  593. }
  594. struct i915_error_state_file_priv {
  595. struct drm_device *dev;
  596. struct drm_i915_error_state *error;
  597. };
  598. static int i915_error_state(struct seq_file *m, void *unused)
  599. {
  600. struct i915_error_state_file_priv *error_priv = m->private;
  601. struct drm_device *dev = error_priv->dev;
  602. drm_i915_private_t *dev_priv = dev->dev_private;
  603. struct drm_i915_error_state *error = error_priv->error;
  604. struct intel_ring_buffer *ring;
  605. int i, j, page, offset, elt;
  606. if (!error) {
  607. seq_printf(m, "no error state collected\n");
  608. return 0;
  609. }
  610. seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
  611. error->time.tv_usec);
  612. seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
  613. seq_printf(m, "EIR: 0x%08x\n", error->eir);
  614. seq_printf(m, "IER: 0x%08x\n", error->ier);
  615. seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  616. seq_printf(m, "CCID: 0x%08x\n", error->ccid);
  617. for (i = 0; i < dev_priv->num_fence_regs; i++)
  618. seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  619. if (INTEL_INFO(dev)->gen >= 6) {
  620. seq_printf(m, "ERROR: 0x%08x\n", error->error);
  621. seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  622. }
  623. for_each_ring(ring, dev_priv, i)
  624. i915_ring_error_state(m, dev, error, i);
  625. if (error->active_bo)
  626. print_error_buffers(m, "Active",
  627. error->active_bo,
  628. error->active_bo_count);
  629. if (error->pinned_bo)
  630. print_error_buffers(m, "Pinned",
  631. error->pinned_bo,
  632. error->pinned_bo_count);
  633. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  634. struct drm_i915_error_object *obj;
  635. if ((obj = error->ring[i].batchbuffer)) {
  636. seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
  637. dev_priv->ring[i].name,
  638. obj->gtt_offset);
  639. offset = 0;
  640. for (page = 0; page < obj->page_count; page++) {
  641. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  642. seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
  643. offset += 4;
  644. }
  645. }
  646. }
  647. if (error->ring[i].num_requests) {
  648. seq_printf(m, "%s --- %d requests\n",
  649. dev_priv->ring[i].name,
  650. error->ring[i].num_requests);
  651. for (j = 0; j < error->ring[i].num_requests; j++) {
  652. seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
  653. error->ring[i].requests[j].seqno,
  654. error->ring[i].requests[j].jiffies,
  655. error->ring[i].requests[j].tail);
  656. }
  657. }
  658. if ((obj = error->ring[i].ringbuffer)) {
  659. seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
  660. dev_priv->ring[i].name,
  661. obj->gtt_offset);
  662. offset = 0;
  663. for (page = 0; page < obj->page_count; page++) {
  664. for (elt = 0; elt < PAGE_SIZE/4; elt++) {
  665. seq_printf(m, "%08x : %08x\n",
  666. offset,
  667. obj->pages[page][elt]);
  668. offset += 4;
  669. }
  670. }
  671. }
  672. }
  673. if (error->overlay)
  674. intel_overlay_print_error_state(m, error->overlay);
  675. if (error->display)
  676. intel_display_print_error_state(m, dev, error->display);
  677. return 0;
  678. }
  679. static ssize_t
  680. i915_error_state_write(struct file *filp,
  681. const char __user *ubuf,
  682. size_t cnt,
  683. loff_t *ppos)
  684. {
  685. struct seq_file *m = filp->private_data;
  686. struct i915_error_state_file_priv *error_priv = m->private;
  687. struct drm_device *dev = error_priv->dev;
  688. int ret;
  689. DRM_DEBUG_DRIVER("Resetting error state\n");
  690. ret = mutex_lock_interruptible(&dev->struct_mutex);
  691. if (ret)
  692. return ret;
  693. i915_destroy_error_state(dev);
  694. mutex_unlock(&dev->struct_mutex);
  695. return cnt;
  696. }
  697. static int i915_error_state_open(struct inode *inode, struct file *file)
  698. {
  699. struct drm_device *dev = inode->i_private;
  700. drm_i915_private_t *dev_priv = dev->dev_private;
  701. struct i915_error_state_file_priv *error_priv;
  702. unsigned long flags;
  703. error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
  704. if (!error_priv)
  705. return -ENOMEM;
  706. error_priv->dev = dev;
  707. spin_lock_irqsave(&dev_priv->error_lock, flags);
  708. error_priv->error = dev_priv->first_error;
  709. if (error_priv->error)
  710. kref_get(&error_priv->error->ref);
  711. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  712. return single_open(file, i915_error_state, error_priv);
  713. }
  714. static int i915_error_state_release(struct inode *inode, struct file *file)
  715. {
  716. struct seq_file *m = file->private_data;
  717. struct i915_error_state_file_priv *error_priv = m->private;
  718. if (error_priv->error)
  719. kref_put(&error_priv->error->ref, i915_error_state_free);
  720. kfree(error_priv);
  721. return single_release(inode, file);
  722. }
  723. static const struct file_operations i915_error_state_fops = {
  724. .owner = THIS_MODULE,
  725. .open = i915_error_state_open,
  726. .read = seq_read,
  727. .write = i915_error_state_write,
  728. .llseek = default_llseek,
  729. .release = i915_error_state_release,
  730. };
  731. static int i915_rstdby_delays(struct seq_file *m, void *unused)
  732. {
  733. struct drm_info_node *node = (struct drm_info_node *) m->private;
  734. struct drm_device *dev = node->minor->dev;
  735. drm_i915_private_t *dev_priv = dev->dev_private;
  736. u16 crstanddelay;
  737. int ret;
  738. ret = mutex_lock_interruptible(&dev->struct_mutex);
  739. if (ret)
  740. return ret;
  741. crstanddelay = I915_READ16(CRSTANDVID);
  742. mutex_unlock(&dev->struct_mutex);
  743. seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
  744. return 0;
  745. }
  746. static int i915_cur_delayinfo(struct seq_file *m, void *unused)
  747. {
  748. struct drm_info_node *node = (struct drm_info_node *) m->private;
  749. struct drm_device *dev = node->minor->dev;
  750. drm_i915_private_t *dev_priv = dev->dev_private;
  751. int ret;
  752. if (IS_GEN5(dev)) {
  753. u16 rgvswctl = I915_READ16(MEMSWCTL);
  754. u16 rgvstat = I915_READ16(MEMSTAT_ILK);
  755. seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
  756. seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
  757. seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
  758. MEMSTAT_VID_SHIFT);
  759. seq_printf(m, "Current P-state: %d\n",
  760. (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
  761. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  762. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  763. u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
  764. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  765. u32 rpstat;
  766. u32 rpupei, rpcurup, rpprevup;
  767. u32 rpdownei, rpcurdown, rpprevdown;
  768. int max_freq;
  769. /* RPSTAT1 is in the GT power well */
  770. ret = mutex_lock_interruptible(&dev->struct_mutex);
  771. if (ret)
  772. return ret;
  773. gen6_gt_force_wake_get(dev_priv);
  774. rpstat = I915_READ(GEN6_RPSTAT1);
  775. rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
  776. rpcurup = I915_READ(GEN6_RP_CUR_UP);
  777. rpprevup = I915_READ(GEN6_RP_PREV_UP);
  778. rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
  779. rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
  780. rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
  781. gen6_gt_force_wake_put(dev_priv);
  782. mutex_unlock(&dev->struct_mutex);
  783. seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
  784. seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
  785. seq_printf(m, "Render p-state ratio: %d\n",
  786. (gt_perf_status & 0xff00) >> 8);
  787. seq_printf(m, "Render p-state VID: %d\n",
  788. gt_perf_status & 0xff);
  789. seq_printf(m, "Render p-state limit: %d\n",
  790. rp_state_limits & 0xff);
  791. seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
  792. GEN6_CAGF_SHIFT) * 50);
  793. seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
  794. GEN6_CURICONT_MASK);
  795. seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
  796. GEN6_CURBSYTAVG_MASK);
  797. seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
  798. GEN6_CURBSYTAVG_MASK);
  799. seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
  800. GEN6_CURIAVG_MASK);
  801. seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
  802. GEN6_CURBSYTAVG_MASK);
  803. seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
  804. GEN6_CURBSYTAVG_MASK);
  805. max_freq = (rp_state_cap & 0xff0000) >> 16;
  806. seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
  807. max_freq * 50);
  808. max_freq = (rp_state_cap & 0xff00) >> 8;
  809. seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
  810. max_freq * 50);
  811. max_freq = rp_state_cap & 0xff;
  812. seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
  813. max_freq * 50);
  814. } else {
  815. seq_printf(m, "no P-state info available\n");
  816. }
  817. return 0;
  818. }
  819. static int i915_delayfreq_table(struct seq_file *m, void *unused)
  820. {
  821. struct drm_info_node *node = (struct drm_info_node *) m->private;
  822. struct drm_device *dev = node->minor->dev;
  823. drm_i915_private_t *dev_priv = dev->dev_private;
  824. u32 delayfreq;
  825. int ret, i;
  826. ret = mutex_lock_interruptible(&dev->struct_mutex);
  827. if (ret)
  828. return ret;
  829. for (i = 0; i < 16; i++) {
  830. delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
  831. seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
  832. (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
  833. }
  834. mutex_unlock(&dev->struct_mutex);
  835. return 0;
  836. }
  837. static inline int MAP_TO_MV(int map)
  838. {
  839. return 1250 - (map * 25);
  840. }
  841. static int i915_inttoext_table(struct seq_file *m, void *unused)
  842. {
  843. struct drm_info_node *node = (struct drm_info_node *) m->private;
  844. struct drm_device *dev = node->minor->dev;
  845. drm_i915_private_t *dev_priv = dev->dev_private;
  846. u32 inttoext;
  847. int ret, i;
  848. ret = mutex_lock_interruptible(&dev->struct_mutex);
  849. if (ret)
  850. return ret;
  851. for (i = 1; i <= 32; i++) {
  852. inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
  853. seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
  854. }
  855. mutex_unlock(&dev->struct_mutex);
  856. return 0;
  857. }
  858. static int ironlake_drpc_info(struct seq_file *m)
  859. {
  860. struct drm_info_node *node = (struct drm_info_node *) m->private;
  861. struct drm_device *dev = node->minor->dev;
  862. drm_i915_private_t *dev_priv = dev->dev_private;
  863. u32 rgvmodectl, rstdbyctl;
  864. u16 crstandvid;
  865. int ret;
  866. ret = mutex_lock_interruptible(&dev->struct_mutex);
  867. if (ret)
  868. return ret;
  869. rgvmodectl = I915_READ(MEMMODECTL);
  870. rstdbyctl = I915_READ(RSTDBYCTL);
  871. crstandvid = I915_READ16(CRSTANDVID);
  872. mutex_unlock(&dev->struct_mutex);
  873. seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
  874. "yes" : "no");
  875. seq_printf(m, "Boost freq: %d\n",
  876. (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
  877. MEMMODE_BOOST_FREQ_SHIFT);
  878. seq_printf(m, "HW control enabled: %s\n",
  879. rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
  880. seq_printf(m, "SW control enabled: %s\n",
  881. rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
  882. seq_printf(m, "Gated voltage change: %s\n",
  883. rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
  884. seq_printf(m, "Starting frequency: P%d\n",
  885. (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
  886. seq_printf(m, "Max P-state: P%d\n",
  887. (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
  888. seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
  889. seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
  890. seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
  891. seq_printf(m, "Render standby enabled: %s\n",
  892. (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
  893. seq_printf(m, "Current RS state: ");
  894. switch (rstdbyctl & RSX_STATUS_MASK) {
  895. case RSX_STATUS_ON:
  896. seq_printf(m, "on\n");
  897. break;
  898. case RSX_STATUS_RC1:
  899. seq_printf(m, "RC1\n");
  900. break;
  901. case RSX_STATUS_RC1E:
  902. seq_printf(m, "RC1E\n");
  903. break;
  904. case RSX_STATUS_RS1:
  905. seq_printf(m, "RS1\n");
  906. break;
  907. case RSX_STATUS_RS2:
  908. seq_printf(m, "RS2 (RC6)\n");
  909. break;
  910. case RSX_STATUS_RS3:
  911. seq_printf(m, "RC3 (RC6+)\n");
  912. break;
  913. default:
  914. seq_printf(m, "unknown\n");
  915. break;
  916. }
  917. return 0;
  918. }
  919. static int gen6_drpc_info(struct seq_file *m)
  920. {
  921. struct drm_info_node *node = (struct drm_info_node *) m->private;
  922. struct drm_device *dev = node->minor->dev;
  923. struct drm_i915_private *dev_priv = dev->dev_private;
  924. u32 rpmodectl1, gt_core_status, rcctl1;
  925. unsigned forcewake_count;
  926. int count=0, ret;
  927. ret = mutex_lock_interruptible(&dev->struct_mutex);
  928. if (ret)
  929. return ret;
  930. spin_lock_irq(&dev_priv->gt_lock);
  931. forcewake_count = dev_priv->forcewake_count;
  932. spin_unlock_irq(&dev_priv->gt_lock);
  933. if (forcewake_count) {
  934. seq_printf(m, "RC information inaccurate because somebody "
  935. "holds a forcewake reference \n");
  936. } else {
  937. /* NB: we cannot use forcewake, else we read the wrong values */
  938. while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  939. udelay(10);
  940. seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
  941. }
  942. gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
  943. trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
  944. rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
  945. rcctl1 = I915_READ(GEN6_RC_CONTROL);
  946. mutex_unlock(&dev->struct_mutex);
  947. seq_printf(m, "Video Turbo Mode: %s\n",
  948. yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
  949. seq_printf(m, "HW control enabled: %s\n",
  950. yesno(rpmodectl1 & GEN6_RP_ENABLE));
  951. seq_printf(m, "SW control enabled: %s\n",
  952. yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
  953. GEN6_RP_MEDIA_SW_MODE));
  954. seq_printf(m, "RC1e Enabled: %s\n",
  955. yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
  956. seq_printf(m, "RC6 Enabled: %s\n",
  957. yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
  958. seq_printf(m, "Deep RC6 Enabled: %s\n",
  959. yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
  960. seq_printf(m, "Deepest RC6 Enabled: %s\n",
  961. yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
  962. seq_printf(m, "Current RC state: ");
  963. switch (gt_core_status & GEN6_RCn_MASK) {
  964. case GEN6_RC0:
  965. if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
  966. seq_printf(m, "Core Power Down\n");
  967. else
  968. seq_printf(m, "on\n");
  969. break;
  970. case GEN6_RC3:
  971. seq_printf(m, "RC3\n");
  972. break;
  973. case GEN6_RC6:
  974. seq_printf(m, "RC6\n");
  975. break;
  976. case GEN6_RC7:
  977. seq_printf(m, "RC7\n");
  978. break;
  979. default:
  980. seq_printf(m, "Unknown\n");
  981. break;
  982. }
  983. seq_printf(m, "Core Power Down: %s\n",
  984. yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
  985. /* Not exactly sure what this is */
  986. seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
  987. I915_READ(GEN6_GT_GFX_RC6_LOCKED));
  988. seq_printf(m, "RC6 residency since boot: %u\n",
  989. I915_READ(GEN6_GT_GFX_RC6));
  990. seq_printf(m, "RC6+ residency since boot: %u\n",
  991. I915_READ(GEN6_GT_GFX_RC6p));
  992. seq_printf(m, "RC6++ residency since boot: %u\n",
  993. I915_READ(GEN6_GT_GFX_RC6pp));
  994. return 0;
  995. }
  996. static int i915_drpc_info(struct seq_file *m, void *unused)
  997. {
  998. struct drm_info_node *node = (struct drm_info_node *) m->private;
  999. struct drm_device *dev = node->minor->dev;
  1000. if (IS_GEN6(dev) || IS_GEN7(dev))
  1001. return gen6_drpc_info(m);
  1002. else
  1003. return ironlake_drpc_info(m);
  1004. }
  1005. static int i915_fbc_status(struct seq_file *m, void *unused)
  1006. {
  1007. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1008. struct drm_device *dev = node->minor->dev;
  1009. drm_i915_private_t *dev_priv = dev->dev_private;
  1010. if (!I915_HAS_FBC(dev)) {
  1011. seq_printf(m, "FBC unsupported on this chipset\n");
  1012. return 0;
  1013. }
  1014. if (intel_fbc_enabled(dev)) {
  1015. seq_printf(m, "FBC enabled\n");
  1016. } else {
  1017. seq_printf(m, "FBC disabled: ");
  1018. switch (dev_priv->no_fbc_reason) {
  1019. case FBC_NO_OUTPUT:
  1020. seq_printf(m, "no outputs");
  1021. break;
  1022. case FBC_STOLEN_TOO_SMALL:
  1023. seq_printf(m, "not enough stolen memory");
  1024. break;
  1025. case FBC_UNSUPPORTED_MODE:
  1026. seq_printf(m, "mode not supported");
  1027. break;
  1028. case FBC_MODE_TOO_LARGE:
  1029. seq_printf(m, "mode too large");
  1030. break;
  1031. case FBC_BAD_PLANE:
  1032. seq_printf(m, "FBC unsupported on plane");
  1033. break;
  1034. case FBC_NOT_TILED:
  1035. seq_printf(m, "scanout buffer not tiled");
  1036. break;
  1037. case FBC_MULTIPLE_PIPES:
  1038. seq_printf(m, "multiple pipes are enabled");
  1039. break;
  1040. case FBC_MODULE_PARAM:
  1041. seq_printf(m, "disabled per module param (default off)");
  1042. break;
  1043. default:
  1044. seq_printf(m, "unknown reason");
  1045. }
  1046. seq_printf(m, "\n");
  1047. }
  1048. return 0;
  1049. }
  1050. static int i915_sr_status(struct seq_file *m, void *unused)
  1051. {
  1052. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1053. struct drm_device *dev = node->minor->dev;
  1054. drm_i915_private_t *dev_priv = dev->dev_private;
  1055. bool sr_enabled = false;
  1056. if (HAS_PCH_SPLIT(dev))
  1057. sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
  1058. else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
  1059. sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
  1060. else if (IS_I915GM(dev))
  1061. sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
  1062. else if (IS_PINEVIEW(dev))
  1063. sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
  1064. seq_printf(m, "self-refresh: %s\n",
  1065. sr_enabled ? "enabled" : "disabled");
  1066. return 0;
  1067. }
  1068. static int i915_emon_status(struct seq_file *m, void *unused)
  1069. {
  1070. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1071. struct drm_device *dev = node->minor->dev;
  1072. drm_i915_private_t *dev_priv = dev->dev_private;
  1073. unsigned long temp, chipset, gfx;
  1074. int ret;
  1075. if (!IS_GEN5(dev))
  1076. return -ENODEV;
  1077. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1078. if (ret)
  1079. return ret;
  1080. temp = i915_mch_val(dev_priv);
  1081. chipset = i915_chipset_val(dev_priv);
  1082. gfx = i915_gfx_val(dev_priv);
  1083. mutex_unlock(&dev->struct_mutex);
  1084. seq_printf(m, "GMCH temp: %ld\n", temp);
  1085. seq_printf(m, "Chipset power: %ld\n", chipset);
  1086. seq_printf(m, "GFX power: %ld\n", gfx);
  1087. seq_printf(m, "Total power: %ld\n", chipset + gfx);
  1088. return 0;
  1089. }
  1090. static int i915_ring_freq_table(struct seq_file *m, void *unused)
  1091. {
  1092. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1093. struct drm_device *dev = node->minor->dev;
  1094. drm_i915_private_t *dev_priv = dev->dev_private;
  1095. int ret;
  1096. int gpu_freq, ia_freq;
  1097. if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
  1098. seq_printf(m, "unsupported on this chipset\n");
  1099. return 0;
  1100. }
  1101. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1102. if (ret)
  1103. return ret;
  1104. seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
  1105. for (gpu_freq = dev_priv->rps.min_delay;
  1106. gpu_freq <= dev_priv->rps.max_delay;
  1107. gpu_freq++) {
  1108. I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
  1109. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  1110. GEN6_PCODE_READ_MIN_FREQ_TABLE);
  1111. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  1112. GEN6_PCODE_READY) == 0, 10)) {
  1113. DRM_ERROR("pcode read of freq table timed out\n");
  1114. continue;
  1115. }
  1116. ia_freq = I915_READ(GEN6_PCODE_DATA);
  1117. seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
  1118. }
  1119. mutex_unlock(&dev->struct_mutex);
  1120. return 0;
  1121. }
  1122. static int i915_gfxec(struct seq_file *m, void *unused)
  1123. {
  1124. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1125. struct drm_device *dev = node->minor->dev;
  1126. drm_i915_private_t *dev_priv = dev->dev_private;
  1127. int ret;
  1128. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1129. if (ret)
  1130. return ret;
  1131. seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
  1132. mutex_unlock(&dev->struct_mutex);
  1133. return 0;
  1134. }
  1135. static int i915_opregion(struct seq_file *m, void *unused)
  1136. {
  1137. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1138. struct drm_device *dev = node->minor->dev;
  1139. drm_i915_private_t *dev_priv = dev->dev_private;
  1140. struct intel_opregion *opregion = &dev_priv->opregion;
  1141. void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
  1142. int ret;
  1143. if (data == NULL)
  1144. return -ENOMEM;
  1145. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1146. if (ret)
  1147. goto out;
  1148. if (opregion->header) {
  1149. memcpy_fromio(data, opregion->header, OPREGION_SIZE);
  1150. seq_write(m, data, OPREGION_SIZE);
  1151. }
  1152. mutex_unlock(&dev->struct_mutex);
  1153. out:
  1154. kfree(data);
  1155. return 0;
  1156. }
  1157. static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
  1158. {
  1159. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1160. struct drm_device *dev = node->minor->dev;
  1161. drm_i915_private_t *dev_priv = dev->dev_private;
  1162. struct intel_fbdev *ifbdev;
  1163. struct intel_framebuffer *fb;
  1164. int ret;
  1165. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1166. if (ret)
  1167. return ret;
  1168. ifbdev = dev_priv->fbdev;
  1169. fb = to_intel_framebuffer(ifbdev->helper.fb);
  1170. seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
  1171. fb->base.width,
  1172. fb->base.height,
  1173. fb->base.depth,
  1174. fb->base.bits_per_pixel);
  1175. describe_obj(m, fb->obj);
  1176. seq_printf(m, "\n");
  1177. list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
  1178. if (&fb->base == ifbdev->helper.fb)
  1179. continue;
  1180. seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
  1181. fb->base.width,
  1182. fb->base.height,
  1183. fb->base.depth,
  1184. fb->base.bits_per_pixel);
  1185. describe_obj(m, fb->obj);
  1186. seq_printf(m, "\n");
  1187. }
  1188. mutex_unlock(&dev->mode_config.mutex);
  1189. return 0;
  1190. }
  1191. static int i915_context_status(struct seq_file *m, void *unused)
  1192. {
  1193. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1194. struct drm_device *dev = node->minor->dev;
  1195. drm_i915_private_t *dev_priv = dev->dev_private;
  1196. int ret;
  1197. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1198. if (ret)
  1199. return ret;
  1200. if (dev_priv->pwrctx) {
  1201. seq_printf(m, "power context ");
  1202. describe_obj(m, dev_priv->pwrctx);
  1203. seq_printf(m, "\n");
  1204. }
  1205. if (dev_priv->renderctx) {
  1206. seq_printf(m, "render context ");
  1207. describe_obj(m, dev_priv->renderctx);
  1208. seq_printf(m, "\n");
  1209. }
  1210. mutex_unlock(&dev->mode_config.mutex);
  1211. return 0;
  1212. }
  1213. static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
  1214. {
  1215. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1216. struct drm_device *dev = node->minor->dev;
  1217. struct drm_i915_private *dev_priv = dev->dev_private;
  1218. unsigned forcewake_count;
  1219. spin_lock_irq(&dev_priv->gt_lock);
  1220. forcewake_count = dev_priv->forcewake_count;
  1221. spin_unlock_irq(&dev_priv->gt_lock);
  1222. seq_printf(m, "forcewake count = %u\n", forcewake_count);
  1223. return 0;
  1224. }
  1225. static const char *swizzle_string(unsigned swizzle)
  1226. {
  1227. switch(swizzle) {
  1228. case I915_BIT_6_SWIZZLE_NONE:
  1229. return "none";
  1230. case I915_BIT_6_SWIZZLE_9:
  1231. return "bit9";
  1232. case I915_BIT_6_SWIZZLE_9_10:
  1233. return "bit9/bit10";
  1234. case I915_BIT_6_SWIZZLE_9_11:
  1235. return "bit9/bit11";
  1236. case I915_BIT_6_SWIZZLE_9_10_11:
  1237. return "bit9/bit10/bit11";
  1238. case I915_BIT_6_SWIZZLE_9_17:
  1239. return "bit9/bit17";
  1240. case I915_BIT_6_SWIZZLE_9_10_17:
  1241. return "bit9/bit10/bit17";
  1242. case I915_BIT_6_SWIZZLE_UNKNOWN:
  1243. return "unkown";
  1244. }
  1245. return "bug";
  1246. }
  1247. static int i915_swizzle_info(struct seq_file *m, void *data)
  1248. {
  1249. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1250. struct drm_device *dev = node->minor->dev;
  1251. struct drm_i915_private *dev_priv = dev->dev_private;
  1252. int ret;
  1253. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1254. if (ret)
  1255. return ret;
  1256. seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
  1257. swizzle_string(dev_priv->mm.bit_6_swizzle_x));
  1258. seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
  1259. swizzle_string(dev_priv->mm.bit_6_swizzle_y));
  1260. if (IS_GEN3(dev) || IS_GEN4(dev)) {
  1261. seq_printf(m, "DDC = 0x%08x\n",
  1262. I915_READ(DCC));
  1263. seq_printf(m, "C0DRB3 = 0x%04x\n",
  1264. I915_READ16(C0DRB3));
  1265. seq_printf(m, "C1DRB3 = 0x%04x\n",
  1266. I915_READ16(C1DRB3));
  1267. } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
  1268. seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
  1269. I915_READ(MAD_DIMM_C0));
  1270. seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
  1271. I915_READ(MAD_DIMM_C1));
  1272. seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
  1273. I915_READ(MAD_DIMM_C2));
  1274. seq_printf(m, "TILECTL = 0x%08x\n",
  1275. I915_READ(TILECTL));
  1276. seq_printf(m, "ARB_MODE = 0x%08x\n",
  1277. I915_READ(ARB_MODE));
  1278. seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
  1279. I915_READ(DISP_ARB_CTL));
  1280. }
  1281. mutex_unlock(&dev->struct_mutex);
  1282. return 0;
  1283. }
  1284. static int i915_ppgtt_info(struct seq_file *m, void *data)
  1285. {
  1286. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1287. struct drm_device *dev = node->minor->dev;
  1288. struct drm_i915_private *dev_priv = dev->dev_private;
  1289. struct intel_ring_buffer *ring;
  1290. int i, ret;
  1291. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1292. if (ret)
  1293. return ret;
  1294. if (INTEL_INFO(dev)->gen == 6)
  1295. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
  1296. for (i = 0; i < I915_NUM_RINGS; i++) {
  1297. ring = &dev_priv->ring[i];
  1298. seq_printf(m, "%s\n", ring->name);
  1299. if (INTEL_INFO(dev)->gen == 7)
  1300. seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
  1301. seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
  1302. seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
  1303. seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
  1304. }
  1305. if (dev_priv->mm.aliasing_ppgtt) {
  1306. struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  1307. seq_printf(m, "aliasing PPGTT:\n");
  1308. seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
  1309. }
  1310. seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
  1311. mutex_unlock(&dev->struct_mutex);
  1312. return 0;
  1313. }
  1314. static int i915_dpio_info(struct seq_file *m, void *data)
  1315. {
  1316. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1317. struct drm_device *dev = node->minor->dev;
  1318. struct drm_i915_private *dev_priv = dev->dev_private;
  1319. int ret;
  1320. if (!IS_VALLEYVIEW(dev)) {
  1321. seq_printf(m, "unsupported\n");
  1322. return 0;
  1323. }
  1324. ret = mutex_lock_interruptible(&dev->mode_config.mutex);
  1325. if (ret)
  1326. return ret;
  1327. seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
  1328. seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
  1329. intel_dpio_read(dev_priv, _DPIO_DIV_A));
  1330. seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
  1331. intel_dpio_read(dev_priv, _DPIO_DIV_B));
  1332. seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
  1333. intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
  1334. seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
  1335. intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
  1336. seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
  1337. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
  1338. seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
  1339. intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
  1340. seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
  1341. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
  1342. seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
  1343. intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
  1344. seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
  1345. intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
  1346. mutex_unlock(&dev->mode_config.mutex);
  1347. return 0;
  1348. }
  1349. static ssize_t
  1350. i915_wedged_read(struct file *filp,
  1351. char __user *ubuf,
  1352. size_t max,
  1353. loff_t *ppos)
  1354. {
  1355. struct drm_device *dev = filp->private_data;
  1356. drm_i915_private_t *dev_priv = dev->dev_private;
  1357. char buf[80];
  1358. int len;
  1359. len = snprintf(buf, sizeof(buf),
  1360. "wedged : %d\n",
  1361. atomic_read(&dev_priv->mm.wedged));
  1362. if (len > sizeof(buf))
  1363. len = sizeof(buf);
  1364. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1365. }
  1366. static ssize_t
  1367. i915_wedged_write(struct file *filp,
  1368. const char __user *ubuf,
  1369. size_t cnt,
  1370. loff_t *ppos)
  1371. {
  1372. struct drm_device *dev = filp->private_data;
  1373. char buf[20];
  1374. int val = 1;
  1375. if (cnt > 0) {
  1376. if (cnt > sizeof(buf) - 1)
  1377. return -EINVAL;
  1378. if (copy_from_user(buf, ubuf, cnt))
  1379. return -EFAULT;
  1380. buf[cnt] = 0;
  1381. val = simple_strtoul(buf, NULL, 0);
  1382. }
  1383. DRM_INFO("Manually setting wedged to %d\n", val);
  1384. i915_handle_error(dev, val);
  1385. return cnt;
  1386. }
  1387. static const struct file_operations i915_wedged_fops = {
  1388. .owner = THIS_MODULE,
  1389. .open = simple_open,
  1390. .read = i915_wedged_read,
  1391. .write = i915_wedged_write,
  1392. .llseek = default_llseek,
  1393. };
  1394. static ssize_t
  1395. i915_ring_stop_read(struct file *filp,
  1396. char __user *ubuf,
  1397. size_t max,
  1398. loff_t *ppos)
  1399. {
  1400. struct drm_device *dev = filp->private_data;
  1401. drm_i915_private_t *dev_priv = dev->dev_private;
  1402. char buf[20];
  1403. int len;
  1404. len = snprintf(buf, sizeof(buf),
  1405. "0x%08x\n", dev_priv->stop_rings);
  1406. if (len > sizeof(buf))
  1407. len = sizeof(buf);
  1408. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1409. }
  1410. static ssize_t
  1411. i915_ring_stop_write(struct file *filp,
  1412. const char __user *ubuf,
  1413. size_t cnt,
  1414. loff_t *ppos)
  1415. {
  1416. struct drm_device *dev = filp->private_data;
  1417. struct drm_i915_private *dev_priv = dev->dev_private;
  1418. char buf[20];
  1419. int val = 0, ret;
  1420. if (cnt > 0) {
  1421. if (cnt > sizeof(buf) - 1)
  1422. return -EINVAL;
  1423. if (copy_from_user(buf, ubuf, cnt))
  1424. return -EFAULT;
  1425. buf[cnt] = 0;
  1426. val = simple_strtoul(buf, NULL, 0);
  1427. }
  1428. DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
  1429. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1430. if (ret)
  1431. return ret;
  1432. dev_priv->stop_rings = val;
  1433. mutex_unlock(&dev->struct_mutex);
  1434. return cnt;
  1435. }
  1436. static const struct file_operations i915_ring_stop_fops = {
  1437. .owner = THIS_MODULE,
  1438. .open = simple_open,
  1439. .read = i915_ring_stop_read,
  1440. .write = i915_ring_stop_write,
  1441. .llseek = default_llseek,
  1442. };
  1443. static ssize_t
  1444. i915_max_freq_read(struct file *filp,
  1445. char __user *ubuf,
  1446. size_t max,
  1447. loff_t *ppos)
  1448. {
  1449. struct drm_device *dev = filp->private_data;
  1450. drm_i915_private_t *dev_priv = dev->dev_private;
  1451. char buf[80];
  1452. int len, ret;
  1453. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1454. return -ENODEV;
  1455. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1456. if (ret)
  1457. return ret;
  1458. len = snprintf(buf, sizeof(buf),
  1459. "max freq: %d\n", dev_priv->rps.max_delay * 50);
  1460. mutex_unlock(&dev->struct_mutex);
  1461. if (len > sizeof(buf))
  1462. len = sizeof(buf);
  1463. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1464. }
  1465. static ssize_t
  1466. i915_max_freq_write(struct file *filp,
  1467. const char __user *ubuf,
  1468. size_t cnt,
  1469. loff_t *ppos)
  1470. {
  1471. struct drm_device *dev = filp->private_data;
  1472. struct drm_i915_private *dev_priv = dev->dev_private;
  1473. char buf[20];
  1474. int val = 1, ret;
  1475. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1476. return -ENODEV;
  1477. if (cnt > 0) {
  1478. if (cnt > sizeof(buf) - 1)
  1479. return -EINVAL;
  1480. if (copy_from_user(buf, ubuf, cnt))
  1481. return -EFAULT;
  1482. buf[cnt] = 0;
  1483. val = simple_strtoul(buf, NULL, 0);
  1484. }
  1485. DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
  1486. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1487. if (ret)
  1488. return ret;
  1489. /*
  1490. * Turbo will still be enabled, but won't go above the set value.
  1491. */
  1492. dev_priv->rps.max_delay = val / 50;
  1493. gen6_set_rps(dev, val / 50);
  1494. mutex_unlock(&dev->struct_mutex);
  1495. return cnt;
  1496. }
  1497. static const struct file_operations i915_max_freq_fops = {
  1498. .owner = THIS_MODULE,
  1499. .open = simple_open,
  1500. .read = i915_max_freq_read,
  1501. .write = i915_max_freq_write,
  1502. .llseek = default_llseek,
  1503. };
  1504. static ssize_t
  1505. i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
  1506. loff_t *ppos)
  1507. {
  1508. struct drm_device *dev = filp->private_data;
  1509. drm_i915_private_t *dev_priv = dev->dev_private;
  1510. char buf[80];
  1511. int len, ret;
  1512. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1513. return -ENODEV;
  1514. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1515. if (ret)
  1516. return ret;
  1517. len = snprintf(buf, sizeof(buf),
  1518. "min freq: %d\n", dev_priv->rps.min_delay * 50);
  1519. mutex_unlock(&dev->struct_mutex);
  1520. if (len > sizeof(buf))
  1521. len = sizeof(buf);
  1522. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1523. }
  1524. static ssize_t
  1525. i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
  1526. loff_t *ppos)
  1527. {
  1528. struct drm_device *dev = filp->private_data;
  1529. struct drm_i915_private *dev_priv = dev->dev_private;
  1530. char buf[20];
  1531. int val = 1, ret;
  1532. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1533. return -ENODEV;
  1534. if (cnt > 0) {
  1535. if (cnt > sizeof(buf) - 1)
  1536. return -EINVAL;
  1537. if (copy_from_user(buf, ubuf, cnt))
  1538. return -EFAULT;
  1539. buf[cnt] = 0;
  1540. val = simple_strtoul(buf, NULL, 0);
  1541. }
  1542. DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
  1543. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1544. if (ret)
  1545. return ret;
  1546. /*
  1547. * Turbo will still be enabled, but won't go below the set value.
  1548. */
  1549. dev_priv->rps.min_delay = val / 50;
  1550. gen6_set_rps(dev, val / 50);
  1551. mutex_unlock(&dev->struct_mutex);
  1552. return cnt;
  1553. }
  1554. static const struct file_operations i915_min_freq_fops = {
  1555. .owner = THIS_MODULE,
  1556. .open = simple_open,
  1557. .read = i915_min_freq_read,
  1558. .write = i915_min_freq_write,
  1559. .llseek = default_llseek,
  1560. };
  1561. static ssize_t
  1562. i915_cache_sharing_read(struct file *filp,
  1563. char __user *ubuf,
  1564. size_t max,
  1565. loff_t *ppos)
  1566. {
  1567. struct drm_device *dev = filp->private_data;
  1568. drm_i915_private_t *dev_priv = dev->dev_private;
  1569. char buf[80];
  1570. u32 snpcr;
  1571. int len, ret;
  1572. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1573. return -ENODEV;
  1574. ret = mutex_lock_interruptible(&dev->struct_mutex);
  1575. if (ret)
  1576. return ret;
  1577. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1578. mutex_unlock(&dev_priv->dev->struct_mutex);
  1579. len = snprintf(buf, sizeof(buf),
  1580. "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
  1581. GEN6_MBC_SNPCR_SHIFT);
  1582. if (len > sizeof(buf))
  1583. len = sizeof(buf);
  1584. return simple_read_from_buffer(ubuf, max, ppos, buf, len);
  1585. }
  1586. static ssize_t
  1587. i915_cache_sharing_write(struct file *filp,
  1588. const char __user *ubuf,
  1589. size_t cnt,
  1590. loff_t *ppos)
  1591. {
  1592. struct drm_device *dev = filp->private_data;
  1593. struct drm_i915_private *dev_priv = dev->dev_private;
  1594. char buf[20];
  1595. u32 snpcr;
  1596. int val = 1;
  1597. if (!(IS_GEN6(dev) || IS_GEN7(dev)))
  1598. return -ENODEV;
  1599. if (cnt > 0) {
  1600. if (cnt > sizeof(buf) - 1)
  1601. return -EINVAL;
  1602. if (copy_from_user(buf, ubuf, cnt))
  1603. return -EFAULT;
  1604. buf[cnt] = 0;
  1605. val = simple_strtoul(buf, NULL, 0);
  1606. }
  1607. if (val < 0 || val > 3)
  1608. return -EINVAL;
  1609. DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
  1610. /* Update the cache sharing policy here as well */
  1611. snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
  1612. snpcr &= ~GEN6_MBC_SNPCR_MASK;
  1613. snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
  1614. I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
  1615. return cnt;
  1616. }
  1617. static const struct file_operations i915_cache_sharing_fops = {
  1618. .owner = THIS_MODULE,
  1619. .open = simple_open,
  1620. .read = i915_cache_sharing_read,
  1621. .write = i915_cache_sharing_write,
  1622. .llseek = default_llseek,
  1623. };
  1624. /* As the drm_debugfs_init() routines are called before dev->dev_private is
  1625. * allocated we need to hook into the minor for release. */
  1626. static int
  1627. drm_add_fake_info_node(struct drm_minor *minor,
  1628. struct dentry *ent,
  1629. const void *key)
  1630. {
  1631. struct drm_info_node *node;
  1632. node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
  1633. if (node == NULL) {
  1634. debugfs_remove(ent);
  1635. return -ENOMEM;
  1636. }
  1637. node->minor = minor;
  1638. node->dent = ent;
  1639. node->info_ent = (void *) key;
  1640. mutex_lock(&minor->debugfs_lock);
  1641. list_add(&node->list, &minor->debugfs_list);
  1642. mutex_unlock(&minor->debugfs_lock);
  1643. return 0;
  1644. }
  1645. static int i915_forcewake_open(struct inode *inode, struct file *file)
  1646. {
  1647. struct drm_device *dev = inode->i_private;
  1648. struct drm_i915_private *dev_priv = dev->dev_private;
  1649. if (INTEL_INFO(dev)->gen < 6)
  1650. return 0;
  1651. gen6_gt_force_wake_get(dev_priv);
  1652. return 0;
  1653. }
  1654. static int i915_forcewake_release(struct inode *inode, struct file *file)
  1655. {
  1656. struct drm_device *dev = inode->i_private;
  1657. struct drm_i915_private *dev_priv = dev->dev_private;
  1658. if (INTEL_INFO(dev)->gen < 6)
  1659. return 0;
  1660. gen6_gt_force_wake_put(dev_priv);
  1661. return 0;
  1662. }
  1663. static const struct file_operations i915_forcewake_fops = {
  1664. .owner = THIS_MODULE,
  1665. .open = i915_forcewake_open,
  1666. .release = i915_forcewake_release,
  1667. };
  1668. static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
  1669. {
  1670. struct drm_device *dev = minor->dev;
  1671. struct dentry *ent;
  1672. ent = debugfs_create_file("i915_forcewake_user",
  1673. S_IRUSR,
  1674. root, dev,
  1675. &i915_forcewake_fops);
  1676. if (IS_ERR(ent))
  1677. return PTR_ERR(ent);
  1678. return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
  1679. }
  1680. static int i915_debugfs_create(struct dentry *root,
  1681. struct drm_minor *minor,
  1682. const char *name,
  1683. const struct file_operations *fops)
  1684. {
  1685. struct drm_device *dev = minor->dev;
  1686. struct dentry *ent;
  1687. ent = debugfs_create_file(name,
  1688. S_IRUGO | S_IWUSR,
  1689. root, dev,
  1690. fops);
  1691. if (IS_ERR(ent))
  1692. return PTR_ERR(ent);
  1693. return drm_add_fake_info_node(minor, ent, fops);
  1694. }
  1695. static struct drm_info_list i915_debugfs_list[] = {
  1696. {"i915_capabilities", i915_capabilities, 0},
  1697. {"i915_gem_objects", i915_gem_object_info, 0},
  1698. {"i915_gem_gtt", i915_gem_gtt_info, 0},
  1699. {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
  1700. {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
  1701. {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
  1702. {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
  1703. {"i915_gem_request", i915_gem_request_info, 0},
  1704. {"i915_gem_seqno", i915_gem_seqno_info, 0},
  1705. {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
  1706. {"i915_gem_interrupt", i915_interrupt_info, 0},
  1707. {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
  1708. {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
  1709. {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
  1710. {"i915_rstdby_delays", i915_rstdby_delays, 0},
  1711. {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
  1712. {"i915_delayfreq_table", i915_delayfreq_table, 0},
  1713. {"i915_inttoext_table", i915_inttoext_table, 0},
  1714. {"i915_drpc_info", i915_drpc_info, 0},
  1715. {"i915_emon_status", i915_emon_status, 0},
  1716. {"i915_ring_freq_table", i915_ring_freq_table, 0},
  1717. {"i915_gfxec", i915_gfxec, 0},
  1718. {"i915_fbc_status", i915_fbc_status, 0},
  1719. {"i915_sr_status", i915_sr_status, 0},
  1720. {"i915_opregion", i915_opregion, 0},
  1721. {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
  1722. {"i915_context_status", i915_context_status, 0},
  1723. {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
  1724. {"i915_swizzle_info", i915_swizzle_info, 0},
  1725. {"i915_ppgtt_info", i915_ppgtt_info, 0},
  1726. {"i915_dpio", i915_dpio_info, 0},
  1727. };
  1728. #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
  1729. int i915_debugfs_init(struct drm_minor *minor)
  1730. {
  1731. int ret;
  1732. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1733. "i915_wedged",
  1734. &i915_wedged_fops);
  1735. if (ret)
  1736. return ret;
  1737. ret = i915_forcewake_create(minor->debugfs_root, minor);
  1738. if (ret)
  1739. return ret;
  1740. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1741. "i915_max_freq",
  1742. &i915_max_freq_fops);
  1743. if (ret)
  1744. return ret;
  1745. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1746. "i915_min_freq",
  1747. &i915_min_freq_fops);
  1748. if (ret)
  1749. return ret;
  1750. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1751. "i915_cache_sharing",
  1752. &i915_cache_sharing_fops);
  1753. if (ret)
  1754. return ret;
  1755. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1756. "i915_ring_stop",
  1757. &i915_ring_stop_fops);
  1758. if (ret)
  1759. return ret;
  1760. ret = i915_debugfs_create(minor->debugfs_root, minor,
  1761. "i915_error_state",
  1762. &i915_error_state_fops);
  1763. if (ret)
  1764. return ret;
  1765. return drm_debugfs_create_files(i915_debugfs_list,
  1766. I915_DEBUGFS_ENTRIES,
  1767. minor->debugfs_root, minor);
  1768. }
  1769. void i915_debugfs_cleanup(struct drm_minor *minor)
  1770. {
  1771. drm_debugfs_remove_files(i915_debugfs_list,
  1772. I915_DEBUGFS_ENTRIES, minor);
  1773. drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
  1774. 1, minor);
  1775. drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
  1776. 1, minor);
  1777. drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
  1778. 1, minor);
  1779. drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
  1780. 1, minor);
  1781. drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
  1782. 1, minor);
  1783. drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
  1784. 1, minor);
  1785. drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
  1786. 1, minor);
  1787. }
  1788. #endif /* CONFIG_DEBUG_FS */