mv643xx_eth.c 65 KB

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  1. /*
  2. * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
  3. * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
  4. *
  5. * Based on the 64360 driver from:
  6. * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
  7. * Rabeeh Khoury <rabeeh@marvell.com>
  8. *
  9. * Copyright (C) 2003 PMC-Sierra, Inc.,
  10. * written by Manish Lachwani
  11. *
  12. * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
  13. *
  14. * Copyright (C) 2004-2006 MontaVista Software, Inc.
  15. * Dale Farnsworth <dale@farnsworth.org>
  16. *
  17. * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
  18. * <sjhill@realitydiluted.com>
  19. *
  20. * Copyright (C) 2007-2008 Marvell Semiconductor
  21. * Lennert Buytenhek <buytenh@marvell.com>
  22. *
  23. * This program is free software; you can redistribute it and/or
  24. * modify it under the terms of the GNU General Public License
  25. * as published by the Free Software Foundation; either version 2
  26. * of the License, or (at your option) any later version.
  27. *
  28. * This program is distributed in the hope that it will be useful,
  29. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. * GNU General Public License for more details.
  32. *
  33. * You should have received a copy of the GNU General Public License
  34. * along with this program; if not, write to the Free Software
  35. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  36. */
  37. #include <linux/init.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/in.h>
  40. #include <linux/ip.h>
  41. #include <linux/tcp.h>
  42. #include <linux/udp.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/delay.h>
  45. #include <linux/ethtool.h>
  46. #include <linux/platform_device.h>
  47. #include <linux/module.h>
  48. #include <linux/kernel.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/workqueue.h>
  51. #include <linux/phy.h>
  52. #include <linux/mv643xx_eth.h>
  53. #include <linux/io.h>
  54. #include <linux/types.h>
  55. #include <asm/system.h>
  56. static char mv643xx_eth_driver_name[] = "mv643xx_eth";
  57. static char mv643xx_eth_driver_version[] = "1.4";
  58. /*
  59. * Registers shared between all ports.
  60. */
  61. #define PHY_ADDR 0x0000
  62. #define SMI_REG 0x0004
  63. #define SMI_BUSY 0x10000000
  64. #define SMI_READ_VALID 0x08000000
  65. #define SMI_OPCODE_READ 0x04000000
  66. #define SMI_OPCODE_WRITE 0x00000000
  67. #define ERR_INT_CAUSE 0x0080
  68. #define ERR_INT_SMI_DONE 0x00000010
  69. #define ERR_INT_MASK 0x0084
  70. #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
  71. #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
  72. #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
  73. #define WINDOW_BAR_ENABLE 0x0290
  74. #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
  75. /*
  76. * Main per-port registers. These live at offset 0x0400 for
  77. * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
  78. */
  79. #define PORT_CONFIG 0x0000
  80. #define UNICAST_PROMISCUOUS_MODE 0x00000001
  81. #define PORT_CONFIG_EXT 0x0004
  82. #define MAC_ADDR_LOW 0x0014
  83. #define MAC_ADDR_HIGH 0x0018
  84. #define SDMA_CONFIG 0x001c
  85. #define PORT_SERIAL_CONTROL 0x003c
  86. #define PORT_STATUS 0x0044
  87. #define TX_FIFO_EMPTY 0x00000400
  88. #define TX_IN_PROGRESS 0x00000080
  89. #define PORT_SPEED_MASK 0x00000030
  90. #define PORT_SPEED_1000 0x00000010
  91. #define PORT_SPEED_100 0x00000020
  92. #define PORT_SPEED_10 0x00000000
  93. #define FLOW_CONTROL_ENABLED 0x00000008
  94. #define FULL_DUPLEX 0x00000004
  95. #define LINK_UP 0x00000002
  96. #define TXQ_COMMAND 0x0048
  97. #define TXQ_FIX_PRIO_CONF 0x004c
  98. #define TX_BW_RATE 0x0050
  99. #define TX_BW_MTU 0x0058
  100. #define TX_BW_BURST 0x005c
  101. #define INT_CAUSE 0x0060
  102. #define INT_TX_END 0x07f80000
  103. #define INT_RX 0x000003fc
  104. #define INT_EXT 0x00000002
  105. #define INT_CAUSE_EXT 0x0064
  106. #define INT_EXT_LINK_PHY 0x00110000
  107. #define INT_EXT_TX 0x000000ff
  108. #define INT_MASK 0x0068
  109. #define INT_MASK_EXT 0x006c
  110. #define TX_FIFO_URGENT_THRESHOLD 0x0074
  111. #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
  112. #define TX_BW_RATE_MOVED 0x00e0
  113. #define TX_BW_MTU_MOVED 0x00e8
  114. #define TX_BW_BURST_MOVED 0x00ec
  115. #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
  116. #define RXQ_COMMAND 0x0280
  117. #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
  118. #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
  119. #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
  120. #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
  121. /*
  122. * Misc per-port registers.
  123. */
  124. #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
  125. #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
  126. #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
  127. #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
  128. /*
  129. * SDMA configuration register.
  130. */
  131. #define RX_BURST_SIZE_4_64BIT (2 << 1)
  132. #define RX_BURST_SIZE_16_64BIT (4 << 1)
  133. #define BLM_RX_NO_SWAP (1 << 4)
  134. #define BLM_TX_NO_SWAP (1 << 5)
  135. #define TX_BURST_SIZE_4_64BIT (2 << 22)
  136. #define TX_BURST_SIZE_16_64BIT (4 << 22)
  137. #if defined(__BIG_ENDIAN)
  138. #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
  139. (RX_BURST_SIZE_4_64BIT | \
  140. TX_BURST_SIZE_4_64BIT)
  141. #elif defined(__LITTLE_ENDIAN)
  142. #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
  143. (RX_BURST_SIZE_4_64BIT | \
  144. BLM_RX_NO_SWAP | \
  145. BLM_TX_NO_SWAP | \
  146. TX_BURST_SIZE_4_64BIT)
  147. #else
  148. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  149. #endif
  150. /*
  151. * Port serial control register.
  152. */
  153. #define SET_MII_SPEED_TO_100 (1 << 24)
  154. #define SET_GMII_SPEED_TO_1000 (1 << 23)
  155. #define SET_FULL_DUPLEX_MODE (1 << 21)
  156. #define MAX_RX_PACKET_9700BYTE (5 << 17)
  157. #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
  158. #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
  159. #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
  160. #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
  161. #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
  162. #define FORCE_LINK_PASS (1 << 1)
  163. #define SERIAL_PORT_ENABLE (1 << 0)
  164. #define DEFAULT_RX_QUEUE_SIZE 128
  165. #define DEFAULT_TX_QUEUE_SIZE 256
  166. /*
  167. * RX/TX descriptors.
  168. */
  169. #if defined(__BIG_ENDIAN)
  170. struct rx_desc {
  171. u16 byte_cnt; /* Descriptor buffer byte count */
  172. u16 buf_size; /* Buffer size */
  173. u32 cmd_sts; /* Descriptor command status */
  174. u32 next_desc_ptr; /* Next descriptor pointer */
  175. u32 buf_ptr; /* Descriptor buffer pointer */
  176. };
  177. struct tx_desc {
  178. u16 byte_cnt; /* buffer byte count */
  179. u16 l4i_chk; /* CPU provided TCP checksum */
  180. u32 cmd_sts; /* Command/status field */
  181. u32 next_desc_ptr; /* Pointer to next descriptor */
  182. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  183. };
  184. #elif defined(__LITTLE_ENDIAN)
  185. struct rx_desc {
  186. u32 cmd_sts; /* Descriptor command status */
  187. u16 buf_size; /* Buffer size */
  188. u16 byte_cnt; /* Descriptor buffer byte count */
  189. u32 buf_ptr; /* Descriptor buffer pointer */
  190. u32 next_desc_ptr; /* Next descriptor pointer */
  191. };
  192. struct tx_desc {
  193. u32 cmd_sts; /* Command/status field */
  194. u16 l4i_chk; /* CPU provided TCP checksum */
  195. u16 byte_cnt; /* buffer byte count */
  196. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  197. u32 next_desc_ptr; /* Pointer to next descriptor */
  198. };
  199. #else
  200. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  201. #endif
  202. /* RX & TX descriptor command */
  203. #define BUFFER_OWNED_BY_DMA 0x80000000
  204. /* RX & TX descriptor status */
  205. #define ERROR_SUMMARY 0x00000001
  206. /* RX descriptor status */
  207. #define LAYER_4_CHECKSUM_OK 0x40000000
  208. #define RX_ENABLE_INTERRUPT 0x20000000
  209. #define RX_FIRST_DESC 0x08000000
  210. #define RX_LAST_DESC 0x04000000
  211. /* TX descriptor command */
  212. #define TX_ENABLE_INTERRUPT 0x00800000
  213. #define GEN_CRC 0x00400000
  214. #define TX_FIRST_DESC 0x00200000
  215. #define TX_LAST_DESC 0x00100000
  216. #define ZERO_PADDING 0x00080000
  217. #define GEN_IP_V4_CHECKSUM 0x00040000
  218. #define GEN_TCP_UDP_CHECKSUM 0x00020000
  219. #define UDP_FRAME 0x00010000
  220. #define MAC_HDR_EXTRA_4_BYTES 0x00008000
  221. #define MAC_HDR_EXTRA_8_BYTES 0x00000200
  222. #define TX_IHL_SHIFT 11
  223. /* global *******************************************************************/
  224. struct mv643xx_eth_shared_private {
  225. /*
  226. * Ethernet controller base address.
  227. */
  228. void __iomem *base;
  229. /*
  230. * Points at the right SMI instance to use.
  231. */
  232. struct mv643xx_eth_shared_private *smi;
  233. /*
  234. * Provides access to local SMI interface.
  235. */
  236. struct mii_bus *smi_bus;
  237. /*
  238. * If we have access to the error interrupt pin (which is
  239. * somewhat misnamed as it not only reflects internal errors
  240. * but also reflects SMI completion), use that to wait for
  241. * SMI access completion instead of polling the SMI busy bit.
  242. */
  243. int err_interrupt;
  244. wait_queue_head_t smi_busy_wait;
  245. /*
  246. * Per-port MBUS window access register value.
  247. */
  248. u32 win_protect;
  249. /*
  250. * Hardware-specific parameters.
  251. */
  252. unsigned int t_clk;
  253. int extended_rx_coal_limit;
  254. int tx_bw_control;
  255. };
  256. #define TX_BW_CONTROL_ABSENT 0
  257. #define TX_BW_CONTROL_OLD_LAYOUT 1
  258. #define TX_BW_CONTROL_NEW_LAYOUT 2
  259. /* per-port *****************************************************************/
  260. struct mib_counters {
  261. u64 good_octets_received;
  262. u32 bad_octets_received;
  263. u32 internal_mac_transmit_err;
  264. u32 good_frames_received;
  265. u32 bad_frames_received;
  266. u32 broadcast_frames_received;
  267. u32 multicast_frames_received;
  268. u32 frames_64_octets;
  269. u32 frames_65_to_127_octets;
  270. u32 frames_128_to_255_octets;
  271. u32 frames_256_to_511_octets;
  272. u32 frames_512_to_1023_octets;
  273. u32 frames_1024_to_max_octets;
  274. u64 good_octets_sent;
  275. u32 good_frames_sent;
  276. u32 excessive_collision;
  277. u32 multicast_frames_sent;
  278. u32 broadcast_frames_sent;
  279. u32 unrec_mac_control_received;
  280. u32 fc_sent;
  281. u32 good_fc_received;
  282. u32 bad_fc_received;
  283. u32 undersize_received;
  284. u32 fragments_received;
  285. u32 oversize_received;
  286. u32 jabber_received;
  287. u32 mac_receive_error;
  288. u32 bad_crc_event;
  289. u32 collision;
  290. u32 late_collision;
  291. };
  292. struct rx_queue {
  293. int index;
  294. int rx_ring_size;
  295. int rx_desc_count;
  296. int rx_curr_desc;
  297. int rx_used_desc;
  298. struct rx_desc *rx_desc_area;
  299. dma_addr_t rx_desc_dma;
  300. int rx_desc_area_size;
  301. struct sk_buff **rx_skb;
  302. };
  303. struct tx_queue {
  304. int index;
  305. int tx_ring_size;
  306. int tx_desc_count;
  307. int tx_curr_desc;
  308. int tx_used_desc;
  309. struct tx_desc *tx_desc_area;
  310. dma_addr_t tx_desc_dma;
  311. int tx_desc_area_size;
  312. struct sk_buff_head tx_skb;
  313. unsigned long tx_packets;
  314. unsigned long tx_bytes;
  315. unsigned long tx_dropped;
  316. };
  317. struct mv643xx_eth_private {
  318. struct mv643xx_eth_shared_private *shared;
  319. void __iomem *base;
  320. int port_num;
  321. struct net_device *dev;
  322. struct phy_device *phy;
  323. struct timer_list mib_counters_timer;
  324. spinlock_t mib_counters_lock;
  325. struct mib_counters mib_counters;
  326. struct work_struct tx_timeout_task;
  327. struct napi_struct napi;
  328. u8 work_link;
  329. u8 work_tx;
  330. u8 work_tx_end;
  331. u8 work_rx;
  332. u8 work_rx_refill;
  333. u8 work_rx_oom;
  334. int skb_size;
  335. struct sk_buff_head rx_recycle;
  336. /*
  337. * RX state.
  338. */
  339. int default_rx_ring_size;
  340. unsigned long rx_desc_sram_addr;
  341. int rx_desc_sram_size;
  342. int rxq_count;
  343. struct timer_list rx_oom;
  344. struct rx_queue rxq[8];
  345. /*
  346. * TX state.
  347. */
  348. int default_tx_ring_size;
  349. unsigned long tx_desc_sram_addr;
  350. int tx_desc_sram_size;
  351. int txq_count;
  352. struct tx_queue txq[8];
  353. };
  354. /* port register accessors **************************************************/
  355. static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
  356. {
  357. return readl(mp->shared->base + offset);
  358. }
  359. static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
  360. {
  361. return readl(mp->base + offset);
  362. }
  363. static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
  364. {
  365. writel(data, mp->shared->base + offset);
  366. }
  367. static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
  368. {
  369. writel(data, mp->base + offset);
  370. }
  371. /* rxq/txq helper functions *************************************************/
  372. static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
  373. {
  374. return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
  375. }
  376. static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
  377. {
  378. return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
  379. }
  380. static void rxq_enable(struct rx_queue *rxq)
  381. {
  382. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  383. wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
  384. }
  385. static void rxq_disable(struct rx_queue *rxq)
  386. {
  387. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  388. u8 mask = 1 << rxq->index;
  389. wrlp(mp, RXQ_COMMAND, mask << 8);
  390. while (rdlp(mp, RXQ_COMMAND) & mask)
  391. udelay(10);
  392. }
  393. static void txq_reset_hw_ptr(struct tx_queue *txq)
  394. {
  395. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  396. u32 addr;
  397. addr = (u32)txq->tx_desc_dma;
  398. addr += txq->tx_curr_desc * sizeof(struct tx_desc);
  399. wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
  400. }
  401. static void txq_enable(struct tx_queue *txq)
  402. {
  403. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  404. wrlp(mp, TXQ_COMMAND, 1 << txq->index);
  405. }
  406. static void txq_disable(struct tx_queue *txq)
  407. {
  408. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  409. u8 mask = 1 << txq->index;
  410. wrlp(mp, TXQ_COMMAND, mask << 8);
  411. while (rdlp(mp, TXQ_COMMAND) & mask)
  412. udelay(10);
  413. }
  414. static void txq_maybe_wake(struct tx_queue *txq)
  415. {
  416. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  417. struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
  418. if (netif_tx_queue_stopped(nq)) {
  419. __netif_tx_lock(nq, smp_processor_id());
  420. if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
  421. netif_tx_wake_queue(nq);
  422. __netif_tx_unlock(nq);
  423. }
  424. }
  425. /* rx napi ******************************************************************/
  426. static int rxq_process(struct rx_queue *rxq, int budget)
  427. {
  428. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  429. struct net_device_stats *stats = &mp->dev->stats;
  430. int rx;
  431. rx = 0;
  432. while (rx < budget && rxq->rx_desc_count) {
  433. struct rx_desc *rx_desc;
  434. unsigned int cmd_sts;
  435. struct sk_buff *skb;
  436. u16 byte_cnt;
  437. rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
  438. cmd_sts = rx_desc->cmd_sts;
  439. if (cmd_sts & BUFFER_OWNED_BY_DMA)
  440. break;
  441. rmb();
  442. skb = rxq->rx_skb[rxq->rx_curr_desc];
  443. rxq->rx_skb[rxq->rx_curr_desc] = NULL;
  444. rxq->rx_curr_desc++;
  445. if (rxq->rx_curr_desc == rxq->rx_ring_size)
  446. rxq->rx_curr_desc = 0;
  447. dma_unmap_single(NULL, rx_desc->buf_ptr,
  448. rx_desc->buf_size, DMA_FROM_DEVICE);
  449. rxq->rx_desc_count--;
  450. rx++;
  451. mp->work_rx_refill |= 1 << rxq->index;
  452. byte_cnt = rx_desc->byte_cnt;
  453. /*
  454. * Update statistics.
  455. *
  456. * Note that the descriptor byte count includes 2 dummy
  457. * bytes automatically inserted by the hardware at the
  458. * start of the packet (which we don't count), and a 4
  459. * byte CRC at the end of the packet (which we do count).
  460. */
  461. stats->rx_packets++;
  462. stats->rx_bytes += byte_cnt - 2;
  463. /*
  464. * In case we received a packet without first / last bits
  465. * on, or the error summary bit is set, the packet needs
  466. * to be dropped.
  467. */
  468. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
  469. != (RX_FIRST_DESC | RX_LAST_DESC))
  470. goto err;
  471. /*
  472. * The -4 is for the CRC in the trailer of the
  473. * received packet
  474. */
  475. skb_put(skb, byte_cnt - 2 - 4);
  476. if (cmd_sts & LAYER_4_CHECKSUM_OK)
  477. skb->ip_summed = CHECKSUM_UNNECESSARY;
  478. skb->protocol = eth_type_trans(skb, mp->dev);
  479. netif_receive_skb(skb);
  480. continue;
  481. err:
  482. stats->rx_dropped++;
  483. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
  484. (RX_FIRST_DESC | RX_LAST_DESC)) {
  485. if (net_ratelimit())
  486. dev_printk(KERN_ERR, &mp->dev->dev,
  487. "received packet spanning "
  488. "multiple descriptors\n");
  489. }
  490. if (cmd_sts & ERROR_SUMMARY)
  491. stats->rx_errors++;
  492. dev_kfree_skb(skb);
  493. }
  494. if (rx < budget)
  495. mp->work_rx &= ~(1 << rxq->index);
  496. return rx;
  497. }
  498. static int rxq_refill(struct rx_queue *rxq, int budget)
  499. {
  500. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  501. int refilled;
  502. refilled = 0;
  503. while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
  504. struct sk_buff *skb;
  505. int unaligned;
  506. int rx;
  507. struct rx_desc *rx_desc;
  508. skb = __skb_dequeue(&mp->rx_recycle);
  509. if (skb == NULL)
  510. skb = dev_alloc_skb(mp->skb_size +
  511. dma_get_cache_alignment() - 1);
  512. if (skb == NULL) {
  513. mp->work_rx_oom |= 1 << rxq->index;
  514. goto oom;
  515. }
  516. unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
  517. if (unaligned)
  518. skb_reserve(skb, dma_get_cache_alignment() - unaligned);
  519. refilled++;
  520. rxq->rx_desc_count++;
  521. rx = rxq->rx_used_desc++;
  522. if (rxq->rx_used_desc == rxq->rx_ring_size)
  523. rxq->rx_used_desc = 0;
  524. rx_desc = rxq->rx_desc_area + rx;
  525. rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
  526. mp->skb_size, DMA_FROM_DEVICE);
  527. rx_desc->buf_size = mp->skb_size;
  528. rxq->rx_skb[rx] = skb;
  529. wmb();
  530. rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
  531. wmb();
  532. /*
  533. * The hardware automatically prepends 2 bytes of
  534. * dummy data to each received packet, so that the
  535. * IP header ends up 16-byte aligned.
  536. */
  537. skb_reserve(skb, 2);
  538. }
  539. if (refilled < budget)
  540. mp->work_rx_refill &= ~(1 << rxq->index);
  541. oom:
  542. return refilled;
  543. }
  544. /* tx ***********************************************************************/
  545. static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
  546. {
  547. int frag;
  548. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  549. skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
  550. if (fragp->size <= 8 && fragp->page_offset & 7)
  551. return 1;
  552. }
  553. return 0;
  554. }
  555. static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
  556. {
  557. int nr_frags = skb_shinfo(skb)->nr_frags;
  558. int frag;
  559. for (frag = 0; frag < nr_frags; frag++) {
  560. skb_frag_t *this_frag;
  561. int tx_index;
  562. struct tx_desc *desc;
  563. this_frag = &skb_shinfo(skb)->frags[frag];
  564. tx_index = txq->tx_curr_desc++;
  565. if (txq->tx_curr_desc == txq->tx_ring_size)
  566. txq->tx_curr_desc = 0;
  567. desc = &txq->tx_desc_area[tx_index];
  568. /*
  569. * The last fragment will generate an interrupt
  570. * which will free the skb on TX completion.
  571. */
  572. if (frag == nr_frags - 1) {
  573. desc->cmd_sts = BUFFER_OWNED_BY_DMA |
  574. ZERO_PADDING | TX_LAST_DESC |
  575. TX_ENABLE_INTERRUPT;
  576. } else {
  577. desc->cmd_sts = BUFFER_OWNED_BY_DMA;
  578. }
  579. desc->l4i_chk = 0;
  580. desc->byte_cnt = this_frag->size;
  581. desc->buf_ptr = dma_map_page(NULL, this_frag->page,
  582. this_frag->page_offset,
  583. this_frag->size,
  584. DMA_TO_DEVICE);
  585. }
  586. }
  587. static inline __be16 sum16_as_be(__sum16 sum)
  588. {
  589. return (__force __be16)sum;
  590. }
  591. static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
  592. {
  593. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  594. int nr_frags = skb_shinfo(skb)->nr_frags;
  595. int tx_index;
  596. struct tx_desc *desc;
  597. u32 cmd_sts;
  598. u16 l4i_chk;
  599. int length;
  600. cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
  601. l4i_chk = 0;
  602. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  603. int tag_bytes;
  604. BUG_ON(skb->protocol != htons(ETH_P_IP) &&
  605. skb->protocol != htons(ETH_P_8021Q));
  606. tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
  607. if (unlikely(tag_bytes & ~12)) {
  608. if (skb_checksum_help(skb) == 0)
  609. goto no_csum;
  610. kfree_skb(skb);
  611. return 1;
  612. }
  613. if (tag_bytes & 4)
  614. cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
  615. if (tag_bytes & 8)
  616. cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
  617. cmd_sts |= GEN_TCP_UDP_CHECKSUM |
  618. GEN_IP_V4_CHECKSUM |
  619. ip_hdr(skb)->ihl << TX_IHL_SHIFT;
  620. switch (ip_hdr(skb)->protocol) {
  621. case IPPROTO_UDP:
  622. cmd_sts |= UDP_FRAME;
  623. l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
  624. break;
  625. case IPPROTO_TCP:
  626. l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
  627. break;
  628. default:
  629. BUG();
  630. }
  631. } else {
  632. no_csum:
  633. /* Errata BTS #50, IHL must be 5 if no HW checksum */
  634. cmd_sts |= 5 << TX_IHL_SHIFT;
  635. }
  636. tx_index = txq->tx_curr_desc++;
  637. if (txq->tx_curr_desc == txq->tx_ring_size)
  638. txq->tx_curr_desc = 0;
  639. desc = &txq->tx_desc_area[tx_index];
  640. if (nr_frags) {
  641. txq_submit_frag_skb(txq, skb);
  642. length = skb_headlen(skb);
  643. } else {
  644. cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
  645. length = skb->len;
  646. }
  647. desc->l4i_chk = l4i_chk;
  648. desc->byte_cnt = length;
  649. desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
  650. __skb_queue_tail(&txq->tx_skb, skb);
  651. /* ensure all other descriptors are written before first cmd_sts */
  652. wmb();
  653. desc->cmd_sts = cmd_sts;
  654. /* clear TX_END status */
  655. mp->work_tx_end &= ~(1 << txq->index);
  656. /* ensure all descriptors are written before poking hardware */
  657. wmb();
  658. txq_enable(txq);
  659. txq->tx_desc_count += nr_frags + 1;
  660. return 0;
  661. }
  662. static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
  663. {
  664. struct mv643xx_eth_private *mp = netdev_priv(dev);
  665. int queue;
  666. struct tx_queue *txq;
  667. struct netdev_queue *nq;
  668. queue = skb_get_queue_mapping(skb);
  669. txq = mp->txq + queue;
  670. nq = netdev_get_tx_queue(dev, queue);
  671. if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
  672. txq->tx_dropped++;
  673. dev_printk(KERN_DEBUG, &dev->dev,
  674. "failed to linearize skb with tiny "
  675. "unaligned fragment\n");
  676. return NETDEV_TX_BUSY;
  677. }
  678. if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
  679. if (net_ratelimit())
  680. dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
  681. kfree_skb(skb);
  682. return NETDEV_TX_OK;
  683. }
  684. if (!txq_submit_skb(txq, skb)) {
  685. int entries_left;
  686. txq->tx_bytes += skb->len;
  687. txq->tx_packets++;
  688. dev->trans_start = jiffies;
  689. entries_left = txq->tx_ring_size - txq->tx_desc_count;
  690. if (entries_left < MAX_SKB_FRAGS + 1)
  691. netif_tx_stop_queue(nq);
  692. }
  693. return NETDEV_TX_OK;
  694. }
  695. /* tx napi ******************************************************************/
  696. static void txq_kick(struct tx_queue *txq)
  697. {
  698. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  699. struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
  700. u32 hw_desc_ptr;
  701. u32 expected_ptr;
  702. __netif_tx_lock(nq, smp_processor_id());
  703. if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
  704. goto out;
  705. hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
  706. expected_ptr = (u32)txq->tx_desc_dma +
  707. txq->tx_curr_desc * sizeof(struct tx_desc);
  708. if (hw_desc_ptr != expected_ptr)
  709. txq_enable(txq);
  710. out:
  711. __netif_tx_unlock(nq);
  712. mp->work_tx_end &= ~(1 << txq->index);
  713. }
  714. static int txq_reclaim(struct tx_queue *txq, int budget, int force)
  715. {
  716. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  717. struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
  718. int reclaimed;
  719. __netif_tx_lock(nq, smp_processor_id());
  720. reclaimed = 0;
  721. while (reclaimed < budget && txq->tx_desc_count > 0) {
  722. int tx_index;
  723. struct tx_desc *desc;
  724. u32 cmd_sts;
  725. struct sk_buff *skb;
  726. tx_index = txq->tx_used_desc;
  727. desc = &txq->tx_desc_area[tx_index];
  728. cmd_sts = desc->cmd_sts;
  729. if (cmd_sts & BUFFER_OWNED_BY_DMA) {
  730. if (!force)
  731. break;
  732. desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
  733. }
  734. txq->tx_used_desc = tx_index + 1;
  735. if (txq->tx_used_desc == txq->tx_ring_size)
  736. txq->tx_used_desc = 0;
  737. reclaimed++;
  738. txq->tx_desc_count--;
  739. skb = NULL;
  740. if (cmd_sts & TX_LAST_DESC)
  741. skb = __skb_dequeue(&txq->tx_skb);
  742. if (cmd_sts & ERROR_SUMMARY) {
  743. dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
  744. mp->dev->stats.tx_errors++;
  745. }
  746. if (cmd_sts & TX_FIRST_DESC) {
  747. dma_unmap_single(NULL, desc->buf_ptr,
  748. desc->byte_cnt, DMA_TO_DEVICE);
  749. } else {
  750. dma_unmap_page(NULL, desc->buf_ptr,
  751. desc->byte_cnt, DMA_TO_DEVICE);
  752. }
  753. if (skb != NULL) {
  754. if (skb_queue_len(&mp->rx_recycle) <
  755. mp->default_rx_ring_size &&
  756. skb_recycle_check(skb, mp->skb_size +
  757. dma_get_cache_alignment() - 1))
  758. __skb_queue_head(&mp->rx_recycle, skb);
  759. else
  760. dev_kfree_skb(skb);
  761. }
  762. }
  763. __netif_tx_unlock(nq);
  764. if (reclaimed < budget)
  765. mp->work_tx &= ~(1 << txq->index);
  766. return reclaimed;
  767. }
  768. /* tx rate control **********************************************************/
  769. /*
  770. * Set total maximum TX rate (shared by all TX queues for this port)
  771. * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
  772. */
  773. static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
  774. {
  775. int token_rate;
  776. int mtu;
  777. int bucket_size;
  778. token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
  779. if (token_rate > 1023)
  780. token_rate = 1023;
  781. mtu = (mp->dev->mtu + 255) >> 8;
  782. if (mtu > 63)
  783. mtu = 63;
  784. bucket_size = (burst + 255) >> 8;
  785. if (bucket_size > 65535)
  786. bucket_size = 65535;
  787. switch (mp->shared->tx_bw_control) {
  788. case TX_BW_CONTROL_OLD_LAYOUT:
  789. wrlp(mp, TX_BW_RATE, token_rate);
  790. wrlp(mp, TX_BW_MTU, mtu);
  791. wrlp(mp, TX_BW_BURST, bucket_size);
  792. break;
  793. case TX_BW_CONTROL_NEW_LAYOUT:
  794. wrlp(mp, TX_BW_RATE_MOVED, token_rate);
  795. wrlp(mp, TX_BW_MTU_MOVED, mtu);
  796. wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
  797. break;
  798. }
  799. }
  800. static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
  801. {
  802. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  803. int token_rate;
  804. int bucket_size;
  805. token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
  806. if (token_rate > 1023)
  807. token_rate = 1023;
  808. bucket_size = (burst + 255) >> 8;
  809. if (bucket_size > 65535)
  810. bucket_size = 65535;
  811. wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
  812. wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
  813. }
  814. static void txq_set_fixed_prio_mode(struct tx_queue *txq)
  815. {
  816. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  817. int off;
  818. u32 val;
  819. /*
  820. * Turn on fixed priority mode.
  821. */
  822. off = 0;
  823. switch (mp->shared->tx_bw_control) {
  824. case TX_BW_CONTROL_OLD_LAYOUT:
  825. off = TXQ_FIX_PRIO_CONF;
  826. break;
  827. case TX_BW_CONTROL_NEW_LAYOUT:
  828. off = TXQ_FIX_PRIO_CONF_MOVED;
  829. break;
  830. }
  831. if (off) {
  832. val = rdlp(mp, off);
  833. val |= 1 << txq->index;
  834. wrlp(mp, off, val);
  835. }
  836. }
  837. static void txq_set_wrr(struct tx_queue *txq, int weight)
  838. {
  839. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  840. int off;
  841. u32 val;
  842. /*
  843. * Turn off fixed priority mode.
  844. */
  845. off = 0;
  846. switch (mp->shared->tx_bw_control) {
  847. case TX_BW_CONTROL_OLD_LAYOUT:
  848. off = TXQ_FIX_PRIO_CONF;
  849. break;
  850. case TX_BW_CONTROL_NEW_LAYOUT:
  851. off = TXQ_FIX_PRIO_CONF_MOVED;
  852. break;
  853. }
  854. if (off) {
  855. val = rdlp(mp, off);
  856. val &= ~(1 << txq->index);
  857. wrlp(mp, off, val);
  858. /*
  859. * Configure WRR weight for this queue.
  860. */
  861. val = rdlp(mp, off);
  862. val = (val & ~0xff) | (weight & 0xff);
  863. wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
  864. }
  865. }
  866. /* mii management interface *************************************************/
  867. static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
  868. {
  869. struct mv643xx_eth_shared_private *msp = dev_id;
  870. if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
  871. writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
  872. wake_up(&msp->smi_busy_wait);
  873. return IRQ_HANDLED;
  874. }
  875. return IRQ_NONE;
  876. }
  877. static int smi_is_done(struct mv643xx_eth_shared_private *msp)
  878. {
  879. return !(readl(msp->base + SMI_REG) & SMI_BUSY);
  880. }
  881. static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
  882. {
  883. if (msp->err_interrupt == NO_IRQ) {
  884. int i;
  885. for (i = 0; !smi_is_done(msp); i++) {
  886. if (i == 10)
  887. return -ETIMEDOUT;
  888. msleep(10);
  889. }
  890. return 0;
  891. }
  892. if (!smi_is_done(msp)) {
  893. wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
  894. msecs_to_jiffies(100));
  895. if (!smi_is_done(msp))
  896. return -ETIMEDOUT;
  897. }
  898. return 0;
  899. }
  900. static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
  901. {
  902. struct mv643xx_eth_shared_private *msp = bus->priv;
  903. void __iomem *smi_reg = msp->base + SMI_REG;
  904. int ret;
  905. if (smi_wait_ready(msp)) {
  906. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  907. return -ETIMEDOUT;
  908. }
  909. writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
  910. if (smi_wait_ready(msp)) {
  911. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  912. return -ETIMEDOUT;
  913. }
  914. ret = readl(smi_reg);
  915. if (!(ret & SMI_READ_VALID)) {
  916. printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
  917. return -ENODEV;
  918. }
  919. return ret & 0xffff;
  920. }
  921. static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
  922. {
  923. struct mv643xx_eth_shared_private *msp = bus->priv;
  924. void __iomem *smi_reg = msp->base + SMI_REG;
  925. if (smi_wait_ready(msp)) {
  926. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  927. return -ETIMEDOUT;
  928. }
  929. writel(SMI_OPCODE_WRITE | (reg << 21) |
  930. (addr << 16) | (val & 0xffff), smi_reg);
  931. if (smi_wait_ready(msp)) {
  932. printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
  933. return -ETIMEDOUT;
  934. }
  935. return 0;
  936. }
  937. /* statistics ***************************************************************/
  938. static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
  939. {
  940. struct mv643xx_eth_private *mp = netdev_priv(dev);
  941. struct net_device_stats *stats = &dev->stats;
  942. unsigned long tx_packets = 0;
  943. unsigned long tx_bytes = 0;
  944. unsigned long tx_dropped = 0;
  945. int i;
  946. for (i = 0; i < mp->txq_count; i++) {
  947. struct tx_queue *txq = mp->txq + i;
  948. tx_packets += txq->tx_packets;
  949. tx_bytes += txq->tx_bytes;
  950. tx_dropped += txq->tx_dropped;
  951. }
  952. stats->tx_packets = tx_packets;
  953. stats->tx_bytes = tx_bytes;
  954. stats->tx_dropped = tx_dropped;
  955. return stats;
  956. }
  957. static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
  958. {
  959. return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
  960. }
  961. static void mib_counters_clear(struct mv643xx_eth_private *mp)
  962. {
  963. int i;
  964. for (i = 0; i < 0x80; i += 4)
  965. mib_read(mp, i);
  966. }
  967. static void mib_counters_update(struct mv643xx_eth_private *mp)
  968. {
  969. struct mib_counters *p = &mp->mib_counters;
  970. spin_lock(&mp->mib_counters_lock);
  971. p->good_octets_received += mib_read(mp, 0x00);
  972. p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
  973. p->bad_octets_received += mib_read(mp, 0x08);
  974. p->internal_mac_transmit_err += mib_read(mp, 0x0c);
  975. p->good_frames_received += mib_read(mp, 0x10);
  976. p->bad_frames_received += mib_read(mp, 0x14);
  977. p->broadcast_frames_received += mib_read(mp, 0x18);
  978. p->multicast_frames_received += mib_read(mp, 0x1c);
  979. p->frames_64_octets += mib_read(mp, 0x20);
  980. p->frames_65_to_127_octets += mib_read(mp, 0x24);
  981. p->frames_128_to_255_octets += mib_read(mp, 0x28);
  982. p->frames_256_to_511_octets += mib_read(mp, 0x2c);
  983. p->frames_512_to_1023_octets += mib_read(mp, 0x30);
  984. p->frames_1024_to_max_octets += mib_read(mp, 0x34);
  985. p->good_octets_sent += mib_read(mp, 0x38);
  986. p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
  987. p->good_frames_sent += mib_read(mp, 0x40);
  988. p->excessive_collision += mib_read(mp, 0x44);
  989. p->multicast_frames_sent += mib_read(mp, 0x48);
  990. p->broadcast_frames_sent += mib_read(mp, 0x4c);
  991. p->unrec_mac_control_received += mib_read(mp, 0x50);
  992. p->fc_sent += mib_read(mp, 0x54);
  993. p->good_fc_received += mib_read(mp, 0x58);
  994. p->bad_fc_received += mib_read(mp, 0x5c);
  995. p->undersize_received += mib_read(mp, 0x60);
  996. p->fragments_received += mib_read(mp, 0x64);
  997. p->oversize_received += mib_read(mp, 0x68);
  998. p->jabber_received += mib_read(mp, 0x6c);
  999. p->mac_receive_error += mib_read(mp, 0x70);
  1000. p->bad_crc_event += mib_read(mp, 0x74);
  1001. p->collision += mib_read(mp, 0x78);
  1002. p->late_collision += mib_read(mp, 0x7c);
  1003. spin_unlock(&mp->mib_counters_lock);
  1004. mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
  1005. }
  1006. static void mib_counters_timer_wrapper(unsigned long _mp)
  1007. {
  1008. struct mv643xx_eth_private *mp = (void *)_mp;
  1009. mib_counters_update(mp);
  1010. }
  1011. /* ethtool ******************************************************************/
  1012. struct mv643xx_eth_stats {
  1013. char stat_string[ETH_GSTRING_LEN];
  1014. int sizeof_stat;
  1015. int netdev_off;
  1016. int mp_off;
  1017. };
  1018. #define SSTAT(m) \
  1019. { #m, FIELD_SIZEOF(struct net_device_stats, m), \
  1020. offsetof(struct net_device, stats.m), -1 }
  1021. #define MIBSTAT(m) \
  1022. { #m, FIELD_SIZEOF(struct mib_counters, m), \
  1023. -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
  1024. static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
  1025. SSTAT(rx_packets),
  1026. SSTAT(tx_packets),
  1027. SSTAT(rx_bytes),
  1028. SSTAT(tx_bytes),
  1029. SSTAT(rx_errors),
  1030. SSTAT(tx_errors),
  1031. SSTAT(rx_dropped),
  1032. SSTAT(tx_dropped),
  1033. MIBSTAT(good_octets_received),
  1034. MIBSTAT(bad_octets_received),
  1035. MIBSTAT(internal_mac_transmit_err),
  1036. MIBSTAT(good_frames_received),
  1037. MIBSTAT(bad_frames_received),
  1038. MIBSTAT(broadcast_frames_received),
  1039. MIBSTAT(multicast_frames_received),
  1040. MIBSTAT(frames_64_octets),
  1041. MIBSTAT(frames_65_to_127_octets),
  1042. MIBSTAT(frames_128_to_255_octets),
  1043. MIBSTAT(frames_256_to_511_octets),
  1044. MIBSTAT(frames_512_to_1023_octets),
  1045. MIBSTAT(frames_1024_to_max_octets),
  1046. MIBSTAT(good_octets_sent),
  1047. MIBSTAT(good_frames_sent),
  1048. MIBSTAT(excessive_collision),
  1049. MIBSTAT(multicast_frames_sent),
  1050. MIBSTAT(broadcast_frames_sent),
  1051. MIBSTAT(unrec_mac_control_received),
  1052. MIBSTAT(fc_sent),
  1053. MIBSTAT(good_fc_received),
  1054. MIBSTAT(bad_fc_received),
  1055. MIBSTAT(undersize_received),
  1056. MIBSTAT(fragments_received),
  1057. MIBSTAT(oversize_received),
  1058. MIBSTAT(jabber_received),
  1059. MIBSTAT(mac_receive_error),
  1060. MIBSTAT(bad_crc_event),
  1061. MIBSTAT(collision),
  1062. MIBSTAT(late_collision),
  1063. };
  1064. static int
  1065. mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
  1066. struct ethtool_cmd *cmd)
  1067. {
  1068. int err;
  1069. err = phy_read_status(mp->phy);
  1070. if (err == 0)
  1071. err = phy_ethtool_gset(mp->phy, cmd);
  1072. /*
  1073. * The MAC does not support 1000baseT_Half.
  1074. */
  1075. cmd->supported &= ~SUPPORTED_1000baseT_Half;
  1076. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  1077. return err;
  1078. }
  1079. static int
  1080. mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
  1081. struct ethtool_cmd *cmd)
  1082. {
  1083. u32 port_status;
  1084. port_status = rdlp(mp, PORT_STATUS);
  1085. cmd->supported = SUPPORTED_MII;
  1086. cmd->advertising = ADVERTISED_MII;
  1087. switch (port_status & PORT_SPEED_MASK) {
  1088. case PORT_SPEED_10:
  1089. cmd->speed = SPEED_10;
  1090. break;
  1091. case PORT_SPEED_100:
  1092. cmd->speed = SPEED_100;
  1093. break;
  1094. case PORT_SPEED_1000:
  1095. cmd->speed = SPEED_1000;
  1096. break;
  1097. default:
  1098. cmd->speed = -1;
  1099. break;
  1100. }
  1101. cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
  1102. cmd->port = PORT_MII;
  1103. cmd->phy_address = 0;
  1104. cmd->transceiver = XCVR_INTERNAL;
  1105. cmd->autoneg = AUTONEG_DISABLE;
  1106. cmd->maxtxpkt = 1;
  1107. cmd->maxrxpkt = 1;
  1108. return 0;
  1109. }
  1110. static int
  1111. mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1112. {
  1113. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1114. if (mp->phy != NULL)
  1115. return mv643xx_eth_get_settings_phy(mp, cmd);
  1116. else
  1117. return mv643xx_eth_get_settings_phyless(mp, cmd);
  1118. }
  1119. static int
  1120. mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1121. {
  1122. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1123. if (mp->phy == NULL)
  1124. return -EINVAL;
  1125. /*
  1126. * The MAC does not support 1000baseT_Half.
  1127. */
  1128. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  1129. return phy_ethtool_sset(mp->phy, cmd);
  1130. }
  1131. static void mv643xx_eth_get_drvinfo(struct net_device *dev,
  1132. struct ethtool_drvinfo *drvinfo)
  1133. {
  1134. strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
  1135. strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
  1136. strncpy(drvinfo->fw_version, "N/A", 32);
  1137. strncpy(drvinfo->bus_info, "platform", 32);
  1138. drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
  1139. }
  1140. static int mv643xx_eth_nway_reset(struct net_device *dev)
  1141. {
  1142. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1143. if (mp->phy == NULL)
  1144. return -EINVAL;
  1145. return genphy_restart_aneg(mp->phy);
  1146. }
  1147. static u32 mv643xx_eth_get_link(struct net_device *dev)
  1148. {
  1149. return !!netif_carrier_ok(dev);
  1150. }
  1151. static void mv643xx_eth_get_strings(struct net_device *dev,
  1152. uint32_t stringset, uint8_t *data)
  1153. {
  1154. int i;
  1155. if (stringset == ETH_SS_STATS) {
  1156. for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
  1157. memcpy(data + i * ETH_GSTRING_LEN,
  1158. mv643xx_eth_stats[i].stat_string,
  1159. ETH_GSTRING_LEN);
  1160. }
  1161. }
  1162. }
  1163. static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
  1164. struct ethtool_stats *stats,
  1165. uint64_t *data)
  1166. {
  1167. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1168. int i;
  1169. mv643xx_eth_get_stats(dev);
  1170. mib_counters_update(mp);
  1171. for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
  1172. const struct mv643xx_eth_stats *stat;
  1173. void *p;
  1174. stat = mv643xx_eth_stats + i;
  1175. if (stat->netdev_off >= 0)
  1176. p = ((void *)mp->dev) + stat->netdev_off;
  1177. else
  1178. p = ((void *)mp) + stat->mp_off;
  1179. data[i] = (stat->sizeof_stat == 8) ?
  1180. *(uint64_t *)p : *(uint32_t *)p;
  1181. }
  1182. }
  1183. static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
  1184. {
  1185. if (sset == ETH_SS_STATS)
  1186. return ARRAY_SIZE(mv643xx_eth_stats);
  1187. return -EOPNOTSUPP;
  1188. }
  1189. static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
  1190. .get_settings = mv643xx_eth_get_settings,
  1191. .set_settings = mv643xx_eth_set_settings,
  1192. .get_drvinfo = mv643xx_eth_get_drvinfo,
  1193. .nway_reset = mv643xx_eth_nway_reset,
  1194. .get_link = mv643xx_eth_get_link,
  1195. .set_sg = ethtool_op_set_sg,
  1196. .get_strings = mv643xx_eth_get_strings,
  1197. .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
  1198. .get_sset_count = mv643xx_eth_get_sset_count,
  1199. };
  1200. /* address handling *********************************************************/
  1201. static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
  1202. {
  1203. unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
  1204. unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
  1205. addr[0] = (mac_h >> 24) & 0xff;
  1206. addr[1] = (mac_h >> 16) & 0xff;
  1207. addr[2] = (mac_h >> 8) & 0xff;
  1208. addr[3] = mac_h & 0xff;
  1209. addr[4] = (mac_l >> 8) & 0xff;
  1210. addr[5] = mac_l & 0xff;
  1211. }
  1212. static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
  1213. {
  1214. wrlp(mp, MAC_ADDR_HIGH,
  1215. (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
  1216. wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
  1217. }
  1218. static u32 uc_addr_filter_mask(struct net_device *dev)
  1219. {
  1220. struct dev_addr_list *uc_ptr;
  1221. u32 nibbles;
  1222. if (dev->flags & IFF_PROMISC)
  1223. return 0;
  1224. nibbles = 1 << (dev->dev_addr[5] & 0x0f);
  1225. for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
  1226. if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
  1227. return 0;
  1228. if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
  1229. return 0;
  1230. nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
  1231. }
  1232. return nibbles;
  1233. }
  1234. static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
  1235. {
  1236. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1237. u32 port_config;
  1238. u32 nibbles;
  1239. int i;
  1240. uc_addr_set(mp, dev->dev_addr);
  1241. port_config = rdlp(mp, PORT_CONFIG);
  1242. nibbles = uc_addr_filter_mask(dev);
  1243. if (!nibbles) {
  1244. port_config |= UNICAST_PROMISCUOUS_MODE;
  1245. wrlp(mp, PORT_CONFIG, port_config);
  1246. return;
  1247. }
  1248. for (i = 0; i < 16; i += 4) {
  1249. int off = UNICAST_TABLE(mp->port_num) + i;
  1250. u32 v;
  1251. v = 0;
  1252. if (nibbles & 1)
  1253. v |= 0x00000001;
  1254. if (nibbles & 2)
  1255. v |= 0x00000100;
  1256. if (nibbles & 4)
  1257. v |= 0x00010000;
  1258. if (nibbles & 8)
  1259. v |= 0x01000000;
  1260. nibbles >>= 4;
  1261. wrl(mp, off, v);
  1262. }
  1263. port_config &= ~UNICAST_PROMISCUOUS_MODE;
  1264. wrlp(mp, PORT_CONFIG, port_config);
  1265. }
  1266. static int addr_crc(unsigned char *addr)
  1267. {
  1268. int crc = 0;
  1269. int i;
  1270. for (i = 0; i < 6; i++) {
  1271. int j;
  1272. crc = (crc ^ addr[i]) << 8;
  1273. for (j = 7; j >= 0; j--) {
  1274. if (crc & (0x100 << j))
  1275. crc ^= 0x107 << j;
  1276. }
  1277. }
  1278. return crc;
  1279. }
  1280. static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
  1281. {
  1282. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1283. u32 *mc_spec;
  1284. u32 *mc_other;
  1285. struct dev_addr_list *addr;
  1286. int i;
  1287. if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
  1288. int port_num;
  1289. u32 accept;
  1290. int i;
  1291. oom:
  1292. port_num = mp->port_num;
  1293. accept = 0x01010101;
  1294. for (i = 0; i < 0x100; i += 4) {
  1295. wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
  1296. wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
  1297. }
  1298. return;
  1299. }
  1300. mc_spec = kmalloc(0x200, GFP_KERNEL);
  1301. if (mc_spec == NULL)
  1302. goto oom;
  1303. mc_other = mc_spec + (0x100 >> 2);
  1304. memset(mc_spec, 0, 0x100);
  1305. memset(mc_other, 0, 0x100);
  1306. for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
  1307. u8 *a = addr->da_addr;
  1308. u32 *table;
  1309. int entry;
  1310. if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
  1311. table = mc_spec;
  1312. entry = a[5];
  1313. } else {
  1314. table = mc_other;
  1315. entry = addr_crc(a);
  1316. }
  1317. table[entry >> 2] |= 1 << (8 * (entry & 3));
  1318. }
  1319. for (i = 0; i < 0x100; i += 4) {
  1320. wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
  1321. wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
  1322. }
  1323. kfree(mc_spec);
  1324. }
  1325. static void mv643xx_eth_set_rx_mode(struct net_device *dev)
  1326. {
  1327. mv643xx_eth_program_unicast_filter(dev);
  1328. mv643xx_eth_program_multicast_filter(dev);
  1329. }
  1330. static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
  1331. {
  1332. struct sockaddr *sa = addr;
  1333. memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
  1334. netif_addr_lock_bh(dev);
  1335. mv643xx_eth_program_unicast_filter(dev);
  1336. netif_addr_unlock_bh(dev);
  1337. return 0;
  1338. }
  1339. /* rx/tx queue initialisation ***********************************************/
  1340. static int rxq_init(struct mv643xx_eth_private *mp, int index)
  1341. {
  1342. struct rx_queue *rxq = mp->rxq + index;
  1343. struct rx_desc *rx_desc;
  1344. int size;
  1345. int i;
  1346. rxq->index = index;
  1347. rxq->rx_ring_size = mp->default_rx_ring_size;
  1348. rxq->rx_desc_count = 0;
  1349. rxq->rx_curr_desc = 0;
  1350. rxq->rx_used_desc = 0;
  1351. size = rxq->rx_ring_size * sizeof(struct rx_desc);
  1352. if (index == 0 && size <= mp->rx_desc_sram_size) {
  1353. rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
  1354. mp->rx_desc_sram_size);
  1355. rxq->rx_desc_dma = mp->rx_desc_sram_addr;
  1356. } else {
  1357. rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
  1358. &rxq->rx_desc_dma,
  1359. GFP_KERNEL);
  1360. }
  1361. if (rxq->rx_desc_area == NULL) {
  1362. dev_printk(KERN_ERR, &mp->dev->dev,
  1363. "can't allocate rx ring (%d bytes)\n", size);
  1364. goto out;
  1365. }
  1366. memset(rxq->rx_desc_area, 0, size);
  1367. rxq->rx_desc_area_size = size;
  1368. rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
  1369. GFP_KERNEL);
  1370. if (rxq->rx_skb == NULL) {
  1371. dev_printk(KERN_ERR, &mp->dev->dev,
  1372. "can't allocate rx skb ring\n");
  1373. goto out_free;
  1374. }
  1375. rx_desc = (struct rx_desc *)rxq->rx_desc_area;
  1376. for (i = 0; i < rxq->rx_ring_size; i++) {
  1377. int nexti;
  1378. nexti = i + 1;
  1379. if (nexti == rxq->rx_ring_size)
  1380. nexti = 0;
  1381. rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
  1382. nexti * sizeof(struct rx_desc);
  1383. }
  1384. return 0;
  1385. out_free:
  1386. if (index == 0 && size <= mp->rx_desc_sram_size)
  1387. iounmap(rxq->rx_desc_area);
  1388. else
  1389. dma_free_coherent(NULL, size,
  1390. rxq->rx_desc_area,
  1391. rxq->rx_desc_dma);
  1392. out:
  1393. return -ENOMEM;
  1394. }
  1395. static void rxq_deinit(struct rx_queue *rxq)
  1396. {
  1397. struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
  1398. int i;
  1399. rxq_disable(rxq);
  1400. for (i = 0; i < rxq->rx_ring_size; i++) {
  1401. if (rxq->rx_skb[i]) {
  1402. dev_kfree_skb(rxq->rx_skb[i]);
  1403. rxq->rx_desc_count--;
  1404. }
  1405. }
  1406. if (rxq->rx_desc_count) {
  1407. dev_printk(KERN_ERR, &mp->dev->dev,
  1408. "error freeing rx ring -- %d skbs stuck\n",
  1409. rxq->rx_desc_count);
  1410. }
  1411. if (rxq->index == 0 &&
  1412. rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
  1413. iounmap(rxq->rx_desc_area);
  1414. else
  1415. dma_free_coherent(NULL, rxq->rx_desc_area_size,
  1416. rxq->rx_desc_area, rxq->rx_desc_dma);
  1417. kfree(rxq->rx_skb);
  1418. }
  1419. static int txq_init(struct mv643xx_eth_private *mp, int index)
  1420. {
  1421. struct tx_queue *txq = mp->txq + index;
  1422. struct tx_desc *tx_desc;
  1423. int size;
  1424. int i;
  1425. txq->index = index;
  1426. txq->tx_ring_size = mp->default_tx_ring_size;
  1427. txq->tx_desc_count = 0;
  1428. txq->tx_curr_desc = 0;
  1429. txq->tx_used_desc = 0;
  1430. size = txq->tx_ring_size * sizeof(struct tx_desc);
  1431. if (index == 0 && size <= mp->tx_desc_sram_size) {
  1432. txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
  1433. mp->tx_desc_sram_size);
  1434. txq->tx_desc_dma = mp->tx_desc_sram_addr;
  1435. } else {
  1436. txq->tx_desc_area = dma_alloc_coherent(NULL, size,
  1437. &txq->tx_desc_dma,
  1438. GFP_KERNEL);
  1439. }
  1440. if (txq->tx_desc_area == NULL) {
  1441. dev_printk(KERN_ERR, &mp->dev->dev,
  1442. "can't allocate tx ring (%d bytes)\n", size);
  1443. return -ENOMEM;
  1444. }
  1445. memset(txq->tx_desc_area, 0, size);
  1446. txq->tx_desc_area_size = size;
  1447. tx_desc = (struct tx_desc *)txq->tx_desc_area;
  1448. for (i = 0; i < txq->tx_ring_size; i++) {
  1449. struct tx_desc *txd = tx_desc + i;
  1450. int nexti;
  1451. nexti = i + 1;
  1452. if (nexti == txq->tx_ring_size)
  1453. nexti = 0;
  1454. txd->cmd_sts = 0;
  1455. txd->next_desc_ptr = txq->tx_desc_dma +
  1456. nexti * sizeof(struct tx_desc);
  1457. }
  1458. skb_queue_head_init(&txq->tx_skb);
  1459. return 0;
  1460. }
  1461. static void txq_deinit(struct tx_queue *txq)
  1462. {
  1463. struct mv643xx_eth_private *mp = txq_to_mp(txq);
  1464. txq_disable(txq);
  1465. txq_reclaim(txq, txq->tx_ring_size, 1);
  1466. BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
  1467. if (txq->index == 0 &&
  1468. txq->tx_desc_area_size <= mp->tx_desc_sram_size)
  1469. iounmap(txq->tx_desc_area);
  1470. else
  1471. dma_free_coherent(NULL, txq->tx_desc_area_size,
  1472. txq->tx_desc_area, txq->tx_desc_dma);
  1473. }
  1474. /* netdev ops and related ***************************************************/
  1475. static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
  1476. {
  1477. u32 int_cause;
  1478. u32 int_cause_ext;
  1479. int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
  1480. if (int_cause == 0)
  1481. return 0;
  1482. int_cause_ext = 0;
  1483. if (int_cause & INT_EXT)
  1484. int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
  1485. int_cause &= INT_TX_END | INT_RX;
  1486. if (int_cause) {
  1487. wrlp(mp, INT_CAUSE, ~int_cause);
  1488. mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
  1489. ~(rdlp(mp, TXQ_COMMAND) & 0xff);
  1490. mp->work_rx |= (int_cause & INT_RX) >> 2;
  1491. }
  1492. int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
  1493. if (int_cause_ext) {
  1494. wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
  1495. if (int_cause_ext & INT_EXT_LINK_PHY)
  1496. mp->work_link = 1;
  1497. mp->work_tx |= int_cause_ext & INT_EXT_TX;
  1498. }
  1499. return 1;
  1500. }
  1501. static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
  1502. {
  1503. struct net_device *dev = (struct net_device *)dev_id;
  1504. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1505. if (unlikely(!mv643xx_eth_collect_events(mp)))
  1506. return IRQ_NONE;
  1507. wrlp(mp, INT_MASK, 0);
  1508. napi_schedule(&mp->napi);
  1509. return IRQ_HANDLED;
  1510. }
  1511. static void handle_link_event(struct mv643xx_eth_private *mp)
  1512. {
  1513. struct net_device *dev = mp->dev;
  1514. u32 port_status;
  1515. int speed;
  1516. int duplex;
  1517. int fc;
  1518. port_status = rdlp(mp, PORT_STATUS);
  1519. if (!(port_status & LINK_UP)) {
  1520. if (netif_carrier_ok(dev)) {
  1521. int i;
  1522. printk(KERN_INFO "%s: link down\n", dev->name);
  1523. netif_carrier_off(dev);
  1524. for (i = 0; i < mp->txq_count; i++) {
  1525. struct tx_queue *txq = mp->txq + i;
  1526. txq_reclaim(txq, txq->tx_ring_size, 1);
  1527. txq_reset_hw_ptr(txq);
  1528. }
  1529. }
  1530. return;
  1531. }
  1532. switch (port_status & PORT_SPEED_MASK) {
  1533. case PORT_SPEED_10:
  1534. speed = 10;
  1535. break;
  1536. case PORT_SPEED_100:
  1537. speed = 100;
  1538. break;
  1539. case PORT_SPEED_1000:
  1540. speed = 1000;
  1541. break;
  1542. default:
  1543. speed = -1;
  1544. break;
  1545. }
  1546. duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
  1547. fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
  1548. printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
  1549. "flow control %sabled\n", dev->name,
  1550. speed, duplex ? "full" : "half",
  1551. fc ? "en" : "dis");
  1552. if (!netif_carrier_ok(dev))
  1553. netif_carrier_on(dev);
  1554. }
  1555. static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
  1556. {
  1557. struct mv643xx_eth_private *mp;
  1558. int work_done;
  1559. mp = container_of(napi, struct mv643xx_eth_private, napi);
  1560. mp->work_rx_refill |= mp->work_rx_oom;
  1561. mp->work_rx_oom = 0;
  1562. work_done = 0;
  1563. while (work_done < budget) {
  1564. u8 queue_mask;
  1565. int queue;
  1566. int work_tbd;
  1567. if (mp->work_link) {
  1568. mp->work_link = 0;
  1569. handle_link_event(mp);
  1570. continue;
  1571. }
  1572. queue_mask = mp->work_tx | mp->work_tx_end |
  1573. mp->work_rx | mp->work_rx_refill;
  1574. if (!queue_mask) {
  1575. if (mv643xx_eth_collect_events(mp))
  1576. continue;
  1577. break;
  1578. }
  1579. queue = fls(queue_mask) - 1;
  1580. queue_mask = 1 << queue;
  1581. work_tbd = budget - work_done;
  1582. if (work_tbd > 16)
  1583. work_tbd = 16;
  1584. if (mp->work_tx_end & queue_mask) {
  1585. txq_kick(mp->txq + queue);
  1586. } else if (mp->work_tx & queue_mask) {
  1587. work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
  1588. txq_maybe_wake(mp->txq + queue);
  1589. } else if (mp->work_rx & queue_mask) {
  1590. work_done += rxq_process(mp->rxq + queue, work_tbd);
  1591. } else if (mp->work_rx_refill & queue_mask) {
  1592. work_done += rxq_refill(mp->rxq + queue, work_tbd);
  1593. } else {
  1594. BUG();
  1595. }
  1596. }
  1597. if (work_done < budget) {
  1598. if (mp->work_rx_oom)
  1599. mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
  1600. napi_complete(napi);
  1601. wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
  1602. }
  1603. return work_done;
  1604. }
  1605. static inline void oom_timer_wrapper(unsigned long data)
  1606. {
  1607. struct mv643xx_eth_private *mp = (void *)data;
  1608. napi_schedule(&mp->napi);
  1609. }
  1610. static void phy_reset(struct mv643xx_eth_private *mp)
  1611. {
  1612. int data;
  1613. data = phy_read(mp->phy, MII_BMCR);
  1614. if (data < 0)
  1615. return;
  1616. data |= BMCR_RESET;
  1617. if (phy_write(mp->phy, MII_BMCR, data) < 0)
  1618. return;
  1619. do {
  1620. data = phy_read(mp->phy, MII_BMCR);
  1621. } while (data >= 0 && data & BMCR_RESET);
  1622. }
  1623. static void port_start(struct mv643xx_eth_private *mp)
  1624. {
  1625. u32 pscr;
  1626. int i;
  1627. /*
  1628. * Perform PHY reset, if there is a PHY.
  1629. */
  1630. if (mp->phy != NULL) {
  1631. struct ethtool_cmd cmd;
  1632. mv643xx_eth_get_settings(mp->dev, &cmd);
  1633. phy_reset(mp);
  1634. mv643xx_eth_set_settings(mp->dev, &cmd);
  1635. }
  1636. /*
  1637. * Configure basic link parameters.
  1638. */
  1639. pscr = rdlp(mp, PORT_SERIAL_CONTROL);
  1640. pscr |= SERIAL_PORT_ENABLE;
  1641. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  1642. pscr |= DO_NOT_FORCE_LINK_FAIL;
  1643. if (mp->phy == NULL)
  1644. pscr |= FORCE_LINK_PASS;
  1645. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  1646. wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
  1647. /*
  1648. * Configure TX path and queues.
  1649. */
  1650. tx_set_rate(mp, 1000000000, 16777216);
  1651. for (i = 0; i < mp->txq_count; i++) {
  1652. struct tx_queue *txq = mp->txq + i;
  1653. txq_reset_hw_ptr(txq);
  1654. txq_set_rate(txq, 1000000000, 16777216);
  1655. txq_set_fixed_prio_mode(txq);
  1656. }
  1657. /*
  1658. * Add configured unicast address to address filter table.
  1659. */
  1660. mv643xx_eth_program_unicast_filter(mp->dev);
  1661. /*
  1662. * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
  1663. * frames to RX queue #0, and include the pseudo-header when
  1664. * calculating receive checksums.
  1665. */
  1666. wrlp(mp, PORT_CONFIG, 0x02000000);
  1667. /*
  1668. * Treat BPDUs as normal multicasts, and disable partition mode.
  1669. */
  1670. wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
  1671. /*
  1672. * Enable the receive queues.
  1673. */
  1674. for (i = 0; i < mp->rxq_count; i++) {
  1675. struct rx_queue *rxq = mp->rxq + i;
  1676. u32 addr;
  1677. addr = (u32)rxq->rx_desc_dma;
  1678. addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
  1679. wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
  1680. rxq_enable(rxq);
  1681. }
  1682. }
  1683. static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
  1684. {
  1685. unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
  1686. u32 val;
  1687. val = rdlp(mp, SDMA_CONFIG);
  1688. if (mp->shared->extended_rx_coal_limit) {
  1689. if (coal > 0xffff)
  1690. coal = 0xffff;
  1691. val &= ~0x023fff80;
  1692. val |= (coal & 0x8000) << 10;
  1693. val |= (coal & 0x7fff) << 7;
  1694. } else {
  1695. if (coal > 0x3fff)
  1696. coal = 0x3fff;
  1697. val &= ~0x003fff00;
  1698. val |= (coal & 0x3fff) << 8;
  1699. }
  1700. wrlp(mp, SDMA_CONFIG, val);
  1701. }
  1702. static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
  1703. {
  1704. unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
  1705. if (coal > 0x3fff)
  1706. coal = 0x3fff;
  1707. wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
  1708. }
  1709. static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
  1710. {
  1711. int skb_size;
  1712. /*
  1713. * Reserve 2+14 bytes for an ethernet header (the hardware
  1714. * automatically prepends 2 bytes of dummy data to each
  1715. * received packet), 16 bytes for up to four VLAN tags, and
  1716. * 4 bytes for the trailing FCS -- 36 bytes total.
  1717. */
  1718. skb_size = mp->dev->mtu + 36;
  1719. /*
  1720. * Make sure that the skb size is a multiple of 8 bytes, as
  1721. * the lower three bits of the receive descriptor's buffer
  1722. * size field are ignored by the hardware.
  1723. */
  1724. mp->skb_size = (skb_size + 7) & ~7;
  1725. }
  1726. static int mv643xx_eth_open(struct net_device *dev)
  1727. {
  1728. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1729. int err;
  1730. int i;
  1731. wrlp(mp, INT_CAUSE, 0);
  1732. wrlp(mp, INT_CAUSE_EXT, 0);
  1733. rdlp(mp, INT_CAUSE_EXT);
  1734. err = request_irq(dev->irq, mv643xx_eth_irq,
  1735. IRQF_SHARED, dev->name, dev);
  1736. if (err) {
  1737. dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
  1738. return -EAGAIN;
  1739. }
  1740. mv643xx_eth_recalc_skb_size(mp);
  1741. napi_enable(&mp->napi);
  1742. skb_queue_head_init(&mp->rx_recycle);
  1743. for (i = 0; i < mp->rxq_count; i++) {
  1744. err = rxq_init(mp, i);
  1745. if (err) {
  1746. while (--i >= 0)
  1747. rxq_deinit(mp->rxq + i);
  1748. goto out;
  1749. }
  1750. rxq_refill(mp->rxq + i, INT_MAX);
  1751. }
  1752. if (mp->work_rx_oom) {
  1753. mp->rx_oom.expires = jiffies + (HZ / 10);
  1754. add_timer(&mp->rx_oom);
  1755. }
  1756. for (i = 0; i < mp->txq_count; i++) {
  1757. err = txq_init(mp, i);
  1758. if (err) {
  1759. while (--i >= 0)
  1760. txq_deinit(mp->txq + i);
  1761. goto out_free;
  1762. }
  1763. }
  1764. netif_carrier_off(dev);
  1765. port_start(mp);
  1766. set_rx_coal(mp, 0);
  1767. set_tx_coal(mp, 0);
  1768. wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
  1769. wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
  1770. return 0;
  1771. out_free:
  1772. for (i = 0; i < mp->rxq_count; i++)
  1773. rxq_deinit(mp->rxq + i);
  1774. out:
  1775. free_irq(dev->irq, dev);
  1776. return err;
  1777. }
  1778. static void port_reset(struct mv643xx_eth_private *mp)
  1779. {
  1780. unsigned int data;
  1781. int i;
  1782. for (i = 0; i < mp->rxq_count; i++)
  1783. rxq_disable(mp->rxq + i);
  1784. for (i = 0; i < mp->txq_count; i++)
  1785. txq_disable(mp->txq + i);
  1786. while (1) {
  1787. u32 ps = rdlp(mp, PORT_STATUS);
  1788. if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
  1789. break;
  1790. udelay(10);
  1791. }
  1792. /* Reset the Enable bit in the Configuration Register */
  1793. data = rdlp(mp, PORT_SERIAL_CONTROL);
  1794. data &= ~(SERIAL_PORT_ENABLE |
  1795. DO_NOT_FORCE_LINK_FAIL |
  1796. FORCE_LINK_PASS);
  1797. wrlp(mp, PORT_SERIAL_CONTROL, data);
  1798. }
  1799. static int mv643xx_eth_stop(struct net_device *dev)
  1800. {
  1801. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1802. int i;
  1803. wrlp(mp, INT_MASK_EXT, 0x00000000);
  1804. wrlp(mp, INT_MASK, 0x00000000);
  1805. rdlp(mp, INT_MASK);
  1806. del_timer_sync(&mp->mib_counters_timer);
  1807. napi_disable(&mp->napi);
  1808. del_timer_sync(&mp->rx_oom);
  1809. netif_carrier_off(dev);
  1810. free_irq(dev->irq, dev);
  1811. port_reset(mp);
  1812. mv643xx_eth_get_stats(dev);
  1813. mib_counters_update(mp);
  1814. skb_queue_purge(&mp->rx_recycle);
  1815. for (i = 0; i < mp->rxq_count; i++)
  1816. rxq_deinit(mp->rxq + i);
  1817. for (i = 0; i < mp->txq_count; i++)
  1818. txq_deinit(mp->txq + i);
  1819. return 0;
  1820. }
  1821. static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1822. {
  1823. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1824. if (mp->phy != NULL)
  1825. return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
  1826. return -EOPNOTSUPP;
  1827. }
  1828. static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
  1829. {
  1830. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1831. if (new_mtu < 64 || new_mtu > 9500)
  1832. return -EINVAL;
  1833. dev->mtu = new_mtu;
  1834. mv643xx_eth_recalc_skb_size(mp);
  1835. tx_set_rate(mp, 1000000000, 16777216);
  1836. if (!netif_running(dev))
  1837. return 0;
  1838. /*
  1839. * Stop and then re-open the interface. This will allocate RX
  1840. * skbs of the new MTU.
  1841. * There is a possible danger that the open will not succeed,
  1842. * due to memory being full.
  1843. */
  1844. mv643xx_eth_stop(dev);
  1845. if (mv643xx_eth_open(dev)) {
  1846. dev_printk(KERN_ERR, &dev->dev,
  1847. "fatal error on re-opening device after "
  1848. "MTU change\n");
  1849. }
  1850. return 0;
  1851. }
  1852. static void tx_timeout_task(struct work_struct *ugly)
  1853. {
  1854. struct mv643xx_eth_private *mp;
  1855. mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
  1856. if (netif_running(mp->dev)) {
  1857. netif_tx_stop_all_queues(mp->dev);
  1858. port_reset(mp);
  1859. port_start(mp);
  1860. netif_tx_wake_all_queues(mp->dev);
  1861. }
  1862. }
  1863. static void mv643xx_eth_tx_timeout(struct net_device *dev)
  1864. {
  1865. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1866. dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
  1867. schedule_work(&mp->tx_timeout_task);
  1868. }
  1869. #ifdef CONFIG_NET_POLL_CONTROLLER
  1870. static void mv643xx_eth_netpoll(struct net_device *dev)
  1871. {
  1872. struct mv643xx_eth_private *mp = netdev_priv(dev);
  1873. wrlp(mp, INT_MASK, 0x00000000);
  1874. rdlp(mp, INT_MASK);
  1875. mv643xx_eth_irq(dev->irq, dev);
  1876. wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
  1877. }
  1878. #endif
  1879. /* platform glue ************************************************************/
  1880. static void
  1881. mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
  1882. struct mbus_dram_target_info *dram)
  1883. {
  1884. void __iomem *base = msp->base;
  1885. u32 win_enable;
  1886. u32 win_protect;
  1887. int i;
  1888. for (i = 0; i < 6; i++) {
  1889. writel(0, base + WINDOW_BASE(i));
  1890. writel(0, base + WINDOW_SIZE(i));
  1891. if (i < 4)
  1892. writel(0, base + WINDOW_REMAP_HIGH(i));
  1893. }
  1894. win_enable = 0x3f;
  1895. win_protect = 0;
  1896. for (i = 0; i < dram->num_cs; i++) {
  1897. struct mbus_dram_window *cs = dram->cs + i;
  1898. writel((cs->base & 0xffff0000) |
  1899. (cs->mbus_attr << 8) |
  1900. dram->mbus_dram_target_id, base + WINDOW_BASE(i));
  1901. writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
  1902. win_enable &= ~(1 << i);
  1903. win_protect |= 3 << (2 * i);
  1904. }
  1905. writel(win_enable, base + WINDOW_BAR_ENABLE);
  1906. msp->win_protect = win_protect;
  1907. }
  1908. static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
  1909. {
  1910. /*
  1911. * Check whether we have a 14-bit coal limit field in bits
  1912. * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
  1913. * SDMA config register.
  1914. */
  1915. writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
  1916. if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
  1917. msp->extended_rx_coal_limit = 1;
  1918. else
  1919. msp->extended_rx_coal_limit = 0;
  1920. /*
  1921. * Check whether the MAC supports TX rate control, and if
  1922. * yes, whether its associated registers are in the old or
  1923. * the new place.
  1924. */
  1925. writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
  1926. if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
  1927. msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
  1928. } else {
  1929. writel(7, msp->base + 0x0400 + TX_BW_RATE);
  1930. if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
  1931. msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
  1932. else
  1933. msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
  1934. }
  1935. }
  1936. static int mv643xx_eth_shared_probe(struct platform_device *pdev)
  1937. {
  1938. static int mv643xx_eth_version_printed;
  1939. struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
  1940. struct mv643xx_eth_shared_private *msp;
  1941. struct resource *res;
  1942. int ret;
  1943. if (!mv643xx_eth_version_printed++)
  1944. printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
  1945. "driver version %s\n", mv643xx_eth_driver_version);
  1946. ret = -EINVAL;
  1947. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1948. if (res == NULL)
  1949. goto out;
  1950. ret = -ENOMEM;
  1951. msp = kmalloc(sizeof(*msp), GFP_KERNEL);
  1952. if (msp == NULL)
  1953. goto out;
  1954. memset(msp, 0, sizeof(*msp));
  1955. msp->base = ioremap(res->start, res->end - res->start + 1);
  1956. if (msp->base == NULL)
  1957. goto out_free;
  1958. /*
  1959. * Set up and register SMI bus.
  1960. */
  1961. if (pd == NULL || pd->shared_smi == NULL) {
  1962. msp->smi_bus = mdiobus_alloc();
  1963. if (msp->smi_bus == NULL)
  1964. goto out_unmap;
  1965. msp->smi_bus->priv = msp;
  1966. msp->smi_bus->name = "mv643xx_eth smi";
  1967. msp->smi_bus->read = smi_bus_read;
  1968. msp->smi_bus->write = smi_bus_write,
  1969. snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
  1970. msp->smi_bus->parent = &pdev->dev;
  1971. msp->smi_bus->phy_mask = 0xffffffff;
  1972. if (mdiobus_register(msp->smi_bus) < 0)
  1973. goto out_free_mii_bus;
  1974. msp->smi = msp;
  1975. } else {
  1976. msp->smi = platform_get_drvdata(pd->shared_smi);
  1977. }
  1978. msp->err_interrupt = NO_IRQ;
  1979. init_waitqueue_head(&msp->smi_busy_wait);
  1980. /*
  1981. * Check whether the error interrupt is hooked up.
  1982. */
  1983. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1984. if (res != NULL) {
  1985. int err;
  1986. err = request_irq(res->start, mv643xx_eth_err_irq,
  1987. IRQF_SHARED, "mv643xx_eth", msp);
  1988. if (!err) {
  1989. writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
  1990. msp->err_interrupt = res->start;
  1991. }
  1992. }
  1993. /*
  1994. * (Re-)program MBUS remapping windows if we are asked to.
  1995. */
  1996. if (pd != NULL && pd->dram != NULL)
  1997. mv643xx_eth_conf_mbus_windows(msp, pd->dram);
  1998. /*
  1999. * Detect hardware parameters.
  2000. */
  2001. msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
  2002. infer_hw_params(msp);
  2003. platform_set_drvdata(pdev, msp);
  2004. return 0;
  2005. out_free_mii_bus:
  2006. mdiobus_free(msp->smi_bus);
  2007. out_unmap:
  2008. iounmap(msp->base);
  2009. out_free:
  2010. kfree(msp);
  2011. out:
  2012. return ret;
  2013. }
  2014. static int mv643xx_eth_shared_remove(struct platform_device *pdev)
  2015. {
  2016. struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
  2017. struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
  2018. if (pd == NULL || pd->shared_smi == NULL) {
  2019. mdiobus_unregister(msp->smi_bus);
  2020. mdiobus_free(msp->smi_bus);
  2021. }
  2022. if (msp->err_interrupt != NO_IRQ)
  2023. free_irq(msp->err_interrupt, msp);
  2024. iounmap(msp->base);
  2025. kfree(msp);
  2026. return 0;
  2027. }
  2028. static struct platform_driver mv643xx_eth_shared_driver = {
  2029. .probe = mv643xx_eth_shared_probe,
  2030. .remove = mv643xx_eth_shared_remove,
  2031. .driver = {
  2032. .name = MV643XX_ETH_SHARED_NAME,
  2033. .owner = THIS_MODULE,
  2034. },
  2035. };
  2036. static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
  2037. {
  2038. int addr_shift = 5 * mp->port_num;
  2039. u32 data;
  2040. data = rdl(mp, PHY_ADDR);
  2041. data &= ~(0x1f << addr_shift);
  2042. data |= (phy_addr & 0x1f) << addr_shift;
  2043. wrl(mp, PHY_ADDR, data);
  2044. }
  2045. static int phy_addr_get(struct mv643xx_eth_private *mp)
  2046. {
  2047. unsigned int data;
  2048. data = rdl(mp, PHY_ADDR);
  2049. return (data >> (5 * mp->port_num)) & 0x1f;
  2050. }
  2051. static void set_params(struct mv643xx_eth_private *mp,
  2052. struct mv643xx_eth_platform_data *pd)
  2053. {
  2054. struct net_device *dev = mp->dev;
  2055. if (is_valid_ether_addr(pd->mac_addr))
  2056. memcpy(dev->dev_addr, pd->mac_addr, 6);
  2057. else
  2058. uc_addr_get(mp, dev->dev_addr);
  2059. mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
  2060. if (pd->rx_queue_size)
  2061. mp->default_rx_ring_size = pd->rx_queue_size;
  2062. mp->rx_desc_sram_addr = pd->rx_sram_addr;
  2063. mp->rx_desc_sram_size = pd->rx_sram_size;
  2064. mp->rxq_count = pd->rx_queue_count ? : 1;
  2065. mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
  2066. if (pd->tx_queue_size)
  2067. mp->default_tx_ring_size = pd->tx_queue_size;
  2068. mp->tx_desc_sram_addr = pd->tx_sram_addr;
  2069. mp->tx_desc_sram_size = pd->tx_sram_size;
  2070. mp->txq_count = pd->tx_queue_count ? : 1;
  2071. }
  2072. static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
  2073. int phy_addr)
  2074. {
  2075. struct mii_bus *bus = mp->shared->smi->smi_bus;
  2076. struct phy_device *phydev;
  2077. int start;
  2078. int num;
  2079. int i;
  2080. if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
  2081. start = phy_addr_get(mp) & 0x1f;
  2082. num = 32;
  2083. } else {
  2084. start = phy_addr & 0x1f;
  2085. num = 1;
  2086. }
  2087. phydev = NULL;
  2088. for (i = 0; i < num; i++) {
  2089. int addr = (start + i) & 0x1f;
  2090. if (bus->phy_map[addr] == NULL)
  2091. mdiobus_scan(bus, addr);
  2092. if (phydev == NULL) {
  2093. phydev = bus->phy_map[addr];
  2094. if (phydev != NULL)
  2095. phy_addr_set(mp, addr);
  2096. }
  2097. }
  2098. return phydev;
  2099. }
  2100. static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
  2101. {
  2102. struct phy_device *phy = mp->phy;
  2103. phy_reset(mp);
  2104. phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
  2105. if (speed == 0) {
  2106. phy->autoneg = AUTONEG_ENABLE;
  2107. phy->speed = 0;
  2108. phy->duplex = 0;
  2109. phy->advertising = phy->supported | ADVERTISED_Autoneg;
  2110. } else {
  2111. phy->autoneg = AUTONEG_DISABLE;
  2112. phy->advertising = 0;
  2113. phy->speed = speed;
  2114. phy->duplex = duplex;
  2115. }
  2116. phy_start_aneg(phy);
  2117. }
  2118. static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
  2119. {
  2120. u32 pscr;
  2121. pscr = rdlp(mp, PORT_SERIAL_CONTROL);
  2122. if (pscr & SERIAL_PORT_ENABLE) {
  2123. pscr &= ~SERIAL_PORT_ENABLE;
  2124. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  2125. }
  2126. pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
  2127. if (mp->phy == NULL) {
  2128. pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
  2129. if (speed == SPEED_1000)
  2130. pscr |= SET_GMII_SPEED_TO_1000;
  2131. else if (speed == SPEED_100)
  2132. pscr |= SET_MII_SPEED_TO_100;
  2133. pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
  2134. pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
  2135. if (duplex == DUPLEX_FULL)
  2136. pscr |= SET_FULL_DUPLEX_MODE;
  2137. }
  2138. wrlp(mp, PORT_SERIAL_CONTROL, pscr);
  2139. }
  2140. static int mv643xx_eth_probe(struct platform_device *pdev)
  2141. {
  2142. struct mv643xx_eth_platform_data *pd;
  2143. struct mv643xx_eth_private *mp;
  2144. struct net_device *dev;
  2145. struct resource *res;
  2146. int err;
  2147. pd = pdev->dev.platform_data;
  2148. if (pd == NULL) {
  2149. dev_printk(KERN_ERR, &pdev->dev,
  2150. "no mv643xx_eth_platform_data\n");
  2151. return -ENODEV;
  2152. }
  2153. if (pd->shared == NULL) {
  2154. dev_printk(KERN_ERR, &pdev->dev,
  2155. "no mv643xx_eth_platform_data->shared\n");
  2156. return -ENODEV;
  2157. }
  2158. dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
  2159. if (!dev)
  2160. return -ENOMEM;
  2161. mp = netdev_priv(dev);
  2162. platform_set_drvdata(pdev, mp);
  2163. mp->shared = platform_get_drvdata(pd->shared);
  2164. mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
  2165. mp->port_num = pd->port_number;
  2166. mp->dev = dev;
  2167. set_params(mp, pd);
  2168. dev->real_num_tx_queues = mp->txq_count;
  2169. if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
  2170. mp->phy = phy_scan(mp, pd->phy_addr);
  2171. if (mp->phy != NULL)
  2172. phy_init(mp, pd->speed, pd->duplex);
  2173. SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
  2174. init_pscr(mp, pd->speed, pd->duplex);
  2175. mib_counters_clear(mp);
  2176. init_timer(&mp->mib_counters_timer);
  2177. mp->mib_counters_timer.data = (unsigned long)mp;
  2178. mp->mib_counters_timer.function = mib_counters_timer_wrapper;
  2179. mp->mib_counters_timer.expires = jiffies + 30 * HZ;
  2180. add_timer(&mp->mib_counters_timer);
  2181. spin_lock_init(&mp->mib_counters_lock);
  2182. INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
  2183. netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
  2184. init_timer(&mp->rx_oom);
  2185. mp->rx_oom.data = (unsigned long)mp;
  2186. mp->rx_oom.function = oom_timer_wrapper;
  2187. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  2188. BUG_ON(!res);
  2189. dev->irq = res->start;
  2190. dev->get_stats = mv643xx_eth_get_stats;
  2191. dev->hard_start_xmit = mv643xx_eth_xmit;
  2192. dev->open = mv643xx_eth_open;
  2193. dev->stop = mv643xx_eth_stop;
  2194. dev->set_rx_mode = mv643xx_eth_set_rx_mode;
  2195. dev->set_mac_address = mv643xx_eth_set_mac_address;
  2196. dev->do_ioctl = mv643xx_eth_ioctl;
  2197. dev->change_mtu = mv643xx_eth_change_mtu;
  2198. dev->tx_timeout = mv643xx_eth_tx_timeout;
  2199. #ifdef CONFIG_NET_POLL_CONTROLLER
  2200. dev->poll_controller = mv643xx_eth_netpoll;
  2201. #endif
  2202. dev->watchdog_timeo = 2 * HZ;
  2203. dev->base_addr = 0;
  2204. dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
  2205. dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
  2206. SET_NETDEV_DEV(dev, &pdev->dev);
  2207. if (mp->shared->win_protect)
  2208. wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
  2209. err = register_netdev(dev);
  2210. if (err)
  2211. goto out;
  2212. dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
  2213. mp->port_num, dev->dev_addr);
  2214. if (mp->tx_desc_sram_size > 0)
  2215. dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
  2216. return 0;
  2217. out:
  2218. free_netdev(dev);
  2219. return err;
  2220. }
  2221. static int mv643xx_eth_remove(struct platform_device *pdev)
  2222. {
  2223. struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
  2224. unregister_netdev(mp->dev);
  2225. if (mp->phy != NULL)
  2226. phy_detach(mp->phy);
  2227. flush_scheduled_work();
  2228. free_netdev(mp->dev);
  2229. platform_set_drvdata(pdev, NULL);
  2230. return 0;
  2231. }
  2232. static void mv643xx_eth_shutdown(struct platform_device *pdev)
  2233. {
  2234. struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
  2235. /* Mask all interrupts on ethernet port */
  2236. wrlp(mp, INT_MASK, 0);
  2237. rdlp(mp, INT_MASK);
  2238. if (netif_running(mp->dev))
  2239. port_reset(mp);
  2240. }
  2241. static struct platform_driver mv643xx_eth_driver = {
  2242. .probe = mv643xx_eth_probe,
  2243. .remove = mv643xx_eth_remove,
  2244. .shutdown = mv643xx_eth_shutdown,
  2245. .driver = {
  2246. .name = MV643XX_ETH_NAME,
  2247. .owner = THIS_MODULE,
  2248. },
  2249. };
  2250. static int __init mv643xx_eth_init_module(void)
  2251. {
  2252. int rc;
  2253. rc = platform_driver_register(&mv643xx_eth_shared_driver);
  2254. if (!rc) {
  2255. rc = platform_driver_register(&mv643xx_eth_driver);
  2256. if (rc)
  2257. platform_driver_unregister(&mv643xx_eth_shared_driver);
  2258. }
  2259. return rc;
  2260. }
  2261. module_init(mv643xx_eth_init_module);
  2262. static void __exit mv643xx_eth_cleanup_module(void)
  2263. {
  2264. platform_driver_unregister(&mv643xx_eth_driver);
  2265. platform_driver_unregister(&mv643xx_eth_shared_driver);
  2266. }
  2267. module_exit(mv643xx_eth_cleanup_module);
  2268. MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
  2269. "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
  2270. MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
  2271. MODULE_LICENSE("GPL");
  2272. MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
  2273. MODULE_ALIAS("platform:" MV643XX_ETH_NAME);