twl4030.c 46 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. };
  122. /*
  123. * read twl4030 register cache
  124. */
  125. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  126. unsigned int reg)
  127. {
  128. u8 *cache = codec->reg_cache;
  129. if (reg >= TWL4030_CACHEREGNUM)
  130. return -EIO;
  131. return cache[reg];
  132. }
  133. /*
  134. * write twl4030 register cache
  135. */
  136. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  137. u8 reg, u8 value)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return;
  142. cache[reg] = value;
  143. }
  144. /*
  145. * write to the twl4030 register space
  146. */
  147. static int twl4030_write(struct snd_soc_codec *codec,
  148. unsigned int reg, unsigned int value)
  149. {
  150. twl4030_write_reg_cache(codec, reg, value);
  151. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  152. }
  153. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  154. {
  155. struct twl4030_priv *twl4030 = codec->private_data;
  156. u8 mode;
  157. if (enable == twl4030->codec_powered)
  158. return;
  159. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  160. if (enable)
  161. mode |= TWL4030_CODECPDZ;
  162. else
  163. mode &= ~TWL4030_CODECPDZ;
  164. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  165. twl4030->codec_powered = enable;
  166. /* REVISIT: this delay is present in TI sample drivers */
  167. /* but there seems to be no TRM requirement for it */
  168. udelay(10);
  169. }
  170. static void twl4030_init_chip(struct snd_soc_codec *codec)
  171. {
  172. int i;
  173. /* clear CODECPDZ prior to setting register defaults */
  174. twl4030_codec_enable(codec, 0);
  175. /* set all audio section registers to reasonable defaults */
  176. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  177. twl4030_write(codec, i, twl4030_reg[i]);
  178. }
  179. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  180. {
  181. struct twl4030_priv *twl4030 = codec->private_data;
  182. u8 reg_val;
  183. if (mute == twl4030->codec_muted)
  184. return;
  185. if (mute) {
  186. /* Bypass the reg_cache and mute the volumes
  187. * Headset mute is done in it's own event handler
  188. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  189. */
  190. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  191. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  192. reg_val & (~TWL4030_EAR_GAIN),
  193. TWL4030_REG_EAR_CTL);
  194. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  195. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  196. reg_val & (~TWL4030_PREDL_GAIN),
  197. TWL4030_REG_PREDL_CTL);
  198. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  199. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  200. reg_val & (~TWL4030_PREDR_GAIN),
  201. TWL4030_REG_PREDL_CTL);
  202. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  203. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  204. reg_val & (~TWL4030_PRECKL_GAIN),
  205. TWL4030_REG_PRECKL_CTL);
  206. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  207. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  208. reg_val & (~TWL4030_PRECKL_GAIN),
  209. TWL4030_REG_PRECKR_CTL);
  210. /* Disable PLL */
  211. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  212. reg_val &= ~TWL4030_APLL_EN;
  213. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  214. } else {
  215. /* Restore the volumes
  216. * Headset mute is done in it's own event handler
  217. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  218. */
  219. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  220. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  221. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  222. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  223. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  224. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  225. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  227. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  229. /* Enable PLL */
  230. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  231. reg_val |= TWL4030_APLL_EN;
  232. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  233. }
  234. twl4030->codec_muted = mute;
  235. }
  236. static void twl4030_power_up(struct snd_soc_codec *codec)
  237. {
  238. struct twl4030_priv *twl4030 = codec->private_data;
  239. u8 anamicl, regmisc1, byte;
  240. int i = 0;
  241. if (twl4030->codec_powered)
  242. return;
  243. /* set CODECPDZ to turn on codec */
  244. twl4030_codec_enable(codec, 1);
  245. /* initiate offset cancellation */
  246. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  247. twl4030_write(codec, TWL4030_REG_ANAMICL,
  248. anamicl | TWL4030_CNCL_OFFSET_START);
  249. /* wait for offset cancellation to complete */
  250. do {
  251. /* this takes a little while, so don't slam i2c */
  252. udelay(2000);
  253. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  254. TWL4030_REG_ANAMICL);
  255. } while ((i++ < 100) &&
  256. ((byte & TWL4030_CNCL_OFFSET_START) ==
  257. TWL4030_CNCL_OFFSET_START));
  258. /* Make sure that the reg_cache has the same value as the HW */
  259. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  260. /* anti-pop when changing analog gain */
  261. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  262. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  263. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  264. /* toggle CODECPDZ as per TRM */
  265. twl4030_codec_enable(codec, 0);
  266. twl4030_codec_enable(codec, 1);
  267. }
  268. /*
  269. * Unconditional power down
  270. */
  271. static void twl4030_power_down(struct snd_soc_codec *codec)
  272. {
  273. /* power down */
  274. twl4030_codec_enable(codec, 0);
  275. }
  276. /* Earpiece */
  277. static const char *twl4030_earpiece_texts[] =
  278. {"Off", "DACL1", "DACL2", "DACR1"};
  279. static const unsigned int twl4030_earpiece_values[] =
  280. {0x0, 0x1, 0x2, 0x4};
  281. static const struct soc_enum twl4030_earpiece_enum =
  282. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
  283. ARRAY_SIZE(twl4030_earpiece_texts),
  284. twl4030_earpiece_texts,
  285. twl4030_earpiece_values);
  286. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  287. SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
  288. /* PreDrive Left */
  289. static const char *twl4030_predrivel_texts[] =
  290. {"Off", "DACL1", "DACL2", "DACR2"};
  291. static const unsigned int twl4030_predrivel_values[] =
  292. {0x0, 0x1, 0x2, 0x4};
  293. static const struct soc_enum twl4030_predrivel_enum =
  294. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
  295. ARRAY_SIZE(twl4030_predrivel_texts),
  296. twl4030_predrivel_texts,
  297. twl4030_predrivel_values);
  298. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  299. SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
  300. /* PreDrive Right */
  301. static const char *twl4030_predriver_texts[] =
  302. {"Off", "DACR1", "DACR2", "DACL2"};
  303. static const unsigned int twl4030_predriver_values[] =
  304. {0x0, 0x1, 0x2, 0x4};
  305. static const struct soc_enum twl4030_predriver_enum =
  306. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
  307. ARRAY_SIZE(twl4030_predriver_texts),
  308. twl4030_predriver_texts,
  309. twl4030_predriver_values);
  310. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  311. SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
  312. /* Headset Left */
  313. static const char *twl4030_hsol_texts[] =
  314. {"Off", "DACL1", "DACL2"};
  315. static const struct soc_enum twl4030_hsol_enum =
  316. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  317. ARRAY_SIZE(twl4030_hsol_texts),
  318. twl4030_hsol_texts);
  319. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  320. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  321. /* Headset Right */
  322. static const char *twl4030_hsor_texts[] =
  323. {"Off", "DACR1", "DACR2"};
  324. static const struct soc_enum twl4030_hsor_enum =
  325. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  326. ARRAY_SIZE(twl4030_hsor_texts),
  327. twl4030_hsor_texts);
  328. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  329. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  330. /* Carkit Left */
  331. static const char *twl4030_carkitl_texts[] =
  332. {"Off", "DACL1", "DACL2"};
  333. static const struct soc_enum twl4030_carkitl_enum =
  334. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  335. ARRAY_SIZE(twl4030_carkitl_texts),
  336. twl4030_carkitl_texts);
  337. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  338. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  339. /* Carkit Right */
  340. static const char *twl4030_carkitr_texts[] =
  341. {"Off", "DACR1", "DACR2"};
  342. static const struct soc_enum twl4030_carkitr_enum =
  343. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  344. ARRAY_SIZE(twl4030_carkitr_texts),
  345. twl4030_carkitr_texts);
  346. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  347. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  348. /* Handsfree Left */
  349. static const char *twl4030_handsfreel_texts[] =
  350. {"Voice", "DACL1", "DACL2", "DACR2"};
  351. static const struct soc_enum twl4030_handsfreel_enum =
  352. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  353. ARRAY_SIZE(twl4030_handsfreel_texts),
  354. twl4030_handsfreel_texts);
  355. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  356. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  357. /* Handsfree Right */
  358. static const char *twl4030_handsfreer_texts[] =
  359. {"Voice", "DACR1", "DACR2", "DACL2"};
  360. static const struct soc_enum twl4030_handsfreer_enum =
  361. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  362. ARRAY_SIZE(twl4030_handsfreer_texts),
  363. twl4030_handsfreer_texts);
  364. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  365. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  366. /* Left analog microphone selection */
  367. static const char *twl4030_analoglmic_texts[] =
  368. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  369. static const unsigned int twl4030_analoglmic_values[] =
  370. {0x0, 0x1, 0x2, 0x4, 0x8};
  371. static const struct soc_enum twl4030_analoglmic_enum =
  372. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  373. ARRAY_SIZE(twl4030_analoglmic_texts),
  374. twl4030_analoglmic_texts,
  375. twl4030_analoglmic_values);
  376. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  377. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  378. /* Right analog microphone selection */
  379. static const char *twl4030_analogrmic_texts[] =
  380. {"Off", "Sub mic", "AUXR"};
  381. static const unsigned int twl4030_analogrmic_values[] =
  382. {0x0, 0x1, 0x4};
  383. static const struct soc_enum twl4030_analogrmic_enum =
  384. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  385. ARRAY_SIZE(twl4030_analogrmic_texts),
  386. twl4030_analogrmic_texts,
  387. twl4030_analogrmic_values);
  388. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  389. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  390. /* TX1 L/R Analog/Digital microphone selection */
  391. static const char *twl4030_micpathtx1_texts[] =
  392. {"Analog", "Digimic0"};
  393. static const struct soc_enum twl4030_micpathtx1_enum =
  394. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  395. ARRAY_SIZE(twl4030_micpathtx1_texts),
  396. twl4030_micpathtx1_texts);
  397. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  398. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  399. /* TX2 L/R Analog/Digital microphone selection */
  400. static const char *twl4030_micpathtx2_texts[] =
  401. {"Analog", "Digimic1"};
  402. static const struct soc_enum twl4030_micpathtx2_enum =
  403. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  404. ARRAY_SIZE(twl4030_micpathtx2_texts),
  405. twl4030_micpathtx2_texts);
  406. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  407. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  408. /* Analog bypass for AudioR1 */
  409. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  410. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  411. /* Analog bypass for AudioL1 */
  412. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  413. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  414. /* Analog bypass for AudioR2 */
  415. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  416. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  417. /* Analog bypass for AudioL2 */
  418. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  419. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  420. /* Digital bypass gain, 0 mutes the bypass */
  421. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  422. TLV_DB_RANGE_HEAD(2),
  423. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  424. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  425. };
  426. /* Digital bypass left (TX1L -> RX2L) */
  427. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  428. SOC_DAPM_SINGLE_TLV("Volume",
  429. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  430. twl4030_dapm_dbypass_tlv);
  431. /* Digital bypass right (TX1R -> RX2R) */
  432. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  433. SOC_DAPM_SINGLE_TLV("Volume",
  434. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  435. twl4030_dapm_dbypass_tlv);
  436. static int micpath_event(struct snd_soc_dapm_widget *w,
  437. struct snd_kcontrol *kcontrol, int event)
  438. {
  439. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  440. unsigned char adcmicsel, micbias_ctl;
  441. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  442. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  443. /* Prepare the bits for the given TX path:
  444. * shift_l == 0: TX1 microphone path
  445. * shift_l == 2: TX2 microphone path */
  446. if (e->shift_l) {
  447. /* TX2 microphone path */
  448. if (adcmicsel & TWL4030_TX2IN_SEL)
  449. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  450. else
  451. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  452. } else {
  453. /* TX1 microphone path */
  454. if (adcmicsel & TWL4030_TX1IN_SEL)
  455. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  456. else
  457. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  458. }
  459. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  460. return 0;
  461. }
  462. static int handsfree_event(struct snd_soc_dapm_widget *w,
  463. struct snd_kcontrol *kcontrol, int event)
  464. {
  465. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  466. unsigned char hs_ctl;
  467. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  468. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  469. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  470. twl4030_write(w->codec, e->reg, hs_ctl);
  471. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  472. twl4030_write(w->codec, e->reg, hs_ctl);
  473. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  474. twl4030_write(w->codec, e->reg, hs_ctl);
  475. } else {
  476. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  477. | TWL4030_HF_CTL_HB_EN);
  478. twl4030_write(w->codec, e->reg, hs_ctl);
  479. }
  480. return 0;
  481. }
  482. static int headsetl_event(struct snd_soc_dapm_widget *w,
  483. struct snd_kcontrol *kcontrol, int event)
  484. {
  485. unsigned char hs_gain, hs_pop;
  486. /* Save the current volume */
  487. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  488. switch (event) {
  489. case SND_SOC_DAPM_POST_PMU:
  490. /* Do the anti-pop/bias ramp enable according to the TRM */
  491. hs_pop = TWL4030_RAMP_DELAY_645MS;
  492. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  493. hs_pop |= TWL4030_VMID_EN;
  494. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  495. /* Is this needed? Can we just use whatever gain here? */
  496. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  497. (hs_gain & (~0x0f)) | 0x0a);
  498. hs_pop |= TWL4030_RAMP_EN;
  499. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  500. /* Restore the original volume */
  501. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  502. break;
  503. case SND_SOC_DAPM_POST_PMD:
  504. /* Do the anti-pop/bias ramp disable according to the TRM */
  505. hs_pop = twl4030_read_reg_cache(w->codec,
  506. TWL4030_REG_HS_POPN_SET);
  507. hs_pop &= ~TWL4030_RAMP_EN;
  508. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  509. /* Bypass the reg_cache to mute the headset */
  510. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  511. hs_gain & (~0x0f),
  512. TWL4030_REG_HS_GAIN_SET);
  513. hs_pop &= ~TWL4030_VMID_EN;
  514. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  515. break;
  516. }
  517. return 0;
  518. }
  519. static int bypass_event(struct snd_soc_dapm_widget *w,
  520. struct snd_kcontrol *kcontrol, int event)
  521. {
  522. struct soc_mixer_control *m =
  523. (struct soc_mixer_control *)w->kcontrols->private_value;
  524. struct twl4030_priv *twl4030 = w->codec->private_data;
  525. unsigned char reg;
  526. reg = twl4030_read_reg_cache(w->codec, m->reg);
  527. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  528. /* Analog bypass */
  529. if (reg & (1 << m->shift))
  530. twl4030->bypass_state |=
  531. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  532. else
  533. twl4030->bypass_state &=
  534. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  535. } else {
  536. /* Digital bypass */
  537. if (reg & (0x7 << m->shift))
  538. twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
  539. else
  540. twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
  541. }
  542. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  543. if (twl4030->bypass_state)
  544. twl4030_codec_mute(w->codec, 0);
  545. else
  546. twl4030_codec_mute(w->codec, 1);
  547. }
  548. return 0;
  549. }
  550. /*
  551. * Some of the gain controls in TWL (mostly those which are associated with
  552. * the outputs) are implemented in an interesting way:
  553. * 0x0 : Power down (mute)
  554. * 0x1 : 6dB
  555. * 0x2 : 0 dB
  556. * 0x3 : -6 dB
  557. * Inverting not going to help with these.
  558. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  559. */
  560. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  561. xinvert, tlv_array) \
  562. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  563. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  564. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  565. .tlv.p = (tlv_array), \
  566. .info = snd_soc_info_volsw, \
  567. .get = snd_soc_get_volsw_twl4030, \
  568. .put = snd_soc_put_volsw_twl4030, \
  569. .private_value = (unsigned long)&(struct soc_mixer_control) \
  570. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  571. .max = xmax, .invert = xinvert} }
  572. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  573. xinvert, tlv_array) \
  574. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  575. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  576. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  577. .tlv.p = (tlv_array), \
  578. .info = snd_soc_info_volsw_2r, \
  579. .get = snd_soc_get_volsw_r2_twl4030,\
  580. .put = snd_soc_put_volsw_r2_twl4030, \
  581. .private_value = (unsigned long)&(struct soc_mixer_control) \
  582. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  583. .rshift = xshift, .max = xmax, .invert = xinvert} }
  584. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  585. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  586. xinvert, tlv_array)
  587. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  588. struct snd_ctl_elem_value *ucontrol)
  589. {
  590. struct soc_mixer_control *mc =
  591. (struct soc_mixer_control *)kcontrol->private_value;
  592. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  593. unsigned int reg = mc->reg;
  594. unsigned int shift = mc->shift;
  595. unsigned int rshift = mc->rshift;
  596. int max = mc->max;
  597. int mask = (1 << fls(max)) - 1;
  598. ucontrol->value.integer.value[0] =
  599. (snd_soc_read(codec, reg) >> shift) & mask;
  600. if (ucontrol->value.integer.value[0])
  601. ucontrol->value.integer.value[0] =
  602. max + 1 - ucontrol->value.integer.value[0];
  603. if (shift != rshift) {
  604. ucontrol->value.integer.value[1] =
  605. (snd_soc_read(codec, reg) >> rshift) & mask;
  606. if (ucontrol->value.integer.value[1])
  607. ucontrol->value.integer.value[1] =
  608. max + 1 - ucontrol->value.integer.value[1];
  609. }
  610. return 0;
  611. }
  612. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  613. struct snd_ctl_elem_value *ucontrol)
  614. {
  615. struct soc_mixer_control *mc =
  616. (struct soc_mixer_control *)kcontrol->private_value;
  617. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  618. unsigned int reg = mc->reg;
  619. unsigned int shift = mc->shift;
  620. unsigned int rshift = mc->rshift;
  621. int max = mc->max;
  622. int mask = (1 << fls(max)) - 1;
  623. unsigned short val, val2, val_mask;
  624. val = (ucontrol->value.integer.value[0] & mask);
  625. val_mask = mask << shift;
  626. if (val)
  627. val = max + 1 - val;
  628. val = val << shift;
  629. if (shift != rshift) {
  630. val2 = (ucontrol->value.integer.value[1] & mask);
  631. val_mask |= mask << rshift;
  632. if (val2)
  633. val2 = max + 1 - val2;
  634. val |= val2 << rshift;
  635. }
  636. return snd_soc_update_bits(codec, reg, val_mask, val);
  637. }
  638. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  639. struct snd_ctl_elem_value *ucontrol)
  640. {
  641. struct soc_mixer_control *mc =
  642. (struct soc_mixer_control *)kcontrol->private_value;
  643. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  644. unsigned int reg = mc->reg;
  645. unsigned int reg2 = mc->rreg;
  646. unsigned int shift = mc->shift;
  647. int max = mc->max;
  648. int mask = (1<<fls(max))-1;
  649. ucontrol->value.integer.value[0] =
  650. (snd_soc_read(codec, reg) >> shift) & mask;
  651. ucontrol->value.integer.value[1] =
  652. (snd_soc_read(codec, reg2) >> shift) & mask;
  653. if (ucontrol->value.integer.value[0])
  654. ucontrol->value.integer.value[0] =
  655. max + 1 - ucontrol->value.integer.value[0];
  656. if (ucontrol->value.integer.value[1])
  657. ucontrol->value.integer.value[1] =
  658. max + 1 - ucontrol->value.integer.value[1];
  659. return 0;
  660. }
  661. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  662. struct snd_ctl_elem_value *ucontrol)
  663. {
  664. struct soc_mixer_control *mc =
  665. (struct soc_mixer_control *)kcontrol->private_value;
  666. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  667. unsigned int reg = mc->reg;
  668. unsigned int reg2 = mc->rreg;
  669. unsigned int shift = mc->shift;
  670. int max = mc->max;
  671. int mask = (1 << fls(max)) - 1;
  672. int err;
  673. unsigned short val, val2, val_mask;
  674. val_mask = mask << shift;
  675. val = (ucontrol->value.integer.value[0] & mask);
  676. val2 = (ucontrol->value.integer.value[1] & mask);
  677. if (val)
  678. val = max + 1 - val;
  679. if (val2)
  680. val2 = max + 1 - val2;
  681. val = val << shift;
  682. val2 = val2 << shift;
  683. err = snd_soc_update_bits(codec, reg, val_mask, val);
  684. if (err < 0)
  685. return err;
  686. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  687. return err;
  688. }
  689. /*
  690. * FGAIN volume control:
  691. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  692. */
  693. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  694. /*
  695. * CGAIN volume control:
  696. * 0 dB to 12 dB in 6 dB steps
  697. * value 2 and 3 means 12 dB
  698. */
  699. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  700. /*
  701. * Analog playback gain
  702. * -24 dB to 12 dB in 2 dB steps
  703. */
  704. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  705. /*
  706. * Gain controls tied to outputs
  707. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  708. */
  709. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  710. /*
  711. * Capture gain after the ADCs
  712. * from 0 dB to 31 dB in 1 dB steps
  713. */
  714. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  715. /*
  716. * Gain control for input amplifiers
  717. * 0 dB to 30 dB in 6 dB steps
  718. */
  719. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  720. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  721. /* Common playback gain controls */
  722. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  723. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  724. 0, 0x3f, 0, digital_fine_tlv),
  725. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  726. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  727. 0, 0x3f, 0, digital_fine_tlv),
  728. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  729. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  730. 6, 0x2, 0, digital_coarse_tlv),
  731. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  732. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  733. 6, 0x2, 0, digital_coarse_tlv),
  734. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  735. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  736. 3, 0x12, 1, analog_tlv),
  737. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  738. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  739. 3, 0x12, 1, analog_tlv),
  740. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  741. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  742. 1, 1, 0),
  743. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  744. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  745. 1, 1, 0),
  746. /* Separate output gain controls */
  747. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  748. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  749. 4, 3, 0, output_tvl),
  750. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  751. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  752. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  753. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  754. 4, 3, 0, output_tvl),
  755. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  756. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  757. /* Common capture gain controls */
  758. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  759. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  760. 0, 0x1f, 0, digital_capture_tlv),
  761. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  762. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  763. 0, 0x1f, 0, digital_capture_tlv),
  764. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  765. 0, 3, 5, 0, input_gain_tlv),
  766. };
  767. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  768. /* Left channel inputs */
  769. SND_SOC_DAPM_INPUT("MAINMIC"),
  770. SND_SOC_DAPM_INPUT("HSMIC"),
  771. SND_SOC_DAPM_INPUT("AUXL"),
  772. SND_SOC_DAPM_INPUT("CARKITMIC"),
  773. /* Right channel inputs */
  774. SND_SOC_DAPM_INPUT("SUBMIC"),
  775. SND_SOC_DAPM_INPUT("AUXR"),
  776. /* Digital microphones (Stereo) */
  777. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  778. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  779. /* Outputs */
  780. SND_SOC_DAPM_OUTPUT("OUTL"),
  781. SND_SOC_DAPM_OUTPUT("OUTR"),
  782. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  783. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  784. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  785. SND_SOC_DAPM_OUTPUT("HSOL"),
  786. SND_SOC_DAPM_OUTPUT("HSOR"),
  787. SND_SOC_DAPM_OUTPUT("CARKITL"),
  788. SND_SOC_DAPM_OUTPUT("CARKITR"),
  789. SND_SOC_DAPM_OUTPUT("HFL"),
  790. SND_SOC_DAPM_OUTPUT("HFR"),
  791. /* DACs */
  792. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  793. SND_SOC_NOPM, 0, 0),
  794. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  795. SND_SOC_NOPM, 0, 0),
  796. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  797. SND_SOC_NOPM, 0, 0),
  798. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  799. SND_SOC_NOPM, 0, 0),
  800. /* Analog PGAs */
  801. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  802. 0, 0, NULL, 0),
  803. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  804. 0, 0, NULL, 0),
  805. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  806. 0, 0, NULL, 0),
  807. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  808. 0, 0, NULL, 0),
  809. /* Analog bypasses */
  810. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  811. &twl4030_dapm_abypassr1_control, bypass_event,
  812. SND_SOC_DAPM_POST_REG),
  813. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  814. &twl4030_dapm_abypassl1_control,
  815. bypass_event, SND_SOC_DAPM_POST_REG),
  816. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  817. &twl4030_dapm_abypassr2_control,
  818. bypass_event, SND_SOC_DAPM_POST_REG),
  819. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  820. &twl4030_dapm_abypassl2_control,
  821. bypass_event, SND_SOC_DAPM_POST_REG),
  822. /* Digital bypasses */
  823. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  824. &twl4030_dapm_dbypassl_control, bypass_event,
  825. SND_SOC_DAPM_POST_REG),
  826. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  827. &twl4030_dapm_dbypassr_control, bypass_event,
  828. SND_SOC_DAPM_POST_REG),
  829. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  830. 0, 0, NULL, 0),
  831. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  832. 1, 0, NULL, 0),
  833. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  834. 2, 0, NULL, 0),
  835. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  836. 3, 0, NULL, 0),
  837. /* Output MUX controls */
  838. /* Earpiece */
  839. SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  840. &twl4030_dapm_earpiece_control),
  841. /* PreDrivL/R */
  842. SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  843. &twl4030_dapm_predrivel_control),
  844. SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  845. &twl4030_dapm_predriver_control),
  846. /* HeadsetL/R */
  847. SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  848. &twl4030_dapm_hsol_control, headsetl_event,
  849. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  850. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  851. &twl4030_dapm_hsor_control),
  852. /* CarkitL/R */
  853. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  854. &twl4030_dapm_carkitl_control),
  855. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  856. &twl4030_dapm_carkitr_control),
  857. /* HandsfreeL/R */
  858. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  859. &twl4030_dapm_handsfreel_control, handsfree_event,
  860. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  861. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  862. &twl4030_dapm_handsfreer_control, handsfree_event,
  863. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  864. /* Introducing four virtual ADC, since TWL4030 have four channel for
  865. capture */
  866. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  867. SND_SOC_NOPM, 0, 0),
  868. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  869. SND_SOC_NOPM, 0, 0),
  870. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  871. SND_SOC_NOPM, 0, 0),
  872. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  873. SND_SOC_NOPM, 0, 0),
  874. /* Analog/Digital mic path selection.
  875. TX1 Left/Right: either analog Left/Right or Digimic0
  876. TX2 Left/Right: either analog Left/Right or Digimic1 */
  877. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  878. &twl4030_dapm_micpathtx1_control, micpath_event,
  879. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  880. SND_SOC_DAPM_POST_REG),
  881. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  882. &twl4030_dapm_micpathtx2_control, micpath_event,
  883. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  884. SND_SOC_DAPM_POST_REG),
  885. /* Analog input muxes with switch for the capture amplifiers */
  886. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  887. TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
  888. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  889. TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
  890. SND_SOC_DAPM_PGA("ADC Physical Left",
  891. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  892. SND_SOC_DAPM_PGA("ADC Physical Right",
  893. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  894. SND_SOC_DAPM_PGA("Digimic0 Enable",
  895. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  896. SND_SOC_DAPM_PGA("Digimic1 Enable",
  897. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  898. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  899. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  900. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  901. };
  902. static const struct snd_soc_dapm_route intercon[] = {
  903. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  904. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  905. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  906. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  907. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  908. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  909. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  910. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  911. /* Internal playback routings */
  912. /* Earpiece */
  913. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  914. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  915. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  916. /* PreDrivL */
  917. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  918. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  919. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  920. /* PreDrivR */
  921. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  922. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  923. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  924. /* HeadsetL */
  925. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  926. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  927. /* HeadsetR */
  928. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  929. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  930. /* CarkitL */
  931. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  932. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  933. /* CarkitR */
  934. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  935. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  936. /* HandsfreeL */
  937. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  938. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  939. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  940. /* HandsfreeR */
  941. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  942. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  943. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  944. /* outputs */
  945. {"OUTL", NULL, "ARXL2_APGA"},
  946. {"OUTR", NULL, "ARXR2_APGA"},
  947. {"EARPIECE", NULL, "Earpiece Mux"},
  948. {"PREDRIVEL", NULL, "PredriveL Mux"},
  949. {"PREDRIVER", NULL, "PredriveR Mux"},
  950. {"HSOL", NULL, "HeadsetL Mux"},
  951. {"HSOR", NULL, "HeadsetR Mux"},
  952. {"CARKITL", NULL, "CarkitL Mux"},
  953. {"CARKITR", NULL, "CarkitR Mux"},
  954. {"HFL", NULL, "HandsfreeL Mux"},
  955. {"HFR", NULL, "HandsfreeR Mux"},
  956. /* Capture path */
  957. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  958. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  959. {"Analog Left Capture Route", "AUXL", "AUXL"},
  960. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  961. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  962. {"Analog Right Capture Route", "AUXR", "AUXR"},
  963. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  964. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  965. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  966. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  967. /* TX1 Left capture path */
  968. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  969. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  970. /* TX1 Right capture path */
  971. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  972. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  973. /* TX2 Left capture path */
  974. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  975. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  976. /* TX2 Right capture path */
  977. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  978. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  979. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  980. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  981. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  982. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  983. /* Analog bypass routes */
  984. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  985. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  986. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  987. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  988. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  989. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  990. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  991. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  992. /* Digital bypass routes */
  993. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  994. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  995. {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
  996. {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
  997. };
  998. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  999. {
  1000. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1001. ARRAY_SIZE(twl4030_dapm_widgets));
  1002. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1003. snd_soc_dapm_new_widgets(codec);
  1004. return 0;
  1005. }
  1006. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1007. enum snd_soc_bias_level level)
  1008. {
  1009. struct twl4030_priv *twl4030 = codec->private_data;
  1010. switch (level) {
  1011. case SND_SOC_BIAS_ON:
  1012. twl4030_codec_mute(codec, 0);
  1013. break;
  1014. case SND_SOC_BIAS_PREPARE:
  1015. twl4030_power_up(codec);
  1016. if (twl4030->bypass_state)
  1017. twl4030_codec_mute(codec, 0);
  1018. else
  1019. twl4030_codec_mute(codec, 1);
  1020. break;
  1021. case SND_SOC_BIAS_STANDBY:
  1022. twl4030_power_up(codec);
  1023. if (twl4030->bypass_state)
  1024. twl4030_codec_mute(codec, 0);
  1025. else
  1026. twl4030_codec_mute(codec, 1);
  1027. break;
  1028. case SND_SOC_BIAS_OFF:
  1029. twl4030_power_down(codec);
  1030. break;
  1031. }
  1032. codec->bias_level = level;
  1033. return 0;
  1034. }
  1035. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1036. struct snd_pcm_hw_params *params,
  1037. struct snd_soc_dai *dai)
  1038. {
  1039. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1040. struct snd_soc_device *socdev = rtd->socdev;
  1041. struct snd_soc_codec *codec = socdev->card->codec;
  1042. u8 mode, old_mode, format, old_format;
  1043. /* bit rate */
  1044. old_mode = twl4030_read_reg_cache(codec,
  1045. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1046. mode = old_mode & ~TWL4030_APLL_RATE;
  1047. switch (params_rate(params)) {
  1048. case 8000:
  1049. mode |= TWL4030_APLL_RATE_8000;
  1050. break;
  1051. case 11025:
  1052. mode |= TWL4030_APLL_RATE_11025;
  1053. break;
  1054. case 12000:
  1055. mode |= TWL4030_APLL_RATE_12000;
  1056. break;
  1057. case 16000:
  1058. mode |= TWL4030_APLL_RATE_16000;
  1059. break;
  1060. case 22050:
  1061. mode |= TWL4030_APLL_RATE_22050;
  1062. break;
  1063. case 24000:
  1064. mode |= TWL4030_APLL_RATE_24000;
  1065. break;
  1066. case 32000:
  1067. mode |= TWL4030_APLL_RATE_32000;
  1068. break;
  1069. case 44100:
  1070. mode |= TWL4030_APLL_RATE_44100;
  1071. break;
  1072. case 48000:
  1073. mode |= TWL4030_APLL_RATE_48000;
  1074. break;
  1075. default:
  1076. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1077. params_rate(params));
  1078. return -EINVAL;
  1079. }
  1080. if (mode != old_mode) {
  1081. /* change rate and set CODECPDZ */
  1082. twl4030_codec_enable(codec, 0);
  1083. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1084. twl4030_codec_enable(codec, 1);
  1085. }
  1086. /* sample size */
  1087. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1088. format = old_format;
  1089. format &= ~TWL4030_DATA_WIDTH;
  1090. switch (params_format(params)) {
  1091. case SNDRV_PCM_FORMAT_S16_LE:
  1092. format |= TWL4030_DATA_WIDTH_16S_16W;
  1093. break;
  1094. case SNDRV_PCM_FORMAT_S24_LE:
  1095. format |= TWL4030_DATA_WIDTH_32S_24W;
  1096. break;
  1097. default:
  1098. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1099. params_format(params));
  1100. return -EINVAL;
  1101. }
  1102. if (format != old_format) {
  1103. /* clear CODECPDZ before changing format (codec requirement) */
  1104. twl4030_codec_enable(codec, 0);
  1105. /* change format */
  1106. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1107. /* set CODECPDZ afterwards */
  1108. twl4030_codec_enable(codec, 1);
  1109. }
  1110. return 0;
  1111. }
  1112. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1113. int clk_id, unsigned int freq, int dir)
  1114. {
  1115. struct snd_soc_codec *codec = codec_dai->codec;
  1116. u8 infreq;
  1117. switch (freq) {
  1118. case 19200000:
  1119. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1120. break;
  1121. case 26000000:
  1122. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1123. break;
  1124. case 38400000:
  1125. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1126. break;
  1127. default:
  1128. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1129. freq);
  1130. return -EINVAL;
  1131. }
  1132. infreq |= TWL4030_APLL_EN;
  1133. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1134. return 0;
  1135. }
  1136. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1137. unsigned int fmt)
  1138. {
  1139. struct snd_soc_codec *codec = codec_dai->codec;
  1140. u8 old_format, format;
  1141. /* get format */
  1142. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1143. format = old_format;
  1144. /* set master/slave audio interface */
  1145. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1146. case SND_SOC_DAIFMT_CBM_CFM:
  1147. format &= ~(TWL4030_AIF_SLAVE_EN);
  1148. format &= ~(TWL4030_CLK256FS_EN);
  1149. break;
  1150. case SND_SOC_DAIFMT_CBS_CFS:
  1151. format |= TWL4030_AIF_SLAVE_EN;
  1152. format |= TWL4030_CLK256FS_EN;
  1153. break;
  1154. default:
  1155. return -EINVAL;
  1156. }
  1157. /* interface format */
  1158. format &= ~TWL4030_AIF_FORMAT;
  1159. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1160. case SND_SOC_DAIFMT_I2S:
  1161. format |= TWL4030_AIF_FORMAT_CODEC;
  1162. break;
  1163. default:
  1164. return -EINVAL;
  1165. }
  1166. if (format != old_format) {
  1167. /* clear CODECPDZ before changing format (codec requirement) */
  1168. twl4030_codec_enable(codec, 0);
  1169. /* change format */
  1170. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1171. /* set CODECPDZ afterwards */
  1172. twl4030_codec_enable(codec, 1);
  1173. }
  1174. return 0;
  1175. }
  1176. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1177. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1178. struct snd_soc_dai twl4030_dai = {
  1179. .name = "twl4030",
  1180. .playback = {
  1181. .stream_name = "Playback",
  1182. .channels_min = 2,
  1183. .channels_max = 2,
  1184. .rates = TWL4030_RATES,
  1185. .formats = TWL4030_FORMATS,},
  1186. .capture = {
  1187. .stream_name = "Capture",
  1188. .channels_min = 2,
  1189. .channels_max = 2,
  1190. .rates = TWL4030_RATES,
  1191. .formats = TWL4030_FORMATS,},
  1192. .ops = {
  1193. .hw_params = twl4030_hw_params,
  1194. .set_sysclk = twl4030_set_dai_sysclk,
  1195. .set_fmt = twl4030_set_dai_fmt,
  1196. }
  1197. };
  1198. EXPORT_SYMBOL_GPL(twl4030_dai);
  1199. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1200. {
  1201. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1202. struct snd_soc_codec *codec = socdev->card->codec;
  1203. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1204. return 0;
  1205. }
  1206. static int twl4030_resume(struct platform_device *pdev)
  1207. {
  1208. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1209. struct snd_soc_codec *codec = socdev->card->codec;
  1210. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1211. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1212. return 0;
  1213. }
  1214. /*
  1215. * initialize the driver
  1216. * register the mixer and dsp interfaces with the kernel
  1217. */
  1218. static int twl4030_init(struct snd_soc_device *socdev)
  1219. {
  1220. struct snd_soc_codec *codec = socdev->card->codec;
  1221. int ret = 0;
  1222. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1223. codec->name = "twl4030";
  1224. codec->owner = THIS_MODULE;
  1225. codec->read = twl4030_read_reg_cache;
  1226. codec->write = twl4030_write;
  1227. codec->set_bias_level = twl4030_set_bias_level;
  1228. codec->dai = &twl4030_dai;
  1229. codec->num_dai = 1;
  1230. codec->reg_cache_size = sizeof(twl4030_reg);
  1231. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1232. GFP_KERNEL);
  1233. if (codec->reg_cache == NULL)
  1234. return -ENOMEM;
  1235. /* register pcms */
  1236. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1237. if (ret < 0) {
  1238. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1239. goto pcm_err;
  1240. }
  1241. twl4030_init_chip(codec);
  1242. /* power on device */
  1243. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1244. snd_soc_add_controls(codec, twl4030_snd_controls,
  1245. ARRAY_SIZE(twl4030_snd_controls));
  1246. twl4030_add_widgets(codec);
  1247. ret = snd_soc_init_card(socdev);
  1248. if (ret < 0) {
  1249. printk(KERN_ERR "twl4030: failed to register card\n");
  1250. goto card_err;
  1251. }
  1252. return ret;
  1253. card_err:
  1254. snd_soc_free_pcms(socdev);
  1255. snd_soc_dapm_free(socdev);
  1256. pcm_err:
  1257. kfree(codec->reg_cache);
  1258. return ret;
  1259. }
  1260. static struct snd_soc_device *twl4030_socdev;
  1261. static int twl4030_probe(struct platform_device *pdev)
  1262. {
  1263. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1264. struct snd_soc_codec *codec;
  1265. struct twl4030_priv *twl4030;
  1266. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1267. if (codec == NULL)
  1268. return -ENOMEM;
  1269. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1270. if (twl4030 == NULL) {
  1271. kfree(codec);
  1272. return -ENOMEM;
  1273. }
  1274. codec->private_data = twl4030;
  1275. socdev->card->codec = codec;
  1276. mutex_init(&codec->mutex);
  1277. INIT_LIST_HEAD(&codec->dapm_widgets);
  1278. INIT_LIST_HEAD(&codec->dapm_paths);
  1279. twl4030_socdev = socdev;
  1280. twl4030_init(socdev);
  1281. return 0;
  1282. }
  1283. static int twl4030_remove(struct platform_device *pdev)
  1284. {
  1285. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1286. struct snd_soc_codec *codec = socdev->card->codec;
  1287. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1288. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1289. snd_soc_free_pcms(socdev);
  1290. snd_soc_dapm_free(socdev);
  1291. kfree(codec->private_data);
  1292. kfree(codec);
  1293. return 0;
  1294. }
  1295. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1296. .probe = twl4030_probe,
  1297. .remove = twl4030_remove,
  1298. .suspend = twl4030_suspend,
  1299. .resume = twl4030_resume,
  1300. };
  1301. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1302. static int __init twl4030_modinit(void)
  1303. {
  1304. return snd_soc_register_dai(&twl4030_dai);
  1305. }
  1306. module_init(twl4030_modinit);
  1307. static void __exit twl4030_exit(void)
  1308. {
  1309. snd_soc_unregister_dai(&twl4030_dai);
  1310. }
  1311. module_exit(twl4030_exit);
  1312. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1313. MODULE_AUTHOR("Steve Sakoman");
  1314. MODULE_LICENSE("GPL");