smpboot.c 34 KB

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  1. /*
  2. * x86 SMP booting functions
  3. *
  4. * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  5. * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
  6. *
  7. * Much of the core SMP work is based on previous work by Thomas Radke, to
  8. * whom a great many thanks are extended.
  9. *
  10. * Thanks to Intel for making available several different Pentium,
  11. * Pentium Pro and Pentium-II/Xeon MP machines.
  12. * Original development of Linux SMP code supported by Caldera.
  13. *
  14. * This code is released under the GNU General Public License version 2 or
  15. * later.
  16. *
  17. * Fixes
  18. * Felix Koop : NR_CPUS used properly
  19. * Jose Renau : Handle single CPU case.
  20. * Alan Cox : By repeated request 8) - Total BogoMIPS report.
  21. * Greg Wright : Fix for kernel stacks panic.
  22. * Erich Boleyn : MP v1.4 and additional changes.
  23. * Matthias Sattler : Changes for 2.1 kernel map.
  24. * Michel Lespinasse : Changes for 2.1 kernel map.
  25. * Michael Chastain : Change trampoline.S to gnu as.
  26. * Alan Cox : Dumb bug: 'B' step PPro's are fine
  27. * Ingo Molnar : Added APIC timers, based on code
  28. * from Jose Renau
  29. * Ingo Molnar : various cleanups and rewrites
  30. * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
  31. * Maciej W. Rozycki : Bits for genuine 82489DX APICs
  32. * Martin J. Bligh : Added support for multi-quad systems
  33. * Dave Jones : Report invalid combinations of Athlon CPUs.
  34. * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
  35. #include <linux/module.h>
  36. #include <linux/config.h>
  37. #include <linux/init.h>
  38. #include <linux/kernel.h>
  39. #include <linux/mm.h>
  40. #include <linux/sched.h>
  41. #include <linux/kernel_stat.h>
  42. #include <linux/smp_lock.h>
  43. #include <linux/bootmem.h>
  44. #include <linux/notifier.h>
  45. #include <linux/cpu.h>
  46. #include <linux/percpu.h>
  47. #include <linux/delay.h>
  48. #include <linux/mc146818rtc.h>
  49. #include <asm/tlbflush.h>
  50. #include <asm/desc.h>
  51. #include <asm/arch_hooks.h>
  52. #include <mach_apic.h>
  53. #include <mach_wakecpu.h>
  54. #include <smpboot_hooks.h>
  55. /* Set if we find a B stepping CPU */
  56. static int __devinitdata smp_b_stepping;
  57. /* Number of siblings per CPU package */
  58. int smp_num_siblings = 1;
  59. #ifdef CONFIG_X86_HT
  60. EXPORT_SYMBOL(smp_num_siblings);
  61. #endif
  62. /* Package ID of each logical CPU */
  63. int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
  64. /* Core ID of each logical CPU */
  65. int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
  66. cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
  67. EXPORT_SYMBOL(cpu_sibling_map);
  68. cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
  69. EXPORT_SYMBOL(cpu_core_map);
  70. /* bitmap of online cpus */
  71. cpumask_t cpu_online_map __read_mostly;
  72. EXPORT_SYMBOL(cpu_online_map);
  73. cpumask_t cpu_callin_map;
  74. cpumask_t cpu_callout_map;
  75. EXPORT_SYMBOL(cpu_callout_map);
  76. #ifdef CONFIG_HOTPLUG_CPU
  77. cpumask_t cpu_possible_map = CPU_MASK_ALL;
  78. #else
  79. cpumask_t cpu_possible_map;
  80. #endif
  81. EXPORT_SYMBOL(cpu_possible_map);
  82. static cpumask_t smp_commenced_mask;
  83. /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
  84. * is no way to resync one AP against BP. TBD: for prescott and above, we
  85. * should use IA64's algorithm
  86. */
  87. static int __devinitdata tsc_sync_disabled;
  88. /* Per CPU bogomips and other parameters */
  89. struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
  90. EXPORT_SYMBOL(cpu_data);
  91. u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
  92. { [0 ... NR_CPUS-1] = 0xff };
  93. EXPORT_SYMBOL(x86_cpu_to_apicid);
  94. /*
  95. * Trampoline 80x86 program as an array.
  96. */
  97. extern unsigned char trampoline_data [];
  98. extern unsigned char trampoline_end [];
  99. static unsigned char *trampoline_base;
  100. static int trampoline_exec;
  101. static void map_cpu_to_logical_apicid(void);
  102. /* State of each CPU. */
  103. DEFINE_PER_CPU(int, cpu_state) = { 0 };
  104. /*
  105. * Currently trivial. Write the real->protected mode
  106. * bootstrap into the page concerned. The caller
  107. * has made sure it's suitably aligned.
  108. */
  109. static unsigned long __devinit setup_trampoline(void)
  110. {
  111. memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
  112. return virt_to_phys(trampoline_base);
  113. }
  114. /*
  115. * We are called very early to get the low memory for the
  116. * SMP bootup trampoline page.
  117. */
  118. void __init smp_alloc_memory(void)
  119. {
  120. trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
  121. /*
  122. * Has to be in very low memory so we can execute
  123. * real-mode AP code.
  124. */
  125. if (__pa(trampoline_base) >= 0x9F000)
  126. BUG();
  127. /*
  128. * Make the SMP trampoline executable:
  129. */
  130. trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
  131. }
  132. /*
  133. * The bootstrap kernel entry code has set these up. Save them for
  134. * a given CPU
  135. */
  136. static void __devinit smp_store_cpu_info(int id)
  137. {
  138. struct cpuinfo_x86 *c = cpu_data + id;
  139. *c = boot_cpu_data;
  140. if (id!=0)
  141. identify_cpu(c);
  142. /*
  143. * Mask B, Pentium, but not Pentium MMX
  144. */
  145. if (c->x86_vendor == X86_VENDOR_INTEL &&
  146. c->x86 == 5 &&
  147. c->x86_mask >= 1 && c->x86_mask <= 4 &&
  148. c->x86_model <= 3)
  149. /*
  150. * Remember we have B step Pentia with bugs
  151. */
  152. smp_b_stepping = 1;
  153. /*
  154. * Certain Athlons might work (for various values of 'work') in SMP
  155. * but they are not certified as MP capable.
  156. */
  157. if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
  158. /* Athlon 660/661 is valid. */
  159. if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
  160. goto valid_k7;
  161. /* Duron 670 is valid */
  162. if ((c->x86_model==7) && (c->x86_mask==0))
  163. goto valid_k7;
  164. /*
  165. * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
  166. * It's worth noting that the A5 stepping (662) of some Athlon XP's
  167. * have the MP bit set.
  168. * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
  169. */
  170. if (((c->x86_model==6) && (c->x86_mask>=2)) ||
  171. ((c->x86_model==7) && (c->x86_mask>=1)) ||
  172. (c->x86_model> 7))
  173. if (cpu_has_mp)
  174. goto valid_k7;
  175. /* If we get here, it's not a certified SMP capable AMD system. */
  176. add_taint(TAINT_UNSAFE_SMP);
  177. }
  178. valid_k7:
  179. ;
  180. }
  181. /*
  182. * TSC synchronization.
  183. *
  184. * We first check whether all CPUs have their TSC's synchronized,
  185. * then we print a warning if not, and always resync.
  186. */
  187. static atomic_t tsc_start_flag = ATOMIC_INIT(0);
  188. static atomic_t tsc_count_start = ATOMIC_INIT(0);
  189. static atomic_t tsc_count_stop = ATOMIC_INIT(0);
  190. static unsigned long long tsc_values[NR_CPUS];
  191. #define NR_LOOPS 5
  192. static void __init synchronize_tsc_bp (void)
  193. {
  194. int i;
  195. unsigned long long t0;
  196. unsigned long long sum, avg;
  197. long long delta;
  198. unsigned int one_usec;
  199. int buggy = 0;
  200. printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
  201. /* convert from kcyc/sec to cyc/usec */
  202. one_usec = cpu_khz / 1000;
  203. atomic_set(&tsc_start_flag, 1);
  204. wmb();
  205. /*
  206. * We loop a few times to get a primed instruction cache,
  207. * then the last pass is more or less synchronized and
  208. * the BP and APs set their cycle counters to zero all at
  209. * once. This reduces the chance of having random offsets
  210. * between the processors, and guarantees that the maximum
  211. * delay between the cycle counters is never bigger than
  212. * the latency of information-passing (cachelines) between
  213. * two CPUs.
  214. */
  215. for (i = 0; i < NR_LOOPS; i++) {
  216. /*
  217. * all APs synchronize but they loop on '== num_cpus'
  218. */
  219. while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
  220. mb();
  221. atomic_set(&tsc_count_stop, 0);
  222. wmb();
  223. /*
  224. * this lets the APs save their current TSC:
  225. */
  226. atomic_inc(&tsc_count_start);
  227. rdtscll(tsc_values[smp_processor_id()]);
  228. /*
  229. * We clear the TSC in the last loop:
  230. */
  231. if (i == NR_LOOPS-1)
  232. write_tsc(0, 0);
  233. /*
  234. * Wait for all APs to leave the synchronization point:
  235. */
  236. while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
  237. mb();
  238. atomic_set(&tsc_count_start, 0);
  239. wmb();
  240. atomic_inc(&tsc_count_stop);
  241. }
  242. sum = 0;
  243. for (i = 0; i < NR_CPUS; i++) {
  244. if (cpu_isset(i, cpu_callout_map)) {
  245. t0 = tsc_values[i];
  246. sum += t0;
  247. }
  248. }
  249. avg = sum;
  250. do_div(avg, num_booting_cpus());
  251. sum = 0;
  252. for (i = 0; i < NR_CPUS; i++) {
  253. if (!cpu_isset(i, cpu_callout_map))
  254. continue;
  255. delta = tsc_values[i] - avg;
  256. if (delta < 0)
  257. delta = -delta;
  258. /*
  259. * We report bigger than 2 microseconds clock differences.
  260. */
  261. if (delta > 2*one_usec) {
  262. long realdelta;
  263. if (!buggy) {
  264. buggy = 1;
  265. printk("\n");
  266. }
  267. realdelta = delta;
  268. do_div(realdelta, one_usec);
  269. if (tsc_values[i] < avg)
  270. realdelta = -realdelta;
  271. printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
  272. }
  273. sum += delta;
  274. }
  275. if (!buggy)
  276. printk("passed.\n");
  277. }
  278. static void __init synchronize_tsc_ap (void)
  279. {
  280. int i;
  281. /*
  282. * Not every cpu is online at the time
  283. * this gets called, so we first wait for the BP to
  284. * finish SMP initialization:
  285. */
  286. while (!atomic_read(&tsc_start_flag)) mb();
  287. for (i = 0; i < NR_LOOPS; i++) {
  288. atomic_inc(&tsc_count_start);
  289. while (atomic_read(&tsc_count_start) != num_booting_cpus())
  290. mb();
  291. rdtscll(tsc_values[smp_processor_id()]);
  292. if (i == NR_LOOPS-1)
  293. write_tsc(0, 0);
  294. atomic_inc(&tsc_count_stop);
  295. while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
  296. }
  297. }
  298. #undef NR_LOOPS
  299. extern void calibrate_delay(void);
  300. static atomic_t init_deasserted;
  301. static void __devinit smp_callin(void)
  302. {
  303. int cpuid, phys_id;
  304. unsigned long timeout;
  305. /*
  306. * If waken up by an INIT in an 82489DX configuration
  307. * we may get here before an INIT-deassert IPI reaches
  308. * our local APIC. We have to wait for the IPI or we'll
  309. * lock up on an APIC access.
  310. */
  311. wait_for_init_deassert(&init_deasserted);
  312. /*
  313. * (This works even if the APIC is not enabled.)
  314. */
  315. phys_id = GET_APIC_ID(apic_read(APIC_ID));
  316. cpuid = smp_processor_id();
  317. if (cpu_isset(cpuid, cpu_callin_map)) {
  318. printk("huh, phys CPU#%d, CPU#%d already present??\n",
  319. phys_id, cpuid);
  320. BUG();
  321. }
  322. Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
  323. /*
  324. * STARTUP IPIs are fragile beasts as they might sometimes
  325. * trigger some glue motherboard logic. Complete APIC bus
  326. * silence for 1 second, this overestimates the time the
  327. * boot CPU is spending to send the up to 2 STARTUP IPIs
  328. * by a factor of two. This should be enough.
  329. */
  330. /*
  331. * Waiting 2s total for startup (udelay is not yet working)
  332. */
  333. timeout = jiffies + 2*HZ;
  334. while (time_before(jiffies, timeout)) {
  335. /*
  336. * Has the boot CPU finished it's STARTUP sequence?
  337. */
  338. if (cpu_isset(cpuid, cpu_callout_map))
  339. break;
  340. rep_nop();
  341. }
  342. if (!time_before(jiffies, timeout)) {
  343. printk("BUG: CPU%d started up but did not get a callout!\n",
  344. cpuid);
  345. BUG();
  346. }
  347. /*
  348. * the boot CPU has finished the init stage and is spinning
  349. * on callin_map until we finish. We are free to set up this
  350. * CPU, first the APIC. (this is probably redundant on most
  351. * boards)
  352. */
  353. Dprintk("CALLIN, before setup_local_APIC().\n");
  354. smp_callin_clear_local_apic();
  355. setup_local_APIC();
  356. map_cpu_to_logical_apicid();
  357. /*
  358. * Get our bogomips.
  359. */
  360. calibrate_delay();
  361. Dprintk("Stack at about %p\n",&cpuid);
  362. /*
  363. * Save our processor parameters
  364. */
  365. smp_store_cpu_info(cpuid);
  366. disable_APIC_timer();
  367. /*
  368. * Allow the master to continue.
  369. */
  370. cpu_set(cpuid, cpu_callin_map);
  371. /*
  372. * Synchronize the TSC with the BP
  373. */
  374. if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
  375. synchronize_tsc_ap();
  376. }
  377. static int cpucount;
  378. static inline void
  379. set_cpu_sibling_map(int cpu)
  380. {
  381. int i;
  382. if (smp_num_siblings > 1) {
  383. for (i = 0; i < NR_CPUS; i++) {
  384. if (!cpu_isset(i, cpu_callout_map))
  385. continue;
  386. if (cpu_core_id[cpu] == cpu_core_id[i]) {
  387. cpu_set(i, cpu_sibling_map[cpu]);
  388. cpu_set(cpu, cpu_sibling_map[i]);
  389. }
  390. }
  391. } else {
  392. cpu_set(cpu, cpu_sibling_map[cpu]);
  393. }
  394. if (current_cpu_data.x86_num_cores > 1) {
  395. for (i = 0; i < NR_CPUS; i++) {
  396. if (!cpu_isset(i, cpu_callout_map))
  397. continue;
  398. if (phys_proc_id[cpu] == phys_proc_id[i]) {
  399. cpu_set(i, cpu_core_map[cpu]);
  400. cpu_set(cpu, cpu_core_map[i]);
  401. }
  402. }
  403. } else {
  404. cpu_core_map[cpu] = cpu_sibling_map[cpu];
  405. }
  406. }
  407. /*
  408. * Activate a secondary processor.
  409. */
  410. static void __devinit start_secondary(void *unused)
  411. {
  412. /*
  413. * Dont put anything before smp_callin(), SMP
  414. * booting is too fragile that we want to limit the
  415. * things done here to the most necessary things.
  416. */
  417. cpu_init();
  418. smp_callin();
  419. while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
  420. rep_nop();
  421. setup_secondary_APIC_clock();
  422. if (nmi_watchdog == NMI_IO_APIC) {
  423. disable_8259A_irq(0);
  424. enable_NMI_through_LVT0(NULL);
  425. enable_8259A_irq(0);
  426. }
  427. enable_APIC_timer();
  428. /*
  429. * low-memory mappings have been cleared, flush them from
  430. * the local TLBs too.
  431. */
  432. local_flush_tlb();
  433. /* This must be done before setting cpu_online_map */
  434. set_cpu_sibling_map(raw_smp_processor_id());
  435. wmb();
  436. /*
  437. * We need to hold call_lock, so there is no inconsistency
  438. * between the time smp_call_function() determines number of
  439. * IPI receipients, and the time when the determination is made
  440. * for which cpus receive the IPI. Holding this
  441. * lock helps us to not include this cpu in a currently in progress
  442. * smp_call_function().
  443. */
  444. lock_ipi_call_lock();
  445. cpu_set(smp_processor_id(), cpu_online_map);
  446. unlock_ipi_call_lock();
  447. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  448. /* We can take interrupts now: we're officially "up". */
  449. local_irq_enable();
  450. wmb();
  451. cpu_idle();
  452. }
  453. /*
  454. * Everything has been set up for the secondary
  455. * CPUs - they just need to reload everything
  456. * from the task structure
  457. * This function must not return.
  458. */
  459. void __devinit initialize_secondary(void)
  460. {
  461. /*
  462. * We don't actually need to load the full TSS,
  463. * basically just the stack pointer and the eip.
  464. */
  465. asm volatile(
  466. "movl %0,%%esp\n\t"
  467. "jmp *%1"
  468. :
  469. :"r" (current->thread.esp),"r" (current->thread.eip));
  470. }
  471. extern struct {
  472. void * esp;
  473. unsigned short ss;
  474. } stack_start;
  475. #ifdef CONFIG_NUMA
  476. /* which logical CPUs are on which nodes */
  477. cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
  478. { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
  479. /* which node each logical CPU is on */
  480. int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
  481. EXPORT_SYMBOL(cpu_2_node);
  482. /* set up a mapping between cpu and node. */
  483. static inline void map_cpu_to_node(int cpu, int node)
  484. {
  485. printk("Mapping cpu %d to node %d\n", cpu, node);
  486. cpu_set(cpu, node_2_cpu_mask[node]);
  487. cpu_2_node[cpu] = node;
  488. }
  489. /* undo a mapping between cpu and node. */
  490. static inline void unmap_cpu_to_node(int cpu)
  491. {
  492. int node;
  493. printk("Unmapping cpu %d from all nodes\n", cpu);
  494. for (node = 0; node < MAX_NUMNODES; node ++)
  495. cpu_clear(cpu, node_2_cpu_mask[node]);
  496. cpu_2_node[cpu] = 0;
  497. }
  498. #else /* !CONFIG_NUMA */
  499. #define map_cpu_to_node(cpu, node) ({})
  500. #define unmap_cpu_to_node(cpu) ({})
  501. #endif /* CONFIG_NUMA */
  502. u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
  503. static void map_cpu_to_logical_apicid(void)
  504. {
  505. int cpu = smp_processor_id();
  506. int apicid = logical_smp_processor_id();
  507. cpu_2_logical_apicid[cpu] = apicid;
  508. map_cpu_to_node(cpu, apicid_to_node(apicid));
  509. }
  510. static void unmap_cpu_to_logical_apicid(int cpu)
  511. {
  512. cpu_2_logical_apicid[cpu] = BAD_APICID;
  513. unmap_cpu_to_node(cpu);
  514. }
  515. #if APIC_DEBUG
  516. static inline void __inquire_remote_apic(int apicid)
  517. {
  518. int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
  519. char *names[] = { "ID", "VERSION", "SPIV" };
  520. int timeout, status;
  521. printk("Inquiring remote APIC #%d...\n", apicid);
  522. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  523. printk("... APIC #%d %s: ", apicid, names[i]);
  524. /*
  525. * Wait for idle.
  526. */
  527. apic_wait_icr_idle();
  528. apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
  529. apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
  530. timeout = 0;
  531. do {
  532. udelay(100);
  533. status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
  534. } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
  535. switch (status) {
  536. case APIC_ICR_RR_VALID:
  537. status = apic_read(APIC_RRR);
  538. printk("%08x\n", status);
  539. break;
  540. default:
  541. printk("failed\n");
  542. }
  543. }
  544. }
  545. #endif
  546. #ifdef WAKE_SECONDARY_VIA_NMI
  547. /*
  548. * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
  549. * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
  550. * won't ... remember to clear down the APIC, etc later.
  551. */
  552. static int __devinit
  553. wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
  554. {
  555. unsigned long send_status = 0, accept_status = 0;
  556. int timeout, maxlvt;
  557. /* Target chip */
  558. apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
  559. /* Boot on the stack */
  560. /* Kick the second */
  561. apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
  562. Dprintk("Waiting for send to finish...\n");
  563. timeout = 0;
  564. do {
  565. Dprintk("+");
  566. udelay(100);
  567. send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
  568. } while (send_status && (timeout++ < 1000));
  569. /*
  570. * Give the other CPU some time to accept the IPI.
  571. */
  572. udelay(200);
  573. /*
  574. * Due to the Pentium erratum 3AP.
  575. */
  576. maxlvt = get_maxlvt();
  577. if (maxlvt > 3) {
  578. apic_read_around(APIC_SPIV);
  579. apic_write(APIC_ESR, 0);
  580. }
  581. accept_status = (apic_read(APIC_ESR) & 0xEF);
  582. Dprintk("NMI sent.\n");
  583. if (send_status)
  584. printk("APIC never delivered???\n");
  585. if (accept_status)
  586. printk("APIC delivery error (%lx).\n", accept_status);
  587. return (send_status | accept_status);
  588. }
  589. #endif /* WAKE_SECONDARY_VIA_NMI */
  590. #ifdef WAKE_SECONDARY_VIA_INIT
  591. static int __devinit
  592. wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
  593. {
  594. unsigned long send_status = 0, accept_status = 0;
  595. int maxlvt, timeout, num_starts, j;
  596. /*
  597. * Be paranoid about clearing APIC errors.
  598. */
  599. if (APIC_INTEGRATED(apic_version[phys_apicid])) {
  600. apic_read_around(APIC_SPIV);
  601. apic_write(APIC_ESR, 0);
  602. apic_read(APIC_ESR);
  603. }
  604. Dprintk("Asserting INIT.\n");
  605. /*
  606. * Turn INIT on target chip
  607. */
  608. apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
  609. /*
  610. * Send IPI
  611. */
  612. apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
  613. | APIC_DM_INIT);
  614. Dprintk("Waiting for send to finish...\n");
  615. timeout = 0;
  616. do {
  617. Dprintk("+");
  618. udelay(100);
  619. send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
  620. } while (send_status && (timeout++ < 1000));
  621. mdelay(10);
  622. Dprintk("Deasserting INIT.\n");
  623. /* Target chip */
  624. apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
  625. /* Send IPI */
  626. apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
  627. Dprintk("Waiting for send to finish...\n");
  628. timeout = 0;
  629. do {
  630. Dprintk("+");
  631. udelay(100);
  632. send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
  633. } while (send_status && (timeout++ < 1000));
  634. atomic_set(&init_deasserted, 1);
  635. /*
  636. * Should we send STARTUP IPIs ?
  637. *
  638. * Determine this based on the APIC version.
  639. * If we don't have an integrated APIC, don't send the STARTUP IPIs.
  640. */
  641. if (APIC_INTEGRATED(apic_version[phys_apicid]))
  642. num_starts = 2;
  643. else
  644. num_starts = 0;
  645. /*
  646. * Run STARTUP IPI loop.
  647. */
  648. Dprintk("#startup loops: %d.\n", num_starts);
  649. maxlvt = get_maxlvt();
  650. for (j = 1; j <= num_starts; j++) {
  651. Dprintk("Sending STARTUP #%d.\n",j);
  652. apic_read_around(APIC_SPIV);
  653. apic_write(APIC_ESR, 0);
  654. apic_read(APIC_ESR);
  655. Dprintk("After apic_write.\n");
  656. /*
  657. * STARTUP IPI
  658. */
  659. /* Target chip */
  660. apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
  661. /* Boot on the stack */
  662. /* Kick the second */
  663. apic_write_around(APIC_ICR, APIC_DM_STARTUP
  664. | (start_eip >> 12));
  665. /*
  666. * Give the other CPU some time to accept the IPI.
  667. */
  668. udelay(300);
  669. Dprintk("Startup point 1.\n");
  670. Dprintk("Waiting for send to finish...\n");
  671. timeout = 0;
  672. do {
  673. Dprintk("+");
  674. udelay(100);
  675. send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
  676. } while (send_status && (timeout++ < 1000));
  677. /*
  678. * Give the other CPU some time to accept the IPI.
  679. */
  680. udelay(200);
  681. /*
  682. * Due to the Pentium erratum 3AP.
  683. */
  684. if (maxlvt > 3) {
  685. apic_read_around(APIC_SPIV);
  686. apic_write(APIC_ESR, 0);
  687. }
  688. accept_status = (apic_read(APIC_ESR) & 0xEF);
  689. if (send_status || accept_status)
  690. break;
  691. }
  692. Dprintk("After Startup.\n");
  693. if (send_status)
  694. printk("APIC never delivered???\n");
  695. if (accept_status)
  696. printk("APIC delivery error (%lx).\n", accept_status);
  697. return (send_status | accept_status);
  698. }
  699. #endif /* WAKE_SECONDARY_VIA_INIT */
  700. extern cpumask_t cpu_initialized;
  701. static inline int alloc_cpu_id(void)
  702. {
  703. cpumask_t tmp_map;
  704. int cpu;
  705. cpus_complement(tmp_map, cpu_present_map);
  706. cpu = first_cpu(tmp_map);
  707. if (cpu >= NR_CPUS)
  708. return -ENODEV;
  709. return cpu;
  710. }
  711. #ifdef CONFIG_HOTPLUG_CPU
  712. static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
  713. static inline struct task_struct * alloc_idle_task(int cpu)
  714. {
  715. struct task_struct *idle;
  716. if ((idle = cpu_idle_tasks[cpu]) != NULL) {
  717. /* initialize thread_struct. we really want to avoid destroy
  718. * idle tread
  719. */
  720. idle->thread.esp = (unsigned long)(((struct pt_regs *)
  721. (THREAD_SIZE + (unsigned long) idle->thread_info)) - 1);
  722. init_idle(idle, cpu);
  723. return idle;
  724. }
  725. idle = fork_idle(cpu);
  726. if (!IS_ERR(idle))
  727. cpu_idle_tasks[cpu] = idle;
  728. return idle;
  729. }
  730. #else
  731. #define alloc_idle_task(cpu) fork_idle(cpu)
  732. #endif
  733. static int __devinit do_boot_cpu(int apicid, int cpu)
  734. /*
  735. * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
  736. * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
  737. * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
  738. */
  739. {
  740. struct task_struct *idle;
  741. unsigned long boot_error;
  742. int timeout;
  743. unsigned long start_eip;
  744. unsigned short nmi_high = 0, nmi_low = 0;
  745. ++cpucount;
  746. /*
  747. * We can't use kernel_thread since we must avoid to
  748. * reschedule the child.
  749. */
  750. idle = alloc_idle_task(cpu);
  751. if (IS_ERR(idle))
  752. panic("failed fork for CPU %d", cpu);
  753. idle->thread.eip = (unsigned long) start_secondary;
  754. /* start_eip had better be page-aligned! */
  755. start_eip = setup_trampoline();
  756. /* So we see what's up */
  757. printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
  758. /* Stack for startup_32 can be just as for start_secondary onwards */
  759. stack_start.esp = (void *) idle->thread.esp;
  760. irq_ctx_init(cpu);
  761. /*
  762. * This grunge runs the startup process for
  763. * the targeted processor.
  764. */
  765. atomic_set(&init_deasserted, 0);
  766. Dprintk("Setting warm reset code and vector.\n");
  767. store_NMI_vector(&nmi_high, &nmi_low);
  768. smpboot_setup_warm_reset_vector(start_eip);
  769. /*
  770. * Starting actual IPI sequence...
  771. */
  772. boot_error = wakeup_secondary_cpu(apicid, start_eip);
  773. if (!boot_error) {
  774. /*
  775. * allow APs to start initializing.
  776. */
  777. Dprintk("Before Callout %d.\n", cpu);
  778. cpu_set(cpu, cpu_callout_map);
  779. Dprintk("After Callout %d.\n", cpu);
  780. /*
  781. * Wait 5s total for a response
  782. */
  783. for (timeout = 0; timeout < 50000; timeout++) {
  784. if (cpu_isset(cpu, cpu_callin_map))
  785. break; /* It has booted */
  786. udelay(100);
  787. }
  788. if (cpu_isset(cpu, cpu_callin_map)) {
  789. /* number CPUs logically, starting from 1 (BSP is 0) */
  790. Dprintk("OK.\n");
  791. printk("CPU%d: ", cpu);
  792. print_cpu_info(&cpu_data[cpu]);
  793. Dprintk("CPU has booted.\n");
  794. } else {
  795. boot_error= 1;
  796. if (*((volatile unsigned char *)trampoline_base)
  797. == 0xA5)
  798. /* trampoline started but...? */
  799. printk("Stuck ??\n");
  800. else
  801. /* trampoline code not run */
  802. printk("Not responding.\n");
  803. inquire_remote_apic(apicid);
  804. }
  805. }
  806. if (boot_error) {
  807. /* Try to put things back the way they were before ... */
  808. unmap_cpu_to_logical_apicid(cpu);
  809. cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
  810. cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
  811. cpucount--;
  812. } else {
  813. x86_cpu_to_apicid[cpu] = apicid;
  814. cpu_set(cpu, cpu_present_map);
  815. }
  816. /* mark "stuck" area as not stuck */
  817. *((volatile unsigned long *)trampoline_base) = 0;
  818. return boot_error;
  819. }
  820. #ifdef CONFIG_HOTPLUG_CPU
  821. void cpu_exit_clear(void)
  822. {
  823. int cpu = raw_smp_processor_id();
  824. idle_task_exit();
  825. cpucount --;
  826. cpu_uninit();
  827. irq_ctx_exit(cpu);
  828. cpu_clear(cpu, cpu_callout_map);
  829. cpu_clear(cpu, cpu_callin_map);
  830. cpu_clear(cpu, cpu_present_map);
  831. cpu_clear(cpu, smp_commenced_mask);
  832. unmap_cpu_to_logical_apicid(cpu);
  833. }
  834. struct warm_boot_cpu_info {
  835. struct completion *complete;
  836. int apicid;
  837. int cpu;
  838. };
  839. static void __devinit do_warm_boot_cpu(void *p)
  840. {
  841. struct warm_boot_cpu_info *info = p;
  842. do_boot_cpu(info->apicid, info->cpu);
  843. complete(info->complete);
  844. }
  845. int __devinit smp_prepare_cpu(int cpu)
  846. {
  847. DECLARE_COMPLETION(done);
  848. struct warm_boot_cpu_info info;
  849. struct work_struct task;
  850. int apicid, ret;
  851. lock_cpu_hotplug();
  852. apicid = x86_cpu_to_apicid[cpu];
  853. if (apicid == BAD_APICID) {
  854. ret = -ENODEV;
  855. goto exit;
  856. }
  857. info.complete = &done;
  858. info.apicid = apicid;
  859. info.cpu = cpu;
  860. INIT_WORK(&task, do_warm_boot_cpu, &info);
  861. tsc_sync_disabled = 1;
  862. /* init low mem mapping */
  863. clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
  864. KERNEL_PGD_PTRS);
  865. flush_tlb_all();
  866. schedule_work(&task);
  867. wait_for_completion(&done);
  868. tsc_sync_disabled = 0;
  869. zap_low_mappings();
  870. ret = 0;
  871. exit:
  872. unlock_cpu_hotplug();
  873. return ret;
  874. }
  875. #endif
  876. static void smp_tune_scheduling (void)
  877. {
  878. unsigned long cachesize; /* kB */
  879. unsigned long bandwidth = 350; /* MB/s */
  880. /*
  881. * Rough estimation for SMP scheduling, this is the number of
  882. * cycles it takes for a fully memory-limited process to flush
  883. * the SMP-local cache.
  884. *
  885. * (For a P5 this pretty much means we will choose another idle
  886. * CPU almost always at wakeup time (this is due to the small
  887. * L1 cache), on PIIs it's around 50-100 usecs, depending on
  888. * the cache size)
  889. */
  890. if (!cpu_khz) {
  891. /*
  892. * this basically disables processor-affinity
  893. * scheduling on SMP without a TSC.
  894. */
  895. return;
  896. } else {
  897. cachesize = boot_cpu_data.x86_cache_size;
  898. if (cachesize == -1) {
  899. cachesize = 16; /* Pentiums, 2x8kB cache */
  900. bandwidth = 100;
  901. }
  902. }
  903. }
  904. /*
  905. * Cycle through the processors sending APIC IPIs to boot each.
  906. */
  907. static int boot_cpu_logical_apicid;
  908. /* Where the IO area was mapped on multiquad, always 0 otherwise */
  909. void *xquad_portio;
  910. #ifdef CONFIG_X86_NUMAQ
  911. EXPORT_SYMBOL(xquad_portio);
  912. #endif
  913. static void __init smp_boot_cpus(unsigned int max_cpus)
  914. {
  915. int apicid, cpu, bit, kicked;
  916. unsigned long bogosum = 0;
  917. /*
  918. * Setup boot CPU information
  919. */
  920. smp_store_cpu_info(0); /* Final full version of the data */
  921. printk("CPU%d: ", 0);
  922. print_cpu_info(&cpu_data[0]);
  923. boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
  924. boot_cpu_logical_apicid = logical_smp_processor_id();
  925. x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
  926. current_thread_info()->cpu = 0;
  927. smp_tune_scheduling();
  928. cpus_clear(cpu_sibling_map[0]);
  929. cpu_set(0, cpu_sibling_map[0]);
  930. cpus_clear(cpu_core_map[0]);
  931. cpu_set(0, cpu_core_map[0]);
  932. /*
  933. * If we couldn't find an SMP configuration at boot time,
  934. * get out of here now!
  935. */
  936. if (!smp_found_config && !acpi_lapic) {
  937. printk(KERN_NOTICE "SMP motherboard not detected.\n");
  938. smpboot_clear_io_apic_irqs();
  939. phys_cpu_present_map = physid_mask_of_physid(0);
  940. if (APIC_init_uniprocessor())
  941. printk(KERN_NOTICE "Local APIC not detected."
  942. " Using dummy APIC emulation.\n");
  943. map_cpu_to_logical_apicid();
  944. cpu_set(0, cpu_sibling_map[0]);
  945. cpu_set(0, cpu_core_map[0]);
  946. return;
  947. }
  948. /*
  949. * Should not be necessary because the MP table should list the boot
  950. * CPU too, but we do it for the sake of robustness anyway.
  951. * Makes no sense to do this check in clustered apic mode, so skip it
  952. */
  953. if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
  954. printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
  955. boot_cpu_physical_apicid);
  956. physid_set(hard_smp_processor_id(), phys_cpu_present_map);
  957. }
  958. /*
  959. * If we couldn't find a local APIC, then get out of here now!
  960. */
  961. if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
  962. printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
  963. boot_cpu_physical_apicid);
  964. printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
  965. smpboot_clear_io_apic_irqs();
  966. phys_cpu_present_map = physid_mask_of_physid(0);
  967. cpu_set(0, cpu_sibling_map[0]);
  968. cpu_set(0, cpu_core_map[0]);
  969. return;
  970. }
  971. verify_local_APIC();
  972. /*
  973. * If SMP should be disabled, then really disable it!
  974. */
  975. if (!max_cpus) {
  976. smp_found_config = 0;
  977. printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
  978. smpboot_clear_io_apic_irqs();
  979. phys_cpu_present_map = physid_mask_of_physid(0);
  980. cpu_set(0, cpu_sibling_map[0]);
  981. cpu_set(0, cpu_core_map[0]);
  982. return;
  983. }
  984. connect_bsp_APIC();
  985. setup_local_APIC();
  986. map_cpu_to_logical_apicid();
  987. setup_portio_remap();
  988. /*
  989. * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
  990. *
  991. * In clustered apic mode, phys_cpu_present_map is a constructed thus:
  992. * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
  993. * clustered apic ID.
  994. */
  995. Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
  996. kicked = 1;
  997. for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
  998. apicid = cpu_present_to_apicid(bit);
  999. /*
  1000. * Don't even attempt to start the boot CPU!
  1001. */
  1002. if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
  1003. continue;
  1004. if (!check_apicid_present(bit))
  1005. continue;
  1006. if (max_cpus <= cpucount+1)
  1007. continue;
  1008. if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
  1009. printk("CPU #%d not responding - cannot use it.\n",
  1010. apicid);
  1011. else
  1012. ++kicked;
  1013. }
  1014. /*
  1015. * Cleanup possible dangling ends...
  1016. */
  1017. smpboot_restore_warm_reset_vector();
  1018. /*
  1019. * Allow the user to impress friends.
  1020. */
  1021. Dprintk("Before bogomips.\n");
  1022. for (cpu = 0; cpu < NR_CPUS; cpu++)
  1023. if (cpu_isset(cpu, cpu_callout_map))
  1024. bogosum += cpu_data[cpu].loops_per_jiffy;
  1025. printk(KERN_INFO
  1026. "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  1027. cpucount+1,
  1028. bogosum/(500000/HZ),
  1029. (bogosum/(5000/HZ))%100);
  1030. Dprintk("Before bogocount - setting activated=1.\n");
  1031. if (smp_b_stepping)
  1032. printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
  1033. /*
  1034. * Don't taint if we are running SMP kernel on a single non-MP
  1035. * approved Athlon
  1036. */
  1037. if (tainted & TAINT_UNSAFE_SMP) {
  1038. if (cpucount)
  1039. printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
  1040. else
  1041. tainted &= ~TAINT_UNSAFE_SMP;
  1042. }
  1043. Dprintk("Boot done.\n");
  1044. /*
  1045. * construct cpu_sibling_map[], so that we can tell sibling CPUs
  1046. * efficiently.
  1047. */
  1048. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  1049. cpus_clear(cpu_sibling_map[cpu]);
  1050. cpus_clear(cpu_core_map[cpu]);
  1051. }
  1052. cpu_set(0, cpu_sibling_map[0]);
  1053. cpu_set(0, cpu_core_map[0]);
  1054. smpboot_setup_io_apic();
  1055. setup_boot_APIC_clock();
  1056. /*
  1057. * Synchronize the TSC with the AP
  1058. */
  1059. if (cpu_has_tsc && cpucount && cpu_khz)
  1060. synchronize_tsc_bp();
  1061. }
  1062. /* These are wrappers to interface to the new boot process. Someone
  1063. who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
  1064. void __init smp_prepare_cpus(unsigned int max_cpus)
  1065. {
  1066. smp_commenced_mask = cpumask_of_cpu(0);
  1067. cpu_callin_map = cpumask_of_cpu(0);
  1068. mb();
  1069. smp_boot_cpus(max_cpus);
  1070. }
  1071. void __devinit smp_prepare_boot_cpu(void)
  1072. {
  1073. cpu_set(smp_processor_id(), cpu_online_map);
  1074. cpu_set(smp_processor_id(), cpu_callout_map);
  1075. cpu_set(smp_processor_id(), cpu_present_map);
  1076. cpu_set(smp_processor_id(), cpu_possible_map);
  1077. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  1078. }
  1079. #ifdef CONFIG_HOTPLUG_CPU
  1080. static void
  1081. remove_siblinginfo(int cpu)
  1082. {
  1083. int sibling;
  1084. for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
  1085. cpu_clear(cpu, cpu_sibling_map[sibling]);
  1086. for_each_cpu_mask(sibling, cpu_core_map[cpu])
  1087. cpu_clear(cpu, cpu_core_map[sibling]);
  1088. cpus_clear(cpu_sibling_map[cpu]);
  1089. cpus_clear(cpu_core_map[cpu]);
  1090. phys_proc_id[cpu] = BAD_APICID;
  1091. cpu_core_id[cpu] = BAD_APICID;
  1092. }
  1093. int __cpu_disable(void)
  1094. {
  1095. cpumask_t map = cpu_online_map;
  1096. int cpu = smp_processor_id();
  1097. /*
  1098. * Perhaps use cpufreq to drop frequency, but that could go
  1099. * into generic code.
  1100. *
  1101. * We won't take down the boot processor on i386 due to some
  1102. * interrupts only being able to be serviced by the BSP.
  1103. * Especially so if we're not using an IOAPIC -zwane
  1104. */
  1105. if (cpu == 0)
  1106. return -EBUSY;
  1107. /* We enable the timer again on the exit path of the death loop */
  1108. disable_APIC_timer();
  1109. /* Allow any queued timer interrupts to get serviced */
  1110. local_irq_enable();
  1111. mdelay(1);
  1112. local_irq_disable();
  1113. remove_siblinginfo(cpu);
  1114. cpu_clear(cpu, map);
  1115. fixup_irqs(map);
  1116. /* It's now safe to remove this processor from the online map */
  1117. cpu_clear(cpu, cpu_online_map);
  1118. return 0;
  1119. }
  1120. void __cpu_die(unsigned int cpu)
  1121. {
  1122. /* We don't do anything here: idle task is faking death itself. */
  1123. unsigned int i;
  1124. for (i = 0; i < 10; i++) {
  1125. /* They ack this in play_dead by setting CPU_DEAD */
  1126. if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
  1127. printk ("CPU %d is now offline\n", cpu);
  1128. return;
  1129. }
  1130. msleep(100);
  1131. }
  1132. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  1133. }
  1134. #else /* ... !CONFIG_HOTPLUG_CPU */
  1135. int __cpu_disable(void)
  1136. {
  1137. return -ENOSYS;
  1138. }
  1139. void __cpu_die(unsigned int cpu)
  1140. {
  1141. /* We said "no" in __cpu_disable */
  1142. BUG();
  1143. }
  1144. #endif /* CONFIG_HOTPLUG_CPU */
  1145. int __devinit __cpu_up(unsigned int cpu)
  1146. {
  1147. /* In case one didn't come up */
  1148. if (!cpu_isset(cpu, cpu_callin_map)) {
  1149. printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
  1150. local_irq_enable();
  1151. return -EIO;
  1152. }
  1153. local_irq_enable();
  1154. per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
  1155. /* Unleash the CPU! */
  1156. cpu_set(cpu, smp_commenced_mask);
  1157. while (!cpu_isset(cpu, cpu_online_map))
  1158. mb();
  1159. return 0;
  1160. }
  1161. void __init smp_cpus_done(unsigned int max_cpus)
  1162. {
  1163. #ifdef CONFIG_X86_IO_APIC
  1164. setup_ioapic_dest();
  1165. #endif
  1166. zap_low_mappings();
  1167. #ifndef CONFIG_HOTPLUG_CPU
  1168. /*
  1169. * Disable executability of the SMP trampoline:
  1170. */
  1171. set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
  1172. #endif
  1173. }
  1174. void __init smp_intr_init(void)
  1175. {
  1176. /*
  1177. * IRQ0 must be given a fixed assignment and initialized,
  1178. * because it's used before the IO-APIC is set up.
  1179. */
  1180. set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
  1181. /*
  1182. * The reschedule interrupt is a CPU-to-CPU reschedule-helper
  1183. * IPI, driven by wakeup.
  1184. */
  1185. set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
  1186. /* IPI for invalidation */
  1187. set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
  1188. /* IPI for generic function call */
  1189. set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
  1190. }