init.c 40 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/moduleparam.h>
  18. #include <linux/errno.h>
  19. #include <linux/export.h>
  20. #include <linux/of.h>
  21. #include <linux/mmc/sdio_func.h>
  22. #include "core.h"
  23. #include "cfg80211.h"
  24. #include "target.h"
  25. #include "debug.h"
  26. #include "hif-ops.h"
  27. static const struct ath6kl_hw hw_list[] = {
  28. {
  29. .id = AR6003_HW_2_0_VERSION,
  30. .name = "ar6003 hw 2.0",
  31. .dataset_patch_addr = 0x57e884,
  32. .app_load_addr = 0x543180,
  33. .board_ext_data_addr = 0x57e500,
  34. .reserved_ram_size = 6912,
  35. .refclk_hz = 26000000,
  36. .uarttx_pin = 8,
  37. /* hw2.0 needs override address hardcoded */
  38. .app_start_override_addr = 0x944C00,
  39. .fw = {
  40. .dir = AR6003_HW_2_0_FW_DIR,
  41. .otp = AR6003_HW_2_0_OTP_FILE,
  42. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  43. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  44. .patch = AR6003_HW_2_0_PATCH_FILE,
  45. },
  46. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  47. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  48. },
  49. {
  50. .id = AR6003_HW_2_1_1_VERSION,
  51. .name = "ar6003 hw 2.1.1",
  52. .dataset_patch_addr = 0x57ff74,
  53. .app_load_addr = 0x1234,
  54. .board_ext_data_addr = 0x542330,
  55. .reserved_ram_size = 512,
  56. .refclk_hz = 26000000,
  57. .uarttx_pin = 8,
  58. .testscript_addr = 0x57ef74,
  59. .fw = {
  60. .dir = AR6003_HW_2_1_1_FW_DIR,
  61. .otp = AR6003_HW_2_1_1_OTP_FILE,
  62. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  63. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  64. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  65. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  66. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  67. },
  68. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  69. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  70. },
  71. {
  72. .id = AR6004_HW_1_0_VERSION,
  73. .name = "ar6004 hw 1.0",
  74. .dataset_patch_addr = 0x57e884,
  75. .app_load_addr = 0x1234,
  76. .board_ext_data_addr = 0x437000,
  77. .reserved_ram_size = 19456,
  78. .board_addr = 0x433900,
  79. .refclk_hz = 26000000,
  80. .uarttx_pin = 11,
  81. .fw = {
  82. .dir = AR6004_HW_1_0_FW_DIR,
  83. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  84. },
  85. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  86. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  87. },
  88. {
  89. .id = AR6004_HW_1_1_VERSION,
  90. .name = "ar6004 hw 1.1",
  91. .dataset_patch_addr = 0x57e884,
  92. .app_load_addr = 0x1234,
  93. .board_ext_data_addr = 0x437000,
  94. .reserved_ram_size = 11264,
  95. .board_addr = 0x43d400,
  96. .refclk_hz = 40000000,
  97. .uarttx_pin = 11,
  98. .fw = {
  99. .dir = AR6004_HW_1_1_FW_DIR,
  100. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  101. },
  102. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  103. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  104. },
  105. };
  106. /*
  107. * Include definitions here that can be used to tune the WLAN module
  108. * behavior. Different customers can tune the behavior as per their needs,
  109. * here.
  110. */
  111. /*
  112. * This configuration item enable/disable keepalive support.
  113. * Keepalive support: In the absence of any data traffic to AP, null
  114. * frames will be sent to the AP at periodic interval, to keep the association
  115. * active. This configuration item defines the periodic interval.
  116. * Use value of zero to disable keepalive support
  117. * Default: 60 seconds
  118. */
  119. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  120. /*
  121. * This configuration item sets the value of disconnect timeout
  122. * Firmware delays sending the disconnec event to the host for this
  123. * timeout after is gets disconnected from the current AP.
  124. * If the firmware successly roams within the disconnect timeout
  125. * it sends a new connect event
  126. */
  127. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  128. #define ATH6KL_DATA_OFFSET 64
  129. struct sk_buff *ath6kl_buf_alloc(int size)
  130. {
  131. struct sk_buff *skb;
  132. u16 reserved;
  133. /* Add chacheline space at front and back of buffer */
  134. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  135. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  136. skb = dev_alloc_skb(size + reserved);
  137. if (skb)
  138. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  139. return skb;
  140. }
  141. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  142. {
  143. vif->ssid_len = 0;
  144. memset(vif->ssid, 0, sizeof(vif->ssid));
  145. vif->dot11_auth_mode = OPEN_AUTH;
  146. vif->auth_mode = NONE_AUTH;
  147. vif->prwise_crypto = NONE_CRYPT;
  148. vif->prwise_crypto_len = 0;
  149. vif->grp_crypto = NONE_CRYPT;
  150. vif->grp_crypto_len = 0;
  151. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  152. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  153. memset(vif->bssid, 0, sizeof(vif->bssid));
  154. vif->bss_ch = 0;
  155. }
  156. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  157. {
  158. u32 address, data;
  159. struct host_app_area host_app_area;
  160. /* Fetch the address of the host_app_area_s
  161. * instance in the host interest area */
  162. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  163. address = TARG_VTOP(ar->target_type, address);
  164. if (ath6kl_diag_read32(ar, address, &data))
  165. return -EIO;
  166. address = TARG_VTOP(ar->target_type, data);
  167. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  168. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  169. sizeof(struct host_app_area)))
  170. return -EIO;
  171. return 0;
  172. }
  173. static inline void set_ac2_ep_map(struct ath6kl *ar,
  174. u8 ac,
  175. enum htc_endpoint_id ep)
  176. {
  177. ar->ac2ep_map[ac] = ep;
  178. ar->ep2ac_map[ep] = ac;
  179. }
  180. /* connect to a service */
  181. static int ath6kl_connectservice(struct ath6kl *ar,
  182. struct htc_service_connect_req *con_req,
  183. char *desc)
  184. {
  185. int status;
  186. struct htc_service_connect_resp response;
  187. memset(&response, 0, sizeof(response));
  188. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  189. if (status) {
  190. ath6kl_err("failed to connect to %s service status:%d\n",
  191. desc, status);
  192. return status;
  193. }
  194. switch (con_req->svc_id) {
  195. case WMI_CONTROL_SVC:
  196. if (test_bit(WMI_ENABLED, &ar->flag))
  197. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  198. ar->ctrl_ep = response.endpoint;
  199. break;
  200. case WMI_DATA_BE_SVC:
  201. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  202. break;
  203. case WMI_DATA_BK_SVC:
  204. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  205. break;
  206. case WMI_DATA_VI_SVC:
  207. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  208. break;
  209. case WMI_DATA_VO_SVC:
  210. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  211. break;
  212. default:
  213. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  214. return -EINVAL;
  215. }
  216. return 0;
  217. }
  218. static int ath6kl_init_service_ep(struct ath6kl *ar)
  219. {
  220. struct htc_service_connect_req connect;
  221. memset(&connect, 0, sizeof(connect));
  222. /* these fields are the same for all service endpoints */
  223. connect.ep_cb.rx = ath6kl_rx;
  224. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  225. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  226. /*
  227. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  228. * gets called.
  229. */
  230. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  231. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  232. if (!connect.ep_cb.rx_refill_thresh)
  233. connect.ep_cb.rx_refill_thresh++;
  234. /* connect to control service */
  235. connect.svc_id = WMI_CONTROL_SVC;
  236. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  237. return -EIO;
  238. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  239. /*
  240. * Limit the HTC message size on the send path, although e can
  241. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  242. * (802.3) frames on the send path.
  243. */
  244. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  245. /*
  246. * To reduce the amount of committed memory for larger A_MSDU
  247. * frames, use the recv-alloc threshold mechanism for larger
  248. * packets.
  249. */
  250. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  251. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  252. /*
  253. * For the remaining data services set the connection flag to
  254. * reduce dribbling, if configured to do so.
  255. */
  256. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  257. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  258. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  259. connect.svc_id = WMI_DATA_BE_SVC;
  260. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  261. return -EIO;
  262. /* connect to back-ground map this to WMI LOW_PRI */
  263. connect.svc_id = WMI_DATA_BK_SVC;
  264. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  265. return -EIO;
  266. /* connect to Video service, map this to to HI PRI */
  267. connect.svc_id = WMI_DATA_VI_SVC;
  268. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  269. return -EIO;
  270. /*
  271. * Connect to VO service, this is currently not mapped to a WMI
  272. * priority stream due to historical reasons. WMI originally
  273. * defined 3 priorities over 3 mailboxes We can change this when
  274. * WMI is reworked so that priorities are not dependent on
  275. * mailboxes.
  276. */
  277. connect.svc_id = WMI_DATA_VO_SVC;
  278. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  279. return -EIO;
  280. return 0;
  281. }
  282. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  283. {
  284. ath6kl_init_profile_info(vif);
  285. vif->def_txkey_index = 0;
  286. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  287. vif->ch_hint = 0;
  288. }
  289. /*
  290. * Set HTC/Mbox operational parameters, this can only be called when the
  291. * target is in the BMI phase.
  292. */
  293. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  294. u8 htc_ctrl_buf)
  295. {
  296. int status;
  297. u32 blk_size;
  298. blk_size = ar->mbox_info.block_size;
  299. if (htc_ctrl_buf)
  300. blk_size |= ((u32)htc_ctrl_buf) << 16;
  301. /* set the host interest area for the block size */
  302. status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
  303. if (status) {
  304. ath6kl_err("bmi_write_memory for IO block size failed\n");
  305. goto out;
  306. }
  307. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  308. blk_size,
  309. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  310. if (mbox_isr_yield_val) {
  311. /* set the host interest area for the mbox ISR yield limit */
  312. status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
  313. mbox_isr_yield_val);
  314. if (status) {
  315. ath6kl_err("bmi_write_memory for yield limit failed\n");
  316. goto out;
  317. }
  318. }
  319. out:
  320. return status;
  321. }
  322. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  323. {
  324. int ret;
  325. /*
  326. * Configure the device for rx dot11 header rules. "0,0" are the
  327. * default values. Required if checksum offload is needed. Set
  328. * RxMetaVersion to 2.
  329. */
  330. ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  331. ar->rx_meta_ver, 0, 0);
  332. if (ret) {
  333. ath6kl_err("unable to set the rx frame format: %d\n", ret);
  334. return ret;
  335. }
  336. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
  337. ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  338. IGNORE_PS_FAIL_DURING_SCAN);
  339. if (ret) {
  340. ath6kl_err("unable to set power save fail event policy: %d\n",
  341. ret);
  342. return ret;
  343. }
  344. }
  345. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
  346. ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  347. WMI_FOLLOW_BARKER_IN_ERP);
  348. if (ret) {
  349. ath6kl_err("unable to set barker preamble policy: %d\n",
  350. ret);
  351. return ret;
  352. }
  353. }
  354. ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  355. WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
  356. if (ret) {
  357. ath6kl_err("unable to set keep alive interval: %d\n", ret);
  358. return ret;
  359. }
  360. ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  361. WLAN_CONFIG_DISCONNECT_TIMEOUT);
  362. if (ret) {
  363. ath6kl_err("unable to set disconnect timeout: %d\n", ret);
  364. return ret;
  365. }
  366. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
  367. ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
  368. if (ret) {
  369. ath6kl_err("unable to set txop bursting: %d\n", ret);
  370. return ret;
  371. }
  372. }
  373. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  374. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  375. P2P_FLAG_CAPABILITIES_REQ |
  376. P2P_FLAG_MACADDR_REQ |
  377. P2P_FLAG_HMODEL_REQ);
  378. if (ret) {
  379. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
  380. "capabilities (%d) - assuming P2P not "
  381. "supported\n", ret);
  382. ar->p2p = false;
  383. }
  384. }
  385. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  386. /* Enable Probe Request reporting for P2P */
  387. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  388. if (ret) {
  389. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
  390. "Request reporting (%d)\n", ret);
  391. }
  392. }
  393. return ret;
  394. }
  395. int ath6kl_configure_target(struct ath6kl *ar)
  396. {
  397. u32 param, ram_reserved_size;
  398. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  399. int i, status;
  400. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  401. if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
  402. ath6kl_err("bmi_write_memory for uart debug failed\n");
  403. return -EIO;
  404. }
  405. /*
  406. * Note: Even though the firmware interface type is
  407. * chosen as BSS_STA for all three interfaces, can
  408. * be configured to IBSS/AP as long as the fw submode
  409. * remains normal mode (0 - AP, STA and IBSS). But
  410. * due to an target assert in firmware only one interface is
  411. * configured for now.
  412. */
  413. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  414. for (i = 0; i < ar->vif_max; i++)
  415. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  416. /*
  417. * By default, submodes :
  418. * vif[0] - AP/STA/IBSS
  419. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  420. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  421. */
  422. for (i = 0; i < ar->max_norm_iface; i++)
  423. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  424. (i * HI_OPTION_FW_SUBMODE_BITS);
  425. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  426. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  427. (i * HI_OPTION_FW_SUBMODE_BITS);
  428. if (ar->p2p && ar->vif_max == 1)
  429. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  430. if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
  431. HTC_PROTOCOL_VERSION) != 0) {
  432. ath6kl_err("bmi_write_memory for htc version failed\n");
  433. return -EIO;
  434. }
  435. /* set the firmware mode to STA/IBSS/AP */
  436. param = 0;
  437. if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
  438. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  439. return -EIO;
  440. }
  441. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  442. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  443. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  444. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  445. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  446. if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
  447. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  448. return -EIO;
  449. }
  450. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  451. /*
  452. * Hardcode the address use for the extended board data
  453. * Ideally this should be pre-allocate by the OS at boot time
  454. * But since it is a new feature and board data is loaded
  455. * at init time, we have to workaround this from host.
  456. * It is difficult to patch the firmware boot code,
  457. * but possible in theory.
  458. */
  459. if (ar->target_type == TARGET_TYPE_AR6003) {
  460. param = ar->hw.board_ext_data_addr;
  461. ram_reserved_size = ar->hw.reserved_ram_size;
  462. if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
  463. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  464. return -EIO;
  465. }
  466. if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
  467. ram_reserved_size) != 0) {
  468. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  469. return -EIO;
  470. }
  471. }
  472. /* set the block size for the target */
  473. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  474. /* use default number of control buffers */
  475. return -EIO;
  476. /* Configure GPIO AR600x UART */
  477. status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
  478. ar->hw.uarttx_pin);
  479. if (status)
  480. return status;
  481. /* Configure target refclk_hz */
  482. status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
  483. if (status)
  484. return status;
  485. return 0;
  486. }
  487. /* firmware upload */
  488. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  489. u8 **fw, size_t *fw_len)
  490. {
  491. const struct firmware *fw_entry;
  492. int ret;
  493. ret = request_firmware(&fw_entry, filename, ar->dev);
  494. if (ret)
  495. return ret;
  496. *fw_len = fw_entry->size;
  497. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  498. if (*fw == NULL)
  499. ret = -ENOMEM;
  500. release_firmware(fw_entry);
  501. return ret;
  502. }
  503. #ifdef CONFIG_OF
  504. /*
  505. * Check the device tree for a board-id and use it to construct
  506. * the pathname to the firmware file. Used (for now) to find a
  507. * fallback to the "bdata.bin" file--typically a symlink to the
  508. * appropriate board-specific file.
  509. */
  510. static bool check_device_tree(struct ath6kl *ar)
  511. {
  512. static const char *board_id_prop = "atheros,board-id";
  513. struct device_node *node;
  514. char board_filename[64];
  515. const char *board_id;
  516. int ret;
  517. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  518. board_id = of_get_property(node, board_id_prop, NULL);
  519. if (board_id == NULL) {
  520. ath6kl_warn("No \"%s\" property on %s node.\n",
  521. board_id_prop, node->name);
  522. continue;
  523. }
  524. snprintf(board_filename, sizeof(board_filename),
  525. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  526. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  527. &ar->fw_board_len);
  528. if (ret) {
  529. ath6kl_err("Failed to get DT board file %s: %d\n",
  530. board_filename, ret);
  531. continue;
  532. }
  533. return true;
  534. }
  535. return false;
  536. }
  537. #else
  538. static bool check_device_tree(struct ath6kl *ar)
  539. {
  540. return false;
  541. }
  542. #endif /* CONFIG_OF */
  543. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  544. {
  545. const char *filename;
  546. int ret;
  547. if (ar->fw_board != NULL)
  548. return 0;
  549. if (WARN_ON(ar->hw.fw_board == NULL))
  550. return -EINVAL;
  551. filename = ar->hw.fw_board;
  552. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  553. &ar->fw_board_len);
  554. if (ret == 0) {
  555. /* managed to get proper board file */
  556. return 0;
  557. }
  558. if (check_device_tree(ar)) {
  559. /* got board file from device tree */
  560. return 0;
  561. }
  562. /* there was no proper board file, try to use default instead */
  563. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  564. filename, ret);
  565. filename = ar->hw.fw_default_board;
  566. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  567. &ar->fw_board_len);
  568. if (ret) {
  569. ath6kl_err("Failed to get default board file %s: %d\n",
  570. filename, ret);
  571. return ret;
  572. }
  573. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  574. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  575. return 0;
  576. }
  577. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  578. {
  579. char filename[100];
  580. int ret;
  581. if (ar->fw_otp != NULL)
  582. return 0;
  583. if (ar->hw.fw.otp == NULL) {
  584. ath6kl_dbg(ATH6KL_DBG_BOOT,
  585. "no OTP file configured for this hw\n");
  586. return 0;
  587. }
  588. snprintf(filename, sizeof(filename), "%s/%s",
  589. ar->hw.fw.dir, ar->hw.fw.otp);
  590. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  591. &ar->fw_otp_len);
  592. if (ret) {
  593. ath6kl_err("Failed to get OTP file %s: %d\n",
  594. filename, ret);
  595. return ret;
  596. }
  597. return 0;
  598. }
  599. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  600. {
  601. char filename[100];
  602. int ret;
  603. if (ar->testmode == 0)
  604. return 0;
  605. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  606. if (ar->testmode == 2) {
  607. if (ar->hw.fw.utf == NULL) {
  608. ath6kl_warn("testmode 2 not supported\n");
  609. return -EOPNOTSUPP;
  610. }
  611. snprintf(filename, sizeof(filename), "%s/%s",
  612. ar->hw.fw.dir, ar->hw.fw.utf);
  613. } else {
  614. if (ar->hw.fw.tcmd == NULL) {
  615. ath6kl_warn("testmode 1 not supported\n");
  616. return -EOPNOTSUPP;
  617. }
  618. snprintf(filename, sizeof(filename), "%s/%s",
  619. ar->hw.fw.dir, ar->hw.fw.tcmd);
  620. }
  621. set_bit(TESTMODE, &ar->flag);
  622. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  623. if (ret) {
  624. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  625. ar->testmode, filename, ret);
  626. return ret;
  627. }
  628. return 0;
  629. }
  630. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  631. {
  632. char filename[100];
  633. int ret;
  634. if (ar->fw != NULL)
  635. return 0;
  636. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  637. if (WARN_ON(ar->hw.fw.fw == NULL))
  638. return -EINVAL;
  639. snprintf(filename, sizeof(filename), "%s/%s",
  640. ar->hw.fw.dir, ar->hw.fw.fw);
  641. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  642. if (ret) {
  643. ath6kl_err("Failed to get firmware file %s: %d\n",
  644. filename, ret);
  645. return ret;
  646. }
  647. return 0;
  648. }
  649. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  650. {
  651. char filename[100];
  652. int ret;
  653. if (ar->fw_patch != NULL)
  654. return 0;
  655. if (ar->hw.fw.patch == NULL)
  656. return 0;
  657. snprintf(filename, sizeof(filename), "%s/%s",
  658. ar->hw.fw.dir, ar->hw.fw.patch);
  659. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  660. &ar->fw_patch_len);
  661. if (ret) {
  662. ath6kl_err("Failed to get patch file %s: %d\n",
  663. filename, ret);
  664. return ret;
  665. }
  666. return 0;
  667. }
  668. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  669. {
  670. char filename[100];
  671. int ret;
  672. if (ar->testmode != 2)
  673. return 0;
  674. if (ar->fw_testscript != NULL)
  675. return 0;
  676. if (ar->hw.fw.testscript == NULL)
  677. return 0;
  678. snprintf(filename, sizeof(filename), "%s/%s",
  679. ar->hw.fw.dir, ar->hw.fw.testscript);
  680. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  681. &ar->fw_testscript_len);
  682. if (ret) {
  683. ath6kl_err("Failed to get testscript file %s: %d\n",
  684. filename, ret);
  685. return ret;
  686. }
  687. return 0;
  688. }
  689. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  690. {
  691. int ret;
  692. ret = ath6kl_fetch_otp_file(ar);
  693. if (ret)
  694. return ret;
  695. ret = ath6kl_fetch_fw_file(ar);
  696. if (ret)
  697. return ret;
  698. ret = ath6kl_fetch_patch_file(ar);
  699. if (ret)
  700. return ret;
  701. ret = ath6kl_fetch_testscript_file(ar);
  702. if (ret)
  703. return ret;
  704. return 0;
  705. }
  706. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  707. {
  708. size_t magic_len, len, ie_len;
  709. const struct firmware *fw;
  710. struct ath6kl_fw_ie *hdr;
  711. char filename[100];
  712. const u8 *data;
  713. int ret, ie_id, i, index, bit;
  714. __le32 *val;
  715. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  716. ret = request_firmware(&fw, filename, ar->dev);
  717. if (ret)
  718. return ret;
  719. data = fw->data;
  720. len = fw->size;
  721. /* magic also includes the null byte, check that as well */
  722. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  723. if (len < magic_len) {
  724. ret = -EINVAL;
  725. goto out;
  726. }
  727. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  728. ret = -EINVAL;
  729. goto out;
  730. }
  731. len -= magic_len;
  732. data += magic_len;
  733. /* loop elements */
  734. while (len > sizeof(struct ath6kl_fw_ie)) {
  735. /* hdr is unaligned! */
  736. hdr = (struct ath6kl_fw_ie *) data;
  737. ie_id = le32_to_cpup(&hdr->id);
  738. ie_len = le32_to_cpup(&hdr->len);
  739. len -= sizeof(*hdr);
  740. data += sizeof(*hdr);
  741. if (len < ie_len) {
  742. ret = -EINVAL;
  743. goto out;
  744. }
  745. switch (ie_id) {
  746. case ATH6KL_FW_IE_OTP_IMAGE:
  747. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  748. ie_len);
  749. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  750. if (ar->fw_otp == NULL) {
  751. ret = -ENOMEM;
  752. goto out;
  753. }
  754. ar->fw_otp_len = ie_len;
  755. break;
  756. case ATH6KL_FW_IE_FW_IMAGE:
  757. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  758. ie_len);
  759. /* in testmode we already might have a fw file */
  760. if (ar->fw != NULL)
  761. break;
  762. ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
  763. if (ar->fw == NULL) {
  764. ret = -ENOMEM;
  765. goto out;
  766. }
  767. ar->fw_len = ie_len;
  768. break;
  769. case ATH6KL_FW_IE_PATCH_IMAGE:
  770. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  771. ie_len);
  772. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  773. if (ar->fw_patch == NULL) {
  774. ret = -ENOMEM;
  775. goto out;
  776. }
  777. ar->fw_patch_len = ie_len;
  778. break;
  779. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  780. val = (__le32 *) data;
  781. ar->hw.reserved_ram_size = le32_to_cpup(val);
  782. ath6kl_dbg(ATH6KL_DBG_BOOT,
  783. "found reserved ram size ie 0x%d\n",
  784. ar->hw.reserved_ram_size);
  785. break;
  786. case ATH6KL_FW_IE_CAPABILITIES:
  787. if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
  788. break;
  789. ath6kl_dbg(ATH6KL_DBG_BOOT,
  790. "found firmware capabilities ie (%zd B)\n",
  791. ie_len);
  792. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  793. index = i / 8;
  794. bit = i % 8;
  795. if (data[index] & (1 << bit))
  796. __set_bit(i, ar->fw_capabilities);
  797. }
  798. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  799. ar->fw_capabilities,
  800. sizeof(ar->fw_capabilities));
  801. break;
  802. case ATH6KL_FW_IE_PATCH_ADDR:
  803. if (ie_len != sizeof(*val))
  804. break;
  805. val = (__le32 *) data;
  806. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  807. ath6kl_dbg(ATH6KL_DBG_BOOT,
  808. "found patch address ie 0x%x\n",
  809. ar->hw.dataset_patch_addr);
  810. break;
  811. case ATH6KL_FW_IE_BOARD_ADDR:
  812. if (ie_len != sizeof(*val))
  813. break;
  814. val = (__le32 *) data;
  815. ar->hw.board_addr = le32_to_cpup(val);
  816. ath6kl_dbg(ATH6KL_DBG_BOOT,
  817. "found board address ie 0x%x\n",
  818. ar->hw.board_addr);
  819. break;
  820. case ATH6KL_FW_IE_VIF_MAX:
  821. if (ie_len != sizeof(*val))
  822. break;
  823. val = (__le32 *) data;
  824. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  825. ATH6KL_VIF_MAX);
  826. if (ar->vif_max > 1 && !ar->p2p)
  827. ar->max_norm_iface = 2;
  828. ath6kl_dbg(ATH6KL_DBG_BOOT,
  829. "found vif max ie %d\n", ar->vif_max);
  830. break;
  831. default:
  832. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  833. le32_to_cpup(&hdr->id));
  834. break;
  835. }
  836. len -= ie_len;
  837. data += ie_len;
  838. };
  839. ret = 0;
  840. out:
  841. release_firmware(fw);
  842. return ret;
  843. }
  844. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  845. {
  846. int ret;
  847. ret = ath6kl_fetch_board_file(ar);
  848. if (ret)
  849. return ret;
  850. ret = ath6kl_fetch_testmode_file(ar);
  851. if (ret)
  852. return ret;
  853. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  854. if (ret == 0) {
  855. ar->fw_api = 3;
  856. goto out;
  857. }
  858. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  859. if (ret == 0) {
  860. ar->fw_api = 2;
  861. goto out;
  862. }
  863. ret = ath6kl_fetch_fw_api1(ar);
  864. if (ret)
  865. return ret;
  866. ar->fw_api = 1;
  867. out:
  868. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  869. return 0;
  870. }
  871. static int ath6kl_upload_board_file(struct ath6kl *ar)
  872. {
  873. u32 board_address, board_ext_address, param;
  874. u32 board_data_size, board_ext_data_size;
  875. int ret;
  876. if (WARN_ON(ar->fw_board == NULL))
  877. return -ENOENT;
  878. /*
  879. * Determine where in Target RAM to write Board Data.
  880. * For AR6004, host determine Target RAM address for
  881. * writing board data.
  882. */
  883. if (ar->hw.board_addr != 0) {
  884. board_address = ar->hw.board_addr;
  885. ath6kl_bmi_write_hi32(ar, hi_board_data,
  886. board_address);
  887. } else {
  888. ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
  889. }
  890. /* determine where in target ram to write extended board data */
  891. ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
  892. if (ar->target_type == TARGET_TYPE_AR6003 &&
  893. board_ext_address == 0) {
  894. ath6kl_err("Failed to get board file target address.\n");
  895. return -EINVAL;
  896. }
  897. switch (ar->target_type) {
  898. case TARGET_TYPE_AR6003:
  899. board_data_size = AR6003_BOARD_DATA_SZ;
  900. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  901. if (ar->fw_board_len > (board_data_size + board_ext_data_size))
  902. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
  903. break;
  904. case TARGET_TYPE_AR6004:
  905. board_data_size = AR6004_BOARD_DATA_SZ;
  906. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  907. break;
  908. default:
  909. WARN_ON(1);
  910. return -EINVAL;
  911. break;
  912. }
  913. if (board_ext_address &&
  914. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  915. /* write extended board data */
  916. ath6kl_dbg(ATH6KL_DBG_BOOT,
  917. "writing extended board data to 0x%x (%d B)\n",
  918. board_ext_address, board_ext_data_size);
  919. ret = ath6kl_bmi_write(ar, board_ext_address,
  920. ar->fw_board + board_data_size,
  921. board_ext_data_size);
  922. if (ret) {
  923. ath6kl_err("Failed to write extended board data: %d\n",
  924. ret);
  925. return ret;
  926. }
  927. /* record that extended board data is initialized */
  928. param = (board_ext_data_size << 16) | 1;
  929. ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
  930. }
  931. if (ar->fw_board_len < board_data_size) {
  932. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  933. ret = -EINVAL;
  934. return ret;
  935. }
  936. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  937. board_address, board_data_size);
  938. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  939. board_data_size);
  940. if (ret) {
  941. ath6kl_err("Board file bmi write failed: %d\n", ret);
  942. return ret;
  943. }
  944. /* record the fact that Board Data IS initialized */
  945. ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
  946. return ret;
  947. }
  948. static int ath6kl_upload_otp(struct ath6kl *ar)
  949. {
  950. u32 address, param;
  951. bool from_hw = false;
  952. int ret;
  953. if (ar->fw_otp == NULL)
  954. return 0;
  955. address = ar->hw.app_load_addr;
  956. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  957. ar->fw_otp_len);
  958. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  959. ar->fw_otp_len);
  960. if (ret) {
  961. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  962. return ret;
  963. }
  964. /* read firmware start address */
  965. ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
  966. if (ret) {
  967. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  968. return ret;
  969. }
  970. if (ar->hw.app_start_override_addr == 0) {
  971. ar->hw.app_start_override_addr = address;
  972. from_hw = true;
  973. }
  974. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  975. from_hw ? " (from hw)" : "",
  976. ar->hw.app_start_override_addr);
  977. /* execute the OTP code */
  978. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  979. ar->hw.app_start_override_addr);
  980. param = 0;
  981. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  982. return ret;
  983. }
  984. static int ath6kl_upload_firmware(struct ath6kl *ar)
  985. {
  986. u32 address;
  987. int ret;
  988. if (WARN_ON(ar->fw == NULL))
  989. return 0;
  990. address = ar->hw.app_load_addr;
  991. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  992. address, ar->fw_len);
  993. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  994. if (ret) {
  995. ath6kl_err("Failed to write firmware: %d\n", ret);
  996. return ret;
  997. }
  998. /*
  999. * Set starting address for firmware
  1000. * Don't need to setup app_start override addr on AR6004
  1001. */
  1002. if (ar->target_type != TARGET_TYPE_AR6004) {
  1003. address = ar->hw.app_start_override_addr;
  1004. ath6kl_bmi_set_app_start(ar, address);
  1005. }
  1006. return ret;
  1007. }
  1008. static int ath6kl_upload_patch(struct ath6kl *ar)
  1009. {
  1010. u32 address;
  1011. int ret;
  1012. if (ar->fw_patch == NULL)
  1013. return 0;
  1014. address = ar->hw.dataset_patch_addr;
  1015. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1016. address, ar->fw_patch_len);
  1017. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1018. if (ret) {
  1019. ath6kl_err("Failed to write patch file: %d\n", ret);
  1020. return ret;
  1021. }
  1022. ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
  1023. return 0;
  1024. }
  1025. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1026. {
  1027. u32 address;
  1028. int ret;
  1029. if (ar->testmode != 2)
  1030. return 0;
  1031. if (ar->fw_testscript == NULL)
  1032. return 0;
  1033. address = ar->hw.testscript_addr;
  1034. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1035. address, ar->fw_testscript_len);
  1036. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1037. ar->fw_testscript_len);
  1038. if (ret) {
  1039. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1040. return ret;
  1041. }
  1042. ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
  1043. ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
  1044. ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
  1045. return 0;
  1046. }
  1047. static int ath6kl_init_upload(struct ath6kl *ar)
  1048. {
  1049. u32 param, options, sleep, address;
  1050. int status = 0;
  1051. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1052. ar->target_type != TARGET_TYPE_AR6004)
  1053. return -EINVAL;
  1054. /* temporarily disable system sleep */
  1055. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1056. status = ath6kl_bmi_reg_read(ar, address, &param);
  1057. if (status)
  1058. return status;
  1059. options = param;
  1060. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1061. status = ath6kl_bmi_reg_write(ar, address, param);
  1062. if (status)
  1063. return status;
  1064. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1065. status = ath6kl_bmi_reg_read(ar, address, &param);
  1066. if (status)
  1067. return status;
  1068. sleep = param;
  1069. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1070. status = ath6kl_bmi_reg_write(ar, address, param);
  1071. if (status)
  1072. return status;
  1073. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1074. options, sleep);
  1075. /* program analog PLL register */
  1076. /* no need to control 40/44MHz clock on AR6004 */
  1077. if (ar->target_type != TARGET_TYPE_AR6004) {
  1078. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1079. 0xF9104001);
  1080. if (status)
  1081. return status;
  1082. /* Run at 80/88MHz by default */
  1083. param = SM(CPU_CLOCK_STANDARD, 1);
  1084. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1085. status = ath6kl_bmi_reg_write(ar, address, param);
  1086. if (status)
  1087. return status;
  1088. }
  1089. param = 0;
  1090. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1091. param = SM(LPO_CAL_ENABLE, 1);
  1092. status = ath6kl_bmi_reg_write(ar, address, param);
  1093. if (status)
  1094. return status;
  1095. /* WAR to avoid SDIO CRC err */
  1096. if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
  1097. ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
  1098. ath6kl_err("temporary war to avoid sdio crc error\n");
  1099. param = 0x20;
  1100. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1101. status = ath6kl_bmi_reg_write(ar, address, param);
  1102. if (status)
  1103. return status;
  1104. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1105. status = ath6kl_bmi_reg_write(ar, address, param);
  1106. if (status)
  1107. return status;
  1108. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1109. status = ath6kl_bmi_reg_write(ar, address, param);
  1110. if (status)
  1111. return status;
  1112. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1113. status = ath6kl_bmi_reg_write(ar, address, param);
  1114. if (status)
  1115. return status;
  1116. }
  1117. /* write EEPROM data to Target RAM */
  1118. status = ath6kl_upload_board_file(ar);
  1119. if (status)
  1120. return status;
  1121. /* transfer One time Programmable data */
  1122. status = ath6kl_upload_otp(ar);
  1123. if (status)
  1124. return status;
  1125. /* Download Target firmware */
  1126. status = ath6kl_upload_firmware(ar);
  1127. if (status)
  1128. return status;
  1129. status = ath6kl_upload_patch(ar);
  1130. if (status)
  1131. return status;
  1132. /* Download the test script */
  1133. status = ath6kl_upload_testscript(ar);
  1134. if (status)
  1135. return status;
  1136. /* Restore system sleep */
  1137. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1138. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1139. if (status)
  1140. return status;
  1141. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1142. param = options | 0x20;
  1143. status = ath6kl_bmi_reg_write(ar, address, param);
  1144. if (status)
  1145. return status;
  1146. return status;
  1147. }
  1148. int ath6kl_init_hw_params(struct ath6kl *ar)
  1149. {
  1150. const struct ath6kl_hw *uninitialized_var(hw);
  1151. int i;
  1152. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1153. hw = &hw_list[i];
  1154. if (hw->id == ar->version.target_ver)
  1155. break;
  1156. }
  1157. if (i == ARRAY_SIZE(hw_list)) {
  1158. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1159. ar->version.target_ver);
  1160. return -EINVAL;
  1161. }
  1162. ar->hw = *hw;
  1163. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1164. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1165. ar->version.target_ver, ar->target_type,
  1166. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1167. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1168. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1169. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1170. ar->hw.reserved_ram_size);
  1171. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1172. "refclk_hz %d uarttx_pin %d",
  1173. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1174. return 0;
  1175. }
  1176. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1177. {
  1178. switch (type) {
  1179. case ATH6KL_HIF_TYPE_SDIO:
  1180. return "sdio";
  1181. case ATH6KL_HIF_TYPE_USB:
  1182. return "usb";
  1183. }
  1184. return NULL;
  1185. }
  1186. int ath6kl_init_hw_start(struct ath6kl *ar)
  1187. {
  1188. long timeleft;
  1189. int ret, i;
  1190. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1191. ret = ath6kl_hif_power_on(ar);
  1192. if (ret)
  1193. return ret;
  1194. ret = ath6kl_configure_target(ar);
  1195. if (ret)
  1196. goto err_power_off;
  1197. ret = ath6kl_init_upload(ar);
  1198. if (ret)
  1199. goto err_power_off;
  1200. /* Do we need to finish the BMI phase */
  1201. /* FIXME: return error from ath6kl_bmi_done() */
  1202. if (ath6kl_bmi_done(ar)) {
  1203. ret = -EIO;
  1204. goto err_power_off;
  1205. }
  1206. /*
  1207. * The reason we have to wait for the target here is that the
  1208. * driver layer has to init BMI in order to set the host block
  1209. * size.
  1210. */
  1211. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1212. ret = -EIO;
  1213. goto err_power_off;
  1214. }
  1215. if (ath6kl_init_service_ep(ar)) {
  1216. ret = -EIO;
  1217. goto err_cleanup_scatter;
  1218. }
  1219. /* setup credit distribution */
  1220. ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
  1221. /* start HTC */
  1222. ret = ath6kl_htc_start(ar->htc_target);
  1223. if (ret) {
  1224. /* FIXME: call this */
  1225. ath6kl_cookie_cleanup(ar);
  1226. goto err_cleanup_scatter;
  1227. }
  1228. /* Wait for Wmi event to be ready */
  1229. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1230. test_bit(WMI_READY,
  1231. &ar->flag),
  1232. WMI_TIMEOUT);
  1233. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1234. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1235. ath6kl_info("%s %s fw %s api %d%s\n",
  1236. ar->hw.name,
  1237. ath6kl_init_get_hif_name(ar->hif_type),
  1238. ar->wiphy->fw_version,
  1239. ar->fw_api,
  1240. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1241. }
  1242. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1243. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1244. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1245. ret = -EIO;
  1246. goto err_htc_stop;
  1247. }
  1248. if (!timeleft || signal_pending(current)) {
  1249. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1250. ret = -EIO;
  1251. goto err_htc_stop;
  1252. }
  1253. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1254. /* communicate the wmi protocol verision to the target */
  1255. /* FIXME: return error */
  1256. if ((ath6kl_set_host_app_area(ar)) != 0)
  1257. ath6kl_err("unable to set the host app area\n");
  1258. for (i = 0; i < ar->vif_max; i++) {
  1259. ret = ath6kl_target_config_wlan_params(ar, i);
  1260. if (ret)
  1261. goto err_htc_stop;
  1262. }
  1263. ar->state = ATH6KL_STATE_ON;
  1264. return 0;
  1265. err_htc_stop:
  1266. ath6kl_htc_stop(ar->htc_target);
  1267. err_cleanup_scatter:
  1268. ath6kl_hif_cleanup_scatter(ar);
  1269. err_power_off:
  1270. ath6kl_hif_power_off(ar);
  1271. return ret;
  1272. }
  1273. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1274. {
  1275. int ret;
  1276. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1277. ath6kl_htc_stop(ar->htc_target);
  1278. ath6kl_hif_stop(ar);
  1279. ath6kl_bmi_reset(ar);
  1280. ret = ath6kl_hif_power_off(ar);
  1281. if (ret)
  1282. ath6kl_warn("failed to power off hif: %d\n", ret);
  1283. ar->state = ATH6KL_STATE_OFF;
  1284. return 0;
  1285. }
  1286. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1287. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1288. {
  1289. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1290. bool discon_issued;
  1291. netif_stop_queue(vif->ndev);
  1292. clear_bit(WLAN_ENABLED, &vif->flags);
  1293. if (wmi_ready) {
  1294. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1295. test_bit(CONNECT_PEND, &vif->flags);
  1296. ath6kl_disconnect(vif);
  1297. del_timer(&vif->disconnect_timer);
  1298. if (discon_issued)
  1299. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1300. (vif->nw_type & AP_NETWORK) ?
  1301. bcast_mac : vif->bssid,
  1302. 0, NULL, 0);
  1303. }
  1304. if (vif->scan_req) {
  1305. cfg80211_scan_done(vif->scan_req, true);
  1306. vif->scan_req = NULL;
  1307. }
  1308. }
  1309. void ath6kl_stop_txrx(struct ath6kl *ar)
  1310. {
  1311. struct ath6kl_vif *vif, *tmp_vif;
  1312. int i;
  1313. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1314. if (down_interruptible(&ar->sem)) {
  1315. ath6kl_err("down_interruptible failed\n");
  1316. return;
  1317. }
  1318. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1319. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1320. spin_lock_bh(&ar->list_lock);
  1321. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1322. list_del(&vif->list);
  1323. spin_unlock_bh(&ar->list_lock);
  1324. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1325. rtnl_lock();
  1326. ath6kl_cfg80211_vif_cleanup(vif);
  1327. rtnl_unlock();
  1328. spin_lock_bh(&ar->list_lock);
  1329. }
  1330. spin_unlock_bh(&ar->list_lock);
  1331. clear_bit(WMI_READY, &ar->flag);
  1332. /*
  1333. * After wmi_shudown all WMI events will be dropped. We
  1334. * need to cleanup the buffers allocated in AP mode and
  1335. * give disconnect notification to stack, which usually
  1336. * happens in the disconnect_event. Simulate the disconnect
  1337. * event by calling the function directly. Sometimes
  1338. * disconnect_event will be received when the debug logs
  1339. * are collected.
  1340. */
  1341. ath6kl_wmi_shutdown(ar->wmi);
  1342. clear_bit(WMI_ENABLED, &ar->flag);
  1343. if (ar->htc_target) {
  1344. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1345. ath6kl_htc_stop(ar->htc_target);
  1346. }
  1347. /*
  1348. * Try to reset the device if we can. The driver may have been
  1349. * configure NOT to reset the target during a debug session.
  1350. */
  1351. ath6kl_dbg(ATH6KL_DBG_TRC,
  1352. "attempting to reset target on instance destroy\n");
  1353. ath6kl_reset_device(ar, ar->target_type, true, true);
  1354. clear_bit(WLAN_ENABLED, &ar->flag);
  1355. up(&ar->sem);
  1356. }
  1357. EXPORT_SYMBOL(ath6kl_stop_txrx);