tg3.c 398 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2010 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/compiler.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/in.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/mii.h>
  33. #include <linux/phy.h>
  34. #include <linux/brcmphy.h>
  35. #include <linux/if_vlan.h>
  36. #include <linux/ip.h>
  37. #include <linux/tcp.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/prefetch.h>
  40. #include <linux/dma-mapping.h>
  41. #include <linux/firmware.h>
  42. #include <net/checksum.h>
  43. #include <net/ip.h>
  44. #include <asm/system.h>
  45. #include <asm/io.h>
  46. #include <asm/byteorder.h>
  47. #include <asm/uaccess.h>
  48. #ifdef CONFIG_SPARC
  49. #include <asm/idprom.h>
  50. #include <asm/prom.h>
  51. #endif
  52. #define BAR_0 0
  53. #define BAR_2 2
  54. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  55. #define TG3_VLAN_TAG_USED 1
  56. #else
  57. #define TG3_VLAN_TAG_USED 0
  58. #endif
  59. #include "tg3.h"
  60. #define DRV_MODULE_NAME "tg3"
  61. #define PFX DRV_MODULE_NAME ": "
  62. #define DRV_MODULE_VERSION "3.106"
  63. #define DRV_MODULE_RELDATE "January 12, 2010"
  64. #define TG3_DEF_MAC_MODE 0
  65. #define TG3_DEF_RX_MODE 0
  66. #define TG3_DEF_TX_MODE 0
  67. #define TG3_DEF_MSG_ENABLE \
  68. (NETIF_MSG_DRV | \
  69. NETIF_MSG_PROBE | \
  70. NETIF_MSG_LINK | \
  71. NETIF_MSG_TIMER | \
  72. NETIF_MSG_IFDOWN | \
  73. NETIF_MSG_IFUP | \
  74. NETIF_MSG_RX_ERR | \
  75. NETIF_MSG_TX_ERR)
  76. /* length of time before we decide the hardware is borked,
  77. * and dev->tx_timeout() should be called to fix the problem
  78. */
  79. #define TG3_TX_TIMEOUT (5 * HZ)
  80. /* hardware minimum and maximum for a single frame's data payload */
  81. #define TG3_MIN_MTU 60
  82. #define TG3_MAX_MTU(tp) \
  83. ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  84. /* These numbers seem to be hard coded in the NIC firmware somehow.
  85. * You can't change the ring sizes, but you can change where you place
  86. * them in the NIC onboard memory.
  87. */
  88. #define TG3_RX_RING_SIZE 512
  89. #define TG3_DEF_RX_RING_PENDING 200
  90. #define TG3_RX_JUMBO_RING_SIZE 256
  91. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  92. #define TG3_RSS_INDIR_TBL_SIZE 128
  93. /* Do not place this n-ring entries value into the tp struct itself,
  94. * we really want to expose these constants to GCC so that modulo et
  95. * al. operations are done with shifts and masks instead of with
  96. * hw multiply/modulo instructions. Another solution would be to
  97. * replace things like '% foo' with '& (foo - 1)'.
  98. */
  99. #define TG3_RX_RCB_RING_SIZE(tp) \
  100. (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
  101. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
  102. #define TG3_TX_RING_SIZE 512
  103. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  104. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  105. TG3_RX_RING_SIZE)
  106. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
  107. TG3_RX_JUMBO_RING_SIZE)
  108. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  109. TG3_RX_RCB_RING_SIZE(tp))
  110. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  111. TG3_TX_RING_SIZE)
  112. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  113. #define TG3_DMA_BYTE_ENAB 64
  114. #define TG3_RX_STD_DMA_SZ 1536
  115. #define TG3_RX_JMB_DMA_SZ 9046
  116. #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
  117. #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
  118. #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
  119. #define TG3_RX_STD_BUFF_RING_SIZE \
  120. (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
  121. #define TG3_RX_JMB_BUFF_RING_SIZE \
  122. (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
  123. /* minimum number of free TX descriptors required to wake up TX process */
  124. #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
  125. #define TG3_RAW_IP_ALIGN 2
  126. /* number of ETHTOOL_GSTATS u64's */
  127. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  128. #define TG3_NUM_TEST 6
  129. #define FIRMWARE_TG3 "tigon/tg3.bin"
  130. #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
  131. #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
  132. static char version[] __devinitdata =
  133. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  134. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  135. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  136. MODULE_LICENSE("GPL");
  137. MODULE_VERSION(DRV_MODULE_VERSION);
  138. MODULE_FIRMWARE(FIRMWARE_TG3);
  139. MODULE_FIRMWARE(FIRMWARE_TG3TSO);
  140. MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
  141. #define TG3_RSS_MIN_NUM_MSIX_VECS 2
  142. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  143. module_param(tg3_debug, int, 0);
  144. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  145. static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
  146. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  158. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  159. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  160. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  161. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  162. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  163. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  164. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  165. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  166. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  167. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  184. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  185. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  186. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  187. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  188. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  189. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  190. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  191. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  192. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  193. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  194. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  195. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  196. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  197. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  198. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  199. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  200. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  201. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  202. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  203. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  204. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
  205. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
  206. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
  207. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
  208. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
  209. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
  210. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
  211. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
  212. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
  213. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
  214. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
  215. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
  216. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
  217. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
  218. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
  219. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
  220. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
  221. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  222. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  223. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  224. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  225. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  226. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  227. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  228. {}
  229. };
  230. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  231. static const struct {
  232. const char string[ETH_GSTRING_LEN];
  233. } ethtool_stats_keys[TG3_NUM_STATS] = {
  234. { "rx_octets" },
  235. { "rx_fragments" },
  236. { "rx_ucast_packets" },
  237. { "rx_mcast_packets" },
  238. { "rx_bcast_packets" },
  239. { "rx_fcs_errors" },
  240. { "rx_align_errors" },
  241. { "rx_xon_pause_rcvd" },
  242. { "rx_xoff_pause_rcvd" },
  243. { "rx_mac_ctrl_rcvd" },
  244. { "rx_xoff_entered" },
  245. { "rx_frame_too_long_errors" },
  246. { "rx_jabbers" },
  247. { "rx_undersize_packets" },
  248. { "rx_in_length_errors" },
  249. { "rx_out_length_errors" },
  250. { "rx_64_or_less_octet_packets" },
  251. { "rx_65_to_127_octet_packets" },
  252. { "rx_128_to_255_octet_packets" },
  253. { "rx_256_to_511_octet_packets" },
  254. { "rx_512_to_1023_octet_packets" },
  255. { "rx_1024_to_1522_octet_packets" },
  256. { "rx_1523_to_2047_octet_packets" },
  257. { "rx_2048_to_4095_octet_packets" },
  258. { "rx_4096_to_8191_octet_packets" },
  259. { "rx_8192_to_9022_octet_packets" },
  260. { "tx_octets" },
  261. { "tx_collisions" },
  262. { "tx_xon_sent" },
  263. { "tx_xoff_sent" },
  264. { "tx_flow_control" },
  265. { "tx_mac_errors" },
  266. { "tx_single_collisions" },
  267. { "tx_mult_collisions" },
  268. { "tx_deferred" },
  269. { "tx_excessive_collisions" },
  270. { "tx_late_collisions" },
  271. { "tx_collide_2times" },
  272. { "tx_collide_3times" },
  273. { "tx_collide_4times" },
  274. { "tx_collide_5times" },
  275. { "tx_collide_6times" },
  276. { "tx_collide_7times" },
  277. { "tx_collide_8times" },
  278. { "tx_collide_9times" },
  279. { "tx_collide_10times" },
  280. { "tx_collide_11times" },
  281. { "tx_collide_12times" },
  282. { "tx_collide_13times" },
  283. { "tx_collide_14times" },
  284. { "tx_collide_15times" },
  285. { "tx_ucast_packets" },
  286. { "tx_mcast_packets" },
  287. { "tx_bcast_packets" },
  288. { "tx_carrier_sense_errors" },
  289. { "tx_discards" },
  290. { "tx_errors" },
  291. { "dma_writeq_full" },
  292. { "dma_write_prioq_full" },
  293. { "rxbds_empty" },
  294. { "rx_discards" },
  295. { "rx_errors" },
  296. { "rx_threshold_hit" },
  297. { "dma_readq_full" },
  298. { "dma_read_prioq_full" },
  299. { "tx_comp_queue_full" },
  300. { "ring_set_send_prod_index" },
  301. { "ring_status_update" },
  302. { "nic_irqs" },
  303. { "nic_avoided_irqs" },
  304. { "nic_tx_threshold_hit" }
  305. };
  306. static const struct {
  307. const char string[ETH_GSTRING_LEN];
  308. } ethtool_test_keys[TG3_NUM_TEST] = {
  309. { "nvram test (online) " },
  310. { "link test (online) " },
  311. { "register test (offline)" },
  312. { "memory test (offline)" },
  313. { "loopback test (offline)" },
  314. { "interrupt test (offline)" },
  315. };
  316. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  317. {
  318. writel(val, tp->regs + off);
  319. }
  320. static u32 tg3_read32(struct tg3 *tp, u32 off)
  321. {
  322. return (readl(tp->regs + off));
  323. }
  324. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  325. {
  326. writel(val, tp->aperegs + off);
  327. }
  328. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  329. {
  330. return (readl(tp->aperegs + off));
  331. }
  332. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  333. {
  334. unsigned long flags;
  335. spin_lock_irqsave(&tp->indirect_lock, flags);
  336. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  337. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  338. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  339. }
  340. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  341. {
  342. writel(val, tp->regs + off);
  343. readl(tp->regs + off);
  344. }
  345. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  346. {
  347. unsigned long flags;
  348. u32 val;
  349. spin_lock_irqsave(&tp->indirect_lock, flags);
  350. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  351. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  352. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  353. return val;
  354. }
  355. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  356. {
  357. unsigned long flags;
  358. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  359. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  360. TG3_64BIT_REG_LOW, val);
  361. return;
  362. }
  363. if (off == TG3_RX_STD_PROD_IDX_REG) {
  364. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  365. TG3_64BIT_REG_LOW, val);
  366. return;
  367. }
  368. spin_lock_irqsave(&tp->indirect_lock, flags);
  369. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  370. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  371. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  372. /* In indirect mode when disabling interrupts, we also need
  373. * to clear the interrupt bit in the GRC local ctrl register.
  374. */
  375. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  376. (val == 0x1)) {
  377. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  378. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  379. }
  380. }
  381. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  382. {
  383. unsigned long flags;
  384. u32 val;
  385. spin_lock_irqsave(&tp->indirect_lock, flags);
  386. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  387. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  388. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  389. return val;
  390. }
  391. /* usec_wait specifies the wait time in usec when writing to certain registers
  392. * where it is unsafe to read back the register without some delay.
  393. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  394. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  395. */
  396. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  397. {
  398. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  399. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  400. /* Non-posted methods */
  401. tp->write32(tp, off, val);
  402. else {
  403. /* Posted method */
  404. tg3_write32(tp, off, val);
  405. if (usec_wait)
  406. udelay(usec_wait);
  407. tp->read32(tp, off);
  408. }
  409. /* Wait again after the read for the posted method to guarantee that
  410. * the wait time is met.
  411. */
  412. if (usec_wait)
  413. udelay(usec_wait);
  414. }
  415. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  416. {
  417. tp->write32_mbox(tp, off, val);
  418. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  419. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  420. tp->read32_mbox(tp, off);
  421. }
  422. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  423. {
  424. void __iomem *mbox = tp->regs + off;
  425. writel(val, mbox);
  426. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  427. writel(val, mbox);
  428. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  429. readl(mbox);
  430. }
  431. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  432. {
  433. return (readl(tp->regs + off + GRCMBOX_BASE));
  434. }
  435. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  436. {
  437. writel(val, tp->regs + off + GRCMBOX_BASE);
  438. }
  439. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  440. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  441. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  442. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  443. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  444. #define tw32(reg,val) tp->write32(tp, reg, val)
  445. #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
  446. #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
  447. #define tr32(reg) tp->read32(tp, reg)
  448. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  449. {
  450. unsigned long flags;
  451. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  452. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  453. return;
  454. spin_lock_irqsave(&tp->indirect_lock, flags);
  455. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  456. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  457. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  458. /* Always leave this as zero. */
  459. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  460. } else {
  461. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  462. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  463. /* Always leave this as zero. */
  464. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  465. }
  466. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  467. }
  468. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  469. {
  470. unsigned long flags;
  471. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  472. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  473. *val = 0;
  474. return;
  475. }
  476. spin_lock_irqsave(&tp->indirect_lock, flags);
  477. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  478. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  479. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  480. /* Always leave this as zero. */
  481. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  482. } else {
  483. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  484. *val = tr32(TG3PCI_MEM_WIN_DATA);
  485. /* Always leave this as zero. */
  486. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  487. }
  488. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  489. }
  490. static void tg3_ape_lock_init(struct tg3 *tp)
  491. {
  492. int i;
  493. /* Make sure the driver hasn't any stale locks. */
  494. for (i = 0; i < 8; i++)
  495. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
  496. APE_LOCK_GRANT_DRIVER);
  497. }
  498. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  499. {
  500. int i, off;
  501. int ret = 0;
  502. u32 status;
  503. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  504. return 0;
  505. switch (locknum) {
  506. case TG3_APE_LOCK_GRC:
  507. case TG3_APE_LOCK_MEM:
  508. break;
  509. default:
  510. return -EINVAL;
  511. }
  512. off = 4 * locknum;
  513. tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
  514. /* Wait for up to 1 millisecond to acquire lock. */
  515. for (i = 0; i < 100; i++) {
  516. status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
  517. if (status == APE_LOCK_GRANT_DRIVER)
  518. break;
  519. udelay(10);
  520. }
  521. if (status != APE_LOCK_GRANT_DRIVER) {
  522. /* Revoke the lock request. */
  523. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
  524. APE_LOCK_GRANT_DRIVER);
  525. ret = -EBUSY;
  526. }
  527. return ret;
  528. }
  529. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  530. {
  531. int off;
  532. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  533. return;
  534. switch (locknum) {
  535. case TG3_APE_LOCK_GRC:
  536. case TG3_APE_LOCK_MEM:
  537. break;
  538. default:
  539. return;
  540. }
  541. off = 4 * locknum;
  542. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
  543. }
  544. static void tg3_disable_ints(struct tg3 *tp)
  545. {
  546. int i;
  547. tw32(TG3PCI_MISC_HOST_CTRL,
  548. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  549. for (i = 0; i < tp->irq_max; i++)
  550. tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
  551. }
  552. static void tg3_enable_ints(struct tg3 *tp)
  553. {
  554. int i;
  555. tp->irq_sync = 0;
  556. wmb();
  557. tw32(TG3PCI_MISC_HOST_CTRL,
  558. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  559. tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
  560. for (i = 0; i < tp->irq_cnt; i++) {
  561. struct tg3_napi *tnapi = &tp->napi[i];
  562. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  563. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  564. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  565. tp->coal_now |= tnapi->coal_now;
  566. }
  567. /* Force an initial interrupt */
  568. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  569. (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
  570. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  571. else
  572. tw32(HOSTCC_MODE, tp->coal_now);
  573. tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
  574. }
  575. static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
  576. {
  577. struct tg3 *tp = tnapi->tp;
  578. struct tg3_hw_status *sblk = tnapi->hw_status;
  579. unsigned int work_exists = 0;
  580. /* check for phy events */
  581. if (!(tp->tg3_flags &
  582. (TG3_FLAG_USE_LINKCHG_REG |
  583. TG3_FLAG_POLL_SERDES))) {
  584. if (sblk->status & SD_STATUS_LINK_CHG)
  585. work_exists = 1;
  586. }
  587. /* check for RX/TX work to do */
  588. if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
  589. *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  590. work_exists = 1;
  591. return work_exists;
  592. }
  593. /* tg3_int_reenable
  594. * similar to tg3_enable_ints, but it accurately determines whether there
  595. * is new work pending and can return without flushing the PIO write
  596. * which reenables interrupts
  597. */
  598. static void tg3_int_reenable(struct tg3_napi *tnapi)
  599. {
  600. struct tg3 *tp = tnapi->tp;
  601. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  602. mmiowb();
  603. /* When doing tagged status, this work check is unnecessary.
  604. * The last_tag we write above tells the chip which piece of
  605. * work we've completed.
  606. */
  607. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  608. tg3_has_work(tnapi))
  609. tw32(HOSTCC_MODE, tp->coalesce_mode |
  610. HOSTCC_MODE_ENABLE | tnapi->coal_now);
  611. }
  612. static void tg3_napi_disable(struct tg3 *tp)
  613. {
  614. int i;
  615. for (i = tp->irq_cnt - 1; i >= 0; i--)
  616. napi_disable(&tp->napi[i].napi);
  617. }
  618. static void tg3_napi_enable(struct tg3 *tp)
  619. {
  620. int i;
  621. for (i = 0; i < tp->irq_cnt; i++)
  622. napi_enable(&tp->napi[i].napi);
  623. }
  624. static inline void tg3_netif_stop(struct tg3 *tp)
  625. {
  626. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  627. tg3_napi_disable(tp);
  628. netif_tx_disable(tp->dev);
  629. }
  630. static inline void tg3_netif_start(struct tg3 *tp)
  631. {
  632. /* NOTE: unconditional netif_tx_wake_all_queues is only
  633. * appropriate so long as all callers are assured to
  634. * have free tx slots (such as after tg3_init_hw)
  635. */
  636. netif_tx_wake_all_queues(tp->dev);
  637. tg3_napi_enable(tp);
  638. tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
  639. tg3_enable_ints(tp);
  640. }
  641. static void tg3_switch_clocks(struct tg3 *tp)
  642. {
  643. u32 clock_ctrl;
  644. u32 orig_clock_ctrl;
  645. if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  646. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  647. return;
  648. clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  649. orig_clock_ctrl = clock_ctrl;
  650. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  651. CLOCK_CTRL_CLKRUN_OENABLE |
  652. 0x1f);
  653. tp->pci_clock_ctrl = clock_ctrl;
  654. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  655. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  656. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  657. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  658. }
  659. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  660. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  661. clock_ctrl |
  662. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  663. 40);
  664. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  665. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  666. 40);
  667. }
  668. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  669. }
  670. #define PHY_BUSY_LOOPS 5000
  671. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  672. {
  673. u32 frame_val;
  674. unsigned int loops;
  675. int ret;
  676. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  677. tw32_f(MAC_MI_MODE,
  678. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  679. udelay(80);
  680. }
  681. *val = 0x0;
  682. frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  683. MI_COM_PHY_ADDR_MASK);
  684. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  685. MI_COM_REG_ADDR_MASK);
  686. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  687. tw32_f(MAC_MI_COM, frame_val);
  688. loops = PHY_BUSY_LOOPS;
  689. while (loops != 0) {
  690. udelay(10);
  691. frame_val = tr32(MAC_MI_COM);
  692. if ((frame_val & MI_COM_BUSY) == 0) {
  693. udelay(5);
  694. frame_val = tr32(MAC_MI_COM);
  695. break;
  696. }
  697. loops -= 1;
  698. }
  699. ret = -EBUSY;
  700. if (loops != 0) {
  701. *val = frame_val & MI_COM_DATA_MASK;
  702. ret = 0;
  703. }
  704. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  705. tw32_f(MAC_MI_MODE, tp->mi_mode);
  706. udelay(80);
  707. }
  708. return ret;
  709. }
  710. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  711. {
  712. u32 frame_val;
  713. unsigned int loops;
  714. int ret;
  715. if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
  716. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  717. return 0;
  718. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  719. tw32_f(MAC_MI_MODE,
  720. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  721. udelay(80);
  722. }
  723. frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  724. MI_COM_PHY_ADDR_MASK);
  725. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  726. MI_COM_REG_ADDR_MASK);
  727. frame_val |= (val & MI_COM_DATA_MASK);
  728. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  729. tw32_f(MAC_MI_COM, frame_val);
  730. loops = PHY_BUSY_LOOPS;
  731. while (loops != 0) {
  732. udelay(10);
  733. frame_val = tr32(MAC_MI_COM);
  734. if ((frame_val & MI_COM_BUSY) == 0) {
  735. udelay(5);
  736. frame_val = tr32(MAC_MI_COM);
  737. break;
  738. }
  739. loops -= 1;
  740. }
  741. ret = -EBUSY;
  742. if (loops != 0)
  743. ret = 0;
  744. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  745. tw32_f(MAC_MI_MODE, tp->mi_mode);
  746. udelay(80);
  747. }
  748. return ret;
  749. }
  750. static int tg3_bmcr_reset(struct tg3 *tp)
  751. {
  752. u32 phy_control;
  753. int limit, err;
  754. /* OK, reset it, and poll the BMCR_RESET bit until it
  755. * clears or we time out.
  756. */
  757. phy_control = BMCR_RESET;
  758. err = tg3_writephy(tp, MII_BMCR, phy_control);
  759. if (err != 0)
  760. return -EBUSY;
  761. limit = 5000;
  762. while (limit--) {
  763. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  764. if (err != 0)
  765. return -EBUSY;
  766. if ((phy_control & BMCR_RESET) == 0) {
  767. udelay(40);
  768. break;
  769. }
  770. udelay(10);
  771. }
  772. if (limit < 0)
  773. return -EBUSY;
  774. return 0;
  775. }
  776. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  777. {
  778. struct tg3 *tp = bp->priv;
  779. u32 val;
  780. spin_lock_bh(&tp->lock);
  781. if (tg3_readphy(tp, reg, &val))
  782. val = -EIO;
  783. spin_unlock_bh(&tp->lock);
  784. return val;
  785. }
  786. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  787. {
  788. struct tg3 *tp = bp->priv;
  789. u32 ret = 0;
  790. spin_lock_bh(&tp->lock);
  791. if (tg3_writephy(tp, reg, val))
  792. ret = -EIO;
  793. spin_unlock_bh(&tp->lock);
  794. return ret;
  795. }
  796. static int tg3_mdio_reset(struct mii_bus *bp)
  797. {
  798. return 0;
  799. }
  800. static void tg3_mdio_config_5785(struct tg3 *tp)
  801. {
  802. u32 val;
  803. struct phy_device *phydev;
  804. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  805. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  806. case TG3_PHY_ID_BCM50610:
  807. case TG3_PHY_ID_BCM50610M:
  808. val = MAC_PHYCFG2_50610_LED_MODES;
  809. break;
  810. case TG3_PHY_ID_BCMAC131:
  811. val = MAC_PHYCFG2_AC131_LED_MODES;
  812. break;
  813. case TG3_PHY_ID_RTL8211C:
  814. val = MAC_PHYCFG2_RTL8211C_LED_MODES;
  815. break;
  816. case TG3_PHY_ID_RTL8201E:
  817. val = MAC_PHYCFG2_RTL8201E_LED_MODES;
  818. break;
  819. default:
  820. return;
  821. }
  822. if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
  823. tw32(MAC_PHYCFG2, val);
  824. val = tr32(MAC_PHYCFG1);
  825. val &= ~(MAC_PHYCFG1_RGMII_INT |
  826. MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
  827. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
  828. tw32(MAC_PHYCFG1, val);
  829. return;
  830. }
  831. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
  832. val |= MAC_PHYCFG2_EMODE_MASK_MASK |
  833. MAC_PHYCFG2_FMODE_MASK_MASK |
  834. MAC_PHYCFG2_GMODE_MASK_MASK |
  835. MAC_PHYCFG2_ACT_MASK_MASK |
  836. MAC_PHYCFG2_QUAL_MASK_MASK |
  837. MAC_PHYCFG2_INBAND_ENABLE;
  838. tw32(MAC_PHYCFG2, val);
  839. val = tr32(MAC_PHYCFG1);
  840. val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
  841. MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
  842. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
  843. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  844. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  845. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  846. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  847. }
  848. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
  849. MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
  850. tw32(MAC_PHYCFG1, val);
  851. val = tr32(MAC_EXT_RGMII_MODE);
  852. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  853. MAC_RGMII_MODE_RX_QUALITY |
  854. MAC_RGMII_MODE_RX_ACTIVITY |
  855. MAC_RGMII_MODE_RX_ENG_DET |
  856. MAC_RGMII_MODE_TX_ENABLE |
  857. MAC_RGMII_MODE_TX_LOWPWR |
  858. MAC_RGMII_MODE_TX_RESET);
  859. if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
  860. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  861. val |= MAC_RGMII_MODE_RX_INT_B |
  862. MAC_RGMII_MODE_RX_QUALITY |
  863. MAC_RGMII_MODE_RX_ACTIVITY |
  864. MAC_RGMII_MODE_RX_ENG_DET;
  865. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  866. val |= MAC_RGMII_MODE_TX_ENABLE |
  867. MAC_RGMII_MODE_TX_LOWPWR |
  868. MAC_RGMII_MODE_TX_RESET;
  869. }
  870. tw32(MAC_EXT_RGMII_MODE, val);
  871. }
  872. static void tg3_mdio_start(struct tg3 *tp)
  873. {
  874. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  875. tw32_f(MAC_MI_MODE, tp->mi_mode);
  876. udelay(80);
  877. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  878. u32 funcnum, is_serdes;
  879. funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
  880. if (funcnum)
  881. tp->phy_addr = 2;
  882. else
  883. tp->phy_addr = 1;
  884. if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
  885. is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  886. else
  887. is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  888. TG3_CPMU_PHY_STRAP_IS_SERDES;
  889. if (is_serdes)
  890. tp->phy_addr += 7;
  891. } else
  892. tp->phy_addr = TG3_PHY_MII_ADDR;
  893. if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
  894. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  895. tg3_mdio_config_5785(tp);
  896. }
  897. static int tg3_mdio_init(struct tg3 *tp)
  898. {
  899. int i;
  900. u32 reg;
  901. struct phy_device *phydev;
  902. tg3_mdio_start(tp);
  903. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
  904. (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
  905. return 0;
  906. tp->mdio_bus = mdiobus_alloc();
  907. if (tp->mdio_bus == NULL)
  908. return -ENOMEM;
  909. tp->mdio_bus->name = "tg3 mdio bus";
  910. snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  911. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  912. tp->mdio_bus->priv = tp;
  913. tp->mdio_bus->parent = &tp->pdev->dev;
  914. tp->mdio_bus->read = &tg3_mdio_read;
  915. tp->mdio_bus->write = &tg3_mdio_write;
  916. tp->mdio_bus->reset = &tg3_mdio_reset;
  917. tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
  918. tp->mdio_bus->irq = &tp->mdio_irq[0];
  919. for (i = 0; i < PHY_MAX_ADDR; i++)
  920. tp->mdio_bus->irq[i] = PHY_POLL;
  921. /* The bus registration will look for all the PHYs on the mdio bus.
  922. * Unfortunately, it does not ensure the PHY is powered up before
  923. * accessing the PHY ID registers. A chip reset is the
  924. * quickest way to bring the device back to an operational state..
  925. */
  926. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  927. tg3_bmcr_reset(tp);
  928. i = mdiobus_register(tp->mdio_bus);
  929. if (i) {
  930. printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
  931. tp->dev->name, i);
  932. mdiobus_free(tp->mdio_bus);
  933. return i;
  934. }
  935. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  936. if (!phydev || !phydev->drv) {
  937. printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
  938. mdiobus_unregister(tp->mdio_bus);
  939. mdiobus_free(tp->mdio_bus);
  940. return -ENODEV;
  941. }
  942. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  943. case TG3_PHY_ID_BCM57780:
  944. phydev->interface = PHY_INTERFACE_MODE_GMII;
  945. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  946. break;
  947. case TG3_PHY_ID_BCM50610:
  948. case TG3_PHY_ID_BCM50610M:
  949. phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
  950. PHY_BRCM_RX_REFCLK_UNUSED |
  951. PHY_BRCM_DIS_TXCRXC_NOENRGY |
  952. PHY_BRCM_AUTO_PWRDWN_ENABLE;
  953. if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
  954. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  955. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
  956. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  957. if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
  958. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  959. /* fallthru */
  960. case TG3_PHY_ID_RTL8211C:
  961. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  962. break;
  963. case TG3_PHY_ID_RTL8201E:
  964. case TG3_PHY_ID_BCMAC131:
  965. phydev->interface = PHY_INTERFACE_MODE_MII;
  966. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  967. tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
  968. break;
  969. }
  970. tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
  971. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  972. tg3_mdio_config_5785(tp);
  973. return 0;
  974. }
  975. static void tg3_mdio_fini(struct tg3 *tp)
  976. {
  977. if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
  978. tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
  979. mdiobus_unregister(tp->mdio_bus);
  980. mdiobus_free(tp->mdio_bus);
  981. }
  982. }
  983. /* tp->lock is held. */
  984. static inline void tg3_generate_fw_event(struct tg3 *tp)
  985. {
  986. u32 val;
  987. val = tr32(GRC_RX_CPU_EVENT);
  988. val |= GRC_RX_CPU_DRIVER_EVENT;
  989. tw32_f(GRC_RX_CPU_EVENT, val);
  990. tp->last_event_jiffies = jiffies;
  991. }
  992. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  993. /* tp->lock is held. */
  994. static void tg3_wait_for_event_ack(struct tg3 *tp)
  995. {
  996. int i;
  997. unsigned int delay_cnt;
  998. long time_remain;
  999. /* If enough time has passed, no wait is necessary. */
  1000. time_remain = (long)(tp->last_event_jiffies + 1 +
  1001. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  1002. (long)jiffies;
  1003. if (time_remain < 0)
  1004. return;
  1005. /* Check if we can shorten the wait time. */
  1006. delay_cnt = jiffies_to_usecs(time_remain);
  1007. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  1008. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  1009. delay_cnt = (delay_cnt >> 3) + 1;
  1010. for (i = 0; i < delay_cnt; i++) {
  1011. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1012. break;
  1013. udelay(8);
  1014. }
  1015. }
  1016. /* tp->lock is held. */
  1017. static void tg3_ump_link_report(struct tg3 *tp)
  1018. {
  1019. u32 reg;
  1020. u32 val;
  1021. if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1022. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  1023. return;
  1024. tg3_wait_for_event_ack(tp);
  1025. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1026. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1027. val = 0;
  1028. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1029. val = reg << 16;
  1030. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1031. val |= (reg & 0xffff);
  1032. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
  1033. val = 0;
  1034. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1035. val = reg << 16;
  1036. if (!tg3_readphy(tp, MII_LPA, &reg))
  1037. val |= (reg & 0xffff);
  1038. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
  1039. val = 0;
  1040. if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
  1041. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1042. val = reg << 16;
  1043. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1044. val |= (reg & 0xffff);
  1045. }
  1046. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
  1047. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1048. val = reg << 16;
  1049. else
  1050. val = 0;
  1051. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
  1052. tg3_generate_fw_event(tp);
  1053. }
  1054. static void tg3_link_report(struct tg3 *tp)
  1055. {
  1056. if (!netif_carrier_ok(tp->dev)) {
  1057. if (netif_msg_link(tp))
  1058. printk(KERN_INFO PFX "%s: Link is down.\n",
  1059. tp->dev->name);
  1060. tg3_ump_link_report(tp);
  1061. } else if (netif_msg_link(tp)) {
  1062. printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
  1063. tp->dev->name,
  1064. (tp->link_config.active_speed == SPEED_1000 ?
  1065. 1000 :
  1066. (tp->link_config.active_speed == SPEED_100 ?
  1067. 100 : 10)),
  1068. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1069. "full" : "half"));
  1070. printk(KERN_INFO PFX
  1071. "%s: Flow control is %s for TX and %s for RX.\n",
  1072. tp->dev->name,
  1073. (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
  1074. "on" : "off",
  1075. (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
  1076. "on" : "off");
  1077. tg3_ump_link_report(tp);
  1078. }
  1079. }
  1080. static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
  1081. {
  1082. u16 miireg;
  1083. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1084. miireg = ADVERTISE_PAUSE_CAP;
  1085. else if (flow_ctrl & FLOW_CTRL_TX)
  1086. miireg = ADVERTISE_PAUSE_ASYM;
  1087. else if (flow_ctrl & FLOW_CTRL_RX)
  1088. miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1089. else
  1090. miireg = 0;
  1091. return miireg;
  1092. }
  1093. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1094. {
  1095. u16 miireg;
  1096. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1097. miireg = ADVERTISE_1000XPAUSE;
  1098. else if (flow_ctrl & FLOW_CTRL_TX)
  1099. miireg = ADVERTISE_1000XPSE_ASYM;
  1100. else if (flow_ctrl & FLOW_CTRL_RX)
  1101. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1102. else
  1103. miireg = 0;
  1104. return miireg;
  1105. }
  1106. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1107. {
  1108. u8 cap = 0;
  1109. if (lcladv & ADVERTISE_1000XPAUSE) {
  1110. if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1111. if (rmtadv & LPA_1000XPAUSE)
  1112. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1113. else if (rmtadv & LPA_1000XPAUSE_ASYM)
  1114. cap = FLOW_CTRL_RX;
  1115. } else {
  1116. if (rmtadv & LPA_1000XPAUSE)
  1117. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1118. }
  1119. } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1120. if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
  1121. cap = FLOW_CTRL_TX;
  1122. }
  1123. return cap;
  1124. }
  1125. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1126. {
  1127. u8 autoneg;
  1128. u8 flowctrl = 0;
  1129. u32 old_rx_mode = tp->rx_mode;
  1130. u32 old_tx_mode = tp->tx_mode;
  1131. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
  1132. autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
  1133. else
  1134. autoneg = tp->link_config.autoneg;
  1135. if (autoneg == AUTONEG_ENABLE &&
  1136. (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
  1137. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  1138. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1139. else
  1140. flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  1141. } else
  1142. flowctrl = tp->link_config.flowctrl;
  1143. tp->link_config.active_flowctrl = flowctrl;
  1144. if (flowctrl & FLOW_CTRL_RX)
  1145. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1146. else
  1147. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1148. if (old_rx_mode != tp->rx_mode)
  1149. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1150. if (flowctrl & FLOW_CTRL_TX)
  1151. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1152. else
  1153. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1154. if (old_tx_mode != tp->tx_mode)
  1155. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1156. }
  1157. static void tg3_adjust_link(struct net_device *dev)
  1158. {
  1159. u8 oldflowctrl, linkmesg = 0;
  1160. u32 mac_mode, lcl_adv, rmt_adv;
  1161. struct tg3 *tp = netdev_priv(dev);
  1162. struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1163. spin_lock_bh(&tp->lock);
  1164. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1165. MAC_MODE_HALF_DUPLEX);
  1166. oldflowctrl = tp->link_config.active_flowctrl;
  1167. if (phydev->link) {
  1168. lcl_adv = 0;
  1169. rmt_adv = 0;
  1170. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1171. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1172. else if (phydev->speed == SPEED_1000 ||
  1173. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
  1174. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1175. else
  1176. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1177. if (phydev->duplex == DUPLEX_HALF)
  1178. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1179. else {
  1180. lcl_adv = tg3_advert_flowctrl_1000T(
  1181. tp->link_config.flowctrl);
  1182. if (phydev->pause)
  1183. rmt_adv = LPA_PAUSE_CAP;
  1184. if (phydev->asym_pause)
  1185. rmt_adv |= LPA_PAUSE_ASYM;
  1186. }
  1187. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1188. } else
  1189. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1190. if (mac_mode != tp->mac_mode) {
  1191. tp->mac_mode = mac_mode;
  1192. tw32_f(MAC_MODE, tp->mac_mode);
  1193. udelay(40);
  1194. }
  1195. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  1196. if (phydev->speed == SPEED_10)
  1197. tw32(MAC_MI_STAT,
  1198. MAC_MI_STAT_10MBPS_MODE |
  1199. MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1200. else
  1201. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1202. }
  1203. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1204. tw32(MAC_TX_LENGTHS,
  1205. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1206. (6 << TX_LENGTHS_IPG_SHIFT) |
  1207. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1208. else
  1209. tw32(MAC_TX_LENGTHS,
  1210. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1211. (6 << TX_LENGTHS_IPG_SHIFT) |
  1212. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1213. if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
  1214. (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
  1215. phydev->speed != tp->link_config.active_speed ||
  1216. phydev->duplex != tp->link_config.active_duplex ||
  1217. oldflowctrl != tp->link_config.active_flowctrl)
  1218. linkmesg = 1;
  1219. tp->link_config.active_speed = phydev->speed;
  1220. tp->link_config.active_duplex = phydev->duplex;
  1221. spin_unlock_bh(&tp->lock);
  1222. if (linkmesg)
  1223. tg3_link_report(tp);
  1224. }
  1225. static int tg3_phy_init(struct tg3 *tp)
  1226. {
  1227. struct phy_device *phydev;
  1228. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
  1229. return 0;
  1230. /* Bring the PHY back to a known state. */
  1231. tg3_bmcr_reset(tp);
  1232. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1233. /* Attach the MAC to the PHY. */
  1234. phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
  1235. phydev->dev_flags, phydev->interface);
  1236. if (IS_ERR(phydev)) {
  1237. printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
  1238. return PTR_ERR(phydev);
  1239. }
  1240. /* Mask with MAC supported features. */
  1241. switch (phydev->interface) {
  1242. case PHY_INTERFACE_MODE_GMII:
  1243. case PHY_INTERFACE_MODE_RGMII:
  1244. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  1245. phydev->supported &= (PHY_GBIT_FEATURES |
  1246. SUPPORTED_Pause |
  1247. SUPPORTED_Asym_Pause);
  1248. break;
  1249. }
  1250. /* fallthru */
  1251. case PHY_INTERFACE_MODE_MII:
  1252. phydev->supported &= (PHY_BASIC_FEATURES |
  1253. SUPPORTED_Pause |
  1254. SUPPORTED_Asym_Pause);
  1255. break;
  1256. default:
  1257. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1258. return -EINVAL;
  1259. }
  1260. tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
  1261. phydev->advertising = phydev->supported;
  1262. return 0;
  1263. }
  1264. static void tg3_phy_start(struct tg3 *tp)
  1265. {
  1266. struct phy_device *phydev;
  1267. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  1268. return;
  1269. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1270. if (tp->link_config.phy_is_low_power) {
  1271. tp->link_config.phy_is_low_power = 0;
  1272. phydev->speed = tp->link_config.orig_speed;
  1273. phydev->duplex = tp->link_config.orig_duplex;
  1274. phydev->autoneg = tp->link_config.orig_autoneg;
  1275. phydev->advertising = tp->link_config.orig_advertising;
  1276. }
  1277. phy_start(phydev);
  1278. phy_start_aneg(phydev);
  1279. }
  1280. static void tg3_phy_stop(struct tg3 *tp)
  1281. {
  1282. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  1283. return;
  1284. phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1285. }
  1286. static void tg3_phy_fini(struct tg3 *tp)
  1287. {
  1288. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
  1289. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1290. tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
  1291. }
  1292. }
  1293. static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  1294. {
  1295. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1296. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  1297. }
  1298. static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
  1299. {
  1300. u32 phytest;
  1301. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1302. u32 phy;
  1303. tg3_writephy(tp, MII_TG3_FET_TEST,
  1304. phytest | MII_TG3_FET_SHADOW_EN);
  1305. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
  1306. if (enable)
  1307. phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1308. else
  1309. phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1310. tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
  1311. }
  1312. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1313. }
  1314. }
  1315. static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
  1316. {
  1317. u32 reg;
  1318. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  1319. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
  1320. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1321. return;
  1322. if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
  1323. tg3_phy_fet_toggle_apd(tp, enable);
  1324. return;
  1325. }
  1326. reg = MII_TG3_MISC_SHDW_WREN |
  1327. MII_TG3_MISC_SHDW_SCR5_SEL |
  1328. MII_TG3_MISC_SHDW_SCR5_LPED |
  1329. MII_TG3_MISC_SHDW_SCR5_DLPTLM |
  1330. MII_TG3_MISC_SHDW_SCR5_SDTL |
  1331. MII_TG3_MISC_SHDW_SCR5_C125OE;
  1332. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
  1333. reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
  1334. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1335. reg = MII_TG3_MISC_SHDW_WREN |
  1336. MII_TG3_MISC_SHDW_APD_SEL |
  1337. MII_TG3_MISC_SHDW_APD_WKTM_84MS;
  1338. if (enable)
  1339. reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
  1340. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1341. }
  1342. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  1343. {
  1344. u32 phy;
  1345. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  1346. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  1347. return;
  1348. if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
  1349. u32 ephy;
  1350. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
  1351. u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
  1352. tg3_writephy(tp, MII_TG3_FET_TEST,
  1353. ephy | MII_TG3_FET_SHADOW_EN);
  1354. if (!tg3_readphy(tp, reg, &phy)) {
  1355. if (enable)
  1356. phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1357. else
  1358. phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1359. tg3_writephy(tp, reg, phy);
  1360. }
  1361. tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
  1362. }
  1363. } else {
  1364. phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
  1365. MII_TG3_AUXCTL_SHDWSEL_MISC;
  1366. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
  1367. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
  1368. if (enable)
  1369. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1370. else
  1371. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1372. phy |= MII_TG3_AUXCTL_MISC_WREN;
  1373. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1374. }
  1375. }
  1376. }
  1377. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1378. {
  1379. u32 val;
  1380. if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
  1381. return;
  1382. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  1383. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  1384. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1385. (val | (1 << 15) | (1 << 4)));
  1386. }
  1387. static void tg3_phy_apply_otp(struct tg3 *tp)
  1388. {
  1389. u32 otp, phy;
  1390. if (!tp->phy_otp)
  1391. return;
  1392. otp = tp->phy_otp;
  1393. /* Enable SM_DSP clock and tx 6dB coding. */
  1394. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  1395. MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
  1396. MII_TG3_AUXCTL_ACTL_TX_6DB;
  1397. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1398. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1399. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1400. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1401. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1402. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1403. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1404. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1405. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1406. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1407. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1408. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1409. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1410. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1411. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1412. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1413. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1414. /* Turn off SM_DSP clock. */
  1415. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  1416. MII_TG3_AUXCTL_ACTL_TX_6DB;
  1417. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  1418. }
  1419. static int tg3_wait_macro_done(struct tg3 *tp)
  1420. {
  1421. int limit = 100;
  1422. while (limit--) {
  1423. u32 tmp32;
  1424. if (!tg3_readphy(tp, 0x16, &tmp32)) {
  1425. if ((tmp32 & 0x1000) == 0)
  1426. break;
  1427. }
  1428. }
  1429. if (limit < 0)
  1430. return -EBUSY;
  1431. return 0;
  1432. }
  1433. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  1434. {
  1435. static const u32 test_pat[4][6] = {
  1436. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  1437. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  1438. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  1439. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  1440. };
  1441. int chan;
  1442. for (chan = 0; chan < 4; chan++) {
  1443. int i;
  1444. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1445. (chan * 0x2000) | 0x0200);
  1446. tg3_writephy(tp, 0x16, 0x0002);
  1447. for (i = 0; i < 6; i++)
  1448. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  1449. test_pat[chan][i]);
  1450. tg3_writephy(tp, 0x16, 0x0202);
  1451. if (tg3_wait_macro_done(tp)) {
  1452. *resetp = 1;
  1453. return -EBUSY;
  1454. }
  1455. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1456. (chan * 0x2000) | 0x0200);
  1457. tg3_writephy(tp, 0x16, 0x0082);
  1458. if (tg3_wait_macro_done(tp)) {
  1459. *resetp = 1;
  1460. return -EBUSY;
  1461. }
  1462. tg3_writephy(tp, 0x16, 0x0802);
  1463. if (tg3_wait_macro_done(tp)) {
  1464. *resetp = 1;
  1465. return -EBUSY;
  1466. }
  1467. for (i = 0; i < 6; i += 2) {
  1468. u32 low, high;
  1469. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  1470. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  1471. tg3_wait_macro_done(tp)) {
  1472. *resetp = 1;
  1473. return -EBUSY;
  1474. }
  1475. low &= 0x7fff;
  1476. high &= 0x000f;
  1477. if (low != test_pat[chan][i] ||
  1478. high != test_pat[chan][i+1]) {
  1479. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  1480. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  1481. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  1482. return -EBUSY;
  1483. }
  1484. }
  1485. }
  1486. return 0;
  1487. }
  1488. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  1489. {
  1490. int chan;
  1491. for (chan = 0; chan < 4; chan++) {
  1492. int i;
  1493. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1494. (chan * 0x2000) | 0x0200);
  1495. tg3_writephy(tp, 0x16, 0x0002);
  1496. for (i = 0; i < 6; i++)
  1497. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  1498. tg3_writephy(tp, 0x16, 0x0202);
  1499. if (tg3_wait_macro_done(tp))
  1500. return -EBUSY;
  1501. }
  1502. return 0;
  1503. }
  1504. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  1505. {
  1506. u32 reg32, phy9_orig;
  1507. int retries, do_phy_reset, err;
  1508. retries = 10;
  1509. do_phy_reset = 1;
  1510. do {
  1511. if (do_phy_reset) {
  1512. err = tg3_bmcr_reset(tp);
  1513. if (err)
  1514. return err;
  1515. do_phy_reset = 0;
  1516. }
  1517. /* Disable transmitter and interrupt. */
  1518. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  1519. continue;
  1520. reg32 |= 0x3000;
  1521. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1522. /* Set full-duplex, 1000 mbps. */
  1523. tg3_writephy(tp, MII_BMCR,
  1524. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  1525. /* Set to master mode. */
  1526. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  1527. continue;
  1528. tg3_writephy(tp, MII_TG3_CTRL,
  1529. (MII_TG3_CTRL_AS_MASTER |
  1530. MII_TG3_CTRL_ENABLE_AS_MASTER));
  1531. /* Enable SM_DSP_CLOCK and 6dB. */
  1532. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1533. /* Block the PHY control access. */
  1534. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  1535. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
  1536. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  1537. if (!err)
  1538. break;
  1539. } while (--retries);
  1540. err = tg3_phy_reset_chanpat(tp);
  1541. if (err)
  1542. return err;
  1543. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  1544. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
  1545. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  1546. tg3_writephy(tp, 0x16, 0x0000);
  1547. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1548. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1549. /* Set Extended packet length bit for jumbo frames */
  1550. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  1551. }
  1552. else {
  1553. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1554. }
  1555. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  1556. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  1557. reg32 &= ~0x3000;
  1558. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  1559. } else if (!err)
  1560. err = -EBUSY;
  1561. return err;
  1562. }
  1563. /* This will reset the tigon3 PHY if there is no valid
  1564. * link unless the FORCE argument is non-zero.
  1565. */
  1566. static int tg3_phy_reset(struct tg3 *tp)
  1567. {
  1568. u32 cpmuctrl;
  1569. u32 phy_status;
  1570. int err;
  1571. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1572. u32 val;
  1573. val = tr32(GRC_MISC_CFG);
  1574. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  1575. udelay(40);
  1576. }
  1577. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  1578. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  1579. if (err != 0)
  1580. return -EBUSY;
  1581. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  1582. netif_carrier_off(tp->dev);
  1583. tg3_link_report(tp);
  1584. }
  1585. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1586. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1587. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  1588. err = tg3_phy_reset_5703_4_5(tp);
  1589. if (err)
  1590. return err;
  1591. goto out;
  1592. }
  1593. cpmuctrl = 0;
  1594. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  1595. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  1596. cpmuctrl = tr32(TG3_CPMU_CTRL);
  1597. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  1598. tw32(TG3_CPMU_CTRL,
  1599. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  1600. }
  1601. err = tg3_bmcr_reset(tp);
  1602. if (err)
  1603. return err;
  1604. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  1605. u32 phy;
  1606. phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  1607. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
  1608. tw32(TG3_CPMU_CTRL, cpmuctrl);
  1609. }
  1610. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
  1611. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
  1612. u32 val;
  1613. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1614. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  1615. CPMU_LSPD_1000MB_MACCLK_12_5) {
  1616. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1617. udelay(40);
  1618. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1619. }
  1620. }
  1621. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
  1622. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
  1623. return 0;
  1624. tg3_phy_apply_otp(tp);
  1625. if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
  1626. tg3_phy_toggle_apd(tp, true);
  1627. else
  1628. tg3_phy_toggle_apd(tp, false);
  1629. out:
  1630. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
  1631. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1632. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1633. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  1634. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1635. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
  1636. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1637. }
  1638. if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
  1639. tg3_writephy(tp, 0x1c, 0x8d68);
  1640. tg3_writephy(tp, 0x1c, 0x8d68);
  1641. }
  1642. if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
  1643. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1644. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1645. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
  1646. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1647. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
  1648. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
  1649. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
  1650. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1651. }
  1652. else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
  1653. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1654. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1655. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
  1656. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  1657. tg3_writephy(tp, MII_TG3_TEST1,
  1658. MII_TG3_TEST1_TRIM_EN | 0x4);
  1659. } else
  1660. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  1661. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1662. }
  1663. /* Set Extended packet length bit (bit 14) on all chips that */
  1664. /* support jumbo frames */
  1665. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1666. /* Cannot do read-modify-write on 5401 */
  1667. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1668. } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  1669. u32 phy_reg;
  1670. /* Set bit 14 with read-modify-write to preserve other bits */
  1671. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  1672. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  1673. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  1674. }
  1675. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  1676. * jumbo frames transmission.
  1677. */
  1678. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  1679. u32 phy_reg;
  1680. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  1681. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1682. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  1683. }
  1684. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1685. /* adjust output voltage */
  1686. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
  1687. }
  1688. tg3_phy_toggle_automdix(tp, 1);
  1689. tg3_phy_set_wirespeed(tp);
  1690. return 0;
  1691. }
  1692. static void tg3_frob_aux_power(struct tg3 *tp)
  1693. {
  1694. struct tg3 *tp_peer = tp;
  1695. /* The GPIOs do something completely different on 57765. */
  1696. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
  1697. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  1698. return;
  1699. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1700. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
  1701. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  1702. struct net_device *dev_peer;
  1703. dev_peer = pci_get_drvdata(tp->pdev_peer);
  1704. /* remove_one() may have been run on the peer. */
  1705. if (!dev_peer)
  1706. tp_peer = tp;
  1707. else
  1708. tp_peer = netdev_priv(dev_peer);
  1709. }
  1710. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1711. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  1712. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1713. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  1714. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1715. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1716. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1717. (GRC_LCLCTRL_GPIO_OE0 |
  1718. GRC_LCLCTRL_GPIO_OE1 |
  1719. GRC_LCLCTRL_GPIO_OE2 |
  1720. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1721. GRC_LCLCTRL_GPIO_OUTPUT1),
  1722. 100);
  1723. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  1724. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  1725. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  1726. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  1727. GRC_LCLCTRL_GPIO_OE1 |
  1728. GRC_LCLCTRL_GPIO_OE2 |
  1729. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1730. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1731. tp->grc_local_ctrl;
  1732. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1733. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  1734. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1735. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  1736. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
  1737. } else {
  1738. u32 no_gpio2;
  1739. u32 grc_local_ctrl = 0;
  1740. if (tp_peer != tp &&
  1741. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1742. return;
  1743. /* Workaround to prevent overdrawing Amps. */
  1744. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1745. ASIC_REV_5714) {
  1746. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  1747. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1748. grc_local_ctrl, 100);
  1749. }
  1750. /* On 5753 and variants, GPIO2 cannot be used. */
  1751. no_gpio2 = tp->nic_sram_data_cfg &
  1752. NIC_SRAM_DATA_CFG_NO_GPIO2;
  1753. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  1754. GRC_LCLCTRL_GPIO_OE1 |
  1755. GRC_LCLCTRL_GPIO_OE2 |
  1756. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1757. GRC_LCLCTRL_GPIO_OUTPUT2;
  1758. if (no_gpio2) {
  1759. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  1760. GRC_LCLCTRL_GPIO_OUTPUT2);
  1761. }
  1762. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1763. grc_local_ctrl, 100);
  1764. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  1765. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1766. grc_local_ctrl, 100);
  1767. if (!no_gpio2) {
  1768. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  1769. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1770. grc_local_ctrl, 100);
  1771. }
  1772. }
  1773. } else {
  1774. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  1775. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  1776. if (tp_peer != tp &&
  1777. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1778. return;
  1779. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1780. (GRC_LCLCTRL_GPIO_OE1 |
  1781. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1782. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1783. GRC_LCLCTRL_GPIO_OE1, 100);
  1784. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1785. (GRC_LCLCTRL_GPIO_OE1 |
  1786. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1787. }
  1788. }
  1789. }
  1790. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  1791. {
  1792. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  1793. return 1;
  1794. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
  1795. if (speed != SPEED_10)
  1796. return 1;
  1797. } else if (speed == SPEED_10)
  1798. return 1;
  1799. return 0;
  1800. }
  1801. static int tg3_setup_phy(struct tg3 *, int);
  1802. #define RESET_KIND_SHUTDOWN 0
  1803. #define RESET_KIND_INIT 1
  1804. #define RESET_KIND_SUSPEND 2
  1805. static void tg3_write_sig_post_reset(struct tg3 *, int);
  1806. static int tg3_halt_cpu(struct tg3 *, u32);
  1807. static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
  1808. {
  1809. u32 val;
  1810. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  1811. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1812. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1813. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1814. sg_dig_ctrl |=
  1815. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1816. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1817. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1818. }
  1819. return;
  1820. }
  1821. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1822. tg3_bmcr_reset(tp);
  1823. val = tr32(GRC_MISC_CFG);
  1824. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1825. udelay(40);
  1826. return;
  1827. } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
  1828. u32 phytest;
  1829. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1830. u32 phy;
  1831. tg3_writephy(tp, MII_ADVERTISE, 0);
  1832. tg3_writephy(tp, MII_BMCR,
  1833. BMCR_ANENABLE | BMCR_ANRESTART);
  1834. tg3_writephy(tp, MII_TG3_FET_TEST,
  1835. phytest | MII_TG3_FET_SHADOW_EN);
  1836. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
  1837. phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
  1838. tg3_writephy(tp,
  1839. MII_TG3_FET_SHDW_AUXMODE4,
  1840. phy);
  1841. }
  1842. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1843. }
  1844. return;
  1845. } else if (do_low_power) {
  1846. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1847. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1848. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1849. MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
  1850. MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  1851. MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
  1852. MII_TG3_AUXCTL_PCTL_VREG_11V);
  1853. }
  1854. /* The PHY should not be powered down on some chips because
  1855. * of bugs.
  1856. */
  1857. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1858. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1859. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1860. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1861. return;
  1862. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
  1863. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
  1864. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1865. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1866. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  1867. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1868. }
  1869. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1870. }
  1871. /* tp->lock is held. */
  1872. static int tg3_nvram_lock(struct tg3 *tp)
  1873. {
  1874. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  1875. int i;
  1876. if (tp->nvram_lock_cnt == 0) {
  1877. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  1878. for (i = 0; i < 8000; i++) {
  1879. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  1880. break;
  1881. udelay(20);
  1882. }
  1883. if (i == 8000) {
  1884. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  1885. return -ENODEV;
  1886. }
  1887. }
  1888. tp->nvram_lock_cnt++;
  1889. }
  1890. return 0;
  1891. }
  1892. /* tp->lock is held. */
  1893. static void tg3_nvram_unlock(struct tg3 *tp)
  1894. {
  1895. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  1896. if (tp->nvram_lock_cnt > 0)
  1897. tp->nvram_lock_cnt--;
  1898. if (tp->nvram_lock_cnt == 0)
  1899. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  1900. }
  1901. }
  1902. /* tp->lock is held. */
  1903. static void tg3_enable_nvram_access(struct tg3 *tp)
  1904. {
  1905. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1906. !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
  1907. u32 nvaccess = tr32(NVRAM_ACCESS);
  1908. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  1909. }
  1910. }
  1911. /* tp->lock is held. */
  1912. static void tg3_disable_nvram_access(struct tg3 *tp)
  1913. {
  1914. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1915. !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
  1916. u32 nvaccess = tr32(NVRAM_ACCESS);
  1917. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  1918. }
  1919. }
  1920. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  1921. u32 offset, u32 *val)
  1922. {
  1923. u32 tmp;
  1924. int i;
  1925. if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
  1926. return -EINVAL;
  1927. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  1928. EEPROM_ADDR_DEVID_MASK |
  1929. EEPROM_ADDR_READ);
  1930. tw32(GRC_EEPROM_ADDR,
  1931. tmp |
  1932. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  1933. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  1934. EEPROM_ADDR_ADDR_MASK) |
  1935. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  1936. for (i = 0; i < 1000; i++) {
  1937. tmp = tr32(GRC_EEPROM_ADDR);
  1938. if (tmp & EEPROM_ADDR_COMPLETE)
  1939. break;
  1940. msleep(1);
  1941. }
  1942. if (!(tmp & EEPROM_ADDR_COMPLETE))
  1943. return -EBUSY;
  1944. tmp = tr32(GRC_EEPROM_DATA);
  1945. /*
  1946. * The data will always be opposite the native endian
  1947. * format. Perform a blind byteswap to compensate.
  1948. */
  1949. *val = swab32(tmp);
  1950. return 0;
  1951. }
  1952. #define NVRAM_CMD_TIMEOUT 10000
  1953. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  1954. {
  1955. int i;
  1956. tw32(NVRAM_CMD, nvram_cmd);
  1957. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  1958. udelay(10);
  1959. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  1960. udelay(10);
  1961. break;
  1962. }
  1963. }
  1964. if (i == NVRAM_CMD_TIMEOUT)
  1965. return -EBUSY;
  1966. return 0;
  1967. }
  1968. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  1969. {
  1970. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  1971. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  1972. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  1973. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  1974. (tp->nvram_jedecnum == JEDEC_ATMEL))
  1975. addr = ((addr / tp->nvram_pagesize) <<
  1976. ATMEL_AT45DB0X1B_PAGE_POS) +
  1977. (addr % tp->nvram_pagesize);
  1978. return addr;
  1979. }
  1980. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  1981. {
  1982. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  1983. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  1984. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  1985. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  1986. (tp->nvram_jedecnum == JEDEC_ATMEL))
  1987. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  1988. tp->nvram_pagesize) +
  1989. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  1990. return addr;
  1991. }
  1992. /* NOTE: Data read in from NVRAM is byteswapped according to
  1993. * the byteswapping settings for all other register accesses.
  1994. * tg3 devices are BE devices, so on a BE machine, the data
  1995. * returned will be exactly as it is seen in NVRAM. On a LE
  1996. * machine, the 32-bit value will be byteswapped.
  1997. */
  1998. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  1999. {
  2000. int ret;
  2001. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  2002. return tg3_nvram_read_using_eeprom(tp, offset, val);
  2003. offset = tg3_nvram_phys_addr(tp, offset);
  2004. if (offset > NVRAM_ADDR_MSK)
  2005. return -EINVAL;
  2006. ret = tg3_nvram_lock(tp);
  2007. if (ret)
  2008. return ret;
  2009. tg3_enable_nvram_access(tp);
  2010. tw32(NVRAM_ADDR, offset);
  2011. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  2012. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2013. if (ret == 0)
  2014. *val = tr32(NVRAM_RDDATA);
  2015. tg3_disable_nvram_access(tp);
  2016. tg3_nvram_unlock(tp);
  2017. return ret;
  2018. }
  2019. /* Ensures NVRAM data is in bytestream format. */
  2020. static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
  2021. {
  2022. u32 v;
  2023. int res = tg3_nvram_read(tp, offset, &v);
  2024. if (!res)
  2025. *val = cpu_to_be32(v);
  2026. return res;
  2027. }
  2028. /* tp->lock is held. */
  2029. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  2030. {
  2031. u32 addr_high, addr_low;
  2032. int i;
  2033. addr_high = ((tp->dev->dev_addr[0] << 8) |
  2034. tp->dev->dev_addr[1]);
  2035. addr_low = ((tp->dev->dev_addr[2] << 24) |
  2036. (tp->dev->dev_addr[3] << 16) |
  2037. (tp->dev->dev_addr[4] << 8) |
  2038. (tp->dev->dev_addr[5] << 0));
  2039. for (i = 0; i < 4; i++) {
  2040. if (i == 1 && skip_mac_1)
  2041. continue;
  2042. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  2043. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  2044. }
  2045. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  2046. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  2047. for (i = 0; i < 12; i++) {
  2048. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  2049. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  2050. }
  2051. }
  2052. addr_high = (tp->dev->dev_addr[0] +
  2053. tp->dev->dev_addr[1] +
  2054. tp->dev->dev_addr[2] +
  2055. tp->dev->dev_addr[3] +
  2056. tp->dev->dev_addr[4] +
  2057. tp->dev->dev_addr[5]) &
  2058. TX_BACKOFF_SEED_MASK;
  2059. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  2060. }
  2061. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  2062. {
  2063. u32 misc_host_ctrl;
  2064. bool device_should_wake, do_low_power;
  2065. /* Make sure register accesses (indirect or otherwise)
  2066. * will function correctly.
  2067. */
  2068. pci_write_config_dword(tp->pdev,
  2069. TG3PCI_MISC_HOST_CTRL,
  2070. tp->misc_host_ctrl);
  2071. switch (state) {
  2072. case PCI_D0:
  2073. pci_enable_wake(tp->pdev, state, false);
  2074. pci_set_power_state(tp->pdev, PCI_D0);
  2075. /* Switch out of Vaux if it is a NIC */
  2076. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  2077. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  2078. return 0;
  2079. case PCI_D1:
  2080. case PCI_D2:
  2081. case PCI_D3hot:
  2082. break;
  2083. default:
  2084. printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
  2085. tp->dev->name, state);
  2086. return -EINVAL;
  2087. }
  2088. /* Restore the CLKREQ setting. */
  2089. if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
  2090. u16 lnkctl;
  2091. pci_read_config_word(tp->pdev,
  2092. tp->pcie_cap + PCI_EXP_LNKCTL,
  2093. &lnkctl);
  2094. lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
  2095. pci_write_config_word(tp->pdev,
  2096. tp->pcie_cap + PCI_EXP_LNKCTL,
  2097. lnkctl);
  2098. }
  2099. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  2100. tw32(TG3PCI_MISC_HOST_CTRL,
  2101. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  2102. device_should_wake = pci_pme_capable(tp->pdev, state) &&
  2103. device_may_wakeup(&tp->pdev->dev) &&
  2104. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
  2105. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  2106. do_low_power = false;
  2107. if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
  2108. !tp->link_config.phy_is_low_power) {
  2109. struct phy_device *phydev;
  2110. u32 phyid, advertising;
  2111. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  2112. tp->link_config.phy_is_low_power = 1;
  2113. tp->link_config.orig_speed = phydev->speed;
  2114. tp->link_config.orig_duplex = phydev->duplex;
  2115. tp->link_config.orig_autoneg = phydev->autoneg;
  2116. tp->link_config.orig_advertising = phydev->advertising;
  2117. advertising = ADVERTISED_TP |
  2118. ADVERTISED_Pause |
  2119. ADVERTISED_Autoneg |
  2120. ADVERTISED_10baseT_Half;
  2121. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  2122. device_should_wake) {
  2123. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  2124. advertising |=
  2125. ADVERTISED_100baseT_Half |
  2126. ADVERTISED_100baseT_Full |
  2127. ADVERTISED_10baseT_Full;
  2128. else
  2129. advertising |= ADVERTISED_10baseT_Full;
  2130. }
  2131. phydev->advertising = advertising;
  2132. phy_start_aneg(phydev);
  2133. phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
  2134. if (phyid != TG3_PHY_ID_BCMAC131) {
  2135. phyid &= TG3_PHY_OUI_MASK;
  2136. if (phyid == TG3_PHY_OUI_1 ||
  2137. phyid == TG3_PHY_OUI_2 ||
  2138. phyid == TG3_PHY_OUI_3)
  2139. do_low_power = true;
  2140. }
  2141. }
  2142. } else {
  2143. do_low_power = true;
  2144. if (tp->link_config.phy_is_low_power == 0) {
  2145. tp->link_config.phy_is_low_power = 1;
  2146. tp->link_config.orig_speed = tp->link_config.speed;
  2147. tp->link_config.orig_duplex = tp->link_config.duplex;
  2148. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  2149. }
  2150. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  2151. tp->link_config.speed = SPEED_10;
  2152. tp->link_config.duplex = DUPLEX_HALF;
  2153. tp->link_config.autoneg = AUTONEG_ENABLE;
  2154. tg3_setup_phy(tp, 0);
  2155. }
  2156. }
  2157. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  2158. u32 val;
  2159. val = tr32(GRC_VCPU_EXT_CTRL);
  2160. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  2161. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  2162. int i;
  2163. u32 val;
  2164. for (i = 0; i < 200; i++) {
  2165. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  2166. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  2167. break;
  2168. msleep(1);
  2169. }
  2170. }
  2171. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  2172. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  2173. WOL_DRV_STATE_SHUTDOWN |
  2174. WOL_DRV_WOL |
  2175. WOL_SET_MAGIC_PKT);
  2176. if (device_should_wake) {
  2177. u32 mac_mode;
  2178. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  2179. if (do_low_power) {
  2180. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  2181. udelay(40);
  2182. }
  2183. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  2184. mac_mode = MAC_MODE_PORT_MODE_GMII;
  2185. else
  2186. mac_mode = MAC_MODE_PORT_MODE_MII;
  2187. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  2188. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2189. ASIC_REV_5700) {
  2190. u32 speed = (tp->tg3_flags &
  2191. TG3_FLAG_WOL_SPEED_100MB) ?
  2192. SPEED_100 : SPEED_10;
  2193. if (tg3_5700_link_polarity(tp, speed))
  2194. mac_mode |= MAC_MODE_LINK_POLARITY;
  2195. else
  2196. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2197. }
  2198. } else {
  2199. mac_mode = MAC_MODE_PORT_MODE_TBI;
  2200. }
  2201. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  2202. tw32(MAC_LED_CTRL, tp->led_ctrl);
  2203. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  2204. if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  2205. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
  2206. ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  2207. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
  2208. mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
  2209. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  2210. mac_mode |= tp->mac_mode &
  2211. (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
  2212. if (mac_mode & MAC_MODE_APE_TX_EN)
  2213. mac_mode |= MAC_MODE_TDE_ENABLE;
  2214. }
  2215. tw32_f(MAC_MODE, mac_mode);
  2216. udelay(100);
  2217. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  2218. udelay(10);
  2219. }
  2220. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  2221. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2222. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  2223. u32 base_val;
  2224. base_val = tp->pci_clock_ctrl;
  2225. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  2226. CLOCK_CTRL_TXCLK_DISABLE);
  2227. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  2228. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  2229. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  2230. (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  2231. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  2232. /* do nothing */
  2233. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  2234. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  2235. u32 newbits1, newbits2;
  2236. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2237. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2238. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  2239. CLOCK_CTRL_TXCLK_DISABLE |
  2240. CLOCK_CTRL_ALTCLK);
  2241. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  2242. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  2243. newbits1 = CLOCK_CTRL_625_CORE;
  2244. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  2245. } else {
  2246. newbits1 = CLOCK_CTRL_ALTCLK;
  2247. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  2248. }
  2249. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  2250. 40);
  2251. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  2252. 40);
  2253. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  2254. u32 newbits3;
  2255. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2256. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2257. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  2258. CLOCK_CTRL_TXCLK_DISABLE |
  2259. CLOCK_CTRL_44MHZ_CORE);
  2260. } else {
  2261. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  2262. }
  2263. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  2264. tp->pci_clock_ctrl | newbits3, 40);
  2265. }
  2266. }
  2267. if (!(device_should_wake) &&
  2268. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  2269. tg3_power_down_phy(tp, do_low_power);
  2270. tg3_frob_aux_power(tp);
  2271. /* Workaround for unstable PLL clock */
  2272. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  2273. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  2274. u32 val = tr32(0x7d00);
  2275. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  2276. tw32(0x7d00, val);
  2277. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  2278. int err;
  2279. err = tg3_nvram_lock(tp);
  2280. tg3_halt_cpu(tp, RX_CPU_BASE);
  2281. if (!err)
  2282. tg3_nvram_unlock(tp);
  2283. }
  2284. }
  2285. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  2286. if (device_should_wake)
  2287. pci_enable_wake(tp->pdev, state, true);
  2288. /* Finally, set the new power state. */
  2289. pci_set_power_state(tp->pdev, state);
  2290. return 0;
  2291. }
  2292. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  2293. {
  2294. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  2295. case MII_TG3_AUX_STAT_10HALF:
  2296. *speed = SPEED_10;
  2297. *duplex = DUPLEX_HALF;
  2298. break;
  2299. case MII_TG3_AUX_STAT_10FULL:
  2300. *speed = SPEED_10;
  2301. *duplex = DUPLEX_FULL;
  2302. break;
  2303. case MII_TG3_AUX_STAT_100HALF:
  2304. *speed = SPEED_100;
  2305. *duplex = DUPLEX_HALF;
  2306. break;
  2307. case MII_TG3_AUX_STAT_100FULL:
  2308. *speed = SPEED_100;
  2309. *duplex = DUPLEX_FULL;
  2310. break;
  2311. case MII_TG3_AUX_STAT_1000HALF:
  2312. *speed = SPEED_1000;
  2313. *duplex = DUPLEX_HALF;
  2314. break;
  2315. case MII_TG3_AUX_STAT_1000FULL:
  2316. *speed = SPEED_1000;
  2317. *duplex = DUPLEX_FULL;
  2318. break;
  2319. default:
  2320. if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
  2321. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  2322. SPEED_10;
  2323. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  2324. DUPLEX_HALF;
  2325. break;
  2326. }
  2327. *speed = SPEED_INVALID;
  2328. *duplex = DUPLEX_INVALID;
  2329. break;
  2330. }
  2331. }
  2332. static void tg3_phy_copper_begin(struct tg3 *tp)
  2333. {
  2334. u32 new_adv;
  2335. int i;
  2336. if (tp->link_config.phy_is_low_power) {
  2337. /* Entering low power mode. Disable gigabit and
  2338. * 100baseT advertisements.
  2339. */
  2340. tg3_writephy(tp, MII_TG3_CTRL, 0);
  2341. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  2342. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  2343. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  2344. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  2345. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2346. } else if (tp->link_config.speed == SPEED_INVALID) {
  2347. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  2348. tp->link_config.advertising &=
  2349. ~(ADVERTISED_1000baseT_Half |
  2350. ADVERTISED_1000baseT_Full);
  2351. new_adv = ADVERTISE_CSMA;
  2352. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  2353. new_adv |= ADVERTISE_10HALF;
  2354. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  2355. new_adv |= ADVERTISE_10FULL;
  2356. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  2357. new_adv |= ADVERTISE_100HALF;
  2358. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  2359. new_adv |= ADVERTISE_100FULL;
  2360. new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2361. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2362. if (tp->link_config.advertising &
  2363. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  2364. new_adv = 0;
  2365. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2366. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  2367. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2368. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  2369. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  2370. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2371. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  2372. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  2373. MII_TG3_CTRL_ENABLE_AS_MASTER);
  2374. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  2375. } else {
  2376. tg3_writephy(tp, MII_TG3_CTRL, 0);
  2377. }
  2378. } else {
  2379. new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2380. new_adv |= ADVERTISE_CSMA;
  2381. /* Asking for a specific link mode. */
  2382. if (tp->link_config.speed == SPEED_1000) {
  2383. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2384. if (tp->link_config.duplex == DUPLEX_FULL)
  2385. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  2386. else
  2387. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  2388. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2389. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  2390. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  2391. MII_TG3_CTRL_ENABLE_AS_MASTER);
  2392. } else {
  2393. if (tp->link_config.speed == SPEED_100) {
  2394. if (tp->link_config.duplex == DUPLEX_FULL)
  2395. new_adv |= ADVERTISE_100FULL;
  2396. else
  2397. new_adv |= ADVERTISE_100HALF;
  2398. } else {
  2399. if (tp->link_config.duplex == DUPLEX_FULL)
  2400. new_adv |= ADVERTISE_10FULL;
  2401. else
  2402. new_adv |= ADVERTISE_10HALF;
  2403. }
  2404. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2405. new_adv = 0;
  2406. }
  2407. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  2408. }
  2409. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  2410. tp->link_config.speed != SPEED_INVALID) {
  2411. u32 bmcr, orig_bmcr;
  2412. tp->link_config.active_speed = tp->link_config.speed;
  2413. tp->link_config.active_duplex = tp->link_config.duplex;
  2414. bmcr = 0;
  2415. switch (tp->link_config.speed) {
  2416. default:
  2417. case SPEED_10:
  2418. break;
  2419. case SPEED_100:
  2420. bmcr |= BMCR_SPEED100;
  2421. break;
  2422. case SPEED_1000:
  2423. bmcr |= TG3_BMCR_SPEED1000;
  2424. break;
  2425. }
  2426. if (tp->link_config.duplex == DUPLEX_FULL)
  2427. bmcr |= BMCR_FULLDPLX;
  2428. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  2429. (bmcr != orig_bmcr)) {
  2430. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  2431. for (i = 0; i < 1500; i++) {
  2432. u32 tmp;
  2433. udelay(10);
  2434. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  2435. tg3_readphy(tp, MII_BMSR, &tmp))
  2436. continue;
  2437. if (!(tmp & BMSR_LSTATUS)) {
  2438. udelay(40);
  2439. break;
  2440. }
  2441. }
  2442. tg3_writephy(tp, MII_BMCR, bmcr);
  2443. udelay(40);
  2444. }
  2445. } else {
  2446. tg3_writephy(tp, MII_BMCR,
  2447. BMCR_ANENABLE | BMCR_ANRESTART);
  2448. }
  2449. }
  2450. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  2451. {
  2452. int err;
  2453. /* Turn off tap power management. */
  2454. /* Set Extended packet length bit */
  2455. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  2456. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
  2457. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
  2458. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
  2459. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
  2460. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  2461. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
  2462. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  2463. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
  2464. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  2465. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
  2466. udelay(40);
  2467. return err;
  2468. }
  2469. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  2470. {
  2471. u32 adv_reg, all_mask = 0;
  2472. if (mask & ADVERTISED_10baseT_Half)
  2473. all_mask |= ADVERTISE_10HALF;
  2474. if (mask & ADVERTISED_10baseT_Full)
  2475. all_mask |= ADVERTISE_10FULL;
  2476. if (mask & ADVERTISED_100baseT_Half)
  2477. all_mask |= ADVERTISE_100HALF;
  2478. if (mask & ADVERTISED_100baseT_Full)
  2479. all_mask |= ADVERTISE_100FULL;
  2480. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  2481. return 0;
  2482. if ((adv_reg & all_mask) != all_mask)
  2483. return 0;
  2484. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  2485. u32 tg3_ctrl;
  2486. all_mask = 0;
  2487. if (mask & ADVERTISED_1000baseT_Half)
  2488. all_mask |= ADVERTISE_1000HALF;
  2489. if (mask & ADVERTISED_1000baseT_Full)
  2490. all_mask |= ADVERTISE_1000FULL;
  2491. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  2492. return 0;
  2493. if ((tg3_ctrl & all_mask) != all_mask)
  2494. return 0;
  2495. }
  2496. return 1;
  2497. }
  2498. static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
  2499. {
  2500. u32 curadv, reqadv;
  2501. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  2502. return 1;
  2503. curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2504. reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  2505. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  2506. if (curadv != reqadv)
  2507. return 0;
  2508. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
  2509. tg3_readphy(tp, MII_LPA, rmtadv);
  2510. } else {
  2511. /* Reprogram the advertisement register, even if it
  2512. * does not affect the current link. If the link
  2513. * gets renegotiated in the future, we can save an
  2514. * additional renegotiation cycle by advertising
  2515. * it correctly in the first place.
  2516. */
  2517. if (curadv != reqadv) {
  2518. *lcladv &= ~(ADVERTISE_PAUSE_CAP |
  2519. ADVERTISE_PAUSE_ASYM);
  2520. tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
  2521. }
  2522. }
  2523. return 1;
  2524. }
  2525. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  2526. {
  2527. int current_link_up;
  2528. u32 bmsr, dummy;
  2529. u32 lcl_adv, rmt_adv;
  2530. u16 current_speed;
  2531. u8 current_duplex;
  2532. int i, err;
  2533. tw32(MAC_EVENT, 0);
  2534. tw32_f(MAC_STATUS,
  2535. (MAC_STATUS_SYNC_CHANGED |
  2536. MAC_STATUS_CFG_CHANGED |
  2537. MAC_STATUS_MI_COMPLETION |
  2538. MAC_STATUS_LNKSTATE_CHANGED));
  2539. udelay(40);
  2540. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  2541. tw32_f(MAC_MI_MODE,
  2542. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  2543. udelay(80);
  2544. }
  2545. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  2546. /* Some third-party PHYs need to be reset on link going
  2547. * down.
  2548. */
  2549. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  2550. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  2551. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  2552. netif_carrier_ok(tp->dev)) {
  2553. tg3_readphy(tp, MII_BMSR, &bmsr);
  2554. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2555. !(bmsr & BMSR_LSTATUS))
  2556. force_reset = 1;
  2557. }
  2558. if (force_reset)
  2559. tg3_phy_reset(tp);
  2560. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  2561. tg3_readphy(tp, MII_BMSR, &bmsr);
  2562. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  2563. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  2564. bmsr = 0;
  2565. if (!(bmsr & BMSR_LSTATUS)) {
  2566. err = tg3_init_5401phy_dsp(tp);
  2567. if (err)
  2568. return err;
  2569. tg3_readphy(tp, MII_BMSR, &bmsr);
  2570. for (i = 0; i < 1000; i++) {
  2571. udelay(10);
  2572. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2573. (bmsr & BMSR_LSTATUS)) {
  2574. udelay(40);
  2575. break;
  2576. }
  2577. }
  2578. if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
  2579. !(bmsr & BMSR_LSTATUS) &&
  2580. tp->link_config.active_speed == SPEED_1000) {
  2581. err = tg3_phy_reset(tp);
  2582. if (!err)
  2583. err = tg3_init_5401phy_dsp(tp);
  2584. if (err)
  2585. return err;
  2586. }
  2587. }
  2588. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  2589. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  2590. /* 5701 {A0,B0} CRC bug workaround */
  2591. tg3_writephy(tp, 0x15, 0x0a75);
  2592. tg3_writephy(tp, 0x1c, 0x8c68);
  2593. tg3_writephy(tp, 0x1c, 0x8d68);
  2594. tg3_writephy(tp, 0x1c, 0x8c68);
  2595. }
  2596. /* Clear pending interrupts... */
  2597. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  2598. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  2599. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
  2600. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  2601. else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
  2602. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  2603. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  2604. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  2605. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  2606. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2607. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  2608. else
  2609. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  2610. }
  2611. current_link_up = 0;
  2612. current_speed = SPEED_INVALID;
  2613. current_duplex = DUPLEX_INVALID;
  2614. if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
  2615. u32 val;
  2616. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  2617. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  2618. if (!(val & (1 << 10))) {
  2619. val |= (1 << 10);
  2620. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  2621. goto relink;
  2622. }
  2623. }
  2624. bmsr = 0;
  2625. for (i = 0; i < 100; i++) {
  2626. tg3_readphy(tp, MII_BMSR, &bmsr);
  2627. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  2628. (bmsr & BMSR_LSTATUS))
  2629. break;
  2630. udelay(40);
  2631. }
  2632. if (bmsr & BMSR_LSTATUS) {
  2633. u32 aux_stat, bmcr;
  2634. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  2635. for (i = 0; i < 2000; i++) {
  2636. udelay(10);
  2637. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  2638. aux_stat)
  2639. break;
  2640. }
  2641. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  2642. &current_speed,
  2643. &current_duplex);
  2644. bmcr = 0;
  2645. for (i = 0; i < 200; i++) {
  2646. tg3_readphy(tp, MII_BMCR, &bmcr);
  2647. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  2648. continue;
  2649. if (bmcr && bmcr != 0x7fff)
  2650. break;
  2651. udelay(10);
  2652. }
  2653. lcl_adv = 0;
  2654. rmt_adv = 0;
  2655. tp->link_config.active_speed = current_speed;
  2656. tp->link_config.active_duplex = current_duplex;
  2657. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2658. if ((bmcr & BMCR_ANENABLE) &&
  2659. tg3_copper_is_advertising_all(tp,
  2660. tp->link_config.advertising)) {
  2661. if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
  2662. &rmt_adv))
  2663. current_link_up = 1;
  2664. }
  2665. } else {
  2666. if (!(bmcr & BMCR_ANENABLE) &&
  2667. tp->link_config.speed == current_speed &&
  2668. tp->link_config.duplex == current_duplex &&
  2669. tp->link_config.flowctrl ==
  2670. tp->link_config.active_flowctrl) {
  2671. current_link_up = 1;
  2672. }
  2673. }
  2674. if (current_link_up == 1 &&
  2675. tp->link_config.active_duplex == DUPLEX_FULL)
  2676. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  2677. }
  2678. relink:
  2679. if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
  2680. u32 tmp;
  2681. tg3_phy_copper_begin(tp);
  2682. tg3_readphy(tp, MII_BMSR, &tmp);
  2683. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  2684. (tmp & BMSR_LSTATUS))
  2685. current_link_up = 1;
  2686. }
  2687. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  2688. if (current_link_up == 1) {
  2689. if (tp->link_config.active_speed == SPEED_100 ||
  2690. tp->link_config.active_speed == SPEED_10)
  2691. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  2692. else
  2693. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2694. } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
  2695. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  2696. else
  2697. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2698. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2699. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2700. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2701. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  2702. if (current_link_up == 1 &&
  2703. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  2704. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  2705. else
  2706. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  2707. }
  2708. /* ??? Without this setting Netgear GA302T PHY does not
  2709. * ??? send/receive packets...
  2710. */
  2711. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  2712. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  2713. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  2714. tw32_f(MAC_MI_MODE, tp->mi_mode);
  2715. udelay(80);
  2716. }
  2717. tw32_f(MAC_MODE, tp->mac_mode);
  2718. udelay(40);
  2719. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  2720. /* Polled via timer. */
  2721. tw32_f(MAC_EVENT, 0);
  2722. } else {
  2723. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2724. }
  2725. udelay(40);
  2726. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  2727. current_link_up == 1 &&
  2728. tp->link_config.active_speed == SPEED_1000 &&
  2729. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  2730. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  2731. udelay(120);
  2732. tw32_f(MAC_STATUS,
  2733. (MAC_STATUS_SYNC_CHANGED |
  2734. MAC_STATUS_CFG_CHANGED));
  2735. udelay(40);
  2736. tg3_write_mem(tp,
  2737. NIC_SRAM_FIRMWARE_MBOX,
  2738. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  2739. }
  2740. /* Prevent send BD corruption. */
  2741. if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
  2742. u16 oldlnkctl, newlnkctl;
  2743. pci_read_config_word(tp->pdev,
  2744. tp->pcie_cap + PCI_EXP_LNKCTL,
  2745. &oldlnkctl);
  2746. if (tp->link_config.active_speed == SPEED_100 ||
  2747. tp->link_config.active_speed == SPEED_10)
  2748. newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
  2749. else
  2750. newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
  2751. if (newlnkctl != oldlnkctl)
  2752. pci_write_config_word(tp->pdev,
  2753. tp->pcie_cap + PCI_EXP_LNKCTL,
  2754. newlnkctl);
  2755. }
  2756. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2757. if (current_link_up)
  2758. netif_carrier_on(tp->dev);
  2759. else
  2760. netif_carrier_off(tp->dev);
  2761. tg3_link_report(tp);
  2762. }
  2763. return 0;
  2764. }
  2765. struct tg3_fiber_aneginfo {
  2766. int state;
  2767. #define ANEG_STATE_UNKNOWN 0
  2768. #define ANEG_STATE_AN_ENABLE 1
  2769. #define ANEG_STATE_RESTART_INIT 2
  2770. #define ANEG_STATE_RESTART 3
  2771. #define ANEG_STATE_DISABLE_LINK_OK 4
  2772. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  2773. #define ANEG_STATE_ABILITY_DETECT 6
  2774. #define ANEG_STATE_ACK_DETECT_INIT 7
  2775. #define ANEG_STATE_ACK_DETECT 8
  2776. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  2777. #define ANEG_STATE_COMPLETE_ACK 10
  2778. #define ANEG_STATE_IDLE_DETECT_INIT 11
  2779. #define ANEG_STATE_IDLE_DETECT 12
  2780. #define ANEG_STATE_LINK_OK 13
  2781. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  2782. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  2783. u32 flags;
  2784. #define MR_AN_ENABLE 0x00000001
  2785. #define MR_RESTART_AN 0x00000002
  2786. #define MR_AN_COMPLETE 0x00000004
  2787. #define MR_PAGE_RX 0x00000008
  2788. #define MR_NP_LOADED 0x00000010
  2789. #define MR_TOGGLE_TX 0x00000020
  2790. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  2791. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  2792. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  2793. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  2794. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  2795. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  2796. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  2797. #define MR_TOGGLE_RX 0x00002000
  2798. #define MR_NP_RX 0x00004000
  2799. #define MR_LINK_OK 0x80000000
  2800. unsigned long link_time, cur_time;
  2801. u32 ability_match_cfg;
  2802. int ability_match_count;
  2803. char ability_match, idle_match, ack_match;
  2804. u32 txconfig, rxconfig;
  2805. #define ANEG_CFG_NP 0x00000080
  2806. #define ANEG_CFG_ACK 0x00000040
  2807. #define ANEG_CFG_RF2 0x00000020
  2808. #define ANEG_CFG_RF1 0x00000010
  2809. #define ANEG_CFG_PS2 0x00000001
  2810. #define ANEG_CFG_PS1 0x00008000
  2811. #define ANEG_CFG_HD 0x00004000
  2812. #define ANEG_CFG_FD 0x00002000
  2813. #define ANEG_CFG_INVAL 0x00001f06
  2814. };
  2815. #define ANEG_OK 0
  2816. #define ANEG_DONE 1
  2817. #define ANEG_TIMER_ENAB 2
  2818. #define ANEG_FAILED -1
  2819. #define ANEG_STATE_SETTLE_TIME 10000
  2820. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  2821. struct tg3_fiber_aneginfo *ap)
  2822. {
  2823. u16 flowctrl;
  2824. unsigned long delta;
  2825. u32 rx_cfg_reg;
  2826. int ret;
  2827. if (ap->state == ANEG_STATE_UNKNOWN) {
  2828. ap->rxconfig = 0;
  2829. ap->link_time = 0;
  2830. ap->cur_time = 0;
  2831. ap->ability_match_cfg = 0;
  2832. ap->ability_match_count = 0;
  2833. ap->ability_match = 0;
  2834. ap->idle_match = 0;
  2835. ap->ack_match = 0;
  2836. }
  2837. ap->cur_time++;
  2838. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  2839. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  2840. if (rx_cfg_reg != ap->ability_match_cfg) {
  2841. ap->ability_match_cfg = rx_cfg_reg;
  2842. ap->ability_match = 0;
  2843. ap->ability_match_count = 0;
  2844. } else {
  2845. if (++ap->ability_match_count > 1) {
  2846. ap->ability_match = 1;
  2847. ap->ability_match_cfg = rx_cfg_reg;
  2848. }
  2849. }
  2850. if (rx_cfg_reg & ANEG_CFG_ACK)
  2851. ap->ack_match = 1;
  2852. else
  2853. ap->ack_match = 0;
  2854. ap->idle_match = 0;
  2855. } else {
  2856. ap->idle_match = 1;
  2857. ap->ability_match_cfg = 0;
  2858. ap->ability_match_count = 0;
  2859. ap->ability_match = 0;
  2860. ap->ack_match = 0;
  2861. rx_cfg_reg = 0;
  2862. }
  2863. ap->rxconfig = rx_cfg_reg;
  2864. ret = ANEG_OK;
  2865. switch(ap->state) {
  2866. case ANEG_STATE_UNKNOWN:
  2867. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  2868. ap->state = ANEG_STATE_AN_ENABLE;
  2869. /* fallthru */
  2870. case ANEG_STATE_AN_ENABLE:
  2871. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  2872. if (ap->flags & MR_AN_ENABLE) {
  2873. ap->link_time = 0;
  2874. ap->cur_time = 0;
  2875. ap->ability_match_cfg = 0;
  2876. ap->ability_match_count = 0;
  2877. ap->ability_match = 0;
  2878. ap->idle_match = 0;
  2879. ap->ack_match = 0;
  2880. ap->state = ANEG_STATE_RESTART_INIT;
  2881. } else {
  2882. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  2883. }
  2884. break;
  2885. case ANEG_STATE_RESTART_INIT:
  2886. ap->link_time = ap->cur_time;
  2887. ap->flags &= ~(MR_NP_LOADED);
  2888. ap->txconfig = 0;
  2889. tw32(MAC_TX_AUTO_NEG, 0);
  2890. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2891. tw32_f(MAC_MODE, tp->mac_mode);
  2892. udelay(40);
  2893. ret = ANEG_TIMER_ENAB;
  2894. ap->state = ANEG_STATE_RESTART;
  2895. /* fallthru */
  2896. case ANEG_STATE_RESTART:
  2897. delta = ap->cur_time - ap->link_time;
  2898. if (delta > ANEG_STATE_SETTLE_TIME) {
  2899. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  2900. } else {
  2901. ret = ANEG_TIMER_ENAB;
  2902. }
  2903. break;
  2904. case ANEG_STATE_DISABLE_LINK_OK:
  2905. ret = ANEG_DONE;
  2906. break;
  2907. case ANEG_STATE_ABILITY_DETECT_INIT:
  2908. ap->flags &= ~(MR_TOGGLE_TX);
  2909. ap->txconfig = ANEG_CFG_FD;
  2910. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2911. if (flowctrl & ADVERTISE_1000XPAUSE)
  2912. ap->txconfig |= ANEG_CFG_PS1;
  2913. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  2914. ap->txconfig |= ANEG_CFG_PS2;
  2915. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2916. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2917. tw32_f(MAC_MODE, tp->mac_mode);
  2918. udelay(40);
  2919. ap->state = ANEG_STATE_ABILITY_DETECT;
  2920. break;
  2921. case ANEG_STATE_ABILITY_DETECT:
  2922. if (ap->ability_match != 0 && ap->rxconfig != 0) {
  2923. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  2924. }
  2925. break;
  2926. case ANEG_STATE_ACK_DETECT_INIT:
  2927. ap->txconfig |= ANEG_CFG_ACK;
  2928. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2929. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2930. tw32_f(MAC_MODE, tp->mac_mode);
  2931. udelay(40);
  2932. ap->state = ANEG_STATE_ACK_DETECT;
  2933. /* fallthru */
  2934. case ANEG_STATE_ACK_DETECT:
  2935. if (ap->ack_match != 0) {
  2936. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  2937. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  2938. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  2939. } else {
  2940. ap->state = ANEG_STATE_AN_ENABLE;
  2941. }
  2942. } else if (ap->ability_match != 0 &&
  2943. ap->rxconfig == 0) {
  2944. ap->state = ANEG_STATE_AN_ENABLE;
  2945. }
  2946. break;
  2947. case ANEG_STATE_COMPLETE_ACK_INIT:
  2948. if (ap->rxconfig & ANEG_CFG_INVAL) {
  2949. ret = ANEG_FAILED;
  2950. break;
  2951. }
  2952. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  2953. MR_LP_ADV_HALF_DUPLEX |
  2954. MR_LP_ADV_SYM_PAUSE |
  2955. MR_LP_ADV_ASYM_PAUSE |
  2956. MR_LP_ADV_REMOTE_FAULT1 |
  2957. MR_LP_ADV_REMOTE_FAULT2 |
  2958. MR_LP_ADV_NEXT_PAGE |
  2959. MR_TOGGLE_RX |
  2960. MR_NP_RX);
  2961. if (ap->rxconfig & ANEG_CFG_FD)
  2962. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  2963. if (ap->rxconfig & ANEG_CFG_HD)
  2964. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  2965. if (ap->rxconfig & ANEG_CFG_PS1)
  2966. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  2967. if (ap->rxconfig & ANEG_CFG_PS2)
  2968. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  2969. if (ap->rxconfig & ANEG_CFG_RF1)
  2970. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  2971. if (ap->rxconfig & ANEG_CFG_RF2)
  2972. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  2973. if (ap->rxconfig & ANEG_CFG_NP)
  2974. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  2975. ap->link_time = ap->cur_time;
  2976. ap->flags ^= (MR_TOGGLE_TX);
  2977. if (ap->rxconfig & 0x0008)
  2978. ap->flags |= MR_TOGGLE_RX;
  2979. if (ap->rxconfig & ANEG_CFG_NP)
  2980. ap->flags |= MR_NP_RX;
  2981. ap->flags |= MR_PAGE_RX;
  2982. ap->state = ANEG_STATE_COMPLETE_ACK;
  2983. ret = ANEG_TIMER_ENAB;
  2984. break;
  2985. case ANEG_STATE_COMPLETE_ACK:
  2986. if (ap->ability_match != 0 &&
  2987. ap->rxconfig == 0) {
  2988. ap->state = ANEG_STATE_AN_ENABLE;
  2989. break;
  2990. }
  2991. delta = ap->cur_time - ap->link_time;
  2992. if (delta > ANEG_STATE_SETTLE_TIME) {
  2993. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  2994. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2995. } else {
  2996. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  2997. !(ap->flags & MR_NP_RX)) {
  2998. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2999. } else {
  3000. ret = ANEG_FAILED;
  3001. }
  3002. }
  3003. }
  3004. break;
  3005. case ANEG_STATE_IDLE_DETECT_INIT:
  3006. ap->link_time = ap->cur_time;
  3007. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3008. tw32_f(MAC_MODE, tp->mac_mode);
  3009. udelay(40);
  3010. ap->state = ANEG_STATE_IDLE_DETECT;
  3011. ret = ANEG_TIMER_ENAB;
  3012. break;
  3013. case ANEG_STATE_IDLE_DETECT:
  3014. if (ap->ability_match != 0 &&
  3015. ap->rxconfig == 0) {
  3016. ap->state = ANEG_STATE_AN_ENABLE;
  3017. break;
  3018. }
  3019. delta = ap->cur_time - ap->link_time;
  3020. if (delta > ANEG_STATE_SETTLE_TIME) {
  3021. /* XXX another gem from the Broadcom driver :( */
  3022. ap->state = ANEG_STATE_LINK_OK;
  3023. }
  3024. break;
  3025. case ANEG_STATE_LINK_OK:
  3026. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  3027. ret = ANEG_DONE;
  3028. break;
  3029. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  3030. /* ??? unimplemented */
  3031. break;
  3032. case ANEG_STATE_NEXT_PAGE_WAIT:
  3033. /* ??? unimplemented */
  3034. break;
  3035. default:
  3036. ret = ANEG_FAILED;
  3037. break;
  3038. }
  3039. return ret;
  3040. }
  3041. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  3042. {
  3043. int res = 0;
  3044. struct tg3_fiber_aneginfo aninfo;
  3045. int status = ANEG_FAILED;
  3046. unsigned int tick;
  3047. u32 tmp;
  3048. tw32_f(MAC_TX_AUTO_NEG, 0);
  3049. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  3050. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  3051. udelay(40);
  3052. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  3053. udelay(40);
  3054. memset(&aninfo, 0, sizeof(aninfo));
  3055. aninfo.flags |= MR_AN_ENABLE;
  3056. aninfo.state = ANEG_STATE_UNKNOWN;
  3057. aninfo.cur_time = 0;
  3058. tick = 0;
  3059. while (++tick < 195000) {
  3060. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  3061. if (status == ANEG_DONE || status == ANEG_FAILED)
  3062. break;
  3063. udelay(1);
  3064. }
  3065. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3066. tw32_f(MAC_MODE, tp->mac_mode);
  3067. udelay(40);
  3068. *txflags = aninfo.txconfig;
  3069. *rxflags = aninfo.flags;
  3070. if (status == ANEG_DONE &&
  3071. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  3072. MR_LP_ADV_FULL_DUPLEX)))
  3073. res = 1;
  3074. return res;
  3075. }
  3076. static void tg3_init_bcm8002(struct tg3 *tp)
  3077. {
  3078. u32 mac_status = tr32(MAC_STATUS);
  3079. int i;
  3080. /* Reset when initting first time or we have a link. */
  3081. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  3082. !(mac_status & MAC_STATUS_PCS_SYNCED))
  3083. return;
  3084. /* Set PLL lock range. */
  3085. tg3_writephy(tp, 0x16, 0x8007);
  3086. /* SW reset */
  3087. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  3088. /* Wait for reset to complete. */
  3089. /* XXX schedule_timeout() ... */
  3090. for (i = 0; i < 500; i++)
  3091. udelay(10);
  3092. /* Config mode; select PMA/Ch 1 regs. */
  3093. tg3_writephy(tp, 0x10, 0x8411);
  3094. /* Enable auto-lock and comdet, select txclk for tx. */
  3095. tg3_writephy(tp, 0x11, 0x0a10);
  3096. tg3_writephy(tp, 0x18, 0x00a0);
  3097. tg3_writephy(tp, 0x16, 0x41ff);
  3098. /* Assert and deassert POR. */
  3099. tg3_writephy(tp, 0x13, 0x0400);
  3100. udelay(40);
  3101. tg3_writephy(tp, 0x13, 0x0000);
  3102. tg3_writephy(tp, 0x11, 0x0a50);
  3103. udelay(40);
  3104. tg3_writephy(tp, 0x11, 0x0a10);
  3105. /* Wait for signal to stabilize */
  3106. /* XXX schedule_timeout() ... */
  3107. for (i = 0; i < 15000; i++)
  3108. udelay(10);
  3109. /* Deselect the channel register so we can read the PHYID
  3110. * later.
  3111. */
  3112. tg3_writephy(tp, 0x10, 0x8011);
  3113. }
  3114. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  3115. {
  3116. u16 flowctrl;
  3117. u32 sg_dig_ctrl, sg_dig_status;
  3118. u32 serdes_cfg, expected_sg_dig_ctrl;
  3119. int workaround, port_a;
  3120. int current_link_up;
  3121. serdes_cfg = 0;
  3122. expected_sg_dig_ctrl = 0;
  3123. workaround = 0;
  3124. port_a = 1;
  3125. current_link_up = 0;
  3126. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  3127. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  3128. workaround = 1;
  3129. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  3130. port_a = 0;
  3131. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  3132. /* preserve bits 20-23 for voltage regulator */
  3133. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  3134. }
  3135. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  3136. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  3137. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  3138. if (workaround) {
  3139. u32 val = serdes_cfg;
  3140. if (port_a)
  3141. val |= 0xc010000;
  3142. else
  3143. val |= 0x4010000;
  3144. tw32_f(MAC_SERDES_CFG, val);
  3145. }
  3146. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  3147. }
  3148. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  3149. tg3_setup_flow_control(tp, 0, 0);
  3150. current_link_up = 1;
  3151. }
  3152. goto out;
  3153. }
  3154. /* Want auto-negotiation. */
  3155. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  3156. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3157. if (flowctrl & ADVERTISE_1000XPAUSE)
  3158. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  3159. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  3160. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  3161. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  3162. if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  3163. tp->serdes_counter &&
  3164. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  3165. MAC_STATUS_RCVD_CFG)) ==
  3166. MAC_STATUS_PCS_SYNCED)) {
  3167. tp->serdes_counter--;
  3168. current_link_up = 1;
  3169. goto out;
  3170. }
  3171. restart_autoneg:
  3172. if (workaround)
  3173. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  3174. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  3175. udelay(5);
  3176. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  3177. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  3178. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3179. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  3180. MAC_STATUS_SIGNAL_DET)) {
  3181. sg_dig_status = tr32(SG_DIG_STATUS);
  3182. mac_status = tr32(MAC_STATUS);
  3183. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  3184. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  3185. u32 local_adv = 0, remote_adv = 0;
  3186. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  3187. local_adv |= ADVERTISE_1000XPAUSE;
  3188. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  3189. local_adv |= ADVERTISE_1000XPSE_ASYM;
  3190. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  3191. remote_adv |= LPA_1000XPAUSE;
  3192. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  3193. remote_adv |= LPA_1000XPAUSE_ASYM;
  3194. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3195. current_link_up = 1;
  3196. tp->serdes_counter = 0;
  3197. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3198. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  3199. if (tp->serdes_counter)
  3200. tp->serdes_counter--;
  3201. else {
  3202. if (workaround) {
  3203. u32 val = serdes_cfg;
  3204. if (port_a)
  3205. val |= 0xc010000;
  3206. else
  3207. val |= 0x4010000;
  3208. tw32_f(MAC_SERDES_CFG, val);
  3209. }
  3210. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  3211. udelay(40);
  3212. /* Link parallel detection - link is up */
  3213. /* only if we have PCS_SYNC and not */
  3214. /* receiving config code words */
  3215. mac_status = tr32(MAC_STATUS);
  3216. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  3217. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  3218. tg3_setup_flow_control(tp, 0, 0);
  3219. current_link_up = 1;
  3220. tp->tg3_flags2 |=
  3221. TG3_FLG2_PARALLEL_DETECT;
  3222. tp->serdes_counter =
  3223. SERDES_PARALLEL_DET_TIMEOUT;
  3224. } else
  3225. goto restart_autoneg;
  3226. }
  3227. }
  3228. } else {
  3229. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  3230. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3231. }
  3232. out:
  3233. return current_link_up;
  3234. }
  3235. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  3236. {
  3237. int current_link_up = 0;
  3238. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  3239. goto out;
  3240. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3241. u32 txflags, rxflags;
  3242. int i;
  3243. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  3244. u32 local_adv = 0, remote_adv = 0;
  3245. if (txflags & ANEG_CFG_PS1)
  3246. local_adv |= ADVERTISE_1000XPAUSE;
  3247. if (txflags & ANEG_CFG_PS2)
  3248. local_adv |= ADVERTISE_1000XPSE_ASYM;
  3249. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  3250. remote_adv |= LPA_1000XPAUSE;
  3251. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  3252. remote_adv |= LPA_1000XPAUSE_ASYM;
  3253. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3254. current_link_up = 1;
  3255. }
  3256. for (i = 0; i < 30; i++) {
  3257. udelay(20);
  3258. tw32_f(MAC_STATUS,
  3259. (MAC_STATUS_SYNC_CHANGED |
  3260. MAC_STATUS_CFG_CHANGED));
  3261. udelay(40);
  3262. if ((tr32(MAC_STATUS) &
  3263. (MAC_STATUS_SYNC_CHANGED |
  3264. MAC_STATUS_CFG_CHANGED)) == 0)
  3265. break;
  3266. }
  3267. mac_status = tr32(MAC_STATUS);
  3268. if (current_link_up == 0 &&
  3269. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  3270. !(mac_status & MAC_STATUS_RCVD_CFG))
  3271. current_link_up = 1;
  3272. } else {
  3273. tg3_setup_flow_control(tp, 0, 0);
  3274. /* Forcing 1000FD link up. */
  3275. current_link_up = 1;
  3276. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  3277. udelay(40);
  3278. tw32_f(MAC_MODE, tp->mac_mode);
  3279. udelay(40);
  3280. }
  3281. out:
  3282. return current_link_up;
  3283. }
  3284. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  3285. {
  3286. u32 orig_pause_cfg;
  3287. u16 orig_active_speed;
  3288. u8 orig_active_duplex;
  3289. u32 mac_status;
  3290. int current_link_up;
  3291. int i;
  3292. orig_pause_cfg = tp->link_config.active_flowctrl;
  3293. orig_active_speed = tp->link_config.active_speed;
  3294. orig_active_duplex = tp->link_config.active_duplex;
  3295. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  3296. netif_carrier_ok(tp->dev) &&
  3297. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  3298. mac_status = tr32(MAC_STATUS);
  3299. mac_status &= (MAC_STATUS_PCS_SYNCED |
  3300. MAC_STATUS_SIGNAL_DET |
  3301. MAC_STATUS_CFG_CHANGED |
  3302. MAC_STATUS_RCVD_CFG);
  3303. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  3304. MAC_STATUS_SIGNAL_DET)) {
  3305. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  3306. MAC_STATUS_CFG_CHANGED));
  3307. return 0;
  3308. }
  3309. }
  3310. tw32_f(MAC_TX_AUTO_NEG, 0);
  3311. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  3312. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  3313. tw32_f(MAC_MODE, tp->mac_mode);
  3314. udelay(40);
  3315. if (tp->phy_id == PHY_ID_BCM8002)
  3316. tg3_init_bcm8002(tp);
  3317. /* Enable link change event even when serdes polling. */
  3318. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3319. udelay(40);
  3320. current_link_up = 0;
  3321. mac_status = tr32(MAC_STATUS);
  3322. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  3323. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  3324. else
  3325. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  3326. tp->napi[0].hw_status->status =
  3327. (SD_STATUS_UPDATED |
  3328. (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
  3329. for (i = 0; i < 100; i++) {
  3330. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  3331. MAC_STATUS_CFG_CHANGED));
  3332. udelay(5);
  3333. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  3334. MAC_STATUS_CFG_CHANGED |
  3335. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  3336. break;
  3337. }
  3338. mac_status = tr32(MAC_STATUS);
  3339. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  3340. current_link_up = 0;
  3341. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  3342. tp->serdes_counter == 0) {
  3343. tw32_f(MAC_MODE, (tp->mac_mode |
  3344. MAC_MODE_SEND_CONFIGS));
  3345. udelay(1);
  3346. tw32_f(MAC_MODE, tp->mac_mode);
  3347. }
  3348. }
  3349. if (current_link_up == 1) {
  3350. tp->link_config.active_speed = SPEED_1000;
  3351. tp->link_config.active_duplex = DUPLEX_FULL;
  3352. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  3353. LED_CTRL_LNKLED_OVERRIDE |
  3354. LED_CTRL_1000MBPS_ON));
  3355. } else {
  3356. tp->link_config.active_speed = SPEED_INVALID;
  3357. tp->link_config.active_duplex = DUPLEX_INVALID;
  3358. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  3359. LED_CTRL_LNKLED_OVERRIDE |
  3360. LED_CTRL_TRAFFIC_OVERRIDE));
  3361. }
  3362. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3363. if (current_link_up)
  3364. netif_carrier_on(tp->dev);
  3365. else
  3366. netif_carrier_off(tp->dev);
  3367. tg3_link_report(tp);
  3368. } else {
  3369. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  3370. if (orig_pause_cfg != now_pause_cfg ||
  3371. orig_active_speed != tp->link_config.active_speed ||
  3372. orig_active_duplex != tp->link_config.active_duplex)
  3373. tg3_link_report(tp);
  3374. }
  3375. return 0;
  3376. }
  3377. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  3378. {
  3379. int current_link_up, err = 0;
  3380. u32 bmsr, bmcr;
  3381. u16 current_speed;
  3382. u8 current_duplex;
  3383. u32 local_adv, remote_adv;
  3384. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  3385. tw32_f(MAC_MODE, tp->mac_mode);
  3386. udelay(40);
  3387. tw32(MAC_EVENT, 0);
  3388. tw32_f(MAC_STATUS,
  3389. (MAC_STATUS_SYNC_CHANGED |
  3390. MAC_STATUS_CFG_CHANGED |
  3391. MAC_STATUS_MI_COMPLETION |
  3392. MAC_STATUS_LNKSTATE_CHANGED));
  3393. udelay(40);
  3394. if (force_reset)
  3395. tg3_phy_reset(tp);
  3396. current_link_up = 0;
  3397. current_speed = SPEED_INVALID;
  3398. current_duplex = DUPLEX_INVALID;
  3399. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3400. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3401. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  3402. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  3403. bmsr |= BMSR_LSTATUS;
  3404. else
  3405. bmsr &= ~BMSR_LSTATUS;
  3406. }
  3407. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  3408. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  3409. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  3410. /* do nothing, just check for link up at the end */
  3411. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3412. u32 adv, new_adv;
  3413. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  3414. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  3415. ADVERTISE_1000XPAUSE |
  3416. ADVERTISE_1000XPSE_ASYM |
  3417. ADVERTISE_SLCT);
  3418. new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3419. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  3420. new_adv |= ADVERTISE_1000XHALF;
  3421. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  3422. new_adv |= ADVERTISE_1000XFULL;
  3423. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  3424. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  3425. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  3426. tg3_writephy(tp, MII_BMCR, bmcr);
  3427. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3428. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  3429. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3430. return err;
  3431. }
  3432. } else {
  3433. u32 new_bmcr;
  3434. bmcr &= ~BMCR_SPEED1000;
  3435. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  3436. if (tp->link_config.duplex == DUPLEX_FULL)
  3437. new_bmcr |= BMCR_FULLDPLX;
  3438. if (new_bmcr != bmcr) {
  3439. /* BMCR_SPEED1000 is a reserved bit that needs
  3440. * to be set on write.
  3441. */
  3442. new_bmcr |= BMCR_SPEED1000;
  3443. /* Force a linkdown */
  3444. if (netif_carrier_ok(tp->dev)) {
  3445. u32 adv;
  3446. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  3447. adv &= ~(ADVERTISE_1000XFULL |
  3448. ADVERTISE_1000XHALF |
  3449. ADVERTISE_SLCT);
  3450. tg3_writephy(tp, MII_ADVERTISE, adv);
  3451. tg3_writephy(tp, MII_BMCR, bmcr |
  3452. BMCR_ANRESTART |
  3453. BMCR_ANENABLE);
  3454. udelay(10);
  3455. netif_carrier_off(tp->dev);
  3456. }
  3457. tg3_writephy(tp, MII_BMCR, new_bmcr);
  3458. bmcr = new_bmcr;
  3459. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3460. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  3461. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  3462. ASIC_REV_5714) {
  3463. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  3464. bmsr |= BMSR_LSTATUS;
  3465. else
  3466. bmsr &= ~BMSR_LSTATUS;
  3467. }
  3468. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3469. }
  3470. }
  3471. if (bmsr & BMSR_LSTATUS) {
  3472. current_speed = SPEED_1000;
  3473. current_link_up = 1;
  3474. if (bmcr & BMCR_FULLDPLX)
  3475. current_duplex = DUPLEX_FULL;
  3476. else
  3477. current_duplex = DUPLEX_HALF;
  3478. local_adv = 0;
  3479. remote_adv = 0;
  3480. if (bmcr & BMCR_ANENABLE) {
  3481. u32 common;
  3482. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  3483. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  3484. common = local_adv & remote_adv;
  3485. if (common & (ADVERTISE_1000XHALF |
  3486. ADVERTISE_1000XFULL)) {
  3487. if (common & ADVERTISE_1000XFULL)
  3488. current_duplex = DUPLEX_FULL;
  3489. else
  3490. current_duplex = DUPLEX_HALF;
  3491. }
  3492. else
  3493. current_link_up = 0;
  3494. }
  3495. }
  3496. if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
  3497. tg3_setup_flow_control(tp, local_adv, remote_adv);
  3498. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  3499. if (tp->link_config.active_duplex == DUPLEX_HALF)
  3500. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  3501. tw32_f(MAC_MODE, tp->mac_mode);
  3502. udelay(40);
  3503. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3504. tp->link_config.active_speed = current_speed;
  3505. tp->link_config.active_duplex = current_duplex;
  3506. if (current_link_up != netif_carrier_ok(tp->dev)) {
  3507. if (current_link_up)
  3508. netif_carrier_on(tp->dev);
  3509. else {
  3510. netif_carrier_off(tp->dev);
  3511. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3512. }
  3513. tg3_link_report(tp);
  3514. }
  3515. return err;
  3516. }
  3517. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  3518. {
  3519. if (tp->serdes_counter) {
  3520. /* Give autoneg time to complete. */
  3521. tp->serdes_counter--;
  3522. return;
  3523. }
  3524. if (!netif_carrier_ok(tp->dev) &&
  3525. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  3526. u32 bmcr;
  3527. tg3_readphy(tp, MII_BMCR, &bmcr);
  3528. if (bmcr & BMCR_ANENABLE) {
  3529. u32 phy1, phy2;
  3530. /* Select shadow register 0x1f */
  3531. tg3_writephy(tp, 0x1c, 0x7c00);
  3532. tg3_readphy(tp, 0x1c, &phy1);
  3533. /* Select expansion interrupt status register */
  3534. tg3_writephy(tp, 0x17, 0x0f01);
  3535. tg3_readphy(tp, 0x15, &phy2);
  3536. tg3_readphy(tp, 0x15, &phy2);
  3537. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  3538. /* We have signal detect and not receiving
  3539. * config code words, link is up by parallel
  3540. * detection.
  3541. */
  3542. bmcr &= ~BMCR_ANENABLE;
  3543. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  3544. tg3_writephy(tp, MII_BMCR, bmcr);
  3545. tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
  3546. }
  3547. }
  3548. }
  3549. else if (netif_carrier_ok(tp->dev) &&
  3550. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  3551. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  3552. u32 phy2;
  3553. /* Select expansion interrupt status register */
  3554. tg3_writephy(tp, 0x17, 0x0f01);
  3555. tg3_readphy(tp, 0x15, &phy2);
  3556. if (phy2 & 0x20) {
  3557. u32 bmcr;
  3558. /* Config code words received, turn on autoneg. */
  3559. tg3_readphy(tp, MII_BMCR, &bmcr);
  3560. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  3561. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  3562. }
  3563. }
  3564. }
  3565. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  3566. {
  3567. int err;
  3568. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  3569. err = tg3_setup_fiber_phy(tp, force_reset);
  3570. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  3571. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  3572. } else {
  3573. err = tg3_setup_copper_phy(tp, force_reset);
  3574. }
  3575. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  3576. u32 val, scale;
  3577. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  3578. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  3579. scale = 65;
  3580. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  3581. scale = 6;
  3582. else
  3583. scale = 12;
  3584. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  3585. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  3586. tw32(GRC_MISC_CFG, val);
  3587. }
  3588. if (tp->link_config.active_speed == SPEED_1000 &&
  3589. tp->link_config.active_duplex == DUPLEX_HALF)
  3590. tw32(MAC_TX_LENGTHS,
  3591. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  3592. (6 << TX_LENGTHS_IPG_SHIFT) |
  3593. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  3594. else
  3595. tw32(MAC_TX_LENGTHS,
  3596. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  3597. (6 << TX_LENGTHS_IPG_SHIFT) |
  3598. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  3599. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  3600. if (netif_carrier_ok(tp->dev)) {
  3601. tw32(HOSTCC_STAT_COAL_TICKS,
  3602. tp->coal.stats_block_coalesce_usecs);
  3603. } else {
  3604. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  3605. }
  3606. }
  3607. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
  3608. u32 val = tr32(PCIE_PWR_MGMT_THRESH);
  3609. if (!netif_carrier_ok(tp->dev))
  3610. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  3611. tp->pwrmgmt_thresh;
  3612. else
  3613. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  3614. tw32(PCIE_PWR_MGMT_THRESH, val);
  3615. }
  3616. return err;
  3617. }
  3618. /* This is called whenever we suspect that the system chipset is re-
  3619. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  3620. * is bogus tx completions. We try to recover by setting the
  3621. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  3622. * in the workqueue.
  3623. */
  3624. static void tg3_tx_recover(struct tg3 *tp)
  3625. {
  3626. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  3627. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  3628. printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
  3629. "mapped I/O cycles to the network device, attempting to "
  3630. "recover. Please report the problem to the driver maintainer "
  3631. "and include system chipset information.\n", tp->dev->name);
  3632. spin_lock(&tp->lock);
  3633. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  3634. spin_unlock(&tp->lock);
  3635. }
  3636. static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
  3637. {
  3638. smp_mb();
  3639. return tnapi->tx_pending -
  3640. ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
  3641. }
  3642. /* Tigon3 never reports partial packet sends. So we do not
  3643. * need special logic to handle SKBs that have not had all
  3644. * of their frags sent yet, like SunGEM does.
  3645. */
  3646. static void tg3_tx(struct tg3_napi *tnapi)
  3647. {
  3648. struct tg3 *tp = tnapi->tp;
  3649. u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
  3650. u32 sw_idx = tnapi->tx_cons;
  3651. struct netdev_queue *txq;
  3652. int index = tnapi - tp->napi;
  3653. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  3654. index--;
  3655. txq = netdev_get_tx_queue(tp->dev, index);
  3656. while (sw_idx != hw_idx) {
  3657. struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
  3658. struct sk_buff *skb = ri->skb;
  3659. int i, tx_bug = 0;
  3660. if (unlikely(skb == NULL)) {
  3661. tg3_tx_recover(tp);
  3662. return;
  3663. }
  3664. pci_unmap_single(tp->pdev,
  3665. pci_unmap_addr(ri, mapping),
  3666. skb_headlen(skb),
  3667. PCI_DMA_TODEVICE);
  3668. ri->skb = NULL;
  3669. sw_idx = NEXT_TX(sw_idx);
  3670. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  3671. ri = &tnapi->tx_buffers[sw_idx];
  3672. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  3673. tx_bug = 1;
  3674. pci_unmap_page(tp->pdev,
  3675. pci_unmap_addr(ri, mapping),
  3676. skb_shinfo(skb)->frags[i].size,
  3677. PCI_DMA_TODEVICE);
  3678. sw_idx = NEXT_TX(sw_idx);
  3679. }
  3680. dev_kfree_skb(skb);
  3681. if (unlikely(tx_bug)) {
  3682. tg3_tx_recover(tp);
  3683. return;
  3684. }
  3685. }
  3686. tnapi->tx_cons = sw_idx;
  3687. /* Need to make the tx_cons update visible to tg3_start_xmit()
  3688. * before checking for netif_queue_stopped(). Without the
  3689. * memory barrier, there is a small possibility that tg3_start_xmit()
  3690. * will miss it and cause the queue to be stopped forever.
  3691. */
  3692. smp_mb();
  3693. if (unlikely(netif_tx_queue_stopped(txq) &&
  3694. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
  3695. __netif_tx_lock(txq, smp_processor_id());
  3696. if (netif_tx_queue_stopped(txq) &&
  3697. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
  3698. netif_tx_wake_queue(txq);
  3699. __netif_tx_unlock(txq);
  3700. }
  3701. }
  3702. static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
  3703. {
  3704. if (!ri->skb)
  3705. return;
  3706. pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
  3707. map_sz, PCI_DMA_FROMDEVICE);
  3708. dev_kfree_skb_any(ri->skb);
  3709. ri->skb = NULL;
  3710. }
  3711. /* Returns size of skb allocated or < 0 on error.
  3712. *
  3713. * We only need to fill in the address because the other members
  3714. * of the RX descriptor are invariant, see tg3_init_rings.
  3715. *
  3716. * Note the purposeful assymetry of cpu vs. chip accesses. For
  3717. * posting buffers we only dirty the first cache line of the RX
  3718. * descriptor (containing the address). Whereas for the RX status
  3719. * buffers the cpu only reads the last cacheline of the RX descriptor
  3720. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  3721. */
  3722. static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
  3723. u32 opaque_key, u32 dest_idx_unmasked)
  3724. {
  3725. struct tg3_rx_buffer_desc *desc;
  3726. struct ring_info *map, *src_map;
  3727. struct sk_buff *skb;
  3728. dma_addr_t mapping;
  3729. int skb_size, dest_idx;
  3730. src_map = NULL;
  3731. switch (opaque_key) {
  3732. case RXD_OPAQUE_RING_STD:
  3733. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3734. desc = &tpr->rx_std[dest_idx];
  3735. map = &tpr->rx_std_buffers[dest_idx];
  3736. skb_size = tp->rx_pkt_map_sz;
  3737. break;
  3738. case RXD_OPAQUE_RING_JUMBO:
  3739. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3740. desc = &tpr->rx_jmb[dest_idx].std;
  3741. map = &tpr->rx_jmb_buffers[dest_idx];
  3742. skb_size = TG3_RX_JMB_MAP_SZ;
  3743. break;
  3744. default:
  3745. return -EINVAL;
  3746. }
  3747. /* Do not overwrite any of the map or rp information
  3748. * until we are sure we can commit to a new buffer.
  3749. *
  3750. * Callers depend upon this behavior and assume that
  3751. * we leave everything unchanged if we fail.
  3752. */
  3753. skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
  3754. if (skb == NULL)
  3755. return -ENOMEM;
  3756. skb_reserve(skb, tp->rx_offset);
  3757. mapping = pci_map_single(tp->pdev, skb->data, skb_size,
  3758. PCI_DMA_FROMDEVICE);
  3759. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  3760. dev_kfree_skb(skb);
  3761. return -EIO;
  3762. }
  3763. map->skb = skb;
  3764. pci_unmap_addr_set(map, mapping, mapping);
  3765. desc->addr_hi = ((u64)mapping >> 32);
  3766. desc->addr_lo = ((u64)mapping & 0xffffffff);
  3767. return skb_size;
  3768. }
  3769. /* We only need to move over in the address because the other
  3770. * members of the RX descriptor are invariant. See notes above
  3771. * tg3_alloc_rx_skb for full details.
  3772. */
  3773. static void tg3_recycle_rx(struct tg3_napi *tnapi,
  3774. struct tg3_rx_prodring_set *dpr,
  3775. u32 opaque_key, int src_idx,
  3776. u32 dest_idx_unmasked)
  3777. {
  3778. struct tg3 *tp = tnapi->tp;
  3779. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  3780. struct ring_info *src_map, *dest_map;
  3781. int dest_idx;
  3782. struct tg3_rx_prodring_set *spr = &tp->prodring[0];
  3783. switch (opaque_key) {
  3784. case RXD_OPAQUE_RING_STD:
  3785. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3786. dest_desc = &dpr->rx_std[dest_idx];
  3787. dest_map = &dpr->rx_std_buffers[dest_idx];
  3788. src_desc = &spr->rx_std[src_idx];
  3789. src_map = &spr->rx_std_buffers[src_idx];
  3790. break;
  3791. case RXD_OPAQUE_RING_JUMBO:
  3792. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3793. dest_desc = &dpr->rx_jmb[dest_idx].std;
  3794. dest_map = &dpr->rx_jmb_buffers[dest_idx];
  3795. src_desc = &spr->rx_jmb[src_idx].std;
  3796. src_map = &spr->rx_jmb_buffers[src_idx];
  3797. break;
  3798. default:
  3799. return;
  3800. }
  3801. dest_map->skb = src_map->skb;
  3802. pci_unmap_addr_set(dest_map, mapping,
  3803. pci_unmap_addr(src_map, mapping));
  3804. dest_desc->addr_hi = src_desc->addr_hi;
  3805. dest_desc->addr_lo = src_desc->addr_lo;
  3806. /* Ensure that the update to the skb happens after the physical
  3807. * addresses have been transferred to the new BD location.
  3808. */
  3809. smp_wmb();
  3810. src_map->skb = NULL;
  3811. }
  3812. /* The RX ring scheme is composed of multiple rings which post fresh
  3813. * buffers to the chip, and one special ring the chip uses to report
  3814. * status back to the host.
  3815. *
  3816. * The special ring reports the status of received packets to the
  3817. * host. The chip does not write into the original descriptor the
  3818. * RX buffer was obtained from. The chip simply takes the original
  3819. * descriptor as provided by the host, updates the status and length
  3820. * field, then writes this into the next status ring entry.
  3821. *
  3822. * Each ring the host uses to post buffers to the chip is described
  3823. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  3824. * it is first placed into the on-chip ram. When the packet's length
  3825. * is known, it walks down the TG3_BDINFO entries to select the ring.
  3826. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  3827. * which is within the range of the new packet's length is chosen.
  3828. *
  3829. * The "separate ring for rx status" scheme may sound queer, but it makes
  3830. * sense from a cache coherency perspective. If only the host writes
  3831. * to the buffer post rings, and only the chip writes to the rx status
  3832. * rings, then cache lines never move beyond shared-modified state.
  3833. * If both the host and chip were to write into the same ring, cache line
  3834. * eviction could occur since both entities want it in an exclusive state.
  3835. */
  3836. static int tg3_rx(struct tg3_napi *tnapi, int budget)
  3837. {
  3838. struct tg3 *tp = tnapi->tp;
  3839. u32 work_mask, rx_std_posted = 0;
  3840. u32 std_prod_idx, jmb_prod_idx;
  3841. u32 sw_idx = tnapi->rx_rcb_ptr;
  3842. u16 hw_idx;
  3843. int received;
  3844. struct tg3_rx_prodring_set *tpr = tnapi->prodring;
  3845. hw_idx = *(tnapi->rx_rcb_prod_idx);
  3846. /*
  3847. * We need to order the read of hw_idx and the read of
  3848. * the opaque cookie.
  3849. */
  3850. rmb();
  3851. work_mask = 0;
  3852. received = 0;
  3853. std_prod_idx = tpr->rx_std_prod_idx;
  3854. jmb_prod_idx = tpr->rx_jmb_prod_idx;
  3855. while (sw_idx != hw_idx && budget > 0) {
  3856. struct ring_info *ri;
  3857. struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
  3858. unsigned int len;
  3859. struct sk_buff *skb;
  3860. dma_addr_t dma_addr;
  3861. u32 opaque_key, desc_idx, *post_ptr;
  3862. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  3863. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  3864. if (opaque_key == RXD_OPAQUE_RING_STD) {
  3865. ri = &tp->prodring[0].rx_std_buffers[desc_idx];
  3866. dma_addr = pci_unmap_addr(ri, mapping);
  3867. skb = ri->skb;
  3868. post_ptr = &std_prod_idx;
  3869. rx_std_posted++;
  3870. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  3871. ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
  3872. dma_addr = pci_unmap_addr(ri, mapping);
  3873. skb = ri->skb;
  3874. post_ptr = &jmb_prod_idx;
  3875. } else
  3876. goto next_pkt_nopost;
  3877. work_mask |= opaque_key;
  3878. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  3879. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  3880. drop_it:
  3881. tg3_recycle_rx(tnapi, tpr, opaque_key,
  3882. desc_idx, *post_ptr);
  3883. drop_it_no_recycle:
  3884. /* Other statistics kept track of by card. */
  3885. tp->net_stats.rx_dropped++;
  3886. goto next_pkt;
  3887. }
  3888. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
  3889. ETH_FCS_LEN;
  3890. if (len > RX_COPY_THRESHOLD &&
  3891. tp->rx_offset == NET_IP_ALIGN) {
  3892. /* rx_offset will likely not equal NET_IP_ALIGN
  3893. * if this is a 5701 card running in PCI-X mode
  3894. * [see tg3_get_invariants()]
  3895. */
  3896. int skb_size;
  3897. skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
  3898. *post_ptr);
  3899. if (skb_size < 0)
  3900. goto drop_it;
  3901. ri->skb = NULL;
  3902. pci_unmap_single(tp->pdev, dma_addr, skb_size,
  3903. PCI_DMA_FROMDEVICE);
  3904. skb_put(skb, len);
  3905. } else {
  3906. struct sk_buff *copy_skb;
  3907. tg3_recycle_rx(tnapi, tpr, opaque_key,
  3908. desc_idx, *post_ptr);
  3909. copy_skb = netdev_alloc_skb(tp->dev,
  3910. len + TG3_RAW_IP_ALIGN);
  3911. if (copy_skb == NULL)
  3912. goto drop_it_no_recycle;
  3913. skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
  3914. skb_put(copy_skb, len);
  3915. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3916. skb_copy_from_linear_data(skb, copy_skb->data, len);
  3917. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3918. /* We'll reuse the original ring buffer. */
  3919. skb = copy_skb;
  3920. }
  3921. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  3922. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  3923. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  3924. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  3925. skb->ip_summed = CHECKSUM_UNNECESSARY;
  3926. else
  3927. skb->ip_summed = CHECKSUM_NONE;
  3928. skb->protocol = eth_type_trans(skb, tp->dev);
  3929. if (len > (tp->dev->mtu + ETH_HLEN) &&
  3930. skb->protocol != htons(ETH_P_8021Q)) {
  3931. dev_kfree_skb(skb);
  3932. goto next_pkt;
  3933. }
  3934. #if TG3_VLAN_TAG_USED
  3935. if (tp->vlgrp != NULL &&
  3936. desc->type_flags & RXD_FLAG_VLAN) {
  3937. vlan_gro_receive(&tnapi->napi, tp->vlgrp,
  3938. desc->err_vlan & RXD_VLAN_MASK, skb);
  3939. } else
  3940. #endif
  3941. napi_gro_receive(&tnapi->napi, skb);
  3942. received++;
  3943. budget--;
  3944. next_pkt:
  3945. (*post_ptr)++;
  3946. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  3947. tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
  3948. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  3949. tpr->rx_std_prod_idx);
  3950. work_mask &= ~RXD_OPAQUE_RING_STD;
  3951. rx_std_posted = 0;
  3952. }
  3953. next_pkt_nopost:
  3954. sw_idx++;
  3955. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  3956. /* Refresh hw_idx to see if there is new work */
  3957. if (sw_idx == hw_idx) {
  3958. hw_idx = *(tnapi->rx_rcb_prod_idx);
  3959. rmb();
  3960. }
  3961. }
  3962. /* ACK the status ring. */
  3963. tnapi->rx_rcb_ptr = sw_idx;
  3964. tw32_rx_mbox(tnapi->consmbox, sw_idx);
  3965. /* Refill RX ring(s). */
  3966. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
  3967. if (work_mask & RXD_OPAQUE_RING_STD) {
  3968. tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
  3969. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  3970. tpr->rx_std_prod_idx);
  3971. }
  3972. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  3973. tpr->rx_jmb_prod_idx = jmb_prod_idx %
  3974. TG3_RX_JUMBO_RING_SIZE;
  3975. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  3976. tpr->rx_jmb_prod_idx);
  3977. }
  3978. mmiowb();
  3979. } else if (work_mask) {
  3980. /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
  3981. * updated before the producer indices can be updated.
  3982. */
  3983. smp_wmb();
  3984. tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
  3985. tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
  3986. if (tnapi != &tp->napi[1])
  3987. napi_schedule(&tp->napi[1].napi);
  3988. }
  3989. return received;
  3990. }
  3991. static void tg3_poll_link(struct tg3 *tp)
  3992. {
  3993. /* handle link change and other phy events */
  3994. if (!(tp->tg3_flags &
  3995. (TG3_FLAG_USE_LINKCHG_REG |
  3996. TG3_FLAG_POLL_SERDES))) {
  3997. struct tg3_hw_status *sblk = tp->napi[0].hw_status;
  3998. if (sblk->status & SD_STATUS_LINK_CHG) {
  3999. sblk->status = SD_STATUS_UPDATED |
  4000. (sblk->status & ~SD_STATUS_LINK_CHG);
  4001. spin_lock(&tp->lock);
  4002. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  4003. tw32_f(MAC_STATUS,
  4004. (MAC_STATUS_SYNC_CHANGED |
  4005. MAC_STATUS_CFG_CHANGED |
  4006. MAC_STATUS_MI_COMPLETION |
  4007. MAC_STATUS_LNKSTATE_CHANGED));
  4008. udelay(40);
  4009. } else
  4010. tg3_setup_phy(tp, 0);
  4011. spin_unlock(&tp->lock);
  4012. }
  4013. }
  4014. }
  4015. static int tg3_rx_prodring_xfer(struct tg3 *tp,
  4016. struct tg3_rx_prodring_set *dpr,
  4017. struct tg3_rx_prodring_set *spr)
  4018. {
  4019. u32 si, di, cpycnt, src_prod_idx;
  4020. int i, err = 0;
  4021. while (1) {
  4022. src_prod_idx = spr->rx_std_prod_idx;
  4023. /* Make sure updates to the rx_std_buffers[] entries and the
  4024. * standard producer index are seen in the correct order.
  4025. */
  4026. smp_rmb();
  4027. if (spr->rx_std_cons_idx == src_prod_idx)
  4028. break;
  4029. if (spr->rx_std_cons_idx < src_prod_idx)
  4030. cpycnt = src_prod_idx - spr->rx_std_cons_idx;
  4031. else
  4032. cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
  4033. cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
  4034. si = spr->rx_std_cons_idx;
  4035. di = dpr->rx_std_prod_idx;
  4036. for (i = di; i < di + cpycnt; i++) {
  4037. if (dpr->rx_std_buffers[i].skb) {
  4038. cpycnt = i - di;
  4039. err = -ENOSPC;
  4040. break;
  4041. }
  4042. }
  4043. if (!cpycnt)
  4044. break;
  4045. /* Ensure that updates to the rx_std_buffers ring and the
  4046. * shadowed hardware producer ring from tg3_recycle_skb() are
  4047. * ordered correctly WRT the skb check above.
  4048. */
  4049. smp_rmb();
  4050. memcpy(&dpr->rx_std_buffers[di],
  4051. &spr->rx_std_buffers[si],
  4052. cpycnt * sizeof(struct ring_info));
  4053. for (i = 0; i < cpycnt; i++, di++, si++) {
  4054. struct tg3_rx_buffer_desc *sbd, *dbd;
  4055. sbd = &spr->rx_std[si];
  4056. dbd = &dpr->rx_std[di];
  4057. dbd->addr_hi = sbd->addr_hi;
  4058. dbd->addr_lo = sbd->addr_lo;
  4059. }
  4060. spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
  4061. TG3_RX_RING_SIZE;
  4062. dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
  4063. TG3_RX_RING_SIZE;
  4064. }
  4065. while (1) {
  4066. src_prod_idx = spr->rx_jmb_prod_idx;
  4067. /* Make sure updates to the rx_jmb_buffers[] entries and
  4068. * the jumbo producer index are seen in the correct order.
  4069. */
  4070. smp_rmb();
  4071. if (spr->rx_jmb_cons_idx == src_prod_idx)
  4072. break;
  4073. if (spr->rx_jmb_cons_idx < src_prod_idx)
  4074. cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
  4075. else
  4076. cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
  4077. cpycnt = min(cpycnt,
  4078. TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
  4079. si = spr->rx_jmb_cons_idx;
  4080. di = dpr->rx_jmb_prod_idx;
  4081. for (i = di; i < di + cpycnt; i++) {
  4082. if (dpr->rx_jmb_buffers[i].skb) {
  4083. cpycnt = i - di;
  4084. err = -ENOSPC;
  4085. break;
  4086. }
  4087. }
  4088. if (!cpycnt)
  4089. break;
  4090. /* Ensure that updates to the rx_jmb_buffers ring and the
  4091. * shadowed hardware producer ring from tg3_recycle_skb() are
  4092. * ordered correctly WRT the skb check above.
  4093. */
  4094. smp_rmb();
  4095. memcpy(&dpr->rx_jmb_buffers[di],
  4096. &spr->rx_jmb_buffers[si],
  4097. cpycnt * sizeof(struct ring_info));
  4098. for (i = 0; i < cpycnt; i++, di++, si++) {
  4099. struct tg3_rx_buffer_desc *sbd, *dbd;
  4100. sbd = &spr->rx_jmb[si].std;
  4101. dbd = &dpr->rx_jmb[di].std;
  4102. dbd->addr_hi = sbd->addr_hi;
  4103. dbd->addr_lo = sbd->addr_lo;
  4104. }
  4105. spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
  4106. TG3_RX_JUMBO_RING_SIZE;
  4107. dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
  4108. TG3_RX_JUMBO_RING_SIZE;
  4109. }
  4110. return err;
  4111. }
  4112. static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
  4113. {
  4114. struct tg3 *tp = tnapi->tp;
  4115. /* run TX completion thread */
  4116. if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
  4117. tg3_tx(tnapi);
  4118. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  4119. return work_done;
  4120. }
  4121. /* run RX thread, within the bounds set by NAPI.
  4122. * All RX "locking" is done by ensuring outside
  4123. * code synchronizes with tg3->napi.poll()
  4124. */
  4125. if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  4126. work_done += tg3_rx(tnapi, budget - work_done);
  4127. if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
  4128. struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
  4129. int i, err = 0;
  4130. u32 std_prod_idx = dpr->rx_std_prod_idx;
  4131. u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
  4132. for (i = 1; i < tp->irq_cnt; i++)
  4133. err |= tg3_rx_prodring_xfer(tp, dpr,
  4134. tp->napi[i].prodring);
  4135. wmb();
  4136. if (std_prod_idx != dpr->rx_std_prod_idx)
  4137. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  4138. dpr->rx_std_prod_idx);
  4139. if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
  4140. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  4141. dpr->rx_jmb_prod_idx);
  4142. mmiowb();
  4143. if (err)
  4144. tw32_f(HOSTCC_MODE, tp->coal_now);
  4145. }
  4146. return work_done;
  4147. }
  4148. static int tg3_poll_msix(struct napi_struct *napi, int budget)
  4149. {
  4150. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  4151. struct tg3 *tp = tnapi->tp;
  4152. int work_done = 0;
  4153. struct tg3_hw_status *sblk = tnapi->hw_status;
  4154. while (1) {
  4155. work_done = tg3_poll_work(tnapi, work_done, budget);
  4156. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  4157. goto tx_recovery;
  4158. if (unlikely(work_done >= budget))
  4159. break;
  4160. /* tp->last_tag is used in tg3_restart_ints() below
  4161. * to tell the hw how much work has been processed,
  4162. * so we must read it before checking for more work.
  4163. */
  4164. tnapi->last_tag = sblk->status_tag;
  4165. tnapi->last_irq_tag = tnapi->last_tag;
  4166. rmb();
  4167. /* check for RX/TX work to do */
  4168. if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
  4169. *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
  4170. napi_complete(napi);
  4171. /* Reenable interrupts. */
  4172. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  4173. mmiowb();
  4174. break;
  4175. }
  4176. }
  4177. return work_done;
  4178. tx_recovery:
  4179. /* work_done is guaranteed to be less than budget. */
  4180. napi_complete(napi);
  4181. schedule_work(&tp->reset_task);
  4182. return work_done;
  4183. }
  4184. static int tg3_poll(struct napi_struct *napi, int budget)
  4185. {
  4186. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  4187. struct tg3 *tp = tnapi->tp;
  4188. int work_done = 0;
  4189. struct tg3_hw_status *sblk = tnapi->hw_status;
  4190. while (1) {
  4191. tg3_poll_link(tp);
  4192. work_done = tg3_poll_work(tnapi, work_done, budget);
  4193. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  4194. goto tx_recovery;
  4195. if (unlikely(work_done >= budget))
  4196. break;
  4197. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  4198. /* tp->last_tag is used in tg3_int_reenable() below
  4199. * to tell the hw how much work has been processed,
  4200. * so we must read it before checking for more work.
  4201. */
  4202. tnapi->last_tag = sblk->status_tag;
  4203. tnapi->last_irq_tag = tnapi->last_tag;
  4204. rmb();
  4205. } else
  4206. sblk->status &= ~SD_STATUS_UPDATED;
  4207. if (likely(!tg3_has_work(tnapi))) {
  4208. napi_complete(napi);
  4209. tg3_int_reenable(tnapi);
  4210. break;
  4211. }
  4212. }
  4213. return work_done;
  4214. tx_recovery:
  4215. /* work_done is guaranteed to be less than budget. */
  4216. napi_complete(napi);
  4217. schedule_work(&tp->reset_task);
  4218. return work_done;
  4219. }
  4220. static void tg3_irq_quiesce(struct tg3 *tp)
  4221. {
  4222. int i;
  4223. BUG_ON(tp->irq_sync);
  4224. tp->irq_sync = 1;
  4225. smp_mb();
  4226. for (i = 0; i < tp->irq_cnt; i++)
  4227. synchronize_irq(tp->napi[i].irq_vec);
  4228. }
  4229. static inline int tg3_irq_sync(struct tg3 *tp)
  4230. {
  4231. return tp->irq_sync;
  4232. }
  4233. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  4234. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  4235. * with as well. Most of the time, this is not necessary except when
  4236. * shutting down the device.
  4237. */
  4238. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  4239. {
  4240. spin_lock_bh(&tp->lock);
  4241. if (irq_sync)
  4242. tg3_irq_quiesce(tp);
  4243. }
  4244. static inline void tg3_full_unlock(struct tg3 *tp)
  4245. {
  4246. spin_unlock_bh(&tp->lock);
  4247. }
  4248. /* One-shot MSI handler - Chip automatically disables interrupt
  4249. * after sending MSI so driver doesn't have to do it.
  4250. */
  4251. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  4252. {
  4253. struct tg3_napi *tnapi = dev_id;
  4254. struct tg3 *tp = tnapi->tp;
  4255. prefetch(tnapi->hw_status);
  4256. if (tnapi->rx_rcb)
  4257. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4258. if (likely(!tg3_irq_sync(tp)))
  4259. napi_schedule(&tnapi->napi);
  4260. return IRQ_HANDLED;
  4261. }
  4262. /* MSI ISR - No need to check for interrupt sharing and no need to
  4263. * flush status block and interrupt mailbox. PCI ordering rules
  4264. * guarantee that MSI will arrive after the status block.
  4265. */
  4266. static irqreturn_t tg3_msi(int irq, void *dev_id)
  4267. {
  4268. struct tg3_napi *tnapi = dev_id;
  4269. struct tg3 *tp = tnapi->tp;
  4270. prefetch(tnapi->hw_status);
  4271. if (tnapi->rx_rcb)
  4272. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4273. /*
  4274. * Writing any value to intr-mbox-0 clears PCI INTA# and
  4275. * chip-internal interrupt pending events.
  4276. * Writing non-zero to intr-mbox-0 additional tells the
  4277. * NIC to stop sending us irqs, engaging "in-intr-handler"
  4278. * event coalescing.
  4279. */
  4280. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  4281. if (likely(!tg3_irq_sync(tp)))
  4282. napi_schedule(&tnapi->napi);
  4283. return IRQ_RETVAL(1);
  4284. }
  4285. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  4286. {
  4287. struct tg3_napi *tnapi = dev_id;
  4288. struct tg3 *tp = tnapi->tp;
  4289. struct tg3_hw_status *sblk = tnapi->hw_status;
  4290. unsigned int handled = 1;
  4291. /* In INTx mode, it is possible for the interrupt to arrive at
  4292. * the CPU before the status block posted prior to the interrupt.
  4293. * Reading the PCI State register will confirm whether the
  4294. * interrupt is ours and will flush the status block.
  4295. */
  4296. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  4297. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  4298. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  4299. handled = 0;
  4300. goto out;
  4301. }
  4302. }
  4303. /*
  4304. * Writing any value to intr-mbox-0 clears PCI INTA# and
  4305. * chip-internal interrupt pending events.
  4306. * Writing non-zero to intr-mbox-0 additional tells the
  4307. * NIC to stop sending us irqs, engaging "in-intr-handler"
  4308. * event coalescing.
  4309. *
  4310. * Flush the mailbox to de-assert the IRQ immediately to prevent
  4311. * spurious interrupts. The flush impacts performance but
  4312. * excessive spurious interrupts can be worse in some cases.
  4313. */
  4314. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  4315. if (tg3_irq_sync(tp))
  4316. goto out;
  4317. sblk->status &= ~SD_STATUS_UPDATED;
  4318. if (likely(tg3_has_work(tnapi))) {
  4319. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4320. napi_schedule(&tnapi->napi);
  4321. } else {
  4322. /* No work, shared interrupt perhaps? re-enable
  4323. * interrupts, and flush that PCI write
  4324. */
  4325. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  4326. 0x00000000);
  4327. }
  4328. out:
  4329. return IRQ_RETVAL(handled);
  4330. }
  4331. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  4332. {
  4333. struct tg3_napi *tnapi = dev_id;
  4334. struct tg3 *tp = tnapi->tp;
  4335. struct tg3_hw_status *sblk = tnapi->hw_status;
  4336. unsigned int handled = 1;
  4337. /* In INTx mode, it is possible for the interrupt to arrive at
  4338. * the CPU before the status block posted prior to the interrupt.
  4339. * Reading the PCI State register will confirm whether the
  4340. * interrupt is ours and will flush the status block.
  4341. */
  4342. if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
  4343. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  4344. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  4345. handled = 0;
  4346. goto out;
  4347. }
  4348. }
  4349. /*
  4350. * writing any value to intr-mbox-0 clears PCI INTA# and
  4351. * chip-internal interrupt pending events.
  4352. * writing non-zero to intr-mbox-0 additional tells the
  4353. * NIC to stop sending us irqs, engaging "in-intr-handler"
  4354. * event coalescing.
  4355. *
  4356. * Flush the mailbox to de-assert the IRQ immediately to prevent
  4357. * spurious interrupts. The flush impacts performance but
  4358. * excessive spurious interrupts can be worse in some cases.
  4359. */
  4360. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  4361. /*
  4362. * In a shared interrupt configuration, sometimes other devices'
  4363. * interrupts will scream. We record the current status tag here
  4364. * so that the above check can report that the screaming interrupts
  4365. * are unhandled. Eventually they will be silenced.
  4366. */
  4367. tnapi->last_irq_tag = sblk->status_tag;
  4368. if (tg3_irq_sync(tp))
  4369. goto out;
  4370. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  4371. napi_schedule(&tnapi->napi);
  4372. out:
  4373. return IRQ_RETVAL(handled);
  4374. }
  4375. /* ISR for interrupt test */
  4376. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  4377. {
  4378. struct tg3_napi *tnapi = dev_id;
  4379. struct tg3 *tp = tnapi->tp;
  4380. struct tg3_hw_status *sblk = tnapi->hw_status;
  4381. if ((sblk->status & SD_STATUS_UPDATED) ||
  4382. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  4383. tg3_disable_ints(tp);
  4384. return IRQ_RETVAL(1);
  4385. }
  4386. return IRQ_RETVAL(0);
  4387. }
  4388. static int tg3_init_hw(struct tg3 *, int);
  4389. static int tg3_halt(struct tg3 *, int, int);
  4390. /* Restart hardware after configuration changes, self-test, etc.
  4391. * Invoked with tp->lock held.
  4392. */
  4393. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  4394. __releases(tp->lock)
  4395. __acquires(tp->lock)
  4396. {
  4397. int err;
  4398. err = tg3_init_hw(tp, reset_phy);
  4399. if (err) {
  4400. printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
  4401. "aborting.\n", tp->dev->name);
  4402. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  4403. tg3_full_unlock(tp);
  4404. del_timer_sync(&tp->timer);
  4405. tp->irq_sync = 0;
  4406. tg3_napi_enable(tp);
  4407. dev_close(tp->dev);
  4408. tg3_full_lock(tp, 0);
  4409. }
  4410. return err;
  4411. }
  4412. #ifdef CONFIG_NET_POLL_CONTROLLER
  4413. static void tg3_poll_controller(struct net_device *dev)
  4414. {
  4415. int i;
  4416. struct tg3 *tp = netdev_priv(dev);
  4417. for (i = 0; i < tp->irq_cnt; i++)
  4418. tg3_interrupt(tp->napi[i].irq_vec, dev);
  4419. }
  4420. #endif
  4421. static void tg3_reset_task(struct work_struct *work)
  4422. {
  4423. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  4424. int err;
  4425. unsigned int restart_timer;
  4426. tg3_full_lock(tp, 0);
  4427. if (!netif_running(tp->dev)) {
  4428. tg3_full_unlock(tp);
  4429. return;
  4430. }
  4431. tg3_full_unlock(tp);
  4432. tg3_phy_stop(tp);
  4433. tg3_netif_stop(tp);
  4434. tg3_full_lock(tp, 1);
  4435. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  4436. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  4437. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  4438. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  4439. tp->write32_rx_mbox = tg3_write_flush_reg32;
  4440. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  4441. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  4442. }
  4443. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  4444. err = tg3_init_hw(tp, 1);
  4445. if (err)
  4446. goto out;
  4447. tg3_netif_start(tp);
  4448. if (restart_timer)
  4449. mod_timer(&tp->timer, jiffies + 1);
  4450. out:
  4451. tg3_full_unlock(tp);
  4452. if (!err)
  4453. tg3_phy_start(tp);
  4454. }
  4455. static void tg3_dump_short_state(struct tg3 *tp)
  4456. {
  4457. printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  4458. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  4459. printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  4460. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  4461. }
  4462. static void tg3_tx_timeout(struct net_device *dev)
  4463. {
  4464. struct tg3 *tp = netdev_priv(dev);
  4465. if (netif_msg_tx_err(tp)) {
  4466. printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  4467. dev->name);
  4468. tg3_dump_short_state(tp);
  4469. }
  4470. schedule_work(&tp->reset_task);
  4471. }
  4472. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  4473. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  4474. {
  4475. u32 base = (u32) mapping & 0xffffffff;
  4476. return ((base > 0xffffdcc0) &&
  4477. (base + len + 8 < base));
  4478. }
  4479. /* Test for DMA addresses > 40-bit */
  4480. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  4481. int len)
  4482. {
  4483. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  4484. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  4485. return (((u64) mapping + len) > DMA_BIT_MASK(40));
  4486. return 0;
  4487. #else
  4488. return 0;
  4489. #endif
  4490. }
  4491. static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
  4492. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  4493. static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
  4494. struct sk_buff *skb, u32 last_plus_one,
  4495. u32 *start, u32 base_flags, u32 mss)
  4496. {
  4497. struct tg3 *tp = tnapi->tp;
  4498. struct sk_buff *new_skb;
  4499. dma_addr_t new_addr = 0;
  4500. u32 entry = *start;
  4501. int i, ret = 0;
  4502. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  4503. new_skb = skb_copy(skb, GFP_ATOMIC);
  4504. else {
  4505. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  4506. new_skb = skb_copy_expand(skb,
  4507. skb_headroom(skb) + more_headroom,
  4508. skb_tailroom(skb), GFP_ATOMIC);
  4509. }
  4510. if (!new_skb) {
  4511. ret = -1;
  4512. } else {
  4513. /* New SKB is guaranteed to be linear. */
  4514. entry = *start;
  4515. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  4516. PCI_DMA_TODEVICE);
  4517. /* Make sure the mapping succeeded */
  4518. if (pci_dma_mapping_error(tp->pdev, new_addr)) {
  4519. ret = -1;
  4520. dev_kfree_skb(new_skb);
  4521. new_skb = NULL;
  4522. /* Make sure new skb does not cross any 4G boundaries.
  4523. * Drop the packet if it does.
  4524. */
  4525. } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
  4526. tg3_4g_overflow_test(new_addr, new_skb->len)) {
  4527. pci_unmap_single(tp->pdev, new_addr, new_skb->len,
  4528. PCI_DMA_TODEVICE);
  4529. ret = -1;
  4530. dev_kfree_skb(new_skb);
  4531. new_skb = NULL;
  4532. } else {
  4533. tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
  4534. base_flags, 1 | (mss << 1));
  4535. *start = NEXT_TX(entry);
  4536. }
  4537. }
  4538. /* Now clean up the sw ring entries. */
  4539. i = 0;
  4540. while (entry != last_plus_one) {
  4541. int len;
  4542. if (i == 0)
  4543. len = skb_headlen(skb);
  4544. else
  4545. len = skb_shinfo(skb)->frags[i-1].size;
  4546. pci_unmap_single(tp->pdev,
  4547. pci_unmap_addr(&tnapi->tx_buffers[entry],
  4548. mapping),
  4549. len, PCI_DMA_TODEVICE);
  4550. if (i == 0) {
  4551. tnapi->tx_buffers[entry].skb = new_skb;
  4552. pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  4553. new_addr);
  4554. } else {
  4555. tnapi->tx_buffers[entry].skb = NULL;
  4556. }
  4557. entry = NEXT_TX(entry);
  4558. i++;
  4559. }
  4560. dev_kfree_skb(skb);
  4561. return ret;
  4562. }
  4563. static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
  4564. dma_addr_t mapping, int len, u32 flags,
  4565. u32 mss_and_is_end)
  4566. {
  4567. struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
  4568. int is_end = (mss_and_is_end & 0x1);
  4569. u32 mss = (mss_and_is_end >> 1);
  4570. u32 vlan_tag = 0;
  4571. if (is_end)
  4572. flags |= TXD_FLAG_END;
  4573. if (flags & TXD_FLAG_VLAN) {
  4574. vlan_tag = flags >> 16;
  4575. flags &= 0xffff;
  4576. }
  4577. vlan_tag |= (mss << TXD_MSS_SHIFT);
  4578. txd->addr_hi = ((u64) mapping >> 32);
  4579. txd->addr_lo = ((u64) mapping & 0xffffffff);
  4580. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  4581. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  4582. }
  4583. /* hard_start_xmit for devices that don't have any bugs and
  4584. * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
  4585. */
  4586. static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
  4587. struct net_device *dev)
  4588. {
  4589. struct tg3 *tp = netdev_priv(dev);
  4590. u32 len, entry, base_flags, mss;
  4591. dma_addr_t mapping;
  4592. struct tg3_napi *tnapi;
  4593. struct netdev_queue *txq;
  4594. unsigned int i, last;
  4595. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  4596. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  4597. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  4598. tnapi++;
  4599. /* We are running in BH disabled context with netif_tx_lock
  4600. * and TX reclaim runs via tp->napi.poll inside of a software
  4601. * interrupt. Furthermore, IRQ processing runs lockless so we have
  4602. * no IRQ context deadlocks to worry about either. Rejoice!
  4603. */
  4604. if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
  4605. if (!netif_tx_queue_stopped(txq)) {
  4606. netif_tx_stop_queue(txq);
  4607. /* This is a hard error, log it. */
  4608. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  4609. "queue awake!\n", dev->name);
  4610. }
  4611. return NETDEV_TX_BUSY;
  4612. }
  4613. entry = tnapi->tx_prod;
  4614. base_flags = 0;
  4615. mss = 0;
  4616. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  4617. int tcp_opt_len, ip_tcp_len;
  4618. u32 hdrlen;
  4619. if (skb_header_cloned(skb) &&
  4620. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  4621. dev_kfree_skb(skb);
  4622. goto out_unlock;
  4623. }
  4624. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  4625. hdrlen = skb_headlen(skb) - ETH_HLEN;
  4626. else {
  4627. struct iphdr *iph = ip_hdr(skb);
  4628. tcp_opt_len = tcp_optlen(skb);
  4629. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  4630. iph->check = 0;
  4631. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  4632. hdrlen = ip_tcp_len + tcp_opt_len;
  4633. }
  4634. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
  4635. mss |= (hdrlen & 0xc) << 12;
  4636. if (hdrlen & 0x10)
  4637. base_flags |= 0x00000010;
  4638. base_flags |= (hdrlen & 0x3e0) << 5;
  4639. } else
  4640. mss |= hdrlen << 9;
  4641. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  4642. TXD_FLAG_CPU_POST_DMA);
  4643. tcp_hdr(skb)->check = 0;
  4644. }
  4645. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  4646. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  4647. #if TG3_VLAN_TAG_USED
  4648. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  4649. base_flags |= (TXD_FLAG_VLAN |
  4650. (vlan_tx_tag_get(skb) << 16));
  4651. #endif
  4652. len = skb_headlen(skb);
  4653. /* Queue skb data, a.k.a. the main skb fragment. */
  4654. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4655. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  4656. dev_kfree_skb(skb);
  4657. goto out_unlock;
  4658. }
  4659. tnapi->tx_buffers[entry].skb = skb;
  4660. pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  4661. if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
  4662. !mss && skb->len > ETH_DATA_LEN)
  4663. base_flags |= TXD_FLAG_JMB_PKT;
  4664. tg3_set_txd(tnapi, entry, mapping, len, base_flags,
  4665. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  4666. entry = NEXT_TX(entry);
  4667. /* Now loop through additional data fragments, and queue them. */
  4668. if (skb_shinfo(skb)->nr_frags > 0) {
  4669. last = skb_shinfo(skb)->nr_frags - 1;
  4670. for (i = 0; i <= last; i++) {
  4671. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4672. len = frag->size;
  4673. mapping = pci_map_page(tp->pdev,
  4674. frag->page,
  4675. frag->page_offset,
  4676. len, PCI_DMA_TODEVICE);
  4677. if (pci_dma_mapping_error(tp->pdev, mapping))
  4678. goto dma_error;
  4679. tnapi->tx_buffers[entry].skb = NULL;
  4680. pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  4681. mapping);
  4682. tg3_set_txd(tnapi, entry, mapping, len,
  4683. base_flags, (i == last) | (mss << 1));
  4684. entry = NEXT_TX(entry);
  4685. }
  4686. }
  4687. /* Packets are ready, update Tx producer idx local and on card. */
  4688. tw32_tx_mbox(tnapi->prodmbox, entry);
  4689. tnapi->tx_prod = entry;
  4690. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  4691. netif_tx_stop_queue(txq);
  4692. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  4693. netif_tx_wake_queue(txq);
  4694. }
  4695. out_unlock:
  4696. mmiowb();
  4697. return NETDEV_TX_OK;
  4698. dma_error:
  4699. last = i;
  4700. entry = tnapi->tx_prod;
  4701. tnapi->tx_buffers[entry].skb = NULL;
  4702. pci_unmap_single(tp->pdev,
  4703. pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
  4704. skb_headlen(skb),
  4705. PCI_DMA_TODEVICE);
  4706. for (i = 0; i <= last; i++) {
  4707. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4708. entry = NEXT_TX(entry);
  4709. pci_unmap_page(tp->pdev,
  4710. pci_unmap_addr(&tnapi->tx_buffers[entry],
  4711. mapping),
  4712. frag->size, PCI_DMA_TODEVICE);
  4713. }
  4714. dev_kfree_skb(skb);
  4715. return NETDEV_TX_OK;
  4716. }
  4717. static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
  4718. struct net_device *);
  4719. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  4720. * TSO header is greater than 80 bytes.
  4721. */
  4722. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  4723. {
  4724. struct sk_buff *segs, *nskb;
  4725. u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
  4726. /* Estimate the number of fragments in the worst case */
  4727. if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
  4728. netif_stop_queue(tp->dev);
  4729. if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
  4730. return NETDEV_TX_BUSY;
  4731. netif_wake_queue(tp->dev);
  4732. }
  4733. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  4734. if (IS_ERR(segs))
  4735. goto tg3_tso_bug_end;
  4736. do {
  4737. nskb = segs;
  4738. segs = segs->next;
  4739. nskb->next = NULL;
  4740. tg3_start_xmit_dma_bug(nskb, tp->dev);
  4741. } while (segs);
  4742. tg3_tso_bug_end:
  4743. dev_kfree_skb(skb);
  4744. return NETDEV_TX_OK;
  4745. }
  4746. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  4747. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  4748. */
  4749. static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
  4750. struct net_device *dev)
  4751. {
  4752. struct tg3 *tp = netdev_priv(dev);
  4753. u32 len, entry, base_flags, mss;
  4754. int would_hit_hwbug;
  4755. dma_addr_t mapping;
  4756. struct tg3_napi *tnapi;
  4757. struct netdev_queue *txq;
  4758. unsigned int i, last;
  4759. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  4760. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  4761. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  4762. tnapi++;
  4763. /* We are running in BH disabled context with netif_tx_lock
  4764. * and TX reclaim runs via tp->napi.poll inside of a software
  4765. * interrupt. Furthermore, IRQ processing runs lockless so we have
  4766. * no IRQ context deadlocks to worry about either. Rejoice!
  4767. */
  4768. if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
  4769. if (!netif_tx_queue_stopped(txq)) {
  4770. netif_tx_stop_queue(txq);
  4771. /* This is a hard error, log it. */
  4772. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  4773. "queue awake!\n", dev->name);
  4774. }
  4775. return NETDEV_TX_BUSY;
  4776. }
  4777. entry = tnapi->tx_prod;
  4778. base_flags = 0;
  4779. if (skb->ip_summed == CHECKSUM_PARTIAL)
  4780. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  4781. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  4782. struct iphdr *iph;
  4783. u32 tcp_opt_len, ip_tcp_len, hdr_len;
  4784. if (skb_header_cloned(skb) &&
  4785. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  4786. dev_kfree_skb(skb);
  4787. goto out_unlock;
  4788. }
  4789. tcp_opt_len = tcp_optlen(skb);
  4790. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  4791. hdr_len = ip_tcp_len + tcp_opt_len;
  4792. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  4793. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  4794. return (tg3_tso_bug(tp, skb));
  4795. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  4796. TXD_FLAG_CPU_POST_DMA);
  4797. iph = ip_hdr(skb);
  4798. iph->check = 0;
  4799. iph->tot_len = htons(mss + hdr_len);
  4800. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  4801. tcp_hdr(skb)->check = 0;
  4802. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  4803. } else
  4804. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  4805. iph->daddr, 0,
  4806. IPPROTO_TCP,
  4807. 0);
  4808. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
  4809. mss |= (hdr_len & 0xc) << 12;
  4810. if (hdr_len & 0x10)
  4811. base_flags |= 0x00000010;
  4812. base_flags |= (hdr_len & 0x3e0) << 5;
  4813. } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
  4814. mss |= hdr_len << 9;
  4815. else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
  4816. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4817. if (tcp_opt_len || iph->ihl > 5) {
  4818. int tsflags;
  4819. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  4820. mss |= (tsflags << 11);
  4821. }
  4822. } else {
  4823. if (tcp_opt_len || iph->ihl > 5) {
  4824. int tsflags;
  4825. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  4826. base_flags |= tsflags << 12;
  4827. }
  4828. }
  4829. }
  4830. #if TG3_VLAN_TAG_USED
  4831. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  4832. base_flags |= (TXD_FLAG_VLAN |
  4833. (vlan_tx_tag_get(skb) << 16));
  4834. #endif
  4835. if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
  4836. !mss && skb->len > ETH_DATA_LEN)
  4837. base_flags |= TXD_FLAG_JMB_PKT;
  4838. len = skb_headlen(skb);
  4839. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  4840. if (pci_dma_mapping_error(tp->pdev, mapping)) {
  4841. dev_kfree_skb(skb);
  4842. goto out_unlock;
  4843. }
  4844. tnapi->tx_buffers[entry].skb = skb;
  4845. pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  4846. would_hit_hwbug = 0;
  4847. if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
  4848. would_hit_hwbug = 1;
  4849. if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
  4850. tg3_4g_overflow_test(mapping, len))
  4851. would_hit_hwbug = 1;
  4852. if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
  4853. tg3_40bit_overflow_test(tp, mapping, len))
  4854. would_hit_hwbug = 1;
  4855. if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
  4856. would_hit_hwbug = 1;
  4857. tg3_set_txd(tnapi, entry, mapping, len, base_flags,
  4858. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  4859. entry = NEXT_TX(entry);
  4860. /* Now loop through additional data fragments, and queue them. */
  4861. if (skb_shinfo(skb)->nr_frags > 0) {
  4862. last = skb_shinfo(skb)->nr_frags - 1;
  4863. for (i = 0; i <= last; i++) {
  4864. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4865. len = frag->size;
  4866. mapping = pci_map_page(tp->pdev,
  4867. frag->page,
  4868. frag->page_offset,
  4869. len, PCI_DMA_TODEVICE);
  4870. tnapi->tx_buffers[entry].skb = NULL;
  4871. pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  4872. mapping);
  4873. if (pci_dma_mapping_error(tp->pdev, mapping))
  4874. goto dma_error;
  4875. if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
  4876. len <= 8)
  4877. would_hit_hwbug = 1;
  4878. if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
  4879. tg3_4g_overflow_test(mapping, len))
  4880. would_hit_hwbug = 1;
  4881. if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
  4882. tg3_40bit_overflow_test(tp, mapping, len))
  4883. would_hit_hwbug = 1;
  4884. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  4885. tg3_set_txd(tnapi, entry, mapping, len,
  4886. base_flags, (i == last)|(mss << 1));
  4887. else
  4888. tg3_set_txd(tnapi, entry, mapping, len,
  4889. base_flags, (i == last));
  4890. entry = NEXT_TX(entry);
  4891. }
  4892. }
  4893. if (would_hit_hwbug) {
  4894. u32 last_plus_one = entry;
  4895. u32 start;
  4896. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  4897. start &= (TG3_TX_RING_SIZE - 1);
  4898. /* If the workaround fails due to memory/mapping
  4899. * failure, silently drop this packet.
  4900. */
  4901. if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
  4902. &start, base_flags, mss))
  4903. goto out_unlock;
  4904. entry = start;
  4905. }
  4906. /* Packets are ready, update Tx producer idx local and on card. */
  4907. tw32_tx_mbox(tnapi->prodmbox, entry);
  4908. tnapi->tx_prod = entry;
  4909. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  4910. netif_tx_stop_queue(txq);
  4911. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  4912. netif_tx_wake_queue(txq);
  4913. }
  4914. out_unlock:
  4915. mmiowb();
  4916. return NETDEV_TX_OK;
  4917. dma_error:
  4918. last = i;
  4919. entry = tnapi->tx_prod;
  4920. tnapi->tx_buffers[entry].skb = NULL;
  4921. pci_unmap_single(tp->pdev,
  4922. pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
  4923. skb_headlen(skb),
  4924. PCI_DMA_TODEVICE);
  4925. for (i = 0; i <= last; i++) {
  4926. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  4927. entry = NEXT_TX(entry);
  4928. pci_unmap_page(tp->pdev,
  4929. pci_unmap_addr(&tnapi->tx_buffers[entry],
  4930. mapping),
  4931. frag->size, PCI_DMA_TODEVICE);
  4932. }
  4933. dev_kfree_skb(skb);
  4934. return NETDEV_TX_OK;
  4935. }
  4936. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  4937. int new_mtu)
  4938. {
  4939. dev->mtu = new_mtu;
  4940. if (new_mtu > ETH_DATA_LEN) {
  4941. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4942. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  4943. ethtool_op_set_tso(dev, 0);
  4944. }
  4945. else
  4946. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  4947. } else {
  4948. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  4949. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  4950. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  4951. }
  4952. }
  4953. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  4954. {
  4955. struct tg3 *tp = netdev_priv(dev);
  4956. int err;
  4957. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  4958. return -EINVAL;
  4959. if (!netif_running(dev)) {
  4960. /* We'll just catch it later when the
  4961. * device is up'd.
  4962. */
  4963. tg3_set_mtu(dev, tp, new_mtu);
  4964. return 0;
  4965. }
  4966. tg3_phy_stop(tp);
  4967. tg3_netif_stop(tp);
  4968. tg3_full_lock(tp, 1);
  4969. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  4970. tg3_set_mtu(dev, tp, new_mtu);
  4971. err = tg3_restart_hw(tp, 0);
  4972. if (!err)
  4973. tg3_netif_start(tp);
  4974. tg3_full_unlock(tp);
  4975. if (!err)
  4976. tg3_phy_start(tp);
  4977. return err;
  4978. }
  4979. static void tg3_rx_prodring_free(struct tg3 *tp,
  4980. struct tg3_rx_prodring_set *tpr)
  4981. {
  4982. int i;
  4983. if (tpr != &tp->prodring[0]) {
  4984. for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
  4985. i = (i + 1) % TG3_RX_RING_SIZE)
  4986. tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
  4987. tp->rx_pkt_map_sz);
  4988. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  4989. for (i = tpr->rx_jmb_cons_idx;
  4990. i != tpr->rx_jmb_prod_idx;
  4991. i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
  4992. tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
  4993. TG3_RX_JMB_MAP_SZ);
  4994. }
  4995. }
  4996. return;
  4997. }
  4998. for (i = 0; i < TG3_RX_RING_SIZE; i++)
  4999. tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
  5000. tp->rx_pkt_map_sz);
  5001. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  5002. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
  5003. tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
  5004. TG3_RX_JMB_MAP_SZ);
  5005. }
  5006. }
  5007. /* Initialize tx/rx rings for packet processing.
  5008. *
  5009. * The chip has been shut down and the driver detached from
  5010. * the networking, so no interrupts or new tx packets will
  5011. * end up in the driver. tp->{tx,}lock are held and thus
  5012. * we may not sleep.
  5013. */
  5014. static int tg3_rx_prodring_alloc(struct tg3 *tp,
  5015. struct tg3_rx_prodring_set *tpr)
  5016. {
  5017. u32 i, rx_pkt_dma_sz;
  5018. tpr->rx_std_cons_idx = 0;
  5019. tpr->rx_std_prod_idx = 0;
  5020. tpr->rx_jmb_cons_idx = 0;
  5021. tpr->rx_jmb_prod_idx = 0;
  5022. if (tpr != &tp->prodring[0]) {
  5023. memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
  5024. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
  5025. memset(&tpr->rx_jmb_buffers[0], 0,
  5026. TG3_RX_JMB_BUFF_RING_SIZE);
  5027. goto done;
  5028. }
  5029. /* Zero out all descriptors. */
  5030. memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
  5031. rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
  5032. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  5033. tp->dev->mtu > ETH_DATA_LEN)
  5034. rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
  5035. tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
  5036. /* Initialize invariants of the rings, we only set this
  5037. * stuff once. This works because the card does not
  5038. * write into the rx buffer posting rings.
  5039. */
  5040. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  5041. struct tg3_rx_buffer_desc *rxd;
  5042. rxd = &tpr->rx_std[i];
  5043. rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
  5044. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  5045. rxd->opaque = (RXD_OPAQUE_RING_STD |
  5046. (i << RXD_OPAQUE_INDEX_SHIFT));
  5047. }
  5048. /* Now allocate fresh SKBs for each rx ring. */
  5049. for (i = 0; i < tp->rx_pending; i++) {
  5050. if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
  5051. printk(KERN_WARNING PFX
  5052. "%s: Using a smaller RX standard ring, "
  5053. "only %d out of %d buffers were allocated "
  5054. "successfully.\n",
  5055. tp->dev->name, i, tp->rx_pending);
  5056. if (i == 0)
  5057. goto initfail;
  5058. tp->rx_pending = i;
  5059. break;
  5060. }
  5061. }
  5062. if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
  5063. goto done;
  5064. memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
  5065. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  5066. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  5067. struct tg3_rx_buffer_desc *rxd;
  5068. rxd = &tpr->rx_jmb[i].std;
  5069. rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
  5070. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  5071. RXD_FLAG_JUMBO;
  5072. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  5073. (i << RXD_OPAQUE_INDEX_SHIFT));
  5074. }
  5075. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  5076. if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
  5077. i) < 0) {
  5078. printk(KERN_WARNING PFX
  5079. "%s: Using a smaller RX jumbo ring, "
  5080. "only %d out of %d buffers were "
  5081. "allocated successfully.\n",
  5082. tp->dev->name, i, tp->rx_jumbo_pending);
  5083. if (i == 0)
  5084. goto initfail;
  5085. tp->rx_jumbo_pending = i;
  5086. break;
  5087. }
  5088. }
  5089. }
  5090. done:
  5091. return 0;
  5092. initfail:
  5093. tg3_rx_prodring_free(tp, tpr);
  5094. return -ENOMEM;
  5095. }
  5096. static void tg3_rx_prodring_fini(struct tg3 *tp,
  5097. struct tg3_rx_prodring_set *tpr)
  5098. {
  5099. kfree(tpr->rx_std_buffers);
  5100. tpr->rx_std_buffers = NULL;
  5101. kfree(tpr->rx_jmb_buffers);
  5102. tpr->rx_jmb_buffers = NULL;
  5103. if (tpr->rx_std) {
  5104. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  5105. tpr->rx_std, tpr->rx_std_mapping);
  5106. tpr->rx_std = NULL;
  5107. }
  5108. if (tpr->rx_jmb) {
  5109. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  5110. tpr->rx_jmb, tpr->rx_jmb_mapping);
  5111. tpr->rx_jmb = NULL;
  5112. }
  5113. }
  5114. static int tg3_rx_prodring_init(struct tg3 *tp,
  5115. struct tg3_rx_prodring_set *tpr)
  5116. {
  5117. tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
  5118. if (!tpr->rx_std_buffers)
  5119. return -ENOMEM;
  5120. tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  5121. &tpr->rx_std_mapping);
  5122. if (!tpr->rx_std)
  5123. goto err_out;
  5124. if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
  5125. tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
  5126. GFP_KERNEL);
  5127. if (!tpr->rx_jmb_buffers)
  5128. goto err_out;
  5129. tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
  5130. TG3_RX_JUMBO_RING_BYTES,
  5131. &tpr->rx_jmb_mapping);
  5132. if (!tpr->rx_jmb)
  5133. goto err_out;
  5134. }
  5135. return 0;
  5136. err_out:
  5137. tg3_rx_prodring_fini(tp, tpr);
  5138. return -ENOMEM;
  5139. }
  5140. /* Free up pending packets in all rx/tx rings.
  5141. *
  5142. * The chip has been shut down and the driver detached from
  5143. * the networking, so no interrupts or new tx packets will
  5144. * end up in the driver. tp->{tx,}lock is not held and we are not
  5145. * in an interrupt context and thus may sleep.
  5146. */
  5147. static void tg3_free_rings(struct tg3 *tp)
  5148. {
  5149. int i, j;
  5150. for (j = 0; j < tp->irq_cnt; j++) {
  5151. struct tg3_napi *tnapi = &tp->napi[j];
  5152. if (!tnapi->tx_buffers)
  5153. continue;
  5154. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  5155. struct ring_info *txp;
  5156. struct sk_buff *skb;
  5157. unsigned int k;
  5158. txp = &tnapi->tx_buffers[i];
  5159. skb = txp->skb;
  5160. if (skb == NULL) {
  5161. i++;
  5162. continue;
  5163. }
  5164. pci_unmap_single(tp->pdev,
  5165. pci_unmap_addr(txp, mapping),
  5166. skb_headlen(skb),
  5167. PCI_DMA_TODEVICE);
  5168. txp->skb = NULL;
  5169. i++;
  5170. for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
  5171. txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  5172. pci_unmap_page(tp->pdev,
  5173. pci_unmap_addr(txp, mapping),
  5174. skb_shinfo(skb)->frags[k].size,
  5175. PCI_DMA_TODEVICE);
  5176. i++;
  5177. }
  5178. dev_kfree_skb_any(skb);
  5179. }
  5180. tg3_rx_prodring_free(tp, &tp->prodring[j]);
  5181. }
  5182. }
  5183. /* Initialize tx/rx rings for packet processing.
  5184. *
  5185. * The chip has been shut down and the driver detached from
  5186. * the networking, so no interrupts or new tx packets will
  5187. * end up in the driver. tp->{tx,}lock are held and thus
  5188. * we may not sleep.
  5189. */
  5190. static int tg3_init_rings(struct tg3 *tp)
  5191. {
  5192. int i;
  5193. /* Free up all the SKBs. */
  5194. tg3_free_rings(tp);
  5195. for (i = 0; i < tp->irq_cnt; i++) {
  5196. struct tg3_napi *tnapi = &tp->napi[i];
  5197. tnapi->last_tag = 0;
  5198. tnapi->last_irq_tag = 0;
  5199. tnapi->hw_status->status = 0;
  5200. tnapi->hw_status->status_tag = 0;
  5201. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  5202. tnapi->tx_prod = 0;
  5203. tnapi->tx_cons = 0;
  5204. if (tnapi->tx_ring)
  5205. memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
  5206. tnapi->rx_rcb_ptr = 0;
  5207. if (tnapi->rx_rcb)
  5208. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  5209. if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
  5210. tg3_free_rings(tp);
  5211. return -ENOMEM;
  5212. }
  5213. }
  5214. return 0;
  5215. }
  5216. /*
  5217. * Must not be invoked with interrupt sources disabled and
  5218. * the hardware shutdown down.
  5219. */
  5220. static void tg3_free_consistent(struct tg3 *tp)
  5221. {
  5222. int i;
  5223. for (i = 0; i < tp->irq_cnt; i++) {
  5224. struct tg3_napi *tnapi = &tp->napi[i];
  5225. if (tnapi->tx_ring) {
  5226. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  5227. tnapi->tx_ring, tnapi->tx_desc_mapping);
  5228. tnapi->tx_ring = NULL;
  5229. }
  5230. kfree(tnapi->tx_buffers);
  5231. tnapi->tx_buffers = NULL;
  5232. if (tnapi->rx_rcb) {
  5233. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  5234. tnapi->rx_rcb,
  5235. tnapi->rx_rcb_mapping);
  5236. tnapi->rx_rcb = NULL;
  5237. }
  5238. if (tnapi->hw_status) {
  5239. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  5240. tnapi->hw_status,
  5241. tnapi->status_mapping);
  5242. tnapi->hw_status = NULL;
  5243. }
  5244. }
  5245. if (tp->hw_stats) {
  5246. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  5247. tp->hw_stats, tp->stats_mapping);
  5248. tp->hw_stats = NULL;
  5249. }
  5250. for (i = 0; i < tp->irq_cnt; i++)
  5251. tg3_rx_prodring_fini(tp, &tp->prodring[i]);
  5252. }
  5253. /*
  5254. * Must not be invoked with interrupt sources disabled and
  5255. * the hardware shutdown down. Can sleep.
  5256. */
  5257. static int tg3_alloc_consistent(struct tg3 *tp)
  5258. {
  5259. int i;
  5260. for (i = 0; i < tp->irq_cnt; i++) {
  5261. if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
  5262. goto err_out;
  5263. }
  5264. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  5265. sizeof(struct tg3_hw_stats),
  5266. &tp->stats_mapping);
  5267. if (!tp->hw_stats)
  5268. goto err_out;
  5269. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  5270. for (i = 0; i < tp->irq_cnt; i++) {
  5271. struct tg3_napi *tnapi = &tp->napi[i];
  5272. struct tg3_hw_status *sblk;
  5273. tnapi->hw_status = pci_alloc_consistent(tp->pdev,
  5274. TG3_HW_STATUS_SIZE,
  5275. &tnapi->status_mapping);
  5276. if (!tnapi->hw_status)
  5277. goto err_out;
  5278. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  5279. sblk = tnapi->hw_status;
  5280. /* If multivector TSS is enabled, vector 0 does not handle
  5281. * tx interrupts. Don't allocate any resources for it.
  5282. */
  5283. if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
  5284. (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
  5285. tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
  5286. TG3_TX_RING_SIZE,
  5287. GFP_KERNEL);
  5288. if (!tnapi->tx_buffers)
  5289. goto err_out;
  5290. tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
  5291. TG3_TX_RING_BYTES,
  5292. &tnapi->tx_desc_mapping);
  5293. if (!tnapi->tx_ring)
  5294. goto err_out;
  5295. }
  5296. /*
  5297. * When RSS is enabled, the status block format changes
  5298. * slightly. The "rx_jumbo_consumer", "reserved",
  5299. * and "rx_mini_consumer" members get mapped to the
  5300. * other three rx return ring producer indexes.
  5301. */
  5302. switch (i) {
  5303. default:
  5304. tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
  5305. break;
  5306. case 2:
  5307. tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
  5308. break;
  5309. case 3:
  5310. tnapi->rx_rcb_prod_idx = &sblk->reserved;
  5311. break;
  5312. case 4:
  5313. tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
  5314. break;
  5315. }
  5316. tnapi->prodring = &tp->prodring[i];
  5317. /*
  5318. * If multivector RSS is enabled, vector 0 does not handle
  5319. * rx or tx interrupts. Don't allocate any resources for it.
  5320. */
  5321. if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
  5322. continue;
  5323. tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
  5324. TG3_RX_RCB_RING_BYTES(tp),
  5325. &tnapi->rx_rcb_mapping);
  5326. if (!tnapi->rx_rcb)
  5327. goto err_out;
  5328. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  5329. }
  5330. return 0;
  5331. err_out:
  5332. tg3_free_consistent(tp);
  5333. return -ENOMEM;
  5334. }
  5335. #define MAX_WAIT_CNT 1000
  5336. /* To stop a block, clear the enable bit and poll till it
  5337. * clears. tp->lock is held.
  5338. */
  5339. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  5340. {
  5341. unsigned int i;
  5342. u32 val;
  5343. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  5344. switch (ofs) {
  5345. case RCVLSC_MODE:
  5346. case DMAC_MODE:
  5347. case MBFREE_MODE:
  5348. case BUFMGR_MODE:
  5349. case MEMARB_MODE:
  5350. /* We can't enable/disable these bits of the
  5351. * 5705/5750, just say success.
  5352. */
  5353. return 0;
  5354. default:
  5355. break;
  5356. }
  5357. }
  5358. val = tr32(ofs);
  5359. val &= ~enable_bit;
  5360. tw32_f(ofs, val);
  5361. for (i = 0; i < MAX_WAIT_CNT; i++) {
  5362. udelay(100);
  5363. val = tr32(ofs);
  5364. if ((val & enable_bit) == 0)
  5365. break;
  5366. }
  5367. if (i == MAX_WAIT_CNT && !silent) {
  5368. printk(KERN_ERR PFX "tg3_stop_block timed out, "
  5369. "ofs=%lx enable_bit=%x\n",
  5370. ofs, enable_bit);
  5371. return -ENODEV;
  5372. }
  5373. return 0;
  5374. }
  5375. /* tp->lock is held. */
  5376. static int tg3_abort_hw(struct tg3 *tp, int silent)
  5377. {
  5378. int i, err;
  5379. tg3_disable_ints(tp);
  5380. tp->rx_mode &= ~RX_MODE_ENABLE;
  5381. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5382. udelay(10);
  5383. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  5384. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  5385. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  5386. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  5387. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  5388. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  5389. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  5390. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  5391. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  5392. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  5393. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  5394. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  5395. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  5396. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  5397. tw32_f(MAC_MODE, tp->mac_mode);
  5398. udelay(40);
  5399. tp->tx_mode &= ~TX_MODE_ENABLE;
  5400. tw32_f(MAC_TX_MODE, tp->tx_mode);
  5401. for (i = 0; i < MAX_WAIT_CNT; i++) {
  5402. udelay(100);
  5403. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  5404. break;
  5405. }
  5406. if (i >= MAX_WAIT_CNT) {
  5407. printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  5408. "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  5409. tp->dev->name, tr32(MAC_TX_MODE));
  5410. err |= -ENODEV;
  5411. }
  5412. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  5413. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  5414. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  5415. tw32(FTQ_RESET, 0xffffffff);
  5416. tw32(FTQ_RESET, 0x00000000);
  5417. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  5418. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  5419. for (i = 0; i < tp->irq_cnt; i++) {
  5420. struct tg3_napi *tnapi = &tp->napi[i];
  5421. if (tnapi->hw_status)
  5422. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  5423. }
  5424. if (tp->hw_stats)
  5425. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  5426. return err;
  5427. }
  5428. static void tg3_ape_send_event(struct tg3 *tp, u32 event)
  5429. {
  5430. int i;
  5431. u32 apedata;
  5432. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  5433. if (apedata != APE_SEG_SIG_MAGIC)
  5434. return;
  5435. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  5436. if (!(apedata & APE_FW_STATUS_READY))
  5437. return;
  5438. /* Wait for up to 1 millisecond for APE to service previous event. */
  5439. for (i = 0; i < 10; i++) {
  5440. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  5441. return;
  5442. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  5443. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  5444. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  5445. event | APE_EVENT_STATUS_EVENT_PENDING);
  5446. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  5447. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  5448. break;
  5449. udelay(100);
  5450. }
  5451. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  5452. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  5453. }
  5454. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  5455. {
  5456. u32 event;
  5457. u32 apedata;
  5458. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  5459. return;
  5460. switch (kind) {
  5461. case RESET_KIND_INIT:
  5462. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  5463. APE_HOST_SEG_SIG_MAGIC);
  5464. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  5465. APE_HOST_SEG_LEN_MAGIC);
  5466. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  5467. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  5468. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  5469. APE_HOST_DRIVER_ID_MAGIC);
  5470. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  5471. APE_HOST_BEHAV_NO_PHYLOCK);
  5472. event = APE_EVENT_STATUS_STATE_START;
  5473. break;
  5474. case RESET_KIND_SHUTDOWN:
  5475. /* With the interface we are currently using,
  5476. * APE does not track driver state. Wiping
  5477. * out the HOST SEGMENT SIGNATURE forces
  5478. * the APE to assume OS absent status.
  5479. */
  5480. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
  5481. event = APE_EVENT_STATUS_STATE_UNLOAD;
  5482. break;
  5483. case RESET_KIND_SUSPEND:
  5484. event = APE_EVENT_STATUS_STATE_SUSPEND;
  5485. break;
  5486. default:
  5487. return;
  5488. }
  5489. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  5490. tg3_ape_send_event(tp, event);
  5491. }
  5492. /* tp->lock is held. */
  5493. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  5494. {
  5495. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  5496. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  5497. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  5498. switch (kind) {
  5499. case RESET_KIND_INIT:
  5500. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5501. DRV_STATE_START);
  5502. break;
  5503. case RESET_KIND_SHUTDOWN:
  5504. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5505. DRV_STATE_UNLOAD);
  5506. break;
  5507. case RESET_KIND_SUSPEND:
  5508. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5509. DRV_STATE_SUSPEND);
  5510. break;
  5511. default:
  5512. break;
  5513. }
  5514. }
  5515. if (kind == RESET_KIND_INIT ||
  5516. kind == RESET_KIND_SUSPEND)
  5517. tg3_ape_driver_state_change(tp, kind);
  5518. }
  5519. /* tp->lock is held. */
  5520. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  5521. {
  5522. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  5523. switch (kind) {
  5524. case RESET_KIND_INIT:
  5525. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5526. DRV_STATE_START_DONE);
  5527. break;
  5528. case RESET_KIND_SHUTDOWN:
  5529. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5530. DRV_STATE_UNLOAD_DONE);
  5531. break;
  5532. default:
  5533. break;
  5534. }
  5535. }
  5536. if (kind == RESET_KIND_SHUTDOWN)
  5537. tg3_ape_driver_state_change(tp, kind);
  5538. }
  5539. /* tp->lock is held. */
  5540. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  5541. {
  5542. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5543. switch (kind) {
  5544. case RESET_KIND_INIT:
  5545. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5546. DRV_STATE_START);
  5547. break;
  5548. case RESET_KIND_SHUTDOWN:
  5549. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5550. DRV_STATE_UNLOAD);
  5551. break;
  5552. case RESET_KIND_SUSPEND:
  5553. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  5554. DRV_STATE_SUSPEND);
  5555. break;
  5556. default:
  5557. break;
  5558. }
  5559. }
  5560. }
  5561. static int tg3_poll_fw(struct tg3 *tp)
  5562. {
  5563. int i;
  5564. u32 val;
  5565. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5566. /* Wait up to 20ms for init done. */
  5567. for (i = 0; i < 200; i++) {
  5568. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  5569. return 0;
  5570. udelay(100);
  5571. }
  5572. return -ENODEV;
  5573. }
  5574. /* Wait for firmware initialization to complete. */
  5575. for (i = 0; i < 100000; i++) {
  5576. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  5577. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  5578. break;
  5579. udelay(10);
  5580. }
  5581. /* Chip might not be fitted with firmware. Some Sun onboard
  5582. * parts are configured like that. So don't signal the timeout
  5583. * of the above loop as an error, but do report the lack of
  5584. * running firmware once.
  5585. */
  5586. if (i >= 100000 &&
  5587. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  5588. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  5589. printk(KERN_INFO PFX "%s: No firmware running.\n",
  5590. tp->dev->name);
  5591. }
  5592. if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
  5593. /* The 57765 A0 needs a little more
  5594. * time to do some important work.
  5595. */
  5596. mdelay(10);
  5597. }
  5598. return 0;
  5599. }
  5600. /* Save PCI command register before chip reset */
  5601. static void tg3_save_pci_state(struct tg3 *tp)
  5602. {
  5603. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  5604. }
  5605. /* Restore PCI state after chip reset */
  5606. static void tg3_restore_pci_state(struct tg3 *tp)
  5607. {
  5608. u32 val;
  5609. /* Re-enable indirect register accesses. */
  5610. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  5611. tp->misc_host_ctrl);
  5612. /* Set MAX PCI retry to zero. */
  5613. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  5614. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  5615. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  5616. val |= PCISTATE_RETRY_SAME_DMA;
  5617. /* Allow reads and writes to the APE register and memory space. */
  5618. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  5619. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  5620. PCISTATE_ALLOW_APE_SHMEM_WR;
  5621. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  5622. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  5623. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
  5624. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  5625. pcie_set_readrq(tp->pdev, 4096);
  5626. else {
  5627. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  5628. tp->pci_cacheline_sz);
  5629. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  5630. tp->pci_lat_timer);
  5631. }
  5632. }
  5633. /* Make sure PCI-X relaxed ordering bit is clear. */
  5634. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  5635. u16 pcix_cmd;
  5636. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  5637. &pcix_cmd);
  5638. pcix_cmd &= ~PCI_X_CMD_ERO;
  5639. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  5640. pcix_cmd);
  5641. }
  5642. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  5643. /* Chip reset on 5780 will reset MSI enable bit,
  5644. * so need to restore it.
  5645. */
  5646. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  5647. u16 ctrl;
  5648. pci_read_config_word(tp->pdev,
  5649. tp->msi_cap + PCI_MSI_FLAGS,
  5650. &ctrl);
  5651. pci_write_config_word(tp->pdev,
  5652. tp->msi_cap + PCI_MSI_FLAGS,
  5653. ctrl | PCI_MSI_FLAGS_ENABLE);
  5654. val = tr32(MSGINT_MODE);
  5655. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  5656. }
  5657. }
  5658. }
  5659. static void tg3_stop_fw(struct tg3 *);
  5660. /* tp->lock is held. */
  5661. static int tg3_chip_reset(struct tg3 *tp)
  5662. {
  5663. u32 val;
  5664. void (*write_op)(struct tg3 *, u32, u32);
  5665. int i, err;
  5666. tg3_nvram_lock(tp);
  5667. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  5668. /* No matching tg3_nvram_unlock() after this because
  5669. * chip reset below will undo the nvram lock.
  5670. */
  5671. tp->nvram_lock_cnt = 0;
  5672. /* GRC_MISC_CFG core clock reset will clear the memory
  5673. * enable bit in PCI register 4 and the MSI enable bit
  5674. * on some chips, so we save relevant registers here.
  5675. */
  5676. tg3_save_pci_state(tp);
  5677. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  5678. (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
  5679. tw32(GRC_FASTBOOT_PC, 0);
  5680. /*
  5681. * We must avoid the readl() that normally takes place.
  5682. * It locks machines, causes machine checks, and other
  5683. * fun things. So, temporarily disable the 5701
  5684. * hardware workaround, while we do the reset.
  5685. */
  5686. write_op = tp->write32;
  5687. if (write_op == tg3_write_flush_reg32)
  5688. tp->write32 = tg3_write32;
  5689. /* Prevent the irq handler from reading or writing PCI registers
  5690. * during chip reset when the memory enable bit in the PCI command
  5691. * register may be cleared. The chip does not generate interrupt
  5692. * at this time, but the irq handler may still be called due to irq
  5693. * sharing or irqpoll.
  5694. */
  5695. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  5696. for (i = 0; i < tp->irq_cnt; i++) {
  5697. struct tg3_napi *tnapi = &tp->napi[i];
  5698. if (tnapi->hw_status) {
  5699. tnapi->hw_status->status = 0;
  5700. tnapi->hw_status->status_tag = 0;
  5701. }
  5702. tnapi->last_tag = 0;
  5703. tnapi->last_irq_tag = 0;
  5704. }
  5705. smp_mb();
  5706. for (i = 0; i < tp->irq_cnt; i++)
  5707. synchronize_irq(tp->napi[i].irq_vec);
  5708. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  5709. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  5710. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  5711. }
  5712. /* do the reset */
  5713. val = GRC_MISC_CFG_CORECLK_RESET;
  5714. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  5715. if (tr32(0x7e2c) == 0x60) {
  5716. tw32(0x7e2c, 0x20);
  5717. }
  5718. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  5719. tw32(GRC_MISC_CFG, (1 << 29));
  5720. val |= (1 << 29);
  5721. }
  5722. }
  5723. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5724. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  5725. tw32(GRC_VCPU_EXT_CTRL,
  5726. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  5727. }
  5728. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  5729. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  5730. tw32(GRC_MISC_CFG, val);
  5731. /* restore 5701 hardware bug workaround write method */
  5732. tp->write32 = write_op;
  5733. /* Unfortunately, we have to delay before the PCI read back.
  5734. * Some 575X chips even will not respond to a PCI cfg access
  5735. * when the reset command is given to the chip.
  5736. *
  5737. * How do these hardware designers expect things to work
  5738. * properly if the PCI write is posted for a long period
  5739. * of time? It is always necessary to have some method by
  5740. * which a register read back can occur to push the write
  5741. * out which does the reset.
  5742. *
  5743. * For most tg3 variants the trick below was working.
  5744. * Ho hum...
  5745. */
  5746. udelay(120);
  5747. /* Flush PCI posted writes. The normal MMIO registers
  5748. * are inaccessible at this time so this is the only
  5749. * way to make this reliably (actually, this is no longer
  5750. * the case, see above). I tried to use indirect
  5751. * register read/write but this upset some 5701 variants.
  5752. */
  5753. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  5754. udelay(120);
  5755. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
  5756. u16 val16;
  5757. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  5758. int i;
  5759. u32 cfg_val;
  5760. /* Wait for link training to complete. */
  5761. for (i = 0; i < 5000; i++)
  5762. udelay(100);
  5763. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  5764. pci_write_config_dword(tp->pdev, 0xc4,
  5765. cfg_val | (1 << 15));
  5766. }
  5767. /* Clear the "no snoop" and "relaxed ordering" bits. */
  5768. pci_read_config_word(tp->pdev,
  5769. tp->pcie_cap + PCI_EXP_DEVCTL,
  5770. &val16);
  5771. val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
  5772. PCI_EXP_DEVCTL_NOSNOOP_EN);
  5773. /*
  5774. * Older PCIe devices only support the 128 byte
  5775. * MPS setting. Enforce the restriction.
  5776. */
  5777. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  5778. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
  5779. val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
  5780. pci_write_config_word(tp->pdev,
  5781. tp->pcie_cap + PCI_EXP_DEVCTL,
  5782. val16);
  5783. pcie_set_readrq(tp->pdev, 4096);
  5784. /* Clear error status */
  5785. pci_write_config_word(tp->pdev,
  5786. tp->pcie_cap + PCI_EXP_DEVSTA,
  5787. PCI_EXP_DEVSTA_CED |
  5788. PCI_EXP_DEVSTA_NFED |
  5789. PCI_EXP_DEVSTA_FED |
  5790. PCI_EXP_DEVSTA_URD);
  5791. }
  5792. tg3_restore_pci_state(tp);
  5793. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  5794. val = 0;
  5795. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  5796. val = tr32(MEMARB_MODE);
  5797. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  5798. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  5799. tg3_stop_fw(tp);
  5800. tw32(0x5000, 0x400);
  5801. }
  5802. tw32(GRC_MODE, tp->grc_mode);
  5803. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  5804. val = tr32(0xc4);
  5805. tw32(0xc4, val | (1 << 15));
  5806. }
  5807. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  5808. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5809. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  5810. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  5811. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  5812. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  5813. }
  5814. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5815. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  5816. tw32_f(MAC_MODE, tp->mac_mode);
  5817. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  5818. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  5819. tw32_f(MAC_MODE, tp->mac_mode);
  5820. } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  5821. tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
  5822. if (tp->mac_mode & MAC_MODE_APE_TX_EN)
  5823. tp->mac_mode |= MAC_MODE_TDE_ENABLE;
  5824. tw32_f(MAC_MODE, tp->mac_mode);
  5825. } else
  5826. tw32_f(MAC_MODE, 0);
  5827. udelay(40);
  5828. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  5829. err = tg3_poll_fw(tp);
  5830. if (err)
  5831. return err;
  5832. tg3_mdio_start(tp);
  5833. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  5834. u8 phy_addr;
  5835. phy_addr = tp->phy_addr;
  5836. tp->phy_addr = TG3_PHY_PCIE_ADDR;
  5837. tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
  5838. TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
  5839. val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
  5840. TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
  5841. TG3_PCIEPHY_TX0CTRL1_NB_EN;
  5842. tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
  5843. udelay(10);
  5844. tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
  5845. TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
  5846. val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
  5847. TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
  5848. tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
  5849. udelay(10);
  5850. tp->phy_addr = phy_addr;
  5851. }
  5852. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  5853. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  5854. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  5855. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
  5856. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
  5857. val = tr32(0x7c00);
  5858. tw32(0x7c00, val | (1 << 25));
  5859. }
  5860. /* Reprobe ASF enable state. */
  5861. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  5862. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  5863. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  5864. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  5865. u32 nic_cfg;
  5866. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  5867. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  5868. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  5869. tp->last_event_jiffies = jiffies;
  5870. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  5871. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  5872. }
  5873. }
  5874. return 0;
  5875. }
  5876. /* tp->lock is held. */
  5877. static void tg3_stop_fw(struct tg3 *tp)
  5878. {
  5879. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  5880. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  5881. /* Wait for RX cpu to ACK the previous event. */
  5882. tg3_wait_for_event_ack(tp);
  5883. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  5884. tg3_generate_fw_event(tp);
  5885. /* Wait for RX cpu to ACK this event. */
  5886. tg3_wait_for_event_ack(tp);
  5887. }
  5888. }
  5889. /* tp->lock is held. */
  5890. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  5891. {
  5892. int err;
  5893. tg3_stop_fw(tp);
  5894. tg3_write_sig_pre_reset(tp, kind);
  5895. tg3_abort_hw(tp, silent);
  5896. err = tg3_chip_reset(tp);
  5897. __tg3_set_mac_addr(tp, 0);
  5898. tg3_write_sig_legacy(tp, kind);
  5899. tg3_write_sig_post_reset(tp, kind);
  5900. if (err)
  5901. return err;
  5902. return 0;
  5903. }
  5904. #define RX_CPU_SCRATCH_BASE 0x30000
  5905. #define RX_CPU_SCRATCH_SIZE 0x04000
  5906. #define TX_CPU_SCRATCH_BASE 0x34000
  5907. #define TX_CPU_SCRATCH_SIZE 0x04000
  5908. /* tp->lock is held. */
  5909. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  5910. {
  5911. int i;
  5912. BUG_ON(offset == TX_CPU_BASE &&
  5913. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  5914. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5915. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  5916. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  5917. return 0;
  5918. }
  5919. if (offset == RX_CPU_BASE) {
  5920. for (i = 0; i < 10000; i++) {
  5921. tw32(offset + CPU_STATE, 0xffffffff);
  5922. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  5923. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  5924. break;
  5925. }
  5926. tw32(offset + CPU_STATE, 0xffffffff);
  5927. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  5928. udelay(10);
  5929. } else {
  5930. for (i = 0; i < 10000; i++) {
  5931. tw32(offset + CPU_STATE, 0xffffffff);
  5932. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  5933. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  5934. break;
  5935. }
  5936. }
  5937. if (i >= 10000) {
  5938. printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  5939. "and %s CPU\n",
  5940. tp->dev->name,
  5941. (offset == RX_CPU_BASE ? "RX" : "TX"));
  5942. return -ENODEV;
  5943. }
  5944. /* Clear firmware's nvram arbitration. */
  5945. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  5946. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  5947. return 0;
  5948. }
  5949. struct fw_info {
  5950. unsigned int fw_base;
  5951. unsigned int fw_len;
  5952. const __be32 *fw_data;
  5953. };
  5954. /* tp->lock is held. */
  5955. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  5956. int cpu_scratch_size, struct fw_info *info)
  5957. {
  5958. int err, lock_err, i;
  5959. void (*write_op)(struct tg3 *, u32, u32);
  5960. if (cpu_base == TX_CPU_BASE &&
  5961. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5962. printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  5963. "TX cpu firmware on %s which is 5705.\n",
  5964. tp->dev->name);
  5965. return -EINVAL;
  5966. }
  5967. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  5968. write_op = tg3_write_mem;
  5969. else
  5970. write_op = tg3_write_indirect_reg32;
  5971. /* It is possible that bootcode is still loading at this point.
  5972. * Get the nvram lock first before halting the cpu.
  5973. */
  5974. lock_err = tg3_nvram_lock(tp);
  5975. err = tg3_halt_cpu(tp, cpu_base);
  5976. if (!lock_err)
  5977. tg3_nvram_unlock(tp);
  5978. if (err)
  5979. goto out;
  5980. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  5981. write_op(tp, cpu_scratch_base + i, 0);
  5982. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5983. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  5984. for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
  5985. write_op(tp, (cpu_scratch_base +
  5986. (info->fw_base & 0xffff) +
  5987. (i * sizeof(u32))),
  5988. be32_to_cpu(info->fw_data[i]));
  5989. err = 0;
  5990. out:
  5991. return err;
  5992. }
  5993. /* tp->lock is held. */
  5994. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  5995. {
  5996. struct fw_info info;
  5997. const __be32 *fw_data;
  5998. int err, i;
  5999. fw_data = (void *)tp->fw->data;
  6000. /* Firmware blob starts with version numbers, followed by
  6001. start address and length. We are setting complete length.
  6002. length = end_address_of_bss - start_address_of_text.
  6003. Remainder is the blob to be loaded contiguously
  6004. from start address. */
  6005. info.fw_base = be32_to_cpu(fw_data[1]);
  6006. info.fw_len = tp->fw->size - 12;
  6007. info.fw_data = &fw_data[3];
  6008. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  6009. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  6010. &info);
  6011. if (err)
  6012. return err;
  6013. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  6014. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  6015. &info);
  6016. if (err)
  6017. return err;
  6018. /* Now startup only the RX cpu. */
  6019. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  6020. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  6021. for (i = 0; i < 5; i++) {
  6022. if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
  6023. break;
  6024. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  6025. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  6026. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  6027. udelay(1000);
  6028. }
  6029. if (i >= 5) {
  6030. printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  6031. "to set RX CPU PC, is %08x should be %08x\n",
  6032. tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  6033. info.fw_base);
  6034. return -ENODEV;
  6035. }
  6036. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  6037. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  6038. return 0;
  6039. }
  6040. /* 5705 needs a special version of the TSO firmware. */
  6041. /* tp->lock is held. */
  6042. static int tg3_load_tso_firmware(struct tg3 *tp)
  6043. {
  6044. struct fw_info info;
  6045. const __be32 *fw_data;
  6046. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  6047. int err, i;
  6048. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6049. return 0;
  6050. fw_data = (void *)tp->fw->data;
  6051. /* Firmware blob starts with version numbers, followed by
  6052. start address and length. We are setting complete length.
  6053. length = end_address_of_bss - start_address_of_text.
  6054. Remainder is the blob to be loaded contiguously
  6055. from start address. */
  6056. info.fw_base = be32_to_cpu(fw_data[1]);
  6057. cpu_scratch_size = tp->fw_len;
  6058. info.fw_len = tp->fw->size - 12;
  6059. info.fw_data = &fw_data[3];
  6060. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  6061. cpu_base = RX_CPU_BASE;
  6062. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  6063. } else {
  6064. cpu_base = TX_CPU_BASE;
  6065. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  6066. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  6067. }
  6068. err = tg3_load_firmware_cpu(tp, cpu_base,
  6069. cpu_scratch_base, cpu_scratch_size,
  6070. &info);
  6071. if (err)
  6072. return err;
  6073. /* Now startup the cpu. */
  6074. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6075. tw32_f(cpu_base + CPU_PC, info.fw_base);
  6076. for (i = 0; i < 5; i++) {
  6077. if (tr32(cpu_base + CPU_PC) == info.fw_base)
  6078. break;
  6079. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6080. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  6081. tw32_f(cpu_base + CPU_PC, info.fw_base);
  6082. udelay(1000);
  6083. }
  6084. if (i >= 5) {
  6085. printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  6086. "to set CPU PC, is %08x should be %08x\n",
  6087. tp->dev->name, tr32(cpu_base + CPU_PC),
  6088. info.fw_base);
  6089. return -ENODEV;
  6090. }
  6091. tw32(cpu_base + CPU_STATE, 0xffffffff);
  6092. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  6093. return 0;
  6094. }
  6095. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  6096. {
  6097. struct tg3 *tp = netdev_priv(dev);
  6098. struct sockaddr *addr = p;
  6099. int err = 0, skip_mac_1 = 0;
  6100. if (!is_valid_ether_addr(addr->sa_data))
  6101. return -EINVAL;
  6102. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  6103. if (!netif_running(dev))
  6104. return 0;
  6105. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  6106. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  6107. addr0_high = tr32(MAC_ADDR_0_HIGH);
  6108. addr0_low = tr32(MAC_ADDR_0_LOW);
  6109. addr1_high = tr32(MAC_ADDR_1_HIGH);
  6110. addr1_low = tr32(MAC_ADDR_1_LOW);
  6111. /* Skip MAC addr 1 if ASF is using it. */
  6112. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  6113. !(addr1_high == 0 && addr1_low == 0))
  6114. skip_mac_1 = 1;
  6115. }
  6116. spin_lock_bh(&tp->lock);
  6117. __tg3_set_mac_addr(tp, skip_mac_1);
  6118. spin_unlock_bh(&tp->lock);
  6119. return err;
  6120. }
  6121. /* tp->lock is held. */
  6122. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  6123. dma_addr_t mapping, u32 maxlen_flags,
  6124. u32 nic_addr)
  6125. {
  6126. tg3_write_mem(tp,
  6127. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6128. ((u64) mapping >> 32));
  6129. tg3_write_mem(tp,
  6130. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  6131. ((u64) mapping & 0xffffffff));
  6132. tg3_write_mem(tp,
  6133. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  6134. maxlen_flags);
  6135. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6136. tg3_write_mem(tp,
  6137. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  6138. nic_addr);
  6139. }
  6140. static void __tg3_set_rx_mode(struct net_device *);
  6141. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  6142. {
  6143. int i;
  6144. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
  6145. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  6146. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  6147. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  6148. } else {
  6149. tw32(HOSTCC_TXCOL_TICKS, 0);
  6150. tw32(HOSTCC_TXMAX_FRAMES, 0);
  6151. tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  6152. }
  6153. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
  6154. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  6155. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  6156. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  6157. } else {
  6158. tw32(HOSTCC_RXCOL_TICKS, 0);
  6159. tw32(HOSTCC_RXMAX_FRAMES, 0);
  6160. tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
  6161. }
  6162. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6163. u32 val = ec->stats_block_coalesce_usecs;
  6164. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  6165. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  6166. if (!netif_carrier_ok(tp->dev))
  6167. val = 0;
  6168. tw32(HOSTCC_STAT_COAL_TICKS, val);
  6169. }
  6170. for (i = 0; i < tp->irq_cnt - 1; i++) {
  6171. u32 reg;
  6172. reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
  6173. tw32(reg, ec->rx_coalesce_usecs);
  6174. reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
  6175. tw32(reg, ec->rx_max_coalesced_frames);
  6176. reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
  6177. tw32(reg, ec->rx_max_coalesced_frames_irq);
  6178. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
  6179. reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
  6180. tw32(reg, ec->tx_coalesce_usecs);
  6181. reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
  6182. tw32(reg, ec->tx_max_coalesced_frames);
  6183. reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
  6184. tw32(reg, ec->tx_max_coalesced_frames_irq);
  6185. }
  6186. }
  6187. for (; i < tp->irq_max - 1; i++) {
  6188. tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
  6189. tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
  6190. tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  6191. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
  6192. tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
  6193. tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
  6194. tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  6195. }
  6196. }
  6197. }
  6198. /* tp->lock is held. */
  6199. static void tg3_rings_reset(struct tg3 *tp)
  6200. {
  6201. int i;
  6202. u32 stblk, txrcb, rxrcb, limit;
  6203. struct tg3_napi *tnapi = &tp->napi[0];
  6204. /* Disable all transmit rings but the first. */
  6205. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6206. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
  6207. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6208. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
  6209. else
  6210. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  6211. for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  6212. txrcb < limit; txrcb += TG3_BDINFO_SIZE)
  6213. tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
  6214. BDINFO_FLAGS_DISABLED);
  6215. /* Disable all receive return rings but the first. */
  6216. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  6217. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
  6218. else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6219. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
  6220. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  6221. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6222. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
  6223. else
  6224. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  6225. for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  6226. rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
  6227. tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
  6228. BDINFO_FLAGS_DISABLED);
  6229. /* Disable interrupts */
  6230. tw32_mailbox_f(tp->napi[0].int_mbox, 1);
  6231. /* Zero mailbox registers. */
  6232. if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
  6233. for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
  6234. tp->napi[i].tx_prod = 0;
  6235. tp->napi[i].tx_cons = 0;
  6236. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  6237. tw32_mailbox(tp->napi[i].prodmbox, 0);
  6238. tw32_rx_mbox(tp->napi[i].consmbox, 0);
  6239. tw32_mailbox_f(tp->napi[i].int_mbox, 1);
  6240. }
  6241. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
  6242. tw32_mailbox(tp->napi[0].prodmbox, 0);
  6243. } else {
  6244. tp->napi[0].tx_prod = 0;
  6245. tp->napi[0].tx_cons = 0;
  6246. tw32_mailbox(tp->napi[0].prodmbox, 0);
  6247. tw32_rx_mbox(tp->napi[0].consmbox, 0);
  6248. }
  6249. /* Make sure the NIC-based send BD rings are disabled. */
  6250. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6251. u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  6252. for (i = 0; i < 16; i++)
  6253. tw32_tx_mbox(mbox + i * 8, 0);
  6254. }
  6255. txrcb = NIC_SRAM_SEND_RCB;
  6256. rxrcb = NIC_SRAM_RCV_RET_RCB;
  6257. /* Clear status block in ram. */
  6258. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6259. /* Set status block DMA address */
  6260. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6261. ((u64) tnapi->status_mapping >> 32));
  6262. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6263. ((u64) tnapi->status_mapping & 0xffffffff));
  6264. if (tnapi->tx_ring) {
  6265. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  6266. (TG3_TX_RING_SIZE <<
  6267. BDINFO_FLAGS_MAXLEN_SHIFT),
  6268. NIC_SRAM_TX_BUFFER_DESC);
  6269. txrcb += TG3_BDINFO_SIZE;
  6270. }
  6271. if (tnapi->rx_rcb) {
  6272. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  6273. (TG3_RX_RCB_RING_SIZE(tp) <<
  6274. BDINFO_FLAGS_MAXLEN_SHIFT), 0);
  6275. rxrcb += TG3_BDINFO_SIZE;
  6276. }
  6277. stblk = HOSTCC_STATBLCK_RING1;
  6278. for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
  6279. u64 mapping = (u64)tnapi->status_mapping;
  6280. tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
  6281. tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
  6282. /* Clear status block in ram. */
  6283. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6284. if (tnapi->tx_ring) {
  6285. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  6286. (TG3_TX_RING_SIZE <<
  6287. BDINFO_FLAGS_MAXLEN_SHIFT),
  6288. NIC_SRAM_TX_BUFFER_DESC);
  6289. txrcb += TG3_BDINFO_SIZE;
  6290. }
  6291. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  6292. (TG3_RX_RCB_RING_SIZE(tp) <<
  6293. BDINFO_FLAGS_MAXLEN_SHIFT), 0);
  6294. stblk += 8;
  6295. rxrcb += TG3_BDINFO_SIZE;
  6296. }
  6297. }
  6298. /* tp->lock is held. */
  6299. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  6300. {
  6301. u32 val, rdmac_mode;
  6302. int i, err, limit;
  6303. struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
  6304. tg3_disable_ints(tp);
  6305. tg3_stop_fw(tp);
  6306. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  6307. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  6308. tg3_abort_hw(tp, 1);
  6309. }
  6310. if (reset_phy &&
  6311. !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
  6312. tg3_phy_reset(tp);
  6313. err = tg3_chip_reset(tp);
  6314. if (err)
  6315. return err;
  6316. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  6317. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
  6318. val = tr32(TG3_CPMU_CTRL);
  6319. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  6320. tw32(TG3_CPMU_CTRL, val);
  6321. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  6322. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  6323. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  6324. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  6325. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  6326. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  6327. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  6328. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  6329. val = tr32(TG3_CPMU_HST_ACC);
  6330. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  6331. val |= CPMU_HST_ACC_MACCLK_6_25;
  6332. tw32(TG3_CPMU_HST_ACC, val);
  6333. }
  6334. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
  6335. val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
  6336. val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
  6337. PCIE_PWR_MGMT_L1_THRESH_4MS;
  6338. tw32(PCIE_PWR_MGMT_THRESH, val);
  6339. val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
  6340. tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
  6341. tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
  6342. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  6343. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  6344. }
  6345. if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
  6346. u32 grc_mode = tr32(GRC_MODE);
  6347. /* Access the lower 1K of PL PCIE block registers. */
  6348. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  6349. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  6350. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
  6351. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
  6352. val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
  6353. tw32(GRC_MODE, grc_mode);
  6354. }
  6355. /* This works around an issue with Athlon chipsets on
  6356. * B3 tigon3 silicon. This bit has no effect on any
  6357. * other revision. But do not set this on PCI Express
  6358. * chips and don't even touch the clocks if the CPMU is present.
  6359. */
  6360. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
  6361. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  6362. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  6363. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  6364. }
  6365. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  6366. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  6367. val = tr32(TG3PCI_PCISTATE);
  6368. val |= PCISTATE_RETRY_SAME_DMA;
  6369. tw32(TG3PCI_PCISTATE, val);
  6370. }
  6371. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  6372. /* Allow reads and writes to the
  6373. * APE register and memory space.
  6374. */
  6375. val = tr32(TG3PCI_PCISTATE);
  6376. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  6377. PCISTATE_ALLOW_APE_SHMEM_WR;
  6378. tw32(TG3PCI_PCISTATE, val);
  6379. }
  6380. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  6381. /* Enable some hw fixes. */
  6382. val = tr32(TG3PCI_MSI_DATA);
  6383. val |= (1 << 26) | (1 << 28) | (1 << 29);
  6384. tw32(TG3PCI_MSI_DATA, val);
  6385. }
  6386. /* Descriptor ring init may make accesses to the
  6387. * NIC SRAM area to setup the TX descriptors, so we
  6388. * can only do this after the hardware has been
  6389. * successfully reset.
  6390. */
  6391. err = tg3_init_rings(tp);
  6392. if (err)
  6393. return err;
  6394. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  6395. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  6396. val = tr32(TG3PCI_DMA_RW_CTRL) &
  6397. ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  6398. tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
  6399. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  6400. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
  6401. /* This value is determined during the probe time DMA
  6402. * engine test, tg3_test_dma.
  6403. */
  6404. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  6405. }
  6406. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  6407. GRC_MODE_4X_NIC_SEND_RINGS |
  6408. GRC_MODE_NO_TX_PHDR_CSUM |
  6409. GRC_MODE_NO_RX_PHDR_CSUM);
  6410. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  6411. /* Pseudo-header checksum is done by hardware logic and not
  6412. * the offload processers, so make the chip do the pseudo-
  6413. * header checksums on receive. For transmit it is more
  6414. * convenient to do the pseudo-header checksum in software
  6415. * as Linux does that on transmit for us in all cases.
  6416. */
  6417. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  6418. tw32(GRC_MODE,
  6419. tp->grc_mode |
  6420. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  6421. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  6422. val = tr32(GRC_MISC_CFG);
  6423. val &= ~0xff;
  6424. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  6425. tw32(GRC_MISC_CFG, val);
  6426. /* Initialize MBUF/DESC pool. */
  6427. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  6428. /* Do nothing. */
  6429. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  6430. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  6431. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  6432. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  6433. else
  6434. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  6435. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  6436. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  6437. }
  6438. else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6439. int fw_len;
  6440. fw_len = tp->fw_len;
  6441. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  6442. tw32(BUFMGR_MB_POOL_ADDR,
  6443. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  6444. tw32(BUFMGR_MB_POOL_SIZE,
  6445. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  6446. }
  6447. if (tp->dev->mtu <= ETH_DATA_LEN) {
  6448. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6449. tp->bufmgr_config.mbuf_read_dma_low_water);
  6450. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6451. tp->bufmgr_config.mbuf_mac_rx_low_water);
  6452. tw32(BUFMGR_MB_HIGH_WATER,
  6453. tp->bufmgr_config.mbuf_high_water);
  6454. } else {
  6455. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  6456. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  6457. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  6458. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  6459. tw32(BUFMGR_MB_HIGH_WATER,
  6460. tp->bufmgr_config.mbuf_high_water_jumbo);
  6461. }
  6462. tw32(BUFMGR_DMA_LOW_WATER,
  6463. tp->bufmgr_config.dma_low_water);
  6464. tw32(BUFMGR_DMA_HIGH_WATER,
  6465. tp->bufmgr_config.dma_high_water);
  6466. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  6467. for (i = 0; i < 2000; i++) {
  6468. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  6469. break;
  6470. udelay(10);
  6471. }
  6472. if (i >= 2000) {
  6473. printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  6474. tp->dev->name);
  6475. return -ENODEV;
  6476. }
  6477. /* Setup replenish threshold. */
  6478. val = tp->rx_pending / 8;
  6479. if (val == 0)
  6480. val = 1;
  6481. else if (val > tp->rx_std_max_post)
  6482. val = tp->rx_std_max_post;
  6483. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  6484. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  6485. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  6486. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  6487. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  6488. }
  6489. tw32(RCVBDI_STD_THRESH, val);
  6490. /* Initialize TG3_BDINFO's at:
  6491. * RCVDBDI_STD_BD: standard eth size rx ring
  6492. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  6493. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  6494. *
  6495. * like so:
  6496. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  6497. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  6498. * ring attribute flags
  6499. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  6500. *
  6501. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  6502. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  6503. *
  6504. * The size of each ring is fixed in the firmware, but the location is
  6505. * configurable.
  6506. */
  6507. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6508. ((u64) tpr->rx_std_mapping >> 32));
  6509. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  6510. ((u64) tpr->rx_std_mapping & 0xffffffff));
  6511. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
  6512. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  6513. NIC_SRAM_RX_BUFFER_DESC);
  6514. /* Disable the mini ring */
  6515. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6516. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6517. BDINFO_FLAGS_DISABLED);
  6518. /* Program the jumbo buffer descriptor ring control
  6519. * blocks on those devices that have them.
  6520. */
  6521. if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
  6522. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  6523. /* Setup replenish threshold. */
  6524. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  6525. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  6526. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6527. ((u64) tpr->rx_jmb_mapping >> 32));
  6528. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  6529. ((u64) tpr->rx_jmb_mapping & 0xffffffff));
  6530. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6531. (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
  6532. BDINFO_FLAGS_USE_EXT_RECV);
  6533. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
  6534. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  6535. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  6536. } else {
  6537. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  6538. BDINFO_FLAGS_DISABLED);
  6539. }
  6540. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  6541. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6542. val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
  6543. (RX_STD_MAX_SIZE << 2);
  6544. else
  6545. val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
  6546. } else
  6547. val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
  6548. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
  6549. tpr->rx_std_prod_idx = tp->rx_pending;
  6550. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
  6551. tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  6552. tp->rx_jumbo_pending : 0;
  6553. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
  6554. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  6555. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  6556. tw32(STD_REPLENISH_LWM, 32);
  6557. tw32(JMB_REPLENISH_LWM, 16);
  6558. }
  6559. tg3_rings_reset(tp);
  6560. /* Initialize MAC address and backoff seed. */
  6561. __tg3_set_mac_addr(tp, 0);
  6562. /* MTU + ethernet header + FCS + optional VLAN tag */
  6563. tw32(MAC_RX_MTU_SIZE,
  6564. tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  6565. /* The slot time is changed by tg3_setup_phy if we
  6566. * run at gigabit with half duplex.
  6567. */
  6568. tw32(MAC_TX_LENGTHS,
  6569. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  6570. (6 << TX_LENGTHS_IPG_SHIFT) |
  6571. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  6572. /* Receive rules. */
  6573. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  6574. tw32(RCVLPC_CONFIG, 0x0181);
  6575. /* Calculate RDMAC_MODE setting early, we need it to determine
  6576. * the RCVLPC_STATE_ENABLE mask.
  6577. */
  6578. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  6579. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  6580. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  6581. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  6582. RDMAC_MODE_LNGREAD_ENAB);
  6583. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  6584. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  6585. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  6586. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  6587. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  6588. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  6589. /* If statement applies to 5705 and 5750 PCI devices only */
  6590. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6591. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6592. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  6593. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  6594. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  6595. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  6596. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6597. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  6598. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  6599. }
  6600. }
  6601. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  6602. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  6603. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6604. rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
  6605. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
  6606. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  6607. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  6608. rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
  6609. /* Receive/send statistics. */
  6610. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  6611. val = tr32(RCVLPC_STATS_ENABLE);
  6612. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  6613. tw32(RCVLPC_STATS_ENABLE, val);
  6614. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  6615. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  6616. val = tr32(RCVLPC_STATS_ENABLE);
  6617. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  6618. tw32(RCVLPC_STATS_ENABLE, val);
  6619. } else {
  6620. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  6621. }
  6622. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  6623. tw32(SNDDATAI_STATSENAB, 0xffffff);
  6624. tw32(SNDDATAI_STATSCTRL,
  6625. (SNDDATAI_SCTRL_ENABLE |
  6626. SNDDATAI_SCTRL_FASTUPD));
  6627. /* Setup host coalescing engine. */
  6628. tw32(HOSTCC_MODE, 0);
  6629. for (i = 0; i < 2000; i++) {
  6630. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  6631. break;
  6632. udelay(10);
  6633. }
  6634. __tg3_set_coalesce(tp, &tp->coal);
  6635. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6636. /* Status/statistics block address. See tg3_timer,
  6637. * the tg3_periodic_fetch_stats call there, and
  6638. * tg3_get_stats to see how this works for 5705/5750 chips.
  6639. */
  6640. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  6641. ((u64) tp->stats_mapping >> 32));
  6642. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  6643. ((u64) tp->stats_mapping & 0xffffffff));
  6644. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  6645. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  6646. /* Clear statistics and status block memory areas */
  6647. for (i = NIC_SRAM_STATS_BLK;
  6648. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  6649. i += sizeof(u32)) {
  6650. tg3_write_mem(tp, i, 0);
  6651. udelay(40);
  6652. }
  6653. }
  6654. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  6655. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  6656. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  6657. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6658. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  6659. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  6660. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  6661. /* reset to prevent losing 1st rx packet intermittently */
  6662. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6663. udelay(10);
  6664. }
  6665. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6666. tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  6667. else
  6668. tp->mac_mode = 0;
  6669. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  6670. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  6671. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6672. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6673. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  6674. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  6675. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  6676. udelay(40);
  6677. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  6678. * If TG3_FLG2_IS_NIC is zero, we should read the
  6679. * register to preserve the GPIO settings for LOMs. The GPIOs,
  6680. * whether used as inputs or outputs, are set by boot code after
  6681. * reset.
  6682. */
  6683. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  6684. u32 gpio_mask;
  6685. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  6686. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  6687. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  6688. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  6689. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  6690. GRC_LCLCTRL_GPIO_OUTPUT3;
  6691. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  6692. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  6693. tp->grc_local_ctrl &= ~gpio_mask;
  6694. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  6695. /* GPIO1 must be driven high for eeprom write protect */
  6696. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  6697. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  6698. GRC_LCLCTRL_GPIO_OUTPUT1);
  6699. }
  6700. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6701. udelay(100);
  6702. if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
  6703. val = tr32(MSGINT_MODE);
  6704. val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
  6705. tw32(MSGINT_MODE, val);
  6706. }
  6707. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6708. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  6709. udelay(40);
  6710. }
  6711. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  6712. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  6713. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  6714. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  6715. WDMAC_MODE_LNGREAD_ENAB);
  6716. /* If statement applies to 5705 and 5750 PCI devices only */
  6717. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6718. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6719. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  6720. if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  6721. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  6722. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  6723. /* nothing */
  6724. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6725. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  6726. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  6727. val |= WDMAC_MODE_RX_ACCEL;
  6728. }
  6729. }
  6730. /* Enable host coalescing bug fix */
  6731. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  6732. val |= WDMAC_MODE_STATUS_TAG_FIX;
  6733. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  6734. val |= WDMAC_MODE_BURST_ALL_DATA;
  6735. tw32_f(WDMAC_MODE, val);
  6736. udelay(40);
  6737. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  6738. u16 pcix_cmd;
  6739. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6740. &pcix_cmd);
  6741. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  6742. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  6743. pcix_cmd |= PCI_X_CMD_READ_2K;
  6744. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  6745. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  6746. pcix_cmd |= PCI_X_CMD_READ_2K;
  6747. }
  6748. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6749. pcix_cmd);
  6750. }
  6751. tw32_f(RDMAC_MODE, rdmac_mode);
  6752. udelay(40);
  6753. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  6754. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6755. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  6756. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  6757. tw32(SNDDATAC_MODE,
  6758. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  6759. else
  6760. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  6761. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  6762. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  6763. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  6764. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  6765. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6766. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  6767. val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
  6768. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
  6769. val |= SNDBDI_MODE_MULTI_TXQ_EN;
  6770. tw32(SNDBDI_MODE, val);
  6771. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  6772. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  6773. err = tg3_load_5701_a0_firmware_fix(tp);
  6774. if (err)
  6775. return err;
  6776. }
  6777. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6778. err = tg3_load_tso_firmware(tp);
  6779. if (err)
  6780. return err;
  6781. }
  6782. tp->tx_mode = TX_MODE_ENABLE;
  6783. tw32_f(MAC_TX_MODE, tp->tx_mode);
  6784. udelay(100);
  6785. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
  6786. u32 reg = MAC_RSS_INDIR_TBL_0;
  6787. u8 *ent = (u8 *)&val;
  6788. /* Setup the indirection table */
  6789. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
  6790. int idx = i % sizeof(val);
  6791. ent[idx] = i % (tp->irq_cnt - 1);
  6792. if (idx == sizeof(val) - 1) {
  6793. tw32(reg, val);
  6794. reg += 4;
  6795. }
  6796. }
  6797. /* Setup the "secret" hash key. */
  6798. tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
  6799. tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
  6800. tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
  6801. tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
  6802. tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
  6803. tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
  6804. tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
  6805. tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
  6806. tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
  6807. tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
  6808. }
  6809. tp->rx_mode = RX_MODE_ENABLE;
  6810. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  6811. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  6812. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
  6813. tp->rx_mode |= RX_MODE_RSS_ENABLE |
  6814. RX_MODE_RSS_ITBL_HASH_BITS_7 |
  6815. RX_MODE_RSS_IPV6_HASH_EN |
  6816. RX_MODE_RSS_TCP_IPV6_HASH_EN |
  6817. RX_MODE_RSS_IPV4_HASH_EN |
  6818. RX_MODE_RSS_TCP_IPV4_HASH_EN;
  6819. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6820. udelay(10);
  6821. tw32(MAC_LED_CTRL, tp->led_ctrl);
  6822. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  6823. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  6824. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6825. udelay(10);
  6826. }
  6827. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6828. udelay(10);
  6829. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  6830. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  6831. !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
  6832. /* Set drive transmission level to 1.2V */
  6833. /* only if the signal pre-emphasis bit is not set */
  6834. val = tr32(MAC_SERDES_CFG);
  6835. val &= 0xfffff000;
  6836. val |= 0x880;
  6837. tw32(MAC_SERDES_CFG, val);
  6838. }
  6839. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  6840. tw32(MAC_SERDES_CFG, 0x616000);
  6841. }
  6842. /* Prevent chip from dropping frames when flow control
  6843. * is enabled.
  6844. */
  6845. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  6846. val = 1;
  6847. else
  6848. val = 2;
  6849. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
  6850. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  6851. (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  6852. /* Use hardware link auto-negotiation */
  6853. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  6854. }
  6855. if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
  6856. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  6857. u32 tmp;
  6858. tmp = tr32(SERDES_RX_CTRL);
  6859. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  6860. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  6861. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  6862. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6863. }
  6864. if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  6865. if (tp->link_config.phy_is_low_power) {
  6866. tp->link_config.phy_is_low_power = 0;
  6867. tp->link_config.speed = tp->link_config.orig_speed;
  6868. tp->link_config.duplex = tp->link_config.orig_duplex;
  6869. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  6870. }
  6871. err = tg3_setup_phy(tp, 0);
  6872. if (err)
  6873. return err;
  6874. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6875. !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
  6876. u32 tmp;
  6877. /* Clear CRC stats. */
  6878. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  6879. tg3_writephy(tp, MII_TG3_TEST1,
  6880. tmp | MII_TG3_TEST1_CRC_EN);
  6881. tg3_readphy(tp, 0x14, &tmp);
  6882. }
  6883. }
  6884. }
  6885. __tg3_set_rx_mode(tp->dev);
  6886. /* Initialize receive rules. */
  6887. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  6888. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6889. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  6890. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6891. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6892. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  6893. limit = 8;
  6894. else
  6895. limit = 16;
  6896. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  6897. limit -= 4;
  6898. switch (limit) {
  6899. case 16:
  6900. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  6901. case 15:
  6902. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  6903. case 14:
  6904. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  6905. case 13:
  6906. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  6907. case 12:
  6908. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  6909. case 11:
  6910. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  6911. case 10:
  6912. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  6913. case 9:
  6914. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  6915. case 8:
  6916. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  6917. case 7:
  6918. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  6919. case 6:
  6920. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  6921. case 5:
  6922. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  6923. case 4:
  6924. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  6925. case 3:
  6926. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  6927. case 2:
  6928. case 1:
  6929. default:
  6930. break;
  6931. }
  6932. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6933. /* Write our heartbeat update interval to APE. */
  6934. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  6935. APE_HOST_HEARTBEAT_INT_DISABLE);
  6936. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  6937. return 0;
  6938. }
  6939. /* Called at device open time to get the chip ready for
  6940. * packet processing. Invoked with tp->lock held.
  6941. */
  6942. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  6943. {
  6944. tg3_switch_clocks(tp);
  6945. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  6946. return tg3_reset_hw(tp, reset_phy);
  6947. }
  6948. #define TG3_STAT_ADD32(PSTAT, REG) \
  6949. do { u32 __val = tr32(REG); \
  6950. (PSTAT)->low += __val; \
  6951. if ((PSTAT)->low < __val) \
  6952. (PSTAT)->high += 1; \
  6953. } while (0)
  6954. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  6955. {
  6956. struct tg3_hw_stats *sp = tp->hw_stats;
  6957. if (!netif_carrier_ok(tp->dev))
  6958. return;
  6959. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  6960. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  6961. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  6962. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  6963. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  6964. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  6965. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  6966. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  6967. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  6968. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  6969. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  6970. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  6971. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  6972. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  6973. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  6974. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  6975. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  6976. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  6977. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  6978. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  6979. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  6980. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  6981. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  6982. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  6983. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  6984. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  6985. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  6986. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  6987. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  6988. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  6989. }
  6990. static void tg3_timer(unsigned long __opaque)
  6991. {
  6992. struct tg3 *tp = (struct tg3 *) __opaque;
  6993. if (tp->irq_sync)
  6994. goto restart_timer;
  6995. spin_lock(&tp->lock);
  6996. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6997. /* All of this garbage is because when using non-tagged
  6998. * IRQ status the mailbox/status_block protocol the chip
  6999. * uses with the cpu is race prone.
  7000. */
  7001. if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
  7002. tw32(GRC_LOCAL_CTRL,
  7003. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  7004. } else {
  7005. tw32(HOSTCC_MODE, tp->coalesce_mode |
  7006. HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
  7007. }
  7008. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  7009. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  7010. spin_unlock(&tp->lock);
  7011. schedule_work(&tp->reset_task);
  7012. return;
  7013. }
  7014. }
  7015. /* This part only runs once per second. */
  7016. if (!--tp->timer_counter) {
  7017. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  7018. tg3_periodic_fetch_stats(tp);
  7019. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  7020. u32 mac_stat;
  7021. int phy_event;
  7022. mac_stat = tr32(MAC_STATUS);
  7023. phy_event = 0;
  7024. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  7025. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  7026. phy_event = 1;
  7027. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  7028. phy_event = 1;
  7029. if (phy_event)
  7030. tg3_setup_phy(tp, 0);
  7031. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  7032. u32 mac_stat = tr32(MAC_STATUS);
  7033. int need_setup = 0;
  7034. if (netif_carrier_ok(tp->dev) &&
  7035. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  7036. need_setup = 1;
  7037. }
  7038. if (! netif_carrier_ok(tp->dev) &&
  7039. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  7040. MAC_STATUS_SIGNAL_DET))) {
  7041. need_setup = 1;
  7042. }
  7043. if (need_setup) {
  7044. if (!tp->serdes_counter) {
  7045. tw32_f(MAC_MODE,
  7046. (tp->mac_mode &
  7047. ~MAC_MODE_PORT_MODE_MASK));
  7048. udelay(40);
  7049. tw32_f(MAC_MODE, tp->mac_mode);
  7050. udelay(40);
  7051. }
  7052. tg3_setup_phy(tp, 0);
  7053. }
  7054. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  7055. tg3_serdes_parallel_detect(tp);
  7056. tp->timer_counter = tp->timer_multiplier;
  7057. }
  7058. /* Heartbeat is only sent once every 2 seconds.
  7059. *
  7060. * The heartbeat is to tell the ASF firmware that the host
  7061. * driver is still alive. In the event that the OS crashes,
  7062. * ASF needs to reset the hardware to free up the FIFO space
  7063. * that may be filled with rx packets destined for the host.
  7064. * If the FIFO is full, ASF will no longer function properly.
  7065. *
  7066. * Unintended resets have been reported on real time kernels
  7067. * where the timer doesn't run on time. Netpoll will also have
  7068. * same problem.
  7069. *
  7070. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  7071. * to check the ring condition when the heartbeat is expiring
  7072. * before doing the reset. This will prevent most unintended
  7073. * resets.
  7074. */
  7075. if (!--tp->asf_counter) {
  7076. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  7077. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  7078. tg3_wait_for_event_ack(tp);
  7079. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  7080. FWCMD_NICDRV_ALIVE3);
  7081. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  7082. /* 5 seconds timeout */
  7083. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
  7084. tg3_generate_fw_event(tp);
  7085. }
  7086. tp->asf_counter = tp->asf_multiplier;
  7087. }
  7088. spin_unlock(&tp->lock);
  7089. restart_timer:
  7090. tp->timer.expires = jiffies + tp->timer_offset;
  7091. add_timer(&tp->timer);
  7092. }
  7093. static int tg3_request_irq(struct tg3 *tp, int irq_num)
  7094. {
  7095. irq_handler_t fn;
  7096. unsigned long flags;
  7097. char *name;
  7098. struct tg3_napi *tnapi = &tp->napi[irq_num];
  7099. if (tp->irq_cnt == 1)
  7100. name = tp->dev->name;
  7101. else {
  7102. name = &tnapi->irq_lbl[0];
  7103. snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
  7104. name[IFNAMSIZ-1] = 0;
  7105. }
  7106. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
  7107. fn = tg3_msi;
  7108. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  7109. fn = tg3_msi_1shot;
  7110. flags = IRQF_SAMPLE_RANDOM;
  7111. } else {
  7112. fn = tg3_interrupt;
  7113. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  7114. fn = tg3_interrupt_tagged;
  7115. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  7116. }
  7117. return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
  7118. }
  7119. static int tg3_test_interrupt(struct tg3 *tp)
  7120. {
  7121. struct tg3_napi *tnapi = &tp->napi[0];
  7122. struct net_device *dev = tp->dev;
  7123. int err, i, intr_ok = 0;
  7124. u32 val;
  7125. if (!netif_running(dev))
  7126. return -ENODEV;
  7127. tg3_disable_ints(tp);
  7128. free_irq(tnapi->irq_vec, tnapi);
  7129. /*
  7130. * Turn off MSI one shot mode. Otherwise this test has no
  7131. * observable way to know whether the interrupt was delivered.
  7132. */
  7133. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  7134. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
  7135. (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
  7136. val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
  7137. tw32(MSGINT_MODE, val);
  7138. }
  7139. err = request_irq(tnapi->irq_vec, tg3_test_isr,
  7140. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
  7141. if (err)
  7142. return err;
  7143. tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
  7144. tg3_enable_ints(tp);
  7145. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7146. tnapi->coal_now);
  7147. for (i = 0; i < 5; i++) {
  7148. u32 int_mbox, misc_host_ctrl;
  7149. int_mbox = tr32_mailbox(tnapi->int_mbox);
  7150. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  7151. if ((int_mbox != 0) ||
  7152. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  7153. intr_ok = 1;
  7154. break;
  7155. }
  7156. msleep(10);
  7157. }
  7158. tg3_disable_ints(tp);
  7159. free_irq(tnapi->irq_vec, tnapi);
  7160. err = tg3_request_irq(tp, 0);
  7161. if (err)
  7162. return err;
  7163. if (intr_ok) {
  7164. /* Reenable MSI one shot mode. */
  7165. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  7166. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
  7167. (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
  7168. val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
  7169. tw32(MSGINT_MODE, val);
  7170. }
  7171. return 0;
  7172. }
  7173. return -EIO;
  7174. }
  7175. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  7176. * successfully restored
  7177. */
  7178. static int tg3_test_msi(struct tg3 *tp)
  7179. {
  7180. int err;
  7181. u16 pci_cmd;
  7182. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  7183. return 0;
  7184. /* Turn off SERR reporting in case MSI terminates with Master
  7185. * Abort.
  7186. */
  7187. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  7188. pci_write_config_word(tp->pdev, PCI_COMMAND,
  7189. pci_cmd & ~PCI_COMMAND_SERR);
  7190. err = tg3_test_interrupt(tp);
  7191. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  7192. if (!err)
  7193. return 0;
  7194. /* other failures */
  7195. if (err != -EIO)
  7196. return err;
  7197. /* MSI test failed, go back to INTx mode */
  7198. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  7199. "switching to INTx mode. Please report this failure to "
  7200. "the PCI maintainer and include system chipset information.\n",
  7201. tp->dev->name);
  7202. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  7203. pci_disable_msi(tp->pdev);
  7204. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  7205. err = tg3_request_irq(tp, 0);
  7206. if (err)
  7207. return err;
  7208. /* Need to reset the chip because the MSI cycle may have terminated
  7209. * with Master Abort.
  7210. */
  7211. tg3_full_lock(tp, 1);
  7212. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7213. err = tg3_init_hw(tp, 1);
  7214. tg3_full_unlock(tp);
  7215. if (err)
  7216. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  7217. return err;
  7218. }
  7219. static int tg3_request_firmware(struct tg3 *tp)
  7220. {
  7221. const __be32 *fw_data;
  7222. if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
  7223. printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
  7224. tp->dev->name, tp->fw_needed);
  7225. return -ENOENT;
  7226. }
  7227. fw_data = (void *)tp->fw->data;
  7228. /* Firmware blob starts with version numbers, followed by
  7229. * start address and _full_ length including BSS sections
  7230. * (which must be longer than the actual data, of course
  7231. */
  7232. tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
  7233. if (tp->fw_len < (tp->fw->size - 12)) {
  7234. printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
  7235. tp->dev->name, tp->fw_len, tp->fw_needed);
  7236. release_firmware(tp->fw);
  7237. tp->fw = NULL;
  7238. return -EINVAL;
  7239. }
  7240. /* We no longer need firmware; we have it. */
  7241. tp->fw_needed = NULL;
  7242. return 0;
  7243. }
  7244. static bool tg3_enable_msix(struct tg3 *tp)
  7245. {
  7246. int i, rc, cpus = num_online_cpus();
  7247. struct msix_entry msix_ent[tp->irq_max];
  7248. if (cpus == 1)
  7249. /* Just fallback to the simpler MSI mode. */
  7250. return false;
  7251. /*
  7252. * We want as many rx rings enabled as there are cpus.
  7253. * The first MSIX vector only deals with link interrupts, etc,
  7254. * so we add one to the number of vectors we are requesting.
  7255. */
  7256. tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
  7257. for (i = 0; i < tp->irq_max; i++) {
  7258. msix_ent[i].entry = i;
  7259. msix_ent[i].vector = 0;
  7260. }
  7261. rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
  7262. if (rc != 0) {
  7263. if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
  7264. return false;
  7265. if (pci_enable_msix(tp->pdev, msix_ent, rc))
  7266. return false;
  7267. printk(KERN_NOTICE
  7268. "%s: Requested %d MSI-X vectors, received %d\n",
  7269. tp->dev->name, tp->irq_cnt, rc);
  7270. tp->irq_cnt = rc;
  7271. }
  7272. tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
  7273. for (i = 0; i < tp->irq_max; i++)
  7274. tp->napi[i].irq_vec = msix_ent[i].vector;
  7275. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  7276. tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
  7277. tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
  7278. } else
  7279. tp->dev->real_num_tx_queues = 1;
  7280. return true;
  7281. }
  7282. static void tg3_ints_init(struct tg3 *tp)
  7283. {
  7284. if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
  7285. !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  7286. /* All MSI supporting chips should support tagged
  7287. * status. Assert that this is the case.
  7288. */
  7289. printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
  7290. "Not using MSI.\n", tp->dev->name);
  7291. goto defcfg;
  7292. }
  7293. if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
  7294. tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
  7295. else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
  7296. pci_enable_msi(tp->pdev) == 0)
  7297. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  7298. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
  7299. u32 msi_mode = tr32(MSGINT_MODE);
  7300. if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
  7301. msi_mode |= MSGINT_MODE_MULTIVEC_EN;
  7302. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  7303. }
  7304. defcfg:
  7305. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
  7306. tp->irq_cnt = 1;
  7307. tp->napi[0].irq_vec = tp->pdev->irq;
  7308. tp->dev->real_num_tx_queues = 1;
  7309. }
  7310. }
  7311. static void tg3_ints_fini(struct tg3 *tp)
  7312. {
  7313. if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
  7314. pci_disable_msix(tp->pdev);
  7315. else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
  7316. pci_disable_msi(tp->pdev);
  7317. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
  7318. tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
  7319. }
  7320. static int tg3_open(struct net_device *dev)
  7321. {
  7322. struct tg3 *tp = netdev_priv(dev);
  7323. int i, err;
  7324. if (tp->fw_needed) {
  7325. err = tg3_request_firmware(tp);
  7326. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  7327. if (err)
  7328. return err;
  7329. } else if (err) {
  7330. printk(KERN_WARNING "%s: TSO capability disabled.\n",
  7331. tp->dev->name);
  7332. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  7333. } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  7334. printk(KERN_NOTICE "%s: TSO capability restored.\n",
  7335. tp->dev->name);
  7336. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  7337. }
  7338. }
  7339. netif_carrier_off(tp->dev);
  7340. err = tg3_set_power_state(tp, PCI_D0);
  7341. if (err)
  7342. return err;
  7343. tg3_full_lock(tp, 0);
  7344. tg3_disable_ints(tp);
  7345. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  7346. tg3_full_unlock(tp);
  7347. /*
  7348. * Setup interrupts first so we know how
  7349. * many NAPI resources to allocate
  7350. */
  7351. tg3_ints_init(tp);
  7352. /* The placement of this call is tied
  7353. * to the setup and use of Host TX descriptors.
  7354. */
  7355. err = tg3_alloc_consistent(tp);
  7356. if (err)
  7357. goto err_out1;
  7358. tg3_napi_enable(tp);
  7359. for (i = 0; i < tp->irq_cnt; i++) {
  7360. struct tg3_napi *tnapi = &tp->napi[i];
  7361. err = tg3_request_irq(tp, i);
  7362. if (err) {
  7363. for (i--; i >= 0; i--)
  7364. free_irq(tnapi->irq_vec, tnapi);
  7365. break;
  7366. }
  7367. }
  7368. if (err)
  7369. goto err_out2;
  7370. tg3_full_lock(tp, 0);
  7371. err = tg3_init_hw(tp, 1);
  7372. if (err) {
  7373. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7374. tg3_free_rings(tp);
  7375. } else {
  7376. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  7377. tp->timer_offset = HZ;
  7378. else
  7379. tp->timer_offset = HZ / 10;
  7380. BUG_ON(tp->timer_offset > HZ);
  7381. tp->timer_counter = tp->timer_multiplier =
  7382. (HZ / tp->timer_offset);
  7383. tp->asf_counter = tp->asf_multiplier =
  7384. ((HZ / tp->timer_offset) * 2);
  7385. init_timer(&tp->timer);
  7386. tp->timer.expires = jiffies + tp->timer_offset;
  7387. tp->timer.data = (unsigned long) tp;
  7388. tp->timer.function = tg3_timer;
  7389. }
  7390. tg3_full_unlock(tp);
  7391. if (err)
  7392. goto err_out3;
  7393. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  7394. err = tg3_test_msi(tp);
  7395. if (err) {
  7396. tg3_full_lock(tp, 0);
  7397. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7398. tg3_free_rings(tp);
  7399. tg3_full_unlock(tp);
  7400. goto err_out2;
  7401. }
  7402. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
  7403. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
  7404. (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
  7405. (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
  7406. u32 val = tr32(PCIE_TRANSACTION_CFG);
  7407. tw32(PCIE_TRANSACTION_CFG,
  7408. val | PCIE_TRANS_CFG_1SHOT_MSI);
  7409. }
  7410. }
  7411. tg3_phy_start(tp);
  7412. tg3_full_lock(tp, 0);
  7413. add_timer(&tp->timer);
  7414. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  7415. tg3_enable_ints(tp);
  7416. tg3_full_unlock(tp);
  7417. netif_tx_start_all_queues(dev);
  7418. return 0;
  7419. err_out3:
  7420. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  7421. struct tg3_napi *tnapi = &tp->napi[i];
  7422. free_irq(tnapi->irq_vec, tnapi);
  7423. }
  7424. err_out2:
  7425. tg3_napi_disable(tp);
  7426. tg3_free_consistent(tp);
  7427. err_out1:
  7428. tg3_ints_fini(tp);
  7429. return err;
  7430. }
  7431. #if 0
  7432. /*static*/ void tg3_dump_state(struct tg3 *tp)
  7433. {
  7434. u32 val32, val32_2, val32_3, val32_4, val32_5;
  7435. u16 val16;
  7436. int i;
  7437. struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
  7438. pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  7439. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  7440. printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  7441. val16, val32);
  7442. /* MAC block */
  7443. printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  7444. tr32(MAC_MODE), tr32(MAC_STATUS));
  7445. printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  7446. tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  7447. printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  7448. tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  7449. printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  7450. tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  7451. /* Send data initiator control block */
  7452. printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  7453. tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  7454. printk(" SNDDATAI_STATSCTRL[%08x]\n",
  7455. tr32(SNDDATAI_STATSCTRL));
  7456. /* Send data completion control block */
  7457. printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  7458. /* Send BD ring selector block */
  7459. printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  7460. tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  7461. /* Send BD initiator control block */
  7462. printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  7463. tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  7464. /* Send BD completion control block */
  7465. printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  7466. /* Receive list placement control block */
  7467. printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  7468. tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  7469. printk(" RCVLPC_STATSCTRL[%08x]\n",
  7470. tr32(RCVLPC_STATSCTRL));
  7471. /* Receive data and receive BD initiator control block */
  7472. printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  7473. tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  7474. /* Receive data completion control block */
  7475. printk("DEBUG: RCVDCC_MODE[%08x]\n",
  7476. tr32(RCVDCC_MODE));
  7477. /* Receive BD initiator control block */
  7478. printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  7479. tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  7480. /* Receive BD completion control block */
  7481. printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  7482. tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  7483. /* Receive list selector control block */
  7484. printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  7485. tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  7486. /* Mbuf cluster free block */
  7487. printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  7488. tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  7489. /* Host coalescing control block */
  7490. printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  7491. tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  7492. printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  7493. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  7494. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  7495. printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  7496. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  7497. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  7498. printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  7499. tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  7500. printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  7501. tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  7502. /* Memory arbiter control block */
  7503. printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  7504. tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  7505. /* Buffer manager control block */
  7506. printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  7507. tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  7508. printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  7509. tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  7510. printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  7511. "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  7512. tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  7513. tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  7514. /* Read DMA control block */
  7515. printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  7516. tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  7517. /* Write DMA control block */
  7518. printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  7519. tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  7520. /* DMA completion block */
  7521. printk("DEBUG: DMAC_MODE[%08x]\n",
  7522. tr32(DMAC_MODE));
  7523. /* GRC block */
  7524. printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  7525. tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  7526. printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  7527. tr32(GRC_LOCAL_CTRL));
  7528. /* TG3_BDINFOs */
  7529. printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  7530. tr32(RCVDBDI_JUMBO_BD + 0x0),
  7531. tr32(RCVDBDI_JUMBO_BD + 0x4),
  7532. tr32(RCVDBDI_JUMBO_BD + 0x8),
  7533. tr32(RCVDBDI_JUMBO_BD + 0xc));
  7534. printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  7535. tr32(RCVDBDI_STD_BD + 0x0),
  7536. tr32(RCVDBDI_STD_BD + 0x4),
  7537. tr32(RCVDBDI_STD_BD + 0x8),
  7538. tr32(RCVDBDI_STD_BD + 0xc));
  7539. printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  7540. tr32(RCVDBDI_MINI_BD + 0x0),
  7541. tr32(RCVDBDI_MINI_BD + 0x4),
  7542. tr32(RCVDBDI_MINI_BD + 0x8),
  7543. tr32(RCVDBDI_MINI_BD + 0xc));
  7544. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  7545. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  7546. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  7547. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  7548. printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  7549. val32, val32_2, val32_3, val32_4);
  7550. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  7551. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  7552. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  7553. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  7554. printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  7555. val32, val32_2, val32_3, val32_4);
  7556. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  7557. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  7558. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  7559. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  7560. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  7561. printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  7562. val32, val32_2, val32_3, val32_4, val32_5);
  7563. /* SW status block */
  7564. printk(KERN_DEBUG
  7565. "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  7566. sblk->status,
  7567. sblk->status_tag,
  7568. sblk->rx_jumbo_consumer,
  7569. sblk->rx_consumer,
  7570. sblk->rx_mini_consumer,
  7571. sblk->idx[0].rx_producer,
  7572. sblk->idx[0].tx_consumer);
  7573. /* SW statistics block */
  7574. printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  7575. ((u32 *)tp->hw_stats)[0],
  7576. ((u32 *)tp->hw_stats)[1],
  7577. ((u32 *)tp->hw_stats)[2],
  7578. ((u32 *)tp->hw_stats)[3]);
  7579. /* Mailboxes */
  7580. printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  7581. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  7582. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  7583. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  7584. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  7585. /* NIC side send descriptors. */
  7586. for (i = 0; i < 6; i++) {
  7587. unsigned long txd;
  7588. txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  7589. + (i * sizeof(struct tg3_tx_buffer_desc));
  7590. printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  7591. i,
  7592. readl(txd + 0x0), readl(txd + 0x4),
  7593. readl(txd + 0x8), readl(txd + 0xc));
  7594. }
  7595. /* NIC side RX descriptors. */
  7596. for (i = 0; i < 6; i++) {
  7597. unsigned long rxd;
  7598. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  7599. + (i * sizeof(struct tg3_rx_buffer_desc));
  7600. printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  7601. i,
  7602. readl(rxd + 0x0), readl(rxd + 0x4),
  7603. readl(rxd + 0x8), readl(rxd + 0xc));
  7604. rxd += (4 * sizeof(u32));
  7605. printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  7606. i,
  7607. readl(rxd + 0x0), readl(rxd + 0x4),
  7608. readl(rxd + 0x8), readl(rxd + 0xc));
  7609. }
  7610. for (i = 0; i < 6; i++) {
  7611. unsigned long rxd;
  7612. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  7613. + (i * sizeof(struct tg3_rx_buffer_desc));
  7614. printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  7615. i,
  7616. readl(rxd + 0x0), readl(rxd + 0x4),
  7617. readl(rxd + 0x8), readl(rxd + 0xc));
  7618. rxd += (4 * sizeof(u32));
  7619. printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  7620. i,
  7621. readl(rxd + 0x0), readl(rxd + 0x4),
  7622. readl(rxd + 0x8), readl(rxd + 0xc));
  7623. }
  7624. }
  7625. #endif
  7626. static struct net_device_stats *tg3_get_stats(struct net_device *);
  7627. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  7628. static int tg3_close(struct net_device *dev)
  7629. {
  7630. int i;
  7631. struct tg3 *tp = netdev_priv(dev);
  7632. tg3_napi_disable(tp);
  7633. cancel_work_sync(&tp->reset_task);
  7634. netif_tx_stop_all_queues(dev);
  7635. del_timer_sync(&tp->timer);
  7636. tg3_phy_stop(tp);
  7637. tg3_full_lock(tp, 1);
  7638. #if 0
  7639. tg3_dump_state(tp);
  7640. #endif
  7641. tg3_disable_ints(tp);
  7642. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7643. tg3_free_rings(tp);
  7644. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  7645. tg3_full_unlock(tp);
  7646. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  7647. struct tg3_napi *tnapi = &tp->napi[i];
  7648. free_irq(tnapi->irq_vec, tnapi);
  7649. }
  7650. tg3_ints_fini(tp);
  7651. memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  7652. sizeof(tp->net_stats_prev));
  7653. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  7654. sizeof(tp->estats_prev));
  7655. tg3_free_consistent(tp);
  7656. tg3_set_power_state(tp, PCI_D3hot);
  7657. netif_carrier_off(tp->dev);
  7658. return 0;
  7659. }
  7660. static inline unsigned long get_stat64(tg3_stat64_t *val)
  7661. {
  7662. unsigned long ret;
  7663. #if (BITS_PER_LONG == 32)
  7664. ret = val->low;
  7665. #else
  7666. ret = ((u64)val->high << 32) | ((u64)val->low);
  7667. #endif
  7668. return ret;
  7669. }
  7670. static inline u64 get_estat64(tg3_stat64_t *val)
  7671. {
  7672. return ((u64)val->high << 32) | ((u64)val->low);
  7673. }
  7674. static unsigned long calc_crc_errors(struct tg3 *tp)
  7675. {
  7676. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7677. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  7678. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  7679. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  7680. u32 val;
  7681. spin_lock_bh(&tp->lock);
  7682. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  7683. tg3_writephy(tp, MII_TG3_TEST1,
  7684. val | MII_TG3_TEST1_CRC_EN);
  7685. tg3_readphy(tp, 0x14, &val);
  7686. } else
  7687. val = 0;
  7688. spin_unlock_bh(&tp->lock);
  7689. tp->phy_crc_errors += val;
  7690. return tp->phy_crc_errors;
  7691. }
  7692. return get_stat64(&hw_stats->rx_fcs_errors);
  7693. }
  7694. #define ESTAT_ADD(member) \
  7695. estats->member = old_estats->member + \
  7696. get_estat64(&hw_stats->member)
  7697. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  7698. {
  7699. struct tg3_ethtool_stats *estats = &tp->estats;
  7700. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  7701. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7702. if (!hw_stats)
  7703. return old_estats;
  7704. ESTAT_ADD(rx_octets);
  7705. ESTAT_ADD(rx_fragments);
  7706. ESTAT_ADD(rx_ucast_packets);
  7707. ESTAT_ADD(rx_mcast_packets);
  7708. ESTAT_ADD(rx_bcast_packets);
  7709. ESTAT_ADD(rx_fcs_errors);
  7710. ESTAT_ADD(rx_align_errors);
  7711. ESTAT_ADD(rx_xon_pause_rcvd);
  7712. ESTAT_ADD(rx_xoff_pause_rcvd);
  7713. ESTAT_ADD(rx_mac_ctrl_rcvd);
  7714. ESTAT_ADD(rx_xoff_entered);
  7715. ESTAT_ADD(rx_frame_too_long_errors);
  7716. ESTAT_ADD(rx_jabbers);
  7717. ESTAT_ADD(rx_undersize_packets);
  7718. ESTAT_ADD(rx_in_length_errors);
  7719. ESTAT_ADD(rx_out_length_errors);
  7720. ESTAT_ADD(rx_64_or_less_octet_packets);
  7721. ESTAT_ADD(rx_65_to_127_octet_packets);
  7722. ESTAT_ADD(rx_128_to_255_octet_packets);
  7723. ESTAT_ADD(rx_256_to_511_octet_packets);
  7724. ESTAT_ADD(rx_512_to_1023_octet_packets);
  7725. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  7726. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  7727. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  7728. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  7729. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  7730. ESTAT_ADD(tx_octets);
  7731. ESTAT_ADD(tx_collisions);
  7732. ESTAT_ADD(tx_xon_sent);
  7733. ESTAT_ADD(tx_xoff_sent);
  7734. ESTAT_ADD(tx_flow_control);
  7735. ESTAT_ADD(tx_mac_errors);
  7736. ESTAT_ADD(tx_single_collisions);
  7737. ESTAT_ADD(tx_mult_collisions);
  7738. ESTAT_ADD(tx_deferred);
  7739. ESTAT_ADD(tx_excessive_collisions);
  7740. ESTAT_ADD(tx_late_collisions);
  7741. ESTAT_ADD(tx_collide_2times);
  7742. ESTAT_ADD(tx_collide_3times);
  7743. ESTAT_ADD(tx_collide_4times);
  7744. ESTAT_ADD(tx_collide_5times);
  7745. ESTAT_ADD(tx_collide_6times);
  7746. ESTAT_ADD(tx_collide_7times);
  7747. ESTAT_ADD(tx_collide_8times);
  7748. ESTAT_ADD(tx_collide_9times);
  7749. ESTAT_ADD(tx_collide_10times);
  7750. ESTAT_ADD(tx_collide_11times);
  7751. ESTAT_ADD(tx_collide_12times);
  7752. ESTAT_ADD(tx_collide_13times);
  7753. ESTAT_ADD(tx_collide_14times);
  7754. ESTAT_ADD(tx_collide_15times);
  7755. ESTAT_ADD(tx_ucast_packets);
  7756. ESTAT_ADD(tx_mcast_packets);
  7757. ESTAT_ADD(tx_bcast_packets);
  7758. ESTAT_ADD(tx_carrier_sense_errors);
  7759. ESTAT_ADD(tx_discards);
  7760. ESTAT_ADD(tx_errors);
  7761. ESTAT_ADD(dma_writeq_full);
  7762. ESTAT_ADD(dma_write_prioq_full);
  7763. ESTAT_ADD(rxbds_empty);
  7764. ESTAT_ADD(rx_discards);
  7765. ESTAT_ADD(rx_errors);
  7766. ESTAT_ADD(rx_threshold_hit);
  7767. ESTAT_ADD(dma_readq_full);
  7768. ESTAT_ADD(dma_read_prioq_full);
  7769. ESTAT_ADD(tx_comp_queue_full);
  7770. ESTAT_ADD(ring_set_send_prod_index);
  7771. ESTAT_ADD(ring_status_update);
  7772. ESTAT_ADD(nic_irqs);
  7773. ESTAT_ADD(nic_avoided_irqs);
  7774. ESTAT_ADD(nic_tx_threshold_hit);
  7775. return estats;
  7776. }
  7777. static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  7778. {
  7779. struct tg3 *tp = netdev_priv(dev);
  7780. struct net_device_stats *stats = &tp->net_stats;
  7781. struct net_device_stats *old_stats = &tp->net_stats_prev;
  7782. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  7783. if (!hw_stats)
  7784. return old_stats;
  7785. stats->rx_packets = old_stats->rx_packets +
  7786. get_stat64(&hw_stats->rx_ucast_packets) +
  7787. get_stat64(&hw_stats->rx_mcast_packets) +
  7788. get_stat64(&hw_stats->rx_bcast_packets);
  7789. stats->tx_packets = old_stats->tx_packets +
  7790. get_stat64(&hw_stats->tx_ucast_packets) +
  7791. get_stat64(&hw_stats->tx_mcast_packets) +
  7792. get_stat64(&hw_stats->tx_bcast_packets);
  7793. stats->rx_bytes = old_stats->rx_bytes +
  7794. get_stat64(&hw_stats->rx_octets);
  7795. stats->tx_bytes = old_stats->tx_bytes +
  7796. get_stat64(&hw_stats->tx_octets);
  7797. stats->rx_errors = old_stats->rx_errors +
  7798. get_stat64(&hw_stats->rx_errors);
  7799. stats->tx_errors = old_stats->tx_errors +
  7800. get_stat64(&hw_stats->tx_errors) +
  7801. get_stat64(&hw_stats->tx_mac_errors) +
  7802. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  7803. get_stat64(&hw_stats->tx_discards);
  7804. stats->multicast = old_stats->multicast +
  7805. get_stat64(&hw_stats->rx_mcast_packets);
  7806. stats->collisions = old_stats->collisions +
  7807. get_stat64(&hw_stats->tx_collisions);
  7808. stats->rx_length_errors = old_stats->rx_length_errors +
  7809. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  7810. get_stat64(&hw_stats->rx_undersize_packets);
  7811. stats->rx_over_errors = old_stats->rx_over_errors +
  7812. get_stat64(&hw_stats->rxbds_empty);
  7813. stats->rx_frame_errors = old_stats->rx_frame_errors +
  7814. get_stat64(&hw_stats->rx_align_errors);
  7815. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  7816. get_stat64(&hw_stats->tx_discards);
  7817. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  7818. get_stat64(&hw_stats->tx_carrier_sense_errors);
  7819. stats->rx_crc_errors = old_stats->rx_crc_errors +
  7820. calc_crc_errors(tp);
  7821. stats->rx_missed_errors = old_stats->rx_missed_errors +
  7822. get_stat64(&hw_stats->rx_discards);
  7823. return stats;
  7824. }
  7825. static inline u32 calc_crc(unsigned char *buf, int len)
  7826. {
  7827. u32 reg;
  7828. u32 tmp;
  7829. int j, k;
  7830. reg = 0xffffffff;
  7831. for (j = 0; j < len; j++) {
  7832. reg ^= buf[j];
  7833. for (k = 0; k < 8; k++) {
  7834. tmp = reg & 0x01;
  7835. reg >>= 1;
  7836. if (tmp) {
  7837. reg ^= 0xedb88320;
  7838. }
  7839. }
  7840. }
  7841. return ~reg;
  7842. }
  7843. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  7844. {
  7845. /* accept or reject all multicast frames */
  7846. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  7847. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  7848. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  7849. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  7850. }
  7851. static void __tg3_set_rx_mode(struct net_device *dev)
  7852. {
  7853. struct tg3 *tp = netdev_priv(dev);
  7854. u32 rx_mode;
  7855. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7856. RX_MODE_KEEP_VLAN_TAG);
  7857. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7858. * flag clear.
  7859. */
  7860. #if TG3_VLAN_TAG_USED
  7861. if (!tp->vlgrp &&
  7862. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7863. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7864. #else
  7865. /* By definition, VLAN is disabled always in this
  7866. * case.
  7867. */
  7868. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7869. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7870. #endif
  7871. if (dev->flags & IFF_PROMISC) {
  7872. /* Promiscuous mode. */
  7873. rx_mode |= RX_MODE_PROMISC;
  7874. } else if (dev->flags & IFF_ALLMULTI) {
  7875. /* Accept all multicast. */
  7876. tg3_set_multi (tp, 1);
  7877. } else if (netdev_mc_empty(dev)) {
  7878. /* Reject all multicast. */
  7879. tg3_set_multi (tp, 0);
  7880. } else {
  7881. /* Accept one or more multicast(s). */
  7882. struct dev_mc_list *mclist;
  7883. unsigned int i;
  7884. u32 mc_filter[4] = { 0, };
  7885. u32 regidx;
  7886. u32 bit;
  7887. u32 crc;
  7888. for (i = 0, mclist = dev->mc_list; mclist && i < netdev_mc_count(dev);
  7889. i++, mclist = mclist->next) {
  7890. crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  7891. bit = ~crc & 0x7f;
  7892. regidx = (bit & 0x60) >> 5;
  7893. bit &= 0x1f;
  7894. mc_filter[regidx] |= (1 << bit);
  7895. }
  7896. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7897. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7898. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7899. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7900. }
  7901. if (rx_mode != tp->rx_mode) {
  7902. tp->rx_mode = rx_mode;
  7903. tw32_f(MAC_RX_MODE, rx_mode);
  7904. udelay(10);
  7905. }
  7906. }
  7907. static void tg3_set_rx_mode(struct net_device *dev)
  7908. {
  7909. struct tg3 *tp = netdev_priv(dev);
  7910. if (!netif_running(dev))
  7911. return;
  7912. tg3_full_lock(tp, 0);
  7913. __tg3_set_rx_mode(dev);
  7914. tg3_full_unlock(tp);
  7915. }
  7916. #define TG3_REGDUMP_LEN (32 * 1024)
  7917. static int tg3_get_regs_len(struct net_device *dev)
  7918. {
  7919. return TG3_REGDUMP_LEN;
  7920. }
  7921. static void tg3_get_regs(struct net_device *dev,
  7922. struct ethtool_regs *regs, void *_p)
  7923. {
  7924. u32 *p = _p;
  7925. struct tg3 *tp = netdev_priv(dev);
  7926. u8 *orig_p = _p;
  7927. int i;
  7928. regs->version = 0;
  7929. memset(p, 0, TG3_REGDUMP_LEN);
  7930. if (tp->link_config.phy_is_low_power)
  7931. return;
  7932. tg3_full_lock(tp, 0);
  7933. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  7934. #define GET_REG32_LOOP(base,len) \
  7935. do { p = (u32 *)(orig_p + (base)); \
  7936. for (i = 0; i < len; i += 4) \
  7937. __GET_REG32((base) + i); \
  7938. } while (0)
  7939. #define GET_REG32_1(reg) \
  7940. do { p = (u32 *)(orig_p + (reg)); \
  7941. __GET_REG32((reg)); \
  7942. } while (0)
  7943. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  7944. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  7945. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  7946. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  7947. GET_REG32_1(SNDDATAC_MODE);
  7948. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  7949. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  7950. GET_REG32_1(SNDBDC_MODE);
  7951. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  7952. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  7953. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  7954. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  7955. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  7956. GET_REG32_1(RCVDCC_MODE);
  7957. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  7958. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  7959. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  7960. GET_REG32_1(MBFREE_MODE);
  7961. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  7962. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  7963. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  7964. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  7965. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  7966. GET_REG32_1(RX_CPU_MODE);
  7967. GET_REG32_1(RX_CPU_STATE);
  7968. GET_REG32_1(RX_CPU_PGMCTR);
  7969. GET_REG32_1(RX_CPU_HWBKPT);
  7970. GET_REG32_1(TX_CPU_MODE);
  7971. GET_REG32_1(TX_CPU_STATE);
  7972. GET_REG32_1(TX_CPU_PGMCTR);
  7973. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  7974. GET_REG32_LOOP(FTQ_RESET, 0x120);
  7975. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  7976. GET_REG32_1(DMAC_MODE);
  7977. GET_REG32_LOOP(GRC_MODE, 0x4c);
  7978. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  7979. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  7980. #undef __GET_REG32
  7981. #undef GET_REG32_LOOP
  7982. #undef GET_REG32_1
  7983. tg3_full_unlock(tp);
  7984. }
  7985. static int tg3_get_eeprom_len(struct net_device *dev)
  7986. {
  7987. struct tg3 *tp = netdev_priv(dev);
  7988. return tp->nvram_size;
  7989. }
  7990. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7991. {
  7992. struct tg3 *tp = netdev_priv(dev);
  7993. int ret;
  7994. u8 *pd;
  7995. u32 i, offset, len, b_offset, b_count;
  7996. __be32 val;
  7997. if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
  7998. return -EINVAL;
  7999. if (tp->link_config.phy_is_low_power)
  8000. return -EAGAIN;
  8001. offset = eeprom->offset;
  8002. len = eeprom->len;
  8003. eeprom->len = 0;
  8004. eeprom->magic = TG3_EEPROM_MAGIC;
  8005. if (offset & 3) {
  8006. /* adjustments to start on required 4 byte boundary */
  8007. b_offset = offset & 3;
  8008. b_count = 4 - b_offset;
  8009. if (b_count > len) {
  8010. /* i.e. offset=1 len=2 */
  8011. b_count = len;
  8012. }
  8013. ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
  8014. if (ret)
  8015. return ret;
  8016. memcpy(data, ((char*)&val) + b_offset, b_count);
  8017. len -= b_count;
  8018. offset += b_count;
  8019. eeprom->len += b_count;
  8020. }
  8021. /* read bytes upto the last 4 byte boundary */
  8022. pd = &data[eeprom->len];
  8023. for (i = 0; i < (len - (len & 3)); i += 4) {
  8024. ret = tg3_nvram_read_be32(tp, offset + i, &val);
  8025. if (ret) {
  8026. eeprom->len += i;
  8027. return ret;
  8028. }
  8029. memcpy(pd + i, &val, 4);
  8030. }
  8031. eeprom->len += i;
  8032. if (len & 3) {
  8033. /* read last bytes not ending on 4 byte boundary */
  8034. pd = &data[eeprom->len];
  8035. b_count = len & 3;
  8036. b_offset = offset + len - b_count;
  8037. ret = tg3_nvram_read_be32(tp, b_offset, &val);
  8038. if (ret)
  8039. return ret;
  8040. memcpy(pd, &val, b_count);
  8041. eeprom->len += b_count;
  8042. }
  8043. return 0;
  8044. }
  8045. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  8046. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  8047. {
  8048. struct tg3 *tp = netdev_priv(dev);
  8049. int ret;
  8050. u32 offset, len, b_offset, odd_len;
  8051. u8 *buf;
  8052. __be32 start, end;
  8053. if (tp->link_config.phy_is_low_power)
  8054. return -EAGAIN;
  8055. if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
  8056. eeprom->magic != TG3_EEPROM_MAGIC)
  8057. return -EINVAL;
  8058. offset = eeprom->offset;
  8059. len = eeprom->len;
  8060. if ((b_offset = (offset & 3))) {
  8061. /* adjustments to start on required 4 byte boundary */
  8062. ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
  8063. if (ret)
  8064. return ret;
  8065. len += b_offset;
  8066. offset &= ~3;
  8067. if (len < 4)
  8068. len = 4;
  8069. }
  8070. odd_len = 0;
  8071. if (len & 3) {
  8072. /* adjustments to end on required 4 byte boundary */
  8073. odd_len = 1;
  8074. len = (len + 3) & ~3;
  8075. ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
  8076. if (ret)
  8077. return ret;
  8078. }
  8079. buf = data;
  8080. if (b_offset || odd_len) {
  8081. buf = kmalloc(len, GFP_KERNEL);
  8082. if (!buf)
  8083. return -ENOMEM;
  8084. if (b_offset)
  8085. memcpy(buf, &start, 4);
  8086. if (odd_len)
  8087. memcpy(buf+len-4, &end, 4);
  8088. memcpy(buf + b_offset, data, eeprom->len);
  8089. }
  8090. ret = tg3_nvram_write_block(tp, offset, len, buf);
  8091. if (buf != data)
  8092. kfree(buf);
  8093. return ret;
  8094. }
  8095. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  8096. {
  8097. struct tg3 *tp = netdev_priv(dev);
  8098. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8099. struct phy_device *phydev;
  8100. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  8101. return -EAGAIN;
  8102. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8103. return phy_ethtool_gset(phydev, cmd);
  8104. }
  8105. cmd->supported = (SUPPORTED_Autoneg);
  8106. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8107. cmd->supported |= (SUPPORTED_1000baseT_Half |
  8108. SUPPORTED_1000baseT_Full);
  8109. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  8110. cmd->supported |= (SUPPORTED_100baseT_Half |
  8111. SUPPORTED_100baseT_Full |
  8112. SUPPORTED_10baseT_Half |
  8113. SUPPORTED_10baseT_Full |
  8114. SUPPORTED_TP);
  8115. cmd->port = PORT_TP;
  8116. } else {
  8117. cmd->supported |= SUPPORTED_FIBRE;
  8118. cmd->port = PORT_FIBRE;
  8119. }
  8120. cmd->advertising = tp->link_config.advertising;
  8121. if (netif_running(dev)) {
  8122. cmd->speed = tp->link_config.active_speed;
  8123. cmd->duplex = tp->link_config.active_duplex;
  8124. }
  8125. cmd->phy_address = tp->phy_addr;
  8126. cmd->transceiver = XCVR_INTERNAL;
  8127. cmd->autoneg = tp->link_config.autoneg;
  8128. cmd->maxtxpkt = 0;
  8129. cmd->maxrxpkt = 0;
  8130. return 0;
  8131. }
  8132. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  8133. {
  8134. struct tg3 *tp = netdev_priv(dev);
  8135. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8136. struct phy_device *phydev;
  8137. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  8138. return -EAGAIN;
  8139. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8140. return phy_ethtool_sset(phydev, cmd);
  8141. }
  8142. if (cmd->autoneg != AUTONEG_ENABLE &&
  8143. cmd->autoneg != AUTONEG_DISABLE)
  8144. return -EINVAL;
  8145. if (cmd->autoneg == AUTONEG_DISABLE &&
  8146. cmd->duplex != DUPLEX_FULL &&
  8147. cmd->duplex != DUPLEX_HALF)
  8148. return -EINVAL;
  8149. if (cmd->autoneg == AUTONEG_ENABLE) {
  8150. u32 mask = ADVERTISED_Autoneg |
  8151. ADVERTISED_Pause |
  8152. ADVERTISED_Asym_Pause;
  8153. if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
  8154. mask |= ADVERTISED_1000baseT_Half |
  8155. ADVERTISED_1000baseT_Full;
  8156. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  8157. mask |= ADVERTISED_100baseT_Half |
  8158. ADVERTISED_100baseT_Full |
  8159. ADVERTISED_10baseT_Half |
  8160. ADVERTISED_10baseT_Full |
  8161. ADVERTISED_TP;
  8162. else
  8163. mask |= ADVERTISED_FIBRE;
  8164. if (cmd->advertising & ~mask)
  8165. return -EINVAL;
  8166. mask &= (ADVERTISED_1000baseT_Half |
  8167. ADVERTISED_1000baseT_Full |
  8168. ADVERTISED_100baseT_Half |
  8169. ADVERTISED_100baseT_Full |
  8170. ADVERTISED_10baseT_Half |
  8171. ADVERTISED_10baseT_Full);
  8172. cmd->advertising &= mask;
  8173. } else {
  8174. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
  8175. if (cmd->speed != SPEED_1000)
  8176. return -EINVAL;
  8177. if (cmd->duplex != DUPLEX_FULL)
  8178. return -EINVAL;
  8179. } else {
  8180. if (cmd->speed != SPEED_100 &&
  8181. cmd->speed != SPEED_10)
  8182. return -EINVAL;
  8183. }
  8184. }
  8185. tg3_full_lock(tp, 0);
  8186. tp->link_config.autoneg = cmd->autoneg;
  8187. if (cmd->autoneg == AUTONEG_ENABLE) {
  8188. tp->link_config.advertising = (cmd->advertising |
  8189. ADVERTISED_Autoneg);
  8190. tp->link_config.speed = SPEED_INVALID;
  8191. tp->link_config.duplex = DUPLEX_INVALID;
  8192. } else {
  8193. tp->link_config.advertising = 0;
  8194. tp->link_config.speed = cmd->speed;
  8195. tp->link_config.duplex = cmd->duplex;
  8196. }
  8197. tp->link_config.orig_speed = tp->link_config.speed;
  8198. tp->link_config.orig_duplex = tp->link_config.duplex;
  8199. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  8200. if (netif_running(dev))
  8201. tg3_setup_phy(tp, 1);
  8202. tg3_full_unlock(tp);
  8203. return 0;
  8204. }
  8205. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  8206. {
  8207. struct tg3 *tp = netdev_priv(dev);
  8208. strcpy(info->driver, DRV_MODULE_NAME);
  8209. strcpy(info->version, DRV_MODULE_VERSION);
  8210. strcpy(info->fw_version, tp->fw_ver);
  8211. strcpy(info->bus_info, pci_name(tp->pdev));
  8212. }
  8213. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  8214. {
  8215. struct tg3 *tp = netdev_priv(dev);
  8216. if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
  8217. device_can_wakeup(&tp->pdev->dev))
  8218. wol->supported = WAKE_MAGIC;
  8219. else
  8220. wol->supported = 0;
  8221. wol->wolopts = 0;
  8222. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  8223. device_can_wakeup(&tp->pdev->dev))
  8224. wol->wolopts = WAKE_MAGIC;
  8225. memset(&wol->sopass, 0, sizeof(wol->sopass));
  8226. }
  8227. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  8228. {
  8229. struct tg3 *tp = netdev_priv(dev);
  8230. struct device *dp = &tp->pdev->dev;
  8231. if (wol->wolopts & ~WAKE_MAGIC)
  8232. return -EINVAL;
  8233. if ((wol->wolopts & WAKE_MAGIC) &&
  8234. !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
  8235. return -EINVAL;
  8236. spin_lock_bh(&tp->lock);
  8237. if (wol->wolopts & WAKE_MAGIC) {
  8238. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  8239. device_set_wakeup_enable(dp, true);
  8240. } else {
  8241. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  8242. device_set_wakeup_enable(dp, false);
  8243. }
  8244. spin_unlock_bh(&tp->lock);
  8245. return 0;
  8246. }
  8247. static u32 tg3_get_msglevel(struct net_device *dev)
  8248. {
  8249. struct tg3 *tp = netdev_priv(dev);
  8250. return tp->msg_enable;
  8251. }
  8252. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  8253. {
  8254. struct tg3 *tp = netdev_priv(dev);
  8255. tp->msg_enable = value;
  8256. }
  8257. static int tg3_set_tso(struct net_device *dev, u32 value)
  8258. {
  8259. struct tg3 *tp = netdev_priv(dev);
  8260. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  8261. if (value)
  8262. return -EINVAL;
  8263. return 0;
  8264. }
  8265. if ((dev->features & NETIF_F_IPV6_CSUM) &&
  8266. ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
  8267. (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
  8268. if (value) {
  8269. dev->features |= NETIF_F_TSO6;
  8270. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
  8271. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  8272. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  8273. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  8274. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  8275. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  8276. dev->features |= NETIF_F_TSO_ECN;
  8277. } else
  8278. dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
  8279. }
  8280. return ethtool_op_set_tso(dev, value);
  8281. }
  8282. static int tg3_nway_reset(struct net_device *dev)
  8283. {
  8284. struct tg3 *tp = netdev_priv(dev);
  8285. int r;
  8286. if (!netif_running(dev))
  8287. return -EAGAIN;
  8288. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  8289. return -EINVAL;
  8290. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8291. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  8292. return -EAGAIN;
  8293. r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  8294. } else {
  8295. u32 bmcr;
  8296. spin_lock_bh(&tp->lock);
  8297. r = -EINVAL;
  8298. tg3_readphy(tp, MII_BMCR, &bmcr);
  8299. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  8300. ((bmcr & BMCR_ANENABLE) ||
  8301. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
  8302. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  8303. BMCR_ANENABLE);
  8304. r = 0;
  8305. }
  8306. spin_unlock_bh(&tp->lock);
  8307. }
  8308. return r;
  8309. }
  8310. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  8311. {
  8312. struct tg3 *tp = netdev_priv(dev);
  8313. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  8314. ering->rx_mini_max_pending = 0;
  8315. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  8316. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  8317. else
  8318. ering->rx_jumbo_max_pending = 0;
  8319. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  8320. ering->rx_pending = tp->rx_pending;
  8321. ering->rx_mini_pending = 0;
  8322. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  8323. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  8324. else
  8325. ering->rx_jumbo_pending = 0;
  8326. ering->tx_pending = tp->napi[0].tx_pending;
  8327. }
  8328. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  8329. {
  8330. struct tg3 *tp = netdev_priv(dev);
  8331. int i, irq_sync = 0, err = 0;
  8332. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  8333. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  8334. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  8335. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  8336. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  8337. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  8338. return -EINVAL;
  8339. if (netif_running(dev)) {
  8340. tg3_phy_stop(tp);
  8341. tg3_netif_stop(tp);
  8342. irq_sync = 1;
  8343. }
  8344. tg3_full_lock(tp, irq_sync);
  8345. tp->rx_pending = ering->rx_pending;
  8346. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  8347. tp->rx_pending > 63)
  8348. tp->rx_pending = 63;
  8349. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  8350. for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
  8351. tp->napi[i].tx_pending = ering->tx_pending;
  8352. if (netif_running(dev)) {
  8353. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8354. err = tg3_restart_hw(tp, 1);
  8355. if (!err)
  8356. tg3_netif_start(tp);
  8357. }
  8358. tg3_full_unlock(tp);
  8359. if (irq_sync && !err)
  8360. tg3_phy_start(tp);
  8361. return err;
  8362. }
  8363. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  8364. {
  8365. struct tg3 *tp = netdev_priv(dev);
  8366. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  8367. if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
  8368. epause->rx_pause = 1;
  8369. else
  8370. epause->rx_pause = 0;
  8371. if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
  8372. epause->tx_pause = 1;
  8373. else
  8374. epause->tx_pause = 0;
  8375. }
  8376. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  8377. {
  8378. struct tg3 *tp = netdev_priv(dev);
  8379. int err = 0;
  8380. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  8381. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  8382. return -EAGAIN;
  8383. if (epause->autoneg) {
  8384. u32 newadv;
  8385. struct phy_device *phydev;
  8386. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  8387. if (epause->rx_pause) {
  8388. if (epause->tx_pause)
  8389. newadv = ADVERTISED_Pause;
  8390. else
  8391. newadv = ADVERTISED_Pause |
  8392. ADVERTISED_Asym_Pause;
  8393. } else if (epause->tx_pause) {
  8394. newadv = ADVERTISED_Asym_Pause;
  8395. } else
  8396. newadv = 0;
  8397. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
  8398. u32 oldadv = phydev->advertising &
  8399. (ADVERTISED_Pause |
  8400. ADVERTISED_Asym_Pause);
  8401. if (oldadv != newadv) {
  8402. phydev->advertising &=
  8403. ~(ADVERTISED_Pause |
  8404. ADVERTISED_Asym_Pause);
  8405. phydev->advertising |= newadv;
  8406. err = phy_start_aneg(phydev);
  8407. }
  8408. } else {
  8409. tp->link_config.advertising &=
  8410. ~(ADVERTISED_Pause |
  8411. ADVERTISED_Asym_Pause);
  8412. tp->link_config.advertising |= newadv;
  8413. }
  8414. } else {
  8415. if (epause->rx_pause)
  8416. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  8417. else
  8418. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  8419. if (epause->tx_pause)
  8420. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8421. else
  8422. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  8423. if (netif_running(dev))
  8424. tg3_setup_flow_control(tp, 0, 0);
  8425. }
  8426. } else {
  8427. int irq_sync = 0;
  8428. if (netif_running(dev)) {
  8429. tg3_netif_stop(tp);
  8430. irq_sync = 1;
  8431. }
  8432. tg3_full_lock(tp, irq_sync);
  8433. if (epause->autoneg)
  8434. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  8435. else
  8436. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  8437. if (epause->rx_pause)
  8438. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  8439. else
  8440. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  8441. if (epause->tx_pause)
  8442. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  8443. else
  8444. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  8445. if (netif_running(dev)) {
  8446. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8447. err = tg3_restart_hw(tp, 1);
  8448. if (!err)
  8449. tg3_netif_start(tp);
  8450. }
  8451. tg3_full_unlock(tp);
  8452. }
  8453. return err;
  8454. }
  8455. static u32 tg3_get_rx_csum(struct net_device *dev)
  8456. {
  8457. struct tg3 *tp = netdev_priv(dev);
  8458. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  8459. }
  8460. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  8461. {
  8462. struct tg3 *tp = netdev_priv(dev);
  8463. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  8464. if (data != 0)
  8465. return -EINVAL;
  8466. return 0;
  8467. }
  8468. spin_lock_bh(&tp->lock);
  8469. if (data)
  8470. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  8471. else
  8472. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  8473. spin_unlock_bh(&tp->lock);
  8474. return 0;
  8475. }
  8476. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  8477. {
  8478. struct tg3 *tp = netdev_priv(dev);
  8479. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  8480. if (data != 0)
  8481. return -EINVAL;
  8482. return 0;
  8483. }
  8484. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  8485. ethtool_op_set_tx_ipv6_csum(dev, data);
  8486. else
  8487. ethtool_op_set_tx_csum(dev, data);
  8488. return 0;
  8489. }
  8490. static int tg3_get_sset_count (struct net_device *dev, int sset)
  8491. {
  8492. switch (sset) {
  8493. case ETH_SS_TEST:
  8494. return TG3_NUM_TEST;
  8495. case ETH_SS_STATS:
  8496. return TG3_NUM_STATS;
  8497. default:
  8498. return -EOPNOTSUPP;
  8499. }
  8500. }
  8501. static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
  8502. {
  8503. switch (stringset) {
  8504. case ETH_SS_STATS:
  8505. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  8506. break;
  8507. case ETH_SS_TEST:
  8508. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  8509. break;
  8510. default:
  8511. WARN_ON(1); /* we need a WARN() */
  8512. break;
  8513. }
  8514. }
  8515. static int tg3_phys_id(struct net_device *dev, u32 data)
  8516. {
  8517. struct tg3 *tp = netdev_priv(dev);
  8518. int i;
  8519. if (!netif_running(tp->dev))
  8520. return -EAGAIN;
  8521. if (data == 0)
  8522. data = UINT_MAX / 2;
  8523. for (i = 0; i < (data * 2); i++) {
  8524. if ((i % 2) == 0)
  8525. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  8526. LED_CTRL_1000MBPS_ON |
  8527. LED_CTRL_100MBPS_ON |
  8528. LED_CTRL_10MBPS_ON |
  8529. LED_CTRL_TRAFFIC_OVERRIDE |
  8530. LED_CTRL_TRAFFIC_BLINK |
  8531. LED_CTRL_TRAFFIC_LED);
  8532. else
  8533. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  8534. LED_CTRL_TRAFFIC_OVERRIDE);
  8535. if (msleep_interruptible(500))
  8536. break;
  8537. }
  8538. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8539. return 0;
  8540. }
  8541. static void tg3_get_ethtool_stats (struct net_device *dev,
  8542. struct ethtool_stats *estats, u64 *tmp_stats)
  8543. {
  8544. struct tg3 *tp = netdev_priv(dev);
  8545. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  8546. }
  8547. #define NVRAM_TEST_SIZE 0x100
  8548. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  8549. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  8550. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  8551. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  8552. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  8553. static int tg3_test_nvram(struct tg3 *tp)
  8554. {
  8555. u32 csum, magic;
  8556. __be32 *buf;
  8557. int i, j, k, err = 0, size;
  8558. if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
  8559. return 0;
  8560. if (tg3_nvram_read(tp, 0, &magic) != 0)
  8561. return -EIO;
  8562. if (magic == TG3_EEPROM_MAGIC)
  8563. size = NVRAM_TEST_SIZE;
  8564. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  8565. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  8566. TG3_EEPROM_SB_FORMAT_1) {
  8567. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  8568. case TG3_EEPROM_SB_REVISION_0:
  8569. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  8570. break;
  8571. case TG3_EEPROM_SB_REVISION_2:
  8572. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  8573. break;
  8574. case TG3_EEPROM_SB_REVISION_3:
  8575. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  8576. break;
  8577. default:
  8578. return 0;
  8579. }
  8580. } else
  8581. return 0;
  8582. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  8583. size = NVRAM_SELFBOOT_HW_SIZE;
  8584. else
  8585. return -EIO;
  8586. buf = kmalloc(size, GFP_KERNEL);
  8587. if (buf == NULL)
  8588. return -ENOMEM;
  8589. err = -EIO;
  8590. for (i = 0, j = 0; i < size; i += 4, j++) {
  8591. err = tg3_nvram_read_be32(tp, i, &buf[j]);
  8592. if (err)
  8593. break;
  8594. }
  8595. if (i < size)
  8596. goto out;
  8597. /* Selfboot format */
  8598. magic = be32_to_cpu(buf[0]);
  8599. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  8600. TG3_EEPROM_MAGIC_FW) {
  8601. u8 *buf8 = (u8 *) buf, csum8 = 0;
  8602. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  8603. TG3_EEPROM_SB_REVISION_2) {
  8604. /* For rev 2, the csum doesn't include the MBA. */
  8605. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  8606. csum8 += buf8[i];
  8607. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  8608. csum8 += buf8[i];
  8609. } else {
  8610. for (i = 0; i < size; i++)
  8611. csum8 += buf8[i];
  8612. }
  8613. if (csum8 == 0) {
  8614. err = 0;
  8615. goto out;
  8616. }
  8617. err = -EIO;
  8618. goto out;
  8619. }
  8620. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  8621. TG3_EEPROM_MAGIC_HW) {
  8622. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  8623. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  8624. u8 *buf8 = (u8 *) buf;
  8625. /* Separate the parity bits and the data bytes. */
  8626. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  8627. if ((i == 0) || (i == 8)) {
  8628. int l;
  8629. u8 msk;
  8630. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  8631. parity[k++] = buf8[i] & msk;
  8632. i++;
  8633. }
  8634. else if (i == 16) {
  8635. int l;
  8636. u8 msk;
  8637. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  8638. parity[k++] = buf8[i] & msk;
  8639. i++;
  8640. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  8641. parity[k++] = buf8[i] & msk;
  8642. i++;
  8643. }
  8644. data[j++] = buf8[i];
  8645. }
  8646. err = -EIO;
  8647. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  8648. u8 hw8 = hweight8(data[i]);
  8649. if ((hw8 & 0x1) && parity[i])
  8650. goto out;
  8651. else if (!(hw8 & 0x1) && !parity[i])
  8652. goto out;
  8653. }
  8654. err = 0;
  8655. goto out;
  8656. }
  8657. /* Bootstrap checksum at offset 0x10 */
  8658. csum = calc_crc((unsigned char *) buf, 0x10);
  8659. if (csum != be32_to_cpu(buf[0x10/4]))
  8660. goto out;
  8661. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  8662. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  8663. if (csum != be32_to_cpu(buf[0xfc/4]))
  8664. goto out;
  8665. err = 0;
  8666. out:
  8667. kfree(buf);
  8668. return err;
  8669. }
  8670. #define TG3_SERDES_TIMEOUT_SEC 2
  8671. #define TG3_COPPER_TIMEOUT_SEC 6
  8672. static int tg3_test_link(struct tg3 *tp)
  8673. {
  8674. int i, max;
  8675. if (!netif_running(tp->dev))
  8676. return -ENODEV;
  8677. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  8678. max = TG3_SERDES_TIMEOUT_SEC;
  8679. else
  8680. max = TG3_COPPER_TIMEOUT_SEC;
  8681. for (i = 0; i < max; i++) {
  8682. if (netif_carrier_ok(tp->dev))
  8683. return 0;
  8684. if (msleep_interruptible(1000))
  8685. break;
  8686. }
  8687. return -EIO;
  8688. }
  8689. /* Only test the commonly used registers */
  8690. static int tg3_test_registers(struct tg3 *tp)
  8691. {
  8692. int i, is_5705, is_5750;
  8693. u32 offset, read_mask, write_mask, val, save_val, read_val;
  8694. static struct {
  8695. u16 offset;
  8696. u16 flags;
  8697. #define TG3_FL_5705 0x1
  8698. #define TG3_FL_NOT_5705 0x2
  8699. #define TG3_FL_NOT_5788 0x4
  8700. #define TG3_FL_NOT_5750 0x8
  8701. u32 read_mask;
  8702. u32 write_mask;
  8703. } reg_tbl[] = {
  8704. /* MAC Control Registers */
  8705. { MAC_MODE, TG3_FL_NOT_5705,
  8706. 0x00000000, 0x00ef6f8c },
  8707. { MAC_MODE, TG3_FL_5705,
  8708. 0x00000000, 0x01ef6b8c },
  8709. { MAC_STATUS, TG3_FL_NOT_5705,
  8710. 0x03800107, 0x00000000 },
  8711. { MAC_STATUS, TG3_FL_5705,
  8712. 0x03800100, 0x00000000 },
  8713. { MAC_ADDR_0_HIGH, 0x0000,
  8714. 0x00000000, 0x0000ffff },
  8715. { MAC_ADDR_0_LOW, 0x0000,
  8716. 0x00000000, 0xffffffff },
  8717. { MAC_RX_MTU_SIZE, 0x0000,
  8718. 0x00000000, 0x0000ffff },
  8719. { MAC_TX_MODE, 0x0000,
  8720. 0x00000000, 0x00000070 },
  8721. { MAC_TX_LENGTHS, 0x0000,
  8722. 0x00000000, 0x00003fff },
  8723. { MAC_RX_MODE, TG3_FL_NOT_5705,
  8724. 0x00000000, 0x000007fc },
  8725. { MAC_RX_MODE, TG3_FL_5705,
  8726. 0x00000000, 0x000007dc },
  8727. { MAC_HASH_REG_0, 0x0000,
  8728. 0x00000000, 0xffffffff },
  8729. { MAC_HASH_REG_1, 0x0000,
  8730. 0x00000000, 0xffffffff },
  8731. { MAC_HASH_REG_2, 0x0000,
  8732. 0x00000000, 0xffffffff },
  8733. { MAC_HASH_REG_3, 0x0000,
  8734. 0x00000000, 0xffffffff },
  8735. /* Receive Data and Receive BD Initiator Control Registers. */
  8736. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  8737. 0x00000000, 0xffffffff },
  8738. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  8739. 0x00000000, 0xffffffff },
  8740. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  8741. 0x00000000, 0x00000003 },
  8742. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  8743. 0x00000000, 0xffffffff },
  8744. { RCVDBDI_STD_BD+0, 0x0000,
  8745. 0x00000000, 0xffffffff },
  8746. { RCVDBDI_STD_BD+4, 0x0000,
  8747. 0x00000000, 0xffffffff },
  8748. { RCVDBDI_STD_BD+8, 0x0000,
  8749. 0x00000000, 0xffff0002 },
  8750. { RCVDBDI_STD_BD+0xc, 0x0000,
  8751. 0x00000000, 0xffffffff },
  8752. /* Receive BD Initiator Control Registers. */
  8753. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  8754. 0x00000000, 0xffffffff },
  8755. { RCVBDI_STD_THRESH, TG3_FL_5705,
  8756. 0x00000000, 0x000003ff },
  8757. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  8758. 0x00000000, 0xffffffff },
  8759. /* Host Coalescing Control Registers. */
  8760. { HOSTCC_MODE, TG3_FL_NOT_5705,
  8761. 0x00000000, 0x00000004 },
  8762. { HOSTCC_MODE, TG3_FL_5705,
  8763. 0x00000000, 0x000000f6 },
  8764. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  8765. 0x00000000, 0xffffffff },
  8766. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  8767. 0x00000000, 0x000003ff },
  8768. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  8769. 0x00000000, 0xffffffff },
  8770. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  8771. 0x00000000, 0x000003ff },
  8772. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  8773. 0x00000000, 0xffffffff },
  8774. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  8775. 0x00000000, 0x000000ff },
  8776. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  8777. 0x00000000, 0xffffffff },
  8778. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  8779. 0x00000000, 0x000000ff },
  8780. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  8781. 0x00000000, 0xffffffff },
  8782. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  8783. 0x00000000, 0xffffffff },
  8784. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  8785. 0x00000000, 0xffffffff },
  8786. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  8787. 0x00000000, 0x000000ff },
  8788. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  8789. 0x00000000, 0xffffffff },
  8790. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  8791. 0x00000000, 0x000000ff },
  8792. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  8793. 0x00000000, 0xffffffff },
  8794. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  8795. 0x00000000, 0xffffffff },
  8796. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  8797. 0x00000000, 0xffffffff },
  8798. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  8799. 0x00000000, 0xffffffff },
  8800. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  8801. 0x00000000, 0xffffffff },
  8802. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  8803. 0xffffffff, 0x00000000 },
  8804. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  8805. 0xffffffff, 0x00000000 },
  8806. /* Buffer Manager Control Registers. */
  8807. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  8808. 0x00000000, 0x007fff80 },
  8809. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  8810. 0x00000000, 0x007fffff },
  8811. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  8812. 0x00000000, 0x0000003f },
  8813. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  8814. 0x00000000, 0x000001ff },
  8815. { BUFMGR_MB_HIGH_WATER, 0x0000,
  8816. 0x00000000, 0x000001ff },
  8817. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  8818. 0xffffffff, 0x00000000 },
  8819. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  8820. 0xffffffff, 0x00000000 },
  8821. /* Mailbox Registers */
  8822. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  8823. 0x00000000, 0x000001ff },
  8824. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  8825. 0x00000000, 0x000001ff },
  8826. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  8827. 0x00000000, 0x000007ff },
  8828. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  8829. 0x00000000, 0x000001ff },
  8830. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  8831. };
  8832. is_5705 = is_5750 = 0;
  8833. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  8834. is_5705 = 1;
  8835. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8836. is_5750 = 1;
  8837. }
  8838. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  8839. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  8840. continue;
  8841. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  8842. continue;
  8843. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  8844. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  8845. continue;
  8846. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  8847. continue;
  8848. offset = (u32) reg_tbl[i].offset;
  8849. read_mask = reg_tbl[i].read_mask;
  8850. write_mask = reg_tbl[i].write_mask;
  8851. /* Save the original register content */
  8852. save_val = tr32(offset);
  8853. /* Determine the read-only value. */
  8854. read_val = save_val & read_mask;
  8855. /* Write zero to the register, then make sure the read-only bits
  8856. * are not changed and the read/write bits are all zeros.
  8857. */
  8858. tw32(offset, 0);
  8859. val = tr32(offset);
  8860. /* Test the read-only and read/write bits. */
  8861. if (((val & read_mask) != read_val) || (val & write_mask))
  8862. goto out;
  8863. /* Write ones to all the bits defined by RdMask and WrMask, then
  8864. * make sure the read-only bits are not changed and the
  8865. * read/write bits are all ones.
  8866. */
  8867. tw32(offset, read_mask | write_mask);
  8868. val = tr32(offset);
  8869. /* Test the read-only bits. */
  8870. if ((val & read_mask) != read_val)
  8871. goto out;
  8872. /* Test the read/write bits. */
  8873. if ((val & write_mask) != write_mask)
  8874. goto out;
  8875. tw32(offset, save_val);
  8876. }
  8877. return 0;
  8878. out:
  8879. if (netif_msg_hw(tp))
  8880. printk(KERN_ERR PFX "Register test failed at offset %x\n",
  8881. offset);
  8882. tw32(offset, save_val);
  8883. return -EIO;
  8884. }
  8885. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  8886. {
  8887. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  8888. int i;
  8889. u32 j;
  8890. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  8891. for (j = 0; j < len; j += 4) {
  8892. u32 val;
  8893. tg3_write_mem(tp, offset + j, test_pattern[i]);
  8894. tg3_read_mem(tp, offset + j, &val);
  8895. if (val != test_pattern[i])
  8896. return -EIO;
  8897. }
  8898. }
  8899. return 0;
  8900. }
  8901. static int tg3_test_memory(struct tg3 *tp)
  8902. {
  8903. static struct mem_entry {
  8904. u32 offset;
  8905. u32 len;
  8906. } mem_tbl_570x[] = {
  8907. { 0x00000000, 0x00b50},
  8908. { 0x00002000, 0x1c000},
  8909. { 0xffffffff, 0x00000}
  8910. }, mem_tbl_5705[] = {
  8911. { 0x00000100, 0x0000c},
  8912. { 0x00000200, 0x00008},
  8913. { 0x00004000, 0x00800},
  8914. { 0x00006000, 0x01000},
  8915. { 0x00008000, 0x02000},
  8916. { 0x00010000, 0x0e000},
  8917. { 0xffffffff, 0x00000}
  8918. }, mem_tbl_5755[] = {
  8919. { 0x00000200, 0x00008},
  8920. { 0x00004000, 0x00800},
  8921. { 0x00006000, 0x00800},
  8922. { 0x00008000, 0x02000},
  8923. { 0x00010000, 0x0c000},
  8924. { 0xffffffff, 0x00000}
  8925. }, mem_tbl_5906[] = {
  8926. { 0x00000200, 0x00008},
  8927. { 0x00004000, 0x00400},
  8928. { 0x00006000, 0x00400},
  8929. { 0x00008000, 0x01000},
  8930. { 0x00010000, 0x01000},
  8931. { 0xffffffff, 0x00000}
  8932. }, mem_tbl_5717[] = {
  8933. { 0x00000200, 0x00008},
  8934. { 0x00010000, 0x0a000},
  8935. { 0x00020000, 0x13c00},
  8936. { 0xffffffff, 0x00000}
  8937. }, mem_tbl_57765[] = {
  8938. { 0x00000200, 0x00008},
  8939. { 0x00004000, 0x00800},
  8940. { 0x00006000, 0x09800},
  8941. { 0x00010000, 0x0a000},
  8942. { 0xffffffff, 0x00000}
  8943. };
  8944. struct mem_entry *mem_tbl;
  8945. int err = 0;
  8946. int i;
  8947. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  8948. mem_tbl = mem_tbl_5717;
  8949. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  8950. mem_tbl = mem_tbl_57765;
  8951. else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  8952. mem_tbl = mem_tbl_5755;
  8953. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8954. mem_tbl = mem_tbl_5906;
  8955. else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  8956. mem_tbl = mem_tbl_5705;
  8957. else
  8958. mem_tbl = mem_tbl_570x;
  8959. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  8960. if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
  8961. mem_tbl[i].len)) != 0)
  8962. break;
  8963. }
  8964. return err;
  8965. }
  8966. #define TG3_MAC_LOOPBACK 0
  8967. #define TG3_PHY_LOOPBACK 1
  8968. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  8969. {
  8970. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  8971. u32 desc_idx, coal_now;
  8972. struct sk_buff *skb, *rx_skb;
  8973. u8 *tx_data;
  8974. dma_addr_t map;
  8975. int num_pkts, tx_len, rx_len, i, err;
  8976. struct tg3_rx_buffer_desc *desc;
  8977. struct tg3_napi *tnapi, *rnapi;
  8978. struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
  8979. if (tp->irq_cnt > 1) {
  8980. tnapi = &tp->napi[1];
  8981. rnapi = &tp->napi[1];
  8982. } else {
  8983. tnapi = &tp->napi[0];
  8984. rnapi = &tp->napi[0];
  8985. }
  8986. coal_now = tnapi->coal_now | rnapi->coal_now;
  8987. if (loopback_mode == TG3_MAC_LOOPBACK) {
  8988. /* HW errata - mac loopback fails in some cases on 5780.
  8989. * Normal traffic and PHY loopback are not affected by
  8990. * errata.
  8991. */
  8992. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  8993. return 0;
  8994. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  8995. MAC_MODE_PORT_INT_LPBACK;
  8996. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  8997. mac_mode |= MAC_MODE_LINK_POLARITY;
  8998. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  8999. mac_mode |= MAC_MODE_PORT_MODE_MII;
  9000. else
  9001. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  9002. tw32(MAC_MODE, mac_mode);
  9003. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  9004. u32 val;
  9005. if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
  9006. tg3_phy_fet_toggle_apd(tp, false);
  9007. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  9008. } else
  9009. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  9010. tg3_phy_toggle_automdix(tp, 0);
  9011. tg3_writephy(tp, MII_BMCR, val);
  9012. udelay(40);
  9013. mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  9014. if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
  9015. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9016. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
  9017. mac_mode |= MAC_MODE_PORT_MODE_MII;
  9018. } else
  9019. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  9020. /* reset to prevent losing 1st rx packet intermittently */
  9021. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  9022. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  9023. udelay(10);
  9024. tw32_f(MAC_RX_MODE, tp->rx_mode);
  9025. }
  9026. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  9027. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
  9028. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  9029. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
  9030. mac_mode |= MAC_MODE_LINK_POLARITY;
  9031. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  9032. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  9033. }
  9034. tw32(MAC_MODE, mac_mode);
  9035. }
  9036. else
  9037. return -EINVAL;
  9038. err = -EIO;
  9039. tx_len = 1514;
  9040. skb = netdev_alloc_skb(tp->dev, tx_len);
  9041. if (!skb)
  9042. return -ENOMEM;
  9043. tx_data = skb_put(skb, tx_len);
  9044. memcpy(tx_data, tp->dev->dev_addr, 6);
  9045. memset(tx_data + 6, 0x0, 8);
  9046. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  9047. for (i = 14; i < tx_len; i++)
  9048. tx_data[i] = (u8) (i & 0xff);
  9049. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  9050. if (pci_dma_mapping_error(tp->pdev, map)) {
  9051. dev_kfree_skb(skb);
  9052. return -EIO;
  9053. }
  9054. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  9055. rnapi->coal_now);
  9056. udelay(10);
  9057. rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
  9058. num_pkts = 0;
  9059. tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
  9060. tnapi->tx_prod++;
  9061. num_pkts++;
  9062. tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
  9063. tr32_mailbox(tnapi->prodmbox);
  9064. udelay(10);
  9065. /* 350 usec to allow enough time on some 10/100 Mbps devices. */
  9066. for (i = 0; i < 35; i++) {
  9067. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  9068. coal_now);
  9069. udelay(10);
  9070. tx_idx = tnapi->hw_status->idx[0].tx_consumer;
  9071. rx_idx = rnapi->hw_status->idx[0].rx_producer;
  9072. if ((tx_idx == tnapi->tx_prod) &&
  9073. (rx_idx == (rx_start_idx + num_pkts)))
  9074. break;
  9075. }
  9076. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  9077. dev_kfree_skb(skb);
  9078. if (tx_idx != tnapi->tx_prod)
  9079. goto out;
  9080. if (rx_idx != rx_start_idx + num_pkts)
  9081. goto out;
  9082. desc = &rnapi->rx_rcb[rx_start_idx];
  9083. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  9084. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  9085. if (opaque_key != RXD_OPAQUE_RING_STD)
  9086. goto out;
  9087. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  9088. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  9089. goto out;
  9090. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  9091. if (rx_len != tx_len)
  9092. goto out;
  9093. rx_skb = tpr->rx_std_buffers[desc_idx].skb;
  9094. map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
  9095. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  9096. for (i = 14; i < tx_len; i++) {
  9097. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  9098. goto out;
  9099. }
  9100. err = 0;
  9101. /* tg3_free_rings will unmap and free the rx_skb */
  9102. out:
  9103. return err;
  9104. }
  9105. #define TG3_MAC_LOOPBACK_FAILED 1
  9106. #define TG3_PHY_LOOPBACK_FAILED 2
  9107. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  9108. TG3_PHY_LOOPBACK_FAILED)
  9109. static int tg3_test_loopback(struct tg3 *tp)
  9110. {
  9111. int err = 0;
  9112. u32 cpmuctrl = 0;
  9113. if (!netif_running(tp->dev))
  9114. return TG3_LOOPBACK_FAILED;
  9115. err = tg3_reset_hw(tp, 1);
  9116. if (err)
  9117. return TG3_LOOPBACK_FAILED;
  9118. /* Turn off gphy autopowerdown. */
  9119. if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
  9120. tg3_phy_toggle_apd(tp, false);
  9121. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
  9122. int i;
  9123. u32 status;
  9124. tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
  9125. /* Wait for up to 40 microseconds to acquire lock. */
  9126. for (i = 0; i < 4; i++) {
  9127. status = tr32(TG3_CPMU_MUTEX_GNT);
  9128. if (status == CPMU_MUTEX_GNT_DRIVER)
  9129. break;
  9130. udelay(10);
  9131. }
  9132. if (status != CPMU_MUTEX_GNT_DRIVER)
  9133. return TG3_LOOPBACK_FAILED;
  9134. /* Turn off link-based power management. */
  9135. cpmuctrl = tr32(TG3_CPMU_CTRL);
  9136. tw32(TG3_CPMU_CTRL,
  9137. cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
  9138. CPMU_CTRL_LINK_AWARE_MODE));
  9139. }
  9140. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  9141. err |= TG3_MAC_LOOPBACK_FAILED;
  9142. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
  9143. tw32(TG3_CPMU_CTRL, cpmuctrl);
  9144. /* Release the mutex */
  9145. tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
  9146. }
  9147. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  9148. !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
  9149. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  9150. err |= TG3_PHY_LOOPBACK_FAILED;
  9151. }
  9152. /* Re-enable gphy autopowerdown. */
  9153. if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
  9154. tg3_phy_toggle_apd(tp, true);
  9155. return err;
  9156. }
  9157. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  9158. u64 *data)
  9159. {
  9160. struct tg3 *tp = netdev_priv(dev);
  9161. if (tp->link_config.phy_is_low_power)
  9162. tg3_set_power_state(tp, PCI_D0);
  9163. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  9164. if (tg3_test_nvram(tp) != 0) {
  9165. etest->flags |= ETH_TEST_FL_FAILED;
  9166. data[0] = 1;
  9167. }
  9168. if (tg3_test_link(tp) != 0) {
  9169. etest->flags |= ETH_TEST_FL_FAILED;
  9170. data[1] = 1;
  9171. }
  9172. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  9173. int err, err2 = 0, irq_sync = 0;
  9174. if (netif_running(dev)) {
  9175. tg3_phy_stop(tp);
  9176. tg3_netif_stop(tp);
  9177. irq_sync = 1;
  9178. }
  9179. tg3_full_lock(tp, irq_sync);
  9180. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  9181. err = tg3_nvram_lock(tp);
  9182. tg3_halt_cpu(tp, RX_CPU_BASE);
  9183. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  9184. tg3_halt_cpu(tp, TX_CPU_BASE);
  9185. if (!err)
  9186. tg3_nvram_unlock(tp);
  9187. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  9188. tg3_phy_reset(tp);
  9189. if (tg3_test_registers(tp) != 0) {
  9190. etest->flags |= ETH_TEST_FL_FAILED;
  9191. data[2] = 1;
  9192. }
  9193. if (tg3_test_memory(tp) != 0) {
  9194. etest->flags |= ETH_TEST_FL_FAILED;
  9195. data[3] = 1;
  9196. }
  9197. if ((data[4] = tg3_test_loopback(tp)) != 0)
  9198. etest->flags |= ETH_TEST_FL_FAILED;
  9199. tg3_full_unlock(tp);
  9200. if (tg3_test_interrupt(tp) != 0) {
  9201. etest->flags |= ETH_TEST_FL_FAILED;
  9202. data[5] = 1;
  9203. }
  9204. tg3_full_lock(tp, 0);
  9205. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9206. if (netif_running(dev)) {
  9207. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  9208. err2 = tg3_restart_hw(tp, 1);
  9209. if (!err2)
  9210. tg3_netif_start(tp);
  9211. }
  9212. tg3_full_unlock(tp);
  9213. if (irq_sync && !err2)
  9214. tg3_phy_start(tp);
  9215. }
  9216. if (tp->link_config.phy_is_low_power)
  9217. tg3_set_power_state(tp, PCI_D3hot);
  9218. }
  9219. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  9220. {
  9221. struct mii_ioctl_data *data = if_mii(ifr);
  9222. struct tg3 *tp = netdev_priv(dev);
  9223. int err;
  9224. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  9225. struct phy_device *phydev;
  9226. if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
  9227. return -EAGAIN;
  9228. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9229. return phy_mii_ioctl(phydev, data, cmd);
  9230. }
  9231. switch(cmd) {
  9232. case SIOCGMIIPHY:
  9233. data->phy_id = tp->phy_addr;
  9234. /* fallthru */
  9235. case SIOCGMIIREG: {
  9236. u32 mii_regval;
  9237. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  9238. break; /* We have no PHY */
  9239. if (tp->link_config.phy_is_low_power)
  9240. return -EAGAIN;
  9241. spin_lock_bh(&tp->lock);
  9242. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  9243. spin_unlock_bh(&tp->lock);
  9244. data->val_out = mii_regval;
  9245. return err;
  9246. }
  9247. case SIOCSMIIREG:
  9248. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  9249. break; /* We have no PHY */
  9250. if (tp->link_config.phy_is_low_power)
  9251. return -EAGAIN;
  9252. spin_lock_bh(&tp->lock);
  9253. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  9254. spin_unlock_bh(&tp->lock);
  9255. return err;
  9256. default:
  9257. /* do nothing */
  9258. break;
  9259. }
  9260. return -EOPNOTSUPP;
  9261. }
  9262. #if TG3_VLAN_TAG_USED
  9263. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  9264. {
  9265. struct tg3 *tp = netdev_priv(dev);
  9266. if (!netif_running(dev)) {
  9267. tp->vlgrp = grp;
  9268. return;
  9269. }
  9270. tg3_netif_stop(tp);
  9271. tg3_full_lock(tp, 0);
  9272. tp->vlgrp = grp;
  9273. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  9274. __tg3_set_rx_mode(dev);
  9275. tg3_netif_start(tp);
  9276. tg3_full_unlock(tp);
  9277. }
  9278. #endif
  9279. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  9280. {
  9281. struct tg3 *tp = netdev_priv(dev);
  9282. memcpy(ec, &tp->coal, sizeof(*ec));
  9283. return 0;
  9284. }
  9285. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  9286. {
  9287. struct tg3 *tp = netdev_priv(dev);
  9288. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  9289. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  9290. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  9291. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  9292. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  9293. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  9294. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  9295. }
  9296. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  9297. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  9298. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  9299. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  9300. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  9301. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  9302. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  9303. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  9304. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  9305. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  9306. return -EINVAL;
  9307. /* No rx interrupts will be generated if both are zero */
  9308. if ((ec->rx_coalesce_usecs == 0) &&
  9309. (ec->rx_max_coalesced_frames == 0))
  9310. return -EINVAL;
  9311. /* No tx interrupts will be generated if both are zero */
  9312. if ((ec->tx_coalesce_usecs == 0) &&
  9313. (ec->tx_max_coalesced_frames == 0))
  9314. return -EINVAL;
  9315. /* Only copy relevant parameters, ignore all others. */
  9316. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  9317. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  9318. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  9319. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  9320. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  9321. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  9322. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  9323. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  9324. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  9325. if (netif_running(dev)) {
  9326. tg3_full_lock(tp, 0);
  9327. __tg3_set_coalesce(tp, &tp->coal);
  9328. tg3_full_unlock(tp);
  9329. }
  9330. return 0;
  9331. }
  9332. static const struct ethtool_ops tg3_ethtool_ops = {
  9333. .get_settings = tg3_get_settings,
  9334. .set_settings = tg3_set_settings,
  9335. .get_drvinfo = tg3_get_drvinfo,
  9336. .get_regs_len = tg3_get_regs_len,
  9337. .get_regs = tg3_get_regs,
  9338. .get_wol = tg3_get_wol,
  9339. .set_wol = tg3_set_wol,
  9340. .get_msglevel = tg3_get_msglevel,
  9341. .set_msglevel = tg3_set_msglevel,
  9342. .nway_reset = tg3_nway_reset,
  9343. .get_link = ethtool_op_get_link,
  9344. .get_eeprom_len = tg3_get_eeprom_len,
  9345. .get_eeprom = tg3_get_eeprom,
  9346. .set_eeprom = tg3_set_eeprom,
  9347. .get_ringparam = tg3_get_ringparam,
  9348. .set_ringparam = tg3_set_ringparam,
  9349. .get_pauseparam = tg3_get_pauseparam,
  9350. .set_pauseparam = tg3_set_pauseparam,
  9351. .get_rx_csum = tg3_get_rx_csum,
  9352. .set_rx_csum = tg3_set_rx_csum,
  9353. .set_tx_csum = tg3_set_tx_csum,
  9354. .set_sg = ethtool_op_set_sg,
  9355. .set_tso = tg3_set_tso,
  9356. .self_test = tg3_self_test,
  9357. .get_strings = tg3_get_strings,
  9358. .phys_id = tg3_phys_id,
  9359. .get_ethtool_stats = tg3_get_ethtool_stats,
  9360. .get_coalesce = tg3_get_coalesce,
  9361. .set_coalesce = tg3_set_coalesce,
  9362. .get_sset_count = tg3_get_sset_count,
  9363. };
  9364. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  9365. {
  9366. u32 cursize, val, magic;
  9367. tp->nvram_size = EEPROM_CHIP_SIZE;
  9368. if (tg3_nvram_read(tp, 0, &magic) != 0)
  9369. return;
  9370. if ((magic != TG3_EEPROM_MAGIC) &&
  9371. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  9372. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  9373. return;
  9374. /*
  9375. * Size the chip by reading offsets at increasing powers of two.
  9376. * When we encounter our validation signature, we know the addressing
  9377. * has wrapped around, and thus have our chip size.
  9378. */
  9379. cursize = 0x10;
  9380. while (cursize < tp->nvram_size) {
  9381. if (tg3_nvram_read(tp, cursize, &val) != 0)
  9382. return;
  9383. if (val == magic)
  9384. break;
  9385. cursize <<= 1;
  9386. }
  9387. tp->nvram_size = cursize;
  9388. }
  9389. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  9390. {
  9391. u32 val;
  9392. if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
  9393. tg3_nvram_read(tp, 0, &val) != 0)
  9394. return;
  9395. /* Selfboot format */
  9396. if (val != TG3_EEPROM_MAGIC) {
  9397. tg3_get_eeprom_size(tp);
  9398. return;
  9399. }
  9400. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  9401. if (val != 0) {
  9402. /* This is confusing. We want to operate on the
  9403. * 16-bit value at offset 0xf2. The tg3_nvram_read()
  9404. * call will read from NVRAM and byteswap the data
  9405. * according to the byteswapping settings for all
  9406. * other register accesses. This ensures the data we
  9407. * want will always reside in the lower 16-bits.
  9408. * However, the data in NVRAM is in LE format, which
  9409. * means the data from the NVRAM read will always be
  9410. * opposite the endianness of the CPU. The 16-bit
  9411. * byteswap then brings the data to CPU endianness.
  9412. */
  9413. tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
  9414. return;
  9415. }
  9416. }
  9417. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9418. }
  9419. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  9420. {
  9421. u32 nvcfg1;
  9422. nvcfg1 = tr32(NVRAM_CFG1);
  9423. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  9424. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9425. } else {
  9426. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9427. tw32(NVRAM_CFG1, nvcfg1);
  9428. }
  9429. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  9430. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9431. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  9432. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  9433. tp->nvram_jedecnum = JEDEC_ATMEL;
  9434. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  9435. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9436. break;
  9437. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  9438. tp->nvram_jedecnum = JEDEC_ATMEL;
  9439. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  9440. break;
  9441. case FLASH_VENDOR_ATMEL_EEPROM:
  9442. tp->nvram_jedecnum = JEDEC_ATMEL;
  9443. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9444. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9445. break;
  9446. case FLASH_VENDOR_ST:
  9447. tp->nvram_jedecnum = JEDEC_ST;
  9448. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  9449. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9450. break;
  9451. case FLASH_VENDOR_SAIFUN:
  9452. tp->nvram_jedecnum = JEDEC_SAIFUN;
  9453. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  9454. break;
  9455. case FLASH_VENDOR_SST_SMALL:
  9456. case FLASH_VENDOR_SST_LARGE:
  9457. tp->nvram_jedecnum = JEDEC_SST;
  9458. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  9459. break;
  9460. }
  9461. } else {
  9462. tp->nvram_jedecnum = JEDEC_ATMEL;
  9463. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  9464. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9465. }
  9466. }
  9467. static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
  9468. {
  9469. switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  9470. case FLASH_5752PAGE_SIZE_256:
  9471. tp->nvram_pagesize = 256;
  9472. break;
  9473. case FLASH_5752PAGE_SIZE_512:
  9474. tp->nvram_pagesize = 512;
  9475. break;
  9476. case FLASH_5752PAGE_SIZE_1K:
  9477. tp->nvram_pagesize = 1024;
  9478. break;
  9479. case FLASH_5752PAGE_SIZE_2K:
  9480. tp->nvram_pagesize = 2048;
  9481. break;
  9482. case FLASH_5752PAGE_SIZE_4K:
  9483. tp->nvram_pagesize = 4096;
  9484. break;
  9485. case FLASH_5752PAGE_SIZE_264:
  9486. tp->nvram_pagesize = 264;
  9487. break;
  9488. case FLASH_5752PAGE_SIZE_528:
  9489. tp->nvram_pagesize = 528;
  9490. break;
  9491. }
  9492. }
  9493. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  9494. {
  9495. u32 nvcfg1;
  9496. nvcfg1 = tr32(NVRAM_CFG1);
  9497. /* NVRAM protection for TPM */
  9498. if (nvcfg1 & (1 << 27))
  9499. tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
  9500. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9501. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  9502. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  9503. tp->nvram_jedecnum = JEDEC_ATMEL;
  9504. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9505. break;
  9506. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9507. tp->nvram_jedecnum = JEDEC_ATMEL;
  9508. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9509. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9510. break;
  9511. case FLASH_5752VENDOR_ST_M45PE10:
  9512. case FLASH_5752VENDOR_ST_M45PE20:
  9513. case FLASH_5752VENDOR_ST_M45PE40:
  9514. tp->nvram_jedecnum = JEDEC_ST;
  9515. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9516. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9517. break;
  9518. }
  9519. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  9520. tg3_nvram_get_pagesize(tp, nvcfg1);
  9521. } else {
  9522. /* For eeprom, set pagesize to maximum eeprom size */
  9523. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9524. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9525. tw32(NVRAM_CFG1, nvcfg1);
  9526. }
  9527. }
  9528. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  9529. {
  9530. u32 nvcfg1, protect = 0;
  9531. nvcfg1 = tr32(NVRAM_CFG1);
  9532. /* NVRAM protection for TPM */
  9533. if (nvcfg1 & (1 << 27)) {
  9534. tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
  9535. protect = 1;
  9536. }
  9537. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  9538. switch (nvcfg1) {
  9539. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  9540. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  9541. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  9542. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  9543. tp->nvram_jedecnum = JEDEC_ATMEL;
  9544. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9545. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9546. tp->nvram_pagesize = 264;
  9547. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  9548. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  9549. tp->nvram_size = (protect ? 0x3e200 :
  9550. TG3_NVRAM_SIZE_512KB);
  9551. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  9552. tp->nvram_size = (protect ? 0x1f200 :
  9553. TG3_NVRAM_SIZE_256KB);
  9554. else
  9555. tp->nvram_size = (protect ? 0x1f200 :
  9556. TG3_NVRAM_SIZE_128KB);
  9557. break;
  9558. case FLASH_5752VENDOR_ST_M45PE10:
  9559. case FLASH_5752VENDOR_ST_M45PE20:
  9560. case FLASH_5752VENDOR_ST_M45PE40:
  9561. tp->nvram_jedecnum = JEDEC_ST;
  9562. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9563. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9564. tp->nvram_pagesize = 256;
  9565. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  9566. tp->nvram_size = (protect ?
  9567. TG3_NVRAM_SIZE_64KB :
  9568. TG3_NVRAM_SIZE_128KB);
  9569. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  9570. tp->nvram_size = (protect ?
  9571. TG3_NVRAM_SIZE_64KB :
  9572. TG3_NVRAM_SIZE_256KB);
  9573. else
  9574. tp->nvram_size = (protect ?
  9575. TG3_NVRAM_SIZE_128KB :
  9576. TG3_NVRAM_SIZE_512KB);
  9577. break;
  9578. }
  9579. }
  9580. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  9581. {
  9582. u32 nvcfg1;
  9583. nvcfg1 = tr32(NVRAM_CFG1);
  9584. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9585. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  9586. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  9587. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  9588. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  9589. tp->nvram_jedecnum = JEDEC_ATMEL;
  9590. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9591. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9592. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9593. tw32(NVRAM_CFG1, nvcfg1);
  9594. break;
  9595. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9596. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  9597. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  9598. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  9599. tp->nvram_jedecnum = JEDEC_ATMEL;
  9600. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9601. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9602. tp->nvram_pagesize = 264;
  9603. break;
  9604. case FLASH_5752VENDOR_ST_M45PE10:
  9605. case FLASH_5752VENDOR_ST_M45PE20:
  9606. case FLASH_5752VENDOR_ST_M45PE40:
  9607. tp->nvram_jedecnum = JEDEC_ST;
  9608. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9609. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9610. tp->nvram_pagesize = 256;
  9611. break;
  9612. }
  9613. }
  9614. static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
  9615. {
  9616. u32 nvcfg1, protect = 0;
  9617. nvcfg1 = tr32(NVRAM_CFG1);
  9618. /* NVRAM protection for TPM */
  9619. if (nvcfg1 & (1 << 27)) {
  9620. tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
  9621. protect = 1;
  9622. }
  9623. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  9624. switch (nvcfg1) {
  9625. case FLASH_5761VENDOR_ATMEL_ADB021D:
  9626. case FLASH_5761VENDOR_ATMEL_ADB041D:
  9627. case FLASH_5761VENDOR_ATMEL_ADB081D:
  9628. case FLASH_5761VENDOR_ATMEL_ADB161D:
  9629. case FLASH_5761VENDOR_ATMEL_MDB021D:
  9630. case FLASH_5761VENDOR_ATMEL_MDB041D:
  9631. case FLASH_5761VENDOR_ATMEL_MDB081D:
  9632. case FLASH_5761VENDOR_ATMEL_MDB161D:
  9633. tp->nvram_jedecnum = JEDEC_ATMEL;
  9634. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9635. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9636. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9637. tp->nvram_pagesize = 256;
  9638. break;
  9639. case FLASH_5761VENDOR_ST_A_M45PE20:
  9640. case FLASH_5761VENDOR_ST_A_M45PE40:
  9641. case FLASH_5761VENDOR_ST_A_M45PE80:
  9642. case FLASH_5761VENDOR_ST_A_M45PE16:
  9643. case FLASH_5761VENDOR_ST_M_M45PE20:
  9644. case FLASH_5761VENDOR_ST_M_M45PE40:
  9645. case FLASH_5761VENDOR_ST_M_M45PE80:
  9646. case FLASH_5761VENDOR_ST_M_M45PE16:
  9647. tp->nvram_jedecnum = JEDEC_ST;
  9648. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9649. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9650. tp->nvram_pagesize = 256;
  9651. break;
  9652. }
  9653. if (protect) {
  9654. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  9655. } else {
  9656. switch (nvcfg1) {
  9657. case FLASH_5761VENDOR_ATMEL_ADB161D:
  9658. case FLASH_5761VENDOR_ATMEL_MDB161D:
  9659. case FLASH_5761VENDOR_ST_A_M45PE16:
  9660. case FLASH_5761VENDOR_ST_M_M45PE16:
  9661. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  9662. break;
  9663. case FLASH_5761VENDOR_ATMEL_ADB081D:
  9664. case FLASH_5761VENDOR_ATMEL_MDB081D:
  9665. case FLASH_5761VENDOR_ST_A_M45PE80:
  9666. case FLASH_5761VENDOR_ST_M_M45PE80:
  9667. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  9668. break;
  9669. case FLASH_5761VENDOR_ATMEL_ADB041D:
  9670. case FLASH_5761VENDOR_ATMEL_MDB041D:
  9671. case FLASH_5761VENDOR_ST_A_M45PE40:
  9672. case FLASH_5761VENDOR_ST_M_M45PE40:
  9673. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9674. break;
  9675. case FLASH_5761VENDOR_ATMEL_ADB021D:
  9676. case FLASH_5761VENDOR_ATMEL_MDB021D:
  9677. case FLASH_5761VENDOR_ST_A_M45PE20:
  9678. case FLASH_5761VENDOR_ST_M_M45PE20:
  9679. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9680. break;
  9681. }
  9682. }
  9683. }
  9684. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  9685. {
  9686. tp->nvram_jedecnum = JEDEC_ATMEL;
  9687. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9688. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9689. }
  9690. static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
  9691. {
  9692. u32 nvcfg1;
  9693. nvcfg1 = tr32(NVRAM_CFG1);
  9694. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9695. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  9696. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  9697. tp->nvram_jedecnum = JEDEC_ATMEL;
  9698. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9699. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9700. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9701. tw32(NVRAM_CFG1, nvcfg1);
  9702. return;
  9703. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9704. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  9705. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  9706. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  9707. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  9708. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  9709. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  9710. tp->nvram_jedecnum = JEDEC_ATMEL;
  9711. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9712. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9713. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9714. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  9715. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  9716. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  9717. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9718. break;
  9719. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  9720. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  9721. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9722. break;
  9723. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  9724. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  9725. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9726. break;
  9727. }
  9728. break;
  9729. case FLASH_5752VENDOR_ST_M45PE10:
  9730. case FLASH_5752VENDOR_ST_M45PE20:
  9731. case FLASH_5752VENDOR_ST_M45PE40:
  9732. tp->nvram_jedecnum = JEDEC_ST;
  9733. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9734. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9735. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9736. case FLASH_5752VENDOR_ST_M45PE10:
  9737. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9738. break;
  9739. case FLASH_5752VENDOR_ST_M45PE20:
  9740. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9741. break;
  9742. case FLASH_5752VENDOR_ST_M45PE40:
  9743. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  9744. break;
  9745. }
  9746. break;
  9747. default:
  9748. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
  9749. return;
  9750. }
  9751. tg3_nvram_get_pagesize(tp, nvcfg1);
  9752. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  9753. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9754. }
  9755. static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
  9756. {
  9757. u32 nvcfg1;
  9758. nvcfg1 = tr32(NVRAM_CFG1);
  9759. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9760. case FLASH_5717VENDOR_ATMEL_EEPROM:
  9761. case FLASH_5717VENDOR_MICRO_EEPROM:
  9762. tp->nvram_jedecnum = JEDEC_ATMEL;
  9763. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9764. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  9765. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  9766. tw32(NVRAM_CFG1, nvcfg1);
  9767. return;
  9768. case FLASH_5717VENDOR_ATMEL_MDB011D:
  9769. case FLASH_5717VENDOR_ATMEL_ADB011B:
  9770. case FLASH_5717VENDOR_ATMEL_ADB011D:
  9771. case FLASH_5717VENDOR_ATMEL_MDB021D:
  9772. case FLASH_5717VENDOR_ATMEL_ADB021B:
  9773. case FLASH_5717VENDOR_ATMEL_ADB021D:
  9774. case FLASH_5717VENDOR_ATMEL_45USPT:
  9775. tp->nvram_jedecnum = JEDEC_ATMEL;
  9776. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9777. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9778. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9779. case FLASH_5717VENDOR_ATMEL_MDB021D:
  9780. case FLASH_5717VENDOR_ATMEL_ADB021B:
  9781. case FLASH_5717VENDOR_ATMEL_ADB021D:
  9782. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9783. break;
  9784. default:
  9785. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9786. break;
  9787. }
  9788. break;
  9789. case FLASH_5717VENDOR_ST_M_M25PE10:
  9790. case FLASH_5717VENDOR_ST_A_M25PE10:
  9791. case FLASH_5717VENDOR_ST_M_M45PE10:
  9792. case FLASH_5717VENDOR_ST_A_M45PE10:
  9793. case FLASH_5717VENDOR_ST_M_M25PE20:
  9794. case FLASH_5717VENDOR_ST_A_M25PE20:
  9795. case FLASH_5717VENDOR_ST_M_M45PE20:
  9796. case FLASH_5717VENDOR_ST_A_M45PE20:
  9797. case FLASH_5717VENDOR_ST_25USPT:
  9798. case FLASH_5717VENDOR_ST_45USPT:
  9799. tp->nvram_jedecnum = JEDEC_ST;
  9800. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  9801. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  9802. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  9803. case FLASH_5717VENDOR_ST_M_M25PE20:
  9804. case FLASH_5717VENDOR_ST_A_M25PE20:
  9805. case FLASH_5717VENDOR_ST_M_M45PE20:
  9806. case FLASH_5717VENDOR_ST_A_M45PE20:
  9807. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  9808. break;
  9809. default:
  9810. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  9811. break;
  9812. }
  9813. break;
  9814. default:
  9815. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
  9816. return;
  9817. }
  9818. tg3_nvram_get_pagesize(tp, nvcfg1);
  9819. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  9820. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  9821. }
  9822. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  9823. static void __devinit tg3_nvram_init(struct tg3 *tp)
  9824. {
  9825. tw32_f(GRC_EEPROM_ADDR,
  9826. (EEPROM_ADDR_FSM_RESET |
  9827. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  9828. EEPROM_ADDR_CLKPERD_SHIFT)));
  9829. msleep(1);
  9830. /* Enable seeprom accesses. */
  9831. tw32_f(GRC_LOCAL_CTRL,
  9832. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  9833. udelay(100);
  9834. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9835. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  9836. tp->tg3_flags |= TG3_FLAG_NVRAM;
  9837. if (tg3_nvram_lock(tp)) {
  9838. printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
  9839. "tg3_nvram_init failed.\n", tp->dev->name);
  9840. return;
  9841. }
  9842. tg3_enable_nvram_access(tp);
  9843. tp->nvram_size = 0;
  9844. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9845. tg3_get_5752_nvram_info(tp);
  9846. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9847. tg3_get_5755_nvram_info(tp);
  9848. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9849. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9850. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  9851. tg3_get_5787_nvram_info(tp);
  9852. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  9853. tg3_get_5761_nvram_info(tp);
  9854. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9855. tg3_get_5906_nvram_info(tp);
  9856. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  9857. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  9858. tg3_get_57780_nvram_info(tp);
  9859. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  9860. tg3_get_5717_nvram_info(tp);
  9861. else
  9862. tg3_get_nvram_info(tp);
  9863. if (tp->nvram_size == 0)
  9864. tg3_get_nvram_size(tp);
  9865. tg3_disable_nvram_access(tp);
  9866. tg3_nvram_unlock(tp);
  9867. } else {
  9868. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  9869. tg3_get_eeprom_size(tp);
  9870. }
  9871. }
  9872. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  9873. u32 offset, u32 len, u8 *buf)
  9874. {
  9875. int i, j, rc = 0;
  9876. u32 val;
  9877. for (i = 0; i < len; i += 4) {
  9878. u32 addr;
  9879. __be32 data;
  9880. addr = offset + i;
  9881. memcpy(&data, buf + i, 4);
  9882. /*
  9883. * The SEEPROM interface expects the data to always be opposite
  9884. * the native endian format. We accomplish this by reversing
  9885. * all the operations that would have been performed on the
  9886. * data from a call to tg3_nvram_read_be32().
  9887. */
  9888. tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
  9889. val = tr32(GRC_EEPROM_ADDR);
  9890. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  9891. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  9892. EEPROM_ADDR_READ);
  9893. tw32(GRC_EEPROM_ADDR, val |
  9894. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  9895. (addr & EEPROM_ADDR_ADDR_MASK) |
  9896. EEPROM_ADDR_START |
  9897. EEPROM_ADDR_WRITE);
  9898. for (j = 0; j < 1000; j++) {
  9899. val = tr32(GRC_EEPROM_ADDR);
  9900. if (val & EEPROM_ADDR_COMPLETE)
  9901. break;
  9902. msleep(1);
  9903. }
  9904. if (!(val & EEPROM_ADDR_COMPLETE)) {
  9905. rc = -EBUSY;
  9906. break;
  9907. }
  9908. }
  9909. return rc;
  9910. }
  9911. /* offset and length are dword aligned */
  9912. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  9913. u8 *buf)
  9914. {
  9915. int ret = 0;
  9916. u32 pagesize = tp->nvram_pagesize;
  9917. u32 pagemask = pagesize - 1;
  9918. u32 nvram_cmd;
  9919. u8 *tmp;
  9920. tmp = kmalloc(pagesize, GFP_KERNEL);
  9921. if (tmp == NULL)
  9922. return -ENOMEM;
  9923. while (len) {
  9924. int j;
  9925. u32 phy_addr, page_off, size;
  9926. phy_addr = offset & ~pagemask;
  9927. for (j = 0; j < pagesize; j += 4) {
  9928. ret = tg3_nvram_read_be32(tp, phy_addr + j,
  9929. (__be32 *) (tmp + j));
  9930. if (ret)
  9931. break;
  9932. }
  9933. if (ret)
  9934. break;
  9935. page_off = offset & pagemask;
  9936. size = pagesize;
  9937. if (len < size)
  9938. size = len;
  9939. len -= size;
  9940. memcpy(tmp + page_off, buf, size);
  9941. offset = offset + (pagesize - page_off);
  9942. tg3_enable_nvram_access(tp);
  9943. /*
  9944. * Before we can erase the flash page, we need
  9945. * to issue a special "write enable" command.
  9946. */
  9947. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9948. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9949. break;
  9950. /* Erase the target page */
  9951. tw32(NVRAM_ADDR, phy_addr);
  9952. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  9953. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  9954. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9955. break;
  9956. /* Issue another write enable to start the write. */
  9957. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9958. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  9959. break;
  9960. for (j = 0; j < pagesize; j += 4) {
  9961. __be32 data;
  9962. data = *((__be32 *) (tmp + j));
  9963. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  9964. tw32(NVRAM_ADDR, phy_addr + j);
  9965. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  9966. NVRAM_CMD_WR;
  9967. if (j == 0)
  9968. nvram_cmd |= NVRAM_CMD_FIRST;
  9969. else if (j == (pagesize - 4))
  9970. nvram_cmd |= NVRAM_CMD_LAST;
  9971. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  9972. break;
  9973. }
  9974. if (ret)
  9975. break;
  9976. }
  9977. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  9978. tg3_nvram_exec_cmd(tp, nvram_cmd);
  9979. kfree(tmp);
  9980. return ret;
  9981. }
  9982. /* offset and length are dword aligned */
  9983. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  9984. u8 *buf)
  9985. {
  9986. int i, ret = 0;
  9987. for (i = 0; i < len; i += 4, offset += 4) {
  9988. u32 page_off, phy_addr, nvram_cmd;
  9989. __be32 data;
  9990. memcpy(&data, buf + i, 4);
  9991. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  9992. page_off = offset % tp->nvram_pagesize;
  9993. phy_addr = tg3_nvram_phys_addr(tp, offset);
  9994. tw32(NVRAM_ADDR, phy_addr);
  9995. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  9996. if ((page_off == 0) || (i == 0))
  9997. nvram_cmd |= NVRAM_CMD_FIRST;
  9998. if (page_off == (tp->nvram_pagesize - 4))
  9999. nvram_cmd |= NVRAM_CMD_LAST;
  10000. if (i == (len - 4))
  10001. nvram_cmd |= NVRAM_CMD_LAST;
  10002. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  10003. !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
  10004. (tp->nvram_jedecnum == JEDEC_ST) &&
  10005. (nvram_cmd & NVRAM_CMD_FIRST)) {
  10006. if ((ret = tg3_nvram_exec_cmd(tp,
  10007. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  10008. NVRAM_CMD_DONE)))
  10009. break;
  10010. }
  10011. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  10012. /* We always do complete word writes to eeprom. */
  10013. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  10014. }
  10015. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  10016. break;
  10017. }
  10018. return ret;
  10019. }
  10020. /* offset and length are dword aligned */
  10021. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  10022. {
  10023. int ret;
  10024. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  10025. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  10026. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  10027. udelay(40);
  10028. }
  10029. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  10030. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  10031. }
  10032. else {
  10033. u32 grc_mode;
  10034. ret = tg3_nvram_lock(tp);
  10035. if (ret)
  10036. return ret;
  10037. tg3_enable_nvram_access(tp);
  10038. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  10039. !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
  10040. tw32(NVRAM_WRITE1, 0x406);
  10041. grc_mode = tr32(GRC_MODE);
  10042. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  10043. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  10044. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  10045. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  10046. buf);
  10047. }
  10048. else {
  10049. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  10050. buf);
  10051. }
  10052. grc_mode = tr32(GRC_MODE);
  10053. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  10054. tg3_disable_nvram_access(tp);
  10055. tg3_nvram_unlock(tp);
  10056. }
  10057. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  10058. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  10059. udelay(40);
  10060. }
  10061. return ret;
  10062. }
  10063. struct subsys_tbl_ent {
  10064. u16 subsys_vendor, subsys_devid;
  10065. u32 phy_id;
  10066. };
  10067. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  10068. /* Broadcom boards. */
  10069. { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  10070. { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  10071. { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  10072. { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
  10073. { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  10074. { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  10075. { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
  10076. { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  10077. { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  10078. { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
  10079. { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
  10080. /* 3com boards. */
  10081. { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  10082. { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  10083. { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
  10084. { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  10085. { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  10086. /* DELL boards. */
  10087. { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  10088. { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  10089. { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  10090. { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  10091. /* Compaq boards. */
  10092. { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  10093. { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  10094. { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
  10095. { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  10096. { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
  10097. /* IBM boards. */
  10098. { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
  10099. };
  10100. static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
  10101. {
  10102. int i;
  10103. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  10104. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  10105. tp->pdev->subsystem_vendor) &&
  10106. (subsys_id_to_phy_id[i].subsys_devid ==
  10107. tp->pdev->subsystem_device))
  10108. return &subsys_id_to_phy_id[i];
  10109. }
  10110. return NULL;
  10111. }
  10112. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  10113. {
  10114. u32 val;
  10115. u16 pmcsr;
  10116. /* On some early chips the SRAM cannot be accessed in D3hot state,
  10117. * so need make sure we're in D0.
  10118. */
  10119. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  10120. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  10121. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  10122. msleep(1);
  10123. /* Make sure register accesses (indirect or otherwise)
  10124. * will function correctly.
  10125. */
  10126. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10127. tp->misc_host_ctrl);
  10128. /* The memory arbiter has to be enabled in order for SRAM accesses
  10129. * to succeed. Normally on powerup the tg3 chip firmware will make
  10130. * sure it is enabled, but other entities such as system netboot
  10131. * code might disable it.
  10132. */
  10133. val = tr32(MEMARB_MODE);
  10134. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  10135. tp->phy_id = PHY_ID_INVALID;
  10136. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10137. /* Assume an onboard device and WOL capable by default. */
  10138. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
  10139. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10140. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  10141. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  10142. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  10143. }
  10144. val = tr32(VCPU_CFGSHDW);
  10145. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  10146. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  10147. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  10148. (val & VCPU_CFGSHDW_WOL_MAGPKT))
  10149. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  10150. goto done;
  10151. }
  10152. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  10153. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  10154. u32 nic_cfg, led_cfg;
  10155. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  10156. int eeprom_phy_serdes = 0;
  10157. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  10158. tp->nic_sram_data_cfg = nic_cfg;
  10159. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  10160. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  10161. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  10162. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  10163. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  10164. (ver > 0) && (ver < 0x100))
  10165. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  10166. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
  10167. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  10168. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  10169. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  10170. eeprom_phy_serdes = 1;
  10171. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  10172. if (nic_phy_id != 0) {
  10173. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  10174. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  10175. eeprom_phy_id = (id1 >> 16) << 10;
  10176. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  10177. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  10178. } else
  10179. eeprom_phy_id = 0;
  10180. tp->phy_id = eeprom_phy_id;
  10181. if (eeprom_phy_serdes) {
  10182. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  10183. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  10184. tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
  10185. else
  10186. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  10187. }
  10188. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  10189. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  10190. SHASTA_EXT_LED_MODE_MASK);
  10191. else
  10192. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  10193. switch (led_cfg) {
  10194. default:
  10195. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  10196. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10197. break;
  10198. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  10199. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  10200. break;
  10201. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  10202. tp->led_ctrl = LED_CTRL_MODE_MAC;
  10203. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  10204. * read on some older 5700/5701 bootcode.
  10205. */
  10206. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10207. ASIC_REV_5700 ||
  10208. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  10209. ASIC_REV_5701)
  10210. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10211. break;
  10212. case SHASTA_EXT_LED_SHARED:
  10213. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  10214. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  10215. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  10216. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  10217. LED_CTRL_MODE_PHY_2);
  10218. break;
  10219. case SHASTA_EXT_LED_MAC:
  10220. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  10221. break;
  10222. case SHASTA_EXT_LED_COMBO:
  10223. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  10224. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  10225. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  10226. LED_CTRL_MODE_PHY_2);
  10227. break;
  10228. }
  10229. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10230. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  10231. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  10232. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  10233. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
  10234. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  10235. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  10236. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  10237. if ((tp->pdev->subsystem_vendor ==
  10238. PCI_VENDOR_ID_ARIMA) &&
  10239. (tp->pdev->subsystem_device == 0x205a ||
  10240. tp->pdev->subsystem_device == 0x2063))
  10241. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  10242. } else {
  10243. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  10244. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  10245. }
  10246. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  10247. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  10248. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  10249. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  10250. }
  10251. if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
  10252. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  10253. tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
  10254. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
  10255. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  10256. tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
  10257. if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
  10258. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
  10259. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  10260. if (cfg2 & (1 << 17))
  10261. tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
  10262. /* serdes signal pre-emphasis in register 0x590 set by */
  10263. /* bootcode if bit 18 is set */
  10264. if (cfg2 & (1 << 18))
  10265. tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
  10266. if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  10267. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
  10268. (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
  10269. tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
  10270. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  10271. u32 cfg3;
  10272. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  10273. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  10274. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  10275. }
  10276. if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
  10277. tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
  10278. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  10279. tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
  10280. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  10281. tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
  10282. }
  10283. done:
  10284. device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
  10285. device_set_wakeup_enable(&tp->pdev->dev,
  10286. tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
  10287. }
  10288. static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  10289. {
  10290. int i;
  10291. u32 val;
  10292. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  10293. tw32(OTP_CTRL, cmd);
  10294. /* Wait for up to 1 ms for command to execute. */
  10295. for (i = 0; i < 100; i++) {
  10296. val = tr32(OTP_STATUS);
  10297. if (val & OTP_STATUS_CMD_DONE)
  10298. break;
  10299. udelay(10);
  10300. }
  10301. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  10302. }
  10303. /* Read the gphy configuration from the OTP region of the chip. The gphy
  10304. * configuration is a 32-bit value that straddles the alignment boundary.
  10305. * We do two 32-bit reads and then shift and merge the results.
  10306. */
  10307. static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
  10308. {
  10309. u32 bhalf_otp, thalf_otp;
  10310. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  10311. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  10312. return 0;
  10313. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  10314. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  10315. return 0;
  10316. thalf_otp = tr32(OTP_READ_DATA);
  10317. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  10318. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  10319. return 0;
  10320. bhalf_otp = tr32(OTP_READ_DATA);
  10321. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  10322. }
  10323. static int __devinit tg3_phy_probe(struct tg3 *tp)
  10324. {
  10325. u32 hw_phy_id_1, hw_phy_id_2;
  10326. u32 hw_phy_id, hw_phy_id_masked;
  10327. int err;
  10328. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
  10329. return tg3_phy_init(tp);
  10330. /* Reading the PHY ID register can conflict with ASF
  10331. * firmware access to the PHY hardware.
  10332. */
  10333. err = 0;
  10334. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  10335. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  10336. hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
  10337. } else {
  10338. /* Now read the physical PHY_ID from the chip and verify
  10339. * that it is sane. If it doesn't look good, we fall back
  10340. * to either the hard-coded table based PHY_ID and failing
  10341. * that the value found in the eeprom area.
  10342. */
  10343. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  10344. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  10345. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  10346. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  10347. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  10348. hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  10349. }
  10350. if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  10351. tp->phy_id = hw_phy_id;
  10352. if (hw_phy_id_masked == PHY_ID_BCM8002)
  10353. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  10354. else
  10355. tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
  10356. } else {
  10357. if (tp->phy_id != PHY_ID_INVALID) {
  10358. /* Do nothing, phy ID already set up in
  10359. * tg3_get_eeprom_hw_cfg().
  10360. */
  10361. } else {
  10362. struct subsys_tbl_ent *p;
  10363. /* No eeprom signature? Try the hardcoded
  10364. * subsys device table.
  10365. */
  10366. p = lookup_by_subsys(tp);
  10367. if (!p)
  10368. return -ENODEV;
  10369. tp->phy_id = p->phy_id;
  10370. if (!tp->phy_id ||
  10371. tp->phy_id == PHY_ID_BCM8002)
  10372. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  10373. }
  10374. }
  10375. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
  10376. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
  10377. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  10378. u32 bmsr, adv_reg, tg3_ctrl, mask;
  10379. tg3_readphy(tp, MII_BMSR, &bmsr);
  10380. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  10381. (bmsr & BMSR_LSTATUS))
  10382. goto skip_phy_reset;
  10383. err = tg3_phy_reset(tp);
  10384. if (err)
  10385. return err;
  10386. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  10387. ADVERTISE_100HALF | ADVERTISE_100FULL |
  10388. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  10389. tg3_ctrl = 0;
  10390. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  10391. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  10392. MII_TG3_CTRL_ADV_1000_FULL);
  10393. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  10394. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  10395. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  10396. MII_TG3_CTRL_ENABLE_AS_MASTER);
  10397. }
  10398. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  10399. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  10400. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  10401. if (!tg3_copper_is_advertising_all(tp, mask)) {
  10402. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  10403. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  10404. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  10405. tg3_writephy(tp, MII_BMCR,
  10406. BMCR_ANENABLE | BMCR_ANRESTART);
  10407. }
  10408. tg3_phy_set_wirespeed(tp);
  10409. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  10410. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  10411. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  10412. }
  10413. skip_phy_reset:
  10414. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  10415. err = tg3_init_5401phy_dsp(tp);
  10416. if (err)
  10417. return err;
  10418. }
  10419. if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  10420. err = tg3_init_5401phy_dsp(tp);
  10421. }
  10422. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  10423. tp->link_config.advertising =
  10424. (ADVERTISED_1000baseT_Half |
  10425. ADVERTISED_1000baseT_Full |
  10426. ADVERTISED_Autoneg |
  10427. ADVERTISED_FIBRE);
  10428. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  10429. tp->link_config.advertising &=
  10430. ~(ADVERTISED_1000baseT_Half |
  10431. ADVERTISED_1000baseT_Full);
  10432. return err;
  10433. }
  10434. static void __devinit tg3_read_partno(struct tg3 *tp)
  10435. {
  10436. unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
  10437. unsigned int i;
  10438. u32 magic;
  10439. if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
  10440. tg3_nvram_read(tp, 0x0, &magic))
  10441. goto out_not_found;
  10442. if (magic == TG3_EEPROM_MAGIC) {
  10443. for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
  10444. u32 tmp;
  10445. /* The data is in little-endian format in NVRAM.
  10446. * Use the big-endian read routines to preserve
  10447. * the byte order as it exists in NVRAM.
  10448. */
  10449. if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
  10450. goto out_not_found;
  10451. memcpy(&vpd_data[i], &tmp, sizeof(tmp));
  10452. }
  10453. } else {
  10454. ssize_t cnt;
  10455. unsigned int pos = 0, i = 0;
  10456. for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
  10457. cnt = pci_read_vpd(tp->pdev, pos,
  10458. TG3_NVM_VPD_LEN - pos,
  10459. &vpd_data[pos]);
  10460. if (cnt == -ETIMEDOUT || -EINTR)
  10461. cnt = 0;
  10462. else if (cnt < 0)
  10463. goto out_not_found;
  10464. }
  10465. if (pos != TG3_NVM_VPD_LEN)
  10466. goto out_not_found;
  10467. }
  10468. /* Now parse and find the part number. */
  10469. for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
  10470. unsigned char val = vpd_data[i];
  10471. unsigned int block_end;
  10472. if (val == 0x82 || val == 0x91) {
  10473. i = (i + 3 +
  10474. (vpd_data[i + 1] +
  10475. (vpd_data[i + 2] << 8)));
  10476. continue;
  10477. }
  10478. if (val != 0x90)
  10479. goto out_not_found;
  10480. block_end = (i + 3 +
  10481. (vpd_data[i + 1] +
  10482. (vpd_data[i + 2] << 8)));
  10483. i += 3;
  10484. if (block_end > TG3_NVM_VPD_LEN)
  10485. goto out_not_found;
  10486. while (i < (block_end - 2)) {
  10487. if (vpd_data[i + 0] == 'P' &&
  10488. vpd_data[i + 1] == 'N') {
  10489. int partno_len = vpd_data[i + 2];
  10490. i += 3;
  10491. if (partno_len > TG3_BPN_SIZE ||
  10492. (partno_len + i) > TG3_NVM_VPD_LEN)
  10493. goto out_not_found;
  10494. memcpy(tp->board_part_number,
  10495. &vpd_data[i], partno_len);
  10496. /* Success. */
  10497. return;
  10498. }
  10499. i += 3 + vpd_data[i + 2];
  10500. }
  10501. /* Part number not found. */
  10502. goto out_not_found;
  10503. }
  10504. out_not_found:
  10505. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10506. strcpy(tp->board_part_number, "BCM95906");
  10507. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10508. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
  10509. strcpy(tp->board_part_number, "BCM57780");
  10510. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10511. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
  10512. strcpy(tp->board_part_number, "BCM57760");
  10513. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10514. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
  10515. strcpy(tp->board_part_number, "BCM57790");
  10516. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
  10517. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
  10518. strcpy(tp->board_part_number, "BCM57788");
  10519. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  10520. strcpy(tp->board_part_number, "BCM57765");
  10521. else
  10522. strcpy(tp->board_part_number, "none");
  10523. }
  10524. static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  10525. {
  10526. u32 val;
  10527. if (tg3_nvram_read(tp, offset, &val) ||
  10528. (val & 0xfc000000) != 0x0c000000 ||
  10529. tg3_nvram_read(tp, offset + 4, &val) ||
  10530. val != 0)
  10531. return 0;
  10532. return 1;
  10533. }
  10534. static void __devinit tg3_read_bc_ver(struct tg3 *tp)
  10535. {
  10536. u32 val, offset, start, ver_offset;
  10537. int i;
  10538. bool newver = false;
  10539. if (tg3_nvram_read(tp, 0xc, &offset) ||
  10540. tg3_nvram_read(tp, 0x4, &start))
  10541. return;
  10542. offset = tg3_nvram_logical_addr(tp, offset);
  10543. if (tg3_nvram_read(tp, offset, &val))
  10544. return;
  10545. if ((val & 0xfc000000) == 0x0c000000) {
  10546. if (tg3_nvram_read(tp, offset + 4, &val))
  10547. return;
  10548. if (val == 0)
  10549. newver = true;
  10550. }
  10551. if (newver) {
  10552. if (tg3_nvram_read(tp, offset + 8, &ver_offset))
  10553. return;
  10554. offset = offset + ver_offset - start;
  10555. for (i = 0; i < 16; i += 4) {
  10556. __be32 v;
  10557. if (tg3_nvram_read_be32(tp, offset + i, &v))
  10558. return;
  10559. memcpy(tp->fw_ver + i, &v, sizeof(v));
  10560. }
  10561. } else {
  10562. u32 major, minor;
  10563. if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
  10564. return;
  10565. major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
  10566. TG3_NVM_BCVER_MAJSFT;
  10567. minor = ver_offset & TG3_NVM_BCVER_MINMSK;
  10568. snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
  10569. }
  10570. }
  10571. static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
  10572. {
  10573. u32 val, major, minor;
  10574. /* Use native endian representation */
  10575. if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
  10576. return;
  10577. major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
  10578. TG3_NVM_HWSB_CFG1_MAJSFT;
  10579. minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
  10580. TG3_NVM_HWSB_CFG1_MINSFT;
  10581. snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
  10582. }
  10583. static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
  10584. {
  10585. u32 offset, major, minor, build;
  10586. tp->fw_ver[0] = 's';
  10587. tp->fw_ver[1] = 'b';
  10588. tp->fw_ver[2] = '\0';
  10589. if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
  10590. return;
  10591. switch (val & TG3_EEPROM_SB_REVISION_MASK) {
  10592. case TG3_EEPROM_SB_REVISION_0:
  10593. offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
  10594. break;
  10595. case TG3_EEPROM_SB_REVISION_2:
  10596. offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
  10597. break;
  10598. case TG3_EEPROM_SB_REVISION_3:
  10599. offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
  10600. break;
  10601. default:
  10602. return;
  10603. }
  10604. if (tg3_nvram_read(tp, offset, &val))
  10605. return;
  10606. build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
  10607. TG3_EEPROM_SB_EDH_BLD_SHFT;
  10608. major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
  10609. TG3_EEPROM_SB_EDH_MAJ_SHFT;
  10610. minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
  10611. if (minor > 99 || build > 26)
  10612. return;
  10613. snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
  10614. if (build > 0) {
  10615. tp->fw_ver[8] = 'a' + build - 1;
  10616. tp->fw_ver[9] = '\0';
  10617. }
  10618. }
  10619. static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
  10620. {
  10621. u32 val, offset, start;
  10622. int i, vlen;
  10623. for (offset = TG3_NVM_DIR_START;
  10624. offset < TG3_NVM_DIR_END;
  10625. offset += TG3_NVM_DIRENT_SIZE) {
  10626. if (tg3_nvram_read(tp, offset, &val))
  10627. return;
  10628. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  10629. break;
  10630. }
  10631. if (offset == TG3_NVM_DIR_END)
  10632. return;
  10633. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  10634. start = 0x08000000;
  10635. else if (tg3_nvram_read(tp, offset - 4, &start))
  10636. return;
  10637. if (tg3_nvram_read(tp, offset + 4, &offset) ||
  10638. !tg3_fw_img_is_valid(tp, offset) ||
  10639. tg3_nvram_read(tp, offset + 8, &val))
  10640. return;
  10641. offset += val - start;
  10642. vlen = strlen(tp->fw_ver);
  10643. tp->fw_ver[vlen++] = ',';
  10644. tp->fw_ver[vlen++] = ' ';
  10645. for (i = 0; i < 4; i++) {
  10646. __be32 v;
  10647. if (tg3_nvram_read_be32(tp, offset, &v))
  10648. return;
  10649. offset += sizeof(v);
  10650. if (vlen > TG3_VER_SIZE - sizeof(v)) {
  10651. memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
  10652. break;
  10653. }
  10654. memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
  10655. vlen += sizeof(v);
  10656. }
  10657. }
  10658. static void __devinit tg3_read_dash_ver(struct tg3 *tp)
  10659. {
  10660. int vlen;
  10661. u32 apedata;
  10662. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
  10663. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  10664. return;
  10665. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  10666. if (apedata != APE_SEG_SIG_MAGIC)
  10667. return;
  10668. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  10669. if (!(apedata & APE_FW_STATUS_READY))
  10670. return;
  10671. apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
  10672. vlen = strlen(tp->fw_ver);
  10673. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
  10674. (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
  10675. (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
  10676. (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
  10677. (apedata & APE_FW_VERSION_BLDMSK));
  10678. }
  10679. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  10680. {
  10681. u32 val;
  10682. if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
  10683. tp->fw_ver[0] = 's';
  10684. tp->fw_ver[1] = 'b';
  10685. tp->fw_ver[2] = '\0';
  10686. return;
  10687. }
  10688. if (tg3_nvram_read(tp, 0, &val))
  10689. return;
  10690. if (val == TG3_EEPROM_MAGIC)
  10691. tg3_read_bc_ver(tp);
  10692. else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
  10693. tg3_read_sb_ver(tp, val);
  10694. else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  10695. tg3_read_hwsb_ver(tp);
  10696. else
  10697. return;
  10698. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  10699. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  10700. return;
  10701. tg3_read_mgmtfw_ver(tp);
  10702. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  10703. }
  10704. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  10705. static int __devinit tg3_get_invariants(struct tg3 *tp)
  10706. {
  10707. static struct pci_device_id write_reorder_chipsets[] = {
  10708. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  10709. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  10710. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  10711. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  10712. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  10713. PCI_DEVICE_ID_VIA_8385_0) },
  10714. { },
  10715. };
  10716. u32 misc_ctrl_reg;
  10717. u32 pci_state_reg, grc_misc_cfg;
  10718. u32 val;
  10719. u16 pci_cmd;
  10720. int err;
  10721. /* Force memory write invalidate off. If we leave it on,
  10722. * then on 5700_BX chips we have to enable a workaround.
  10723. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  10724. * to match the cacheline size. The Broadcom driver have this
  10725. * workaround but turns MWI off all the times so never uses
  10726. * it. This seems to suggest that the workaround is insufficient.
  10727. */
  10728. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  10729. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  10730. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  10731. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  10732. * has the register indirect write enable bit set before
  10733. * we try to access any of the MMIO registers. It is also
  10734. * critical that the PCI-X hw workaround situation is decided
  10735. * before that as well.
  10736. */
  10737. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10738. &misc_ctrl_reg);
  10739. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  10740. MISC_HOST_CTRL_CHIPREV_SHIFT);
  10741. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
  10742. u32 prod_id_asic_rev;
  10743. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  10744. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  10745. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
  10746. pci_read_config_dword(tp->pdev,
  10747. TG3PCI_GEN2_PRODID_ASICREV,
  10748. &prod_id_asic_rev);
  10749. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
  10750. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
  10751. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
  10752. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
  10753. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  10754. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  10755. pci_read_config_dword(tp->pdev,
  10756. TG3PCI_GEN15_PRODID_ASICREV,
  10757. &prod_id_asic_rev);
  10758. else
  10759. pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
  10760. &prod_id_asic_rev);
  10761. tp->pci_chip_rev_id = prod_id_asic_rev;
  10762. }
  10763. /* Wrong chip ID in 5752 A0. This code can be removed later
  10764. * as A0 is not in production.
  10765. */
  10766. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  10767. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  10768. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  10769. * we need to disable memory and use config. cycles
  10770. * only to access all registers. The 5702/03 chips
  10771. * can mistakenly decode the special cycles from the
  10772. * ICH chipsets as memory write cycles, causing corruption
  10773. * of register and memory space. Only certain ICH bridges
  10774. * will drive special cycles with non-zero data during the
  10775. * address phase which can fall within the 5703's address
  10776. * range. This is not an ICH bug as the PCI spec allows
  10777. * non-zero address during special cycles. However, only
  10778. * these ICH bridges are known to drive non-zero addresses
  10779. * during special cycles.
  10780. *
  10781. * Since special cycles do not cross PCI bridges, we only
  10782. * enable this workaround if the 5703 is on the secondary
  10783. * bus of these ICH bridges.
  10784. */
  10785. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  10786. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  10787. static struct tg3_dev_id {
  10788. u32 vendor;
  10789. u32 device;
  10790. u32 rev;
  10791. } ich_chipsets[] = {
  10792. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  10793. PCI_ANY_ID },
  10794. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  10795. PCI_ANY_ID },
  10796. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  10797. 0xa },
  10798. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  10799. PCI_ANY_ID },
  10800. { },
  10801. };
  10802. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  10803. struct pci_dev *bridge = NULL;
  10804. while (pci_id->vendor != 0) {
  10805. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  10806. bridge);
  10807. if (!bridge) {
  10808. pci_id++;
  10809. continue;
  10810. }
  10811. if (pci_id->rev != PCI_ANY_ID) {
  10812. if (bridge->revision > pci_id->rev)
  10813. continue;
  10814. }
  10815. if (bridge->subordinate &&
  10816. (bridge->subordinate->number ==
  10817. tp->pdev->bus->number)) {
  10818. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  10819. pci_dev_put(bridge);
  10820. break;
  10821. }
  10822. }
  10823. }
  10824. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  10825. static struct tg3_dev_id {
  10826. u32 vendor;
  10827. u32 device;
  10828. } bridge_chipsets[] = {
  10829. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  10830. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  10831. { },
  10832. };
  10833. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  10834. struct pci_dev *bridge = NULL;
  10835. while (pci_id->vendor != 0) {
  10836. bridge = pci_get_device(pci_id->vendor,
  10837. pci_id->device,
  10838. bridge);
  10839. if (!bridge) {
  10840. pci_id++;
  10841. continue;
  10842. }
  10843. if (bridge->subordinate &&
  10844. (bridge->subordinate->number <=
  10845. tp->pdev->bus->number) &&
  10846. (bridge->subordinate->subordinate >=
  10847. tp->pdev->bus->number)) {
  10848. tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
  10849. pci_dev_put(bridge);
  10850. break;
  10851. }
  10852. }
  10853. }
  10854. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  10855. * DMA addresses > 40-bit. This bridge may have other additional
  10856. * 57xx devices behind it in some 4-port NIC designs for example.
  10857. * Any tg3 device found behind the bridge will also need the 40-bit
  10858. * DMA workaround.
  10859. */
  10860. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  10861. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  10862. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  10863. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  10864. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  10865. }
  10866. else {
  10867. struct pci_dev *bridge = NULL;
  10868. do {
  10869. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  10870. PCI_DEVICE_ID_SERVERWORKS_EPB,
  10871. bridge);
  10872. if (bridge && bridge->subordinate &&
  10873. (bridge->subordinate->number <=
  10874. tp->pdev->bus->number) &&
  10875. (bridge->subordinate->subordinate >=
  10876. tp->pdev->bus->number)) {
  10877. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  10878. pci_dev_put(bridge);
  10879. break;
  10880. }
  10881. } while (bridge);
  10882. }
  10883. /* Initialize misc host control in PCI block. */
  10884. tp->misc_host_ctrl |= (misc_ctrl_reg &
  10885. MISC_HOST_CTRL_CHIPREV);
  10886. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10887. tp->misc_host_ctrl);
  10888. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  10889. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
  10890. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
  10891. tp->pdev_peer = tg3_find_peer(tp);
  10892. /* Intentionally exclude ASIC_REV_5906 */
  10893. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10894. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10895. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10896. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10897. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  10898. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  10899. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10900. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  10901. tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
  10902. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  10903. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  10904. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10905. (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  10906. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  10907. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  10908. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  10909. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  10910. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  10911. /* 5700 B0 chips do not support checksumming correctly due
  10912. * to hardware bugs.
  10913. */
  10914. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  10915. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  10916. else {
  10917. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  10918. tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  10919. if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
  10920. tp->dev->features |= NETIF_F_IPV6_CSUM;
  10921. }
  10922. /* Determine TSO capabilities */
  10923. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10924. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  10925. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
  10926. else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  10927. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10928. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  10929. else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  10930. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  10931. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
  10932. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  10933. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  10934. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10935. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  10936. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
  10937. tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
  10938. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
  10939. tp->fw_needed = FIRMWARE_TG3TSO5;
  10940. else
  10941. tp->fw_needed = FIRMWARE_TG3TSO;
  10942. }
  10943. tp->irq_max = 1;
  10944. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  10945. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
  10946. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  10947. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  10948. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  10949. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  10950. tp->pdev_peer == tp->pdev))
  10951. tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
  10952. if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
  10953. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10954. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  10955. }
  10956. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10957. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  10958. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
  10959. tp->irq_max = TG3_IRQ_MAX_VECS;
  10960. }
  10961. }
  10962. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10963. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10964. tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
  10965. else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
  10966. tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
  10967. tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
  10968. }
  10969. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  10970. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  10971. tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
  10972. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  10973. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  10974. (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
  10975. tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
  10976. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  10977. &pci_state_reg);
  10978. tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  10979. if (tp->pcie_cap != 0) {
  10980. u16 lnkctl;
  10981. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  10982. pcie_set_readrq(tp->pdev, 4096);
  10983. pci_read_config_word(tp->pdev,
  10984. tp->pcie_cap + PCI_EXP_LNKCTL,
  10985. &lnkctl);
  10986. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
  10987. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10988. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  10989. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10990. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10991. tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
  10992. tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
  10993. tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
  10994. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
  10995. tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
  10996. }
  10997. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
  10998. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  10999. } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  11000. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  11001. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  11002. if (!tp->pcix_cap) {
  11003. printk(KERN_ERR PFX "Cannot find PCI-X "
  11004. "capability, aborting.\n");
  11005. return -EIO;
  11006. }
  11007. if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
  11008. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  11009. }
  11010. /* If we have an AMD 762 or VIA K8T800 chipset, write
  11011. * reordering to the mailbox registers done by the host
  11012. * controller can cause major troubles. We read back from
  11013. * every mailbox register write to force the writes to be
  11014. * posted to the chip in order.
  11015. */
  11016. if (pci_dev_present(write_reorder_chipsets) &&
  11017. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  11018. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  11019. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  11020. &tp->pci_cacheline_sz);
  11021. pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  11022. &tp->pci_lat_timer);
  11023. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  11024. tp->pci_lat_timer < 64) {
  11025. tp->pci_lat_timer = 64;
  11026. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  11027. tp->pci_lat_timer);
  11028. }
  11029. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  11030. /* 5700 BX chips need to have their TX producer index
  11031. * mailboxes written twice to workaround a bug.
  11032. */
  11033. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  11034. /* If we are in PCI-X mode, enable register write workaround.
  11035. *
  11036. * The workaround is to use indirect register accesses
  11037. * for all chip writes not to mailbox registers.
  11038. */
  11039. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  11040. u32 pm_reg;
  11041. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  11042. /* The chip can have it's power management PCI config
  11043. * space registers clobbered due to this bug.
  11044. * So explicitly force the chip into D0 here.
  11045. */
  11046. pci_read_config_dword(tp->pdev,
  11047. tp->pm_cap + PCI_PM_CTRL,
  11048. &pm_reg);
  11049. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  11050. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  11051. pci_write_config_dword(tp->pdev,
  11052. tp->pm_cap + PCI_PM_CTRL,
  11053. pm_reg);
  11054. /* Also, force SERR#/PERR# in PCI command. */
  11055. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  11056. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  11057. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  11058. }
  11059. }
  11060. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  11061. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  11062. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  11063. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  11064. /* Chip-specific fixup from Broadcom driver */
  11065. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  11066. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  11067. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  11068. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  11069. }
  11070. /* Default fast path register access methods */
  11071. tp->read32 = tg3_read32;
  11072. tp->write32 = tg3_write32;
  11073. tp->read32_mbox = tg3_read32;
  11074. tp->write32_mbox = tg3_write32;
  11075. tp->write32_tx_mbox = tg3_write32;
  11076. tp->write32_rx_mbox = tg3_write32;
  11077. /* Various workaround register access methods */
  11078. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  11079. tp->write32 = tg3_write_indirect_reg32;
  11080. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  11081. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  11082. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  11083. /*
  11084. * Back to back register writes can cause problems on these
  11085. * chips, the workaround is to read back all reg writes
  11086. * except those to mailbox regs.
  11087. *
  11088. * See tg3_write_indirect_reg32().
  11089. */
  11090. tp->write32 = tg3_write_flush_reg32;
  11091. }
  11092. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  11093. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  11094. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  11095. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  11096. tp->write32_rx_mbox = tg3_write_flush_reg32;
  11097. }
  11098. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  11099. tp->read32 = tg3_read_indirect_reg32;
  11100. tp->write32 = tg3_write_indirect_reg32;
  11101. tp->read32_mbox = tg3_read_indirect_mbox;
  11102. tp->write32_mbox = tg3_write_indirect_mbox;
  11103. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  11104. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  11105. iounmap(tp->regs);
  11106. tp->regs = NULL;
  11107. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  11108. pci_cmd &= ~PCI_COMMAND_MEMORY;
  11109. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  11110. }
  11111. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11112. tp->read32_mbox = tg3_read32_mbox_5906;
  11113. tp->write32_mbox = tg3_write32_mbox_5906;
  11114. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  11115. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  11116. }
  11117. if (tp->write32 == tg3_write_indirect_reg32 ||
  11118. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  11119. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11120. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  11121. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  11122. /* Get eeprom hw config before calling tg3_set_power_state().
  11123. * In particular, the TG3_FLG2_IS_NIC flag must be
  11124. * determined before calling tg3_set_power_state() so that
  11125. * we know whether or not to switch out of Vaux power.
  11126. * When the flag is set, it means that GPIO1 is used for eeprom
  11127. * write protect and also implies that it is a LOM where GPIOs
  11128. * are not used to switch power.
  11129. */
  11130. tg3_get_eeprom_hw_cfg(tp);
  11131. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  11132. /* Allow reads and writes to the
  11133. * APE register and memory space.
  11134. */
  11135. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  11136. PCISTATE_ALLOW_APE_SHMEM_WR;
  11137. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11138. pci_state_reg);
  11139. }
  11140. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11141. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  11142. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11143. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11144. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11145. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  11146. tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
  11147. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  11148. * GPIO1 driven high will bring 5700's external PHY out of reset.
  11149. * It is also used as eeprom write protect on LOMs.
  11150. */
  11151. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  11152. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  11153. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  11154. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  11155. GRC_LCLCTRL_GPIO_OUTPUT1);
  11156. /* Unused GPIO3 must be driven as output on 5752 because there
  11157. * are no pull-up resistors on unused GPIO pins.
  11158. */
  11159. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  11160. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  11161. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11162. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
  11163. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  11164. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  11165. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  11166. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  11167. /* Turn off the debug UART. */
  11168. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  11169. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  11170. /* Keep VMain power. */
  11171. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  11172. GRC_LCLCTRL_GPIO_OUTPUT0;
  11173. }
  11174. /* Force the chip into D0. */
  11175. err = tg3_set_power_state(tp, PCI_D0);
  11176. if (err) {
  11177. printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  11178. pci_name(tp->pdev));
  11179. return err;
  11180. }
  11181. /* Derive initial jumbo mode from MTU assigned in
  11182. * ether_setup() via the alloc_etherdev() call
  11183. */
  11184. if (tp->dev->mtu > ETH_DATA_LEN &&
  11185. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  11186. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  11187. /* Determine WakeOnLan speed to use. */
  11188. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11189. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  11190. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  11191. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  11192. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  11193. } else {
  11194. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  11195. }
  11196. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  11197. tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
  11198. /* A few boards don't want Ethernet@WireSpeed phy feature */
  11199. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  11200. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  11201. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  11202. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  11203. (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
  11204. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  11205. tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  11206. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  11207. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  11208. tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
  11209. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  11210. tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
  11211. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  11212. !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
  11213. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
  11214. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
  11215. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
  11216. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
  11217. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  11218. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  11219. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  11220. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  11221. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  11222. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  11223. tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
  11224. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  11225. tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
  11226. } else
  11227. tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
  11228. }
  11229. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  11230. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  11231. tp->phy_otp = tg3_read_otp_phycfg(tp);
  11232. if (tp->phy_otp == 0)
  11233. tp->phy_otp = TG3_OTP_DEFAULT;
  11234. }
  11235. if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
  11236. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  11237. else
  11238. tp->mi_mode = MAC_MI_MODE_BASE;
  11239. tp->coalesce_mode = 0;
  11240. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  11241. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  11242. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  11243. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  11244. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  11245. tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
  11246. err = tg3_mdio_init(tp);
  11247. if (err)
  11248. return err;
  11249. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
  11250. (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
  11251. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  11252. return -ENOTSUPP;
  11253. /* Initialize data/descriptor byte/word swapping. */
  11254. val = tr32(GRC_MODE);
  11255. val &= GRC_MODE_HOST_STACKUP;
  11256. tw32(GRC_MODE, val | tp->grc_mode);
  11257. tg3_switch_clocks(tp);
  11258. /* Clear this out for sanity. */
  11259. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  11260. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  11261. &pci_state_reg);
  11262. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  11263. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  11264. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  11265. if (chiprevid == CHIPREV_ID_5701_A0 ||
  11266. chiprevid == CHIPREV_ID_5701_B0 ||
  11267. chiprevid == CHIPREV_ID_5701_B2 ||
  11268. chiprevid == CHIPREV_ID_5701_B5) {
  11269. void __iomem *sram_base;
  11270. /* Write some dummy words into the SRAM status block
  11271. * area, see if it reads back correctly. If the return
  11272. * value is bad, force enable the PCIX workaround.
  11273. */
  11274. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  11275. writel(0x00000000, sram_base);
  11276. writel(0x00000000, sram_base + 4);
  11277. writel(0xffffffff, sram_base + 4);
  11278. if (readl(sram_base) != 0x00000000)
  11279. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  11280. }
  11281. }
  11282. udelay(50);
  11283. tg3_nvram_init(tp);
  11284. grc_misc_cfg = tr32(GRC_MISC_CFG);
  11285. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  11286. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  11287. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  11288. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  11289. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  11290. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  11291. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  11292. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  11293. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  11294. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  11295. HOSTCC_MODE_CLRTICK_TXBD);
  11296. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  11297. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  11298. tp->misc_host_ctrl);
  11299. }
  11300. /* Preserve the APE MAC_MODE bits */
  11301. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  11302. tp->mac_mode = tr32(MAC_MODE) |
  11303. MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  11304. else
  11305. tp->mac_mode = TG3_DEF_MAC_MODE;
  11306. /* these are limited to 10/100 only */
  11307. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  11308. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  11309. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  11310. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  11311. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  11312. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  11313. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  11314. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  11315. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  11316. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  11317. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  11318. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
  11319. (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
  11320. tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  11321. err = tg3_phy_probe(tp);
  11322. if (err) {
  11323. printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  11324. pci_name(tp->pdev), err);
  11325. /* ... but do not return immediately ... */
  11326. tg3_mdio_fini(tp);
  11327. }
  11328. tg3_read_partno(tp);
  11329. tg3_read_fw_ver(tp);
  11330. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  11331. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  11332. } else {
  11333. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  11334. tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  11335. else
  11336. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  11337. }
  11338. /* 5700 {AX,BX} chips have a broken status block link
  11339. * change bit implementation, so we must use the
  11340. * status register in those cases.
  11341. */
  11342. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  11343. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  11344. else
  11345. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  11346. /* The led_ctrl is set during tg3_phy_probe, here we might
  11347. * have to force the link status polling mechanism based
  11348. * upon subsystem IDs.
  11349. */
  11350. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  11351. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  11352. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  11353. tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  11354. TG3_FLAG_USE_LINKCHG_REG);
  11355. }
  11356. /* For all SERDES we poll the MAC status register. */
  11357. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  11358. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  11359. else
  11360. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  11361. tp->rx_offset = NET_IP_ALIGN;
  11362. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  11363. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  11364. tp->rx_offset = 0;
  11365. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  11366. /* Increment the rx prod index on the rx std ring by at most
  11367. * 8 for these chips to workaround hw errata.
  11368. */
  11369. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  11370. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  11371. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  11372. tp->rx_std_max_post = 8;
  11373. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
  11374. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  11375. PCIE_PWR_MGMT_L1_THRESH_MSK;
  11376. return err;
  11377. }
  11378. #ifdef CONFIG_SPARC
  11379. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  11380. {
  11381. struct net_device *dev = tp->dev;
  11382. struct pci_dev *pdev = tp->pdev;
  11383. struct device_node *dp = pci_device_to_OF_node(pdev);
  11384. const unsigned char *addr;
  11385. int len;
  11386. addr = of_get_property(dp, "local-mac-address", &len);
  11387. if (addr && len == 6) {
  11388. memcpy(dev->dev_addr, addr, 6);
  11389. memcpy(dev->perm_addr, dev->dev_addr, 6);
  11390. return 0;
  11391. }
  11392. return -ENODEV;
  11393. }
  11394. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  11395. {
  11396. struct net_device *dev = tp->dev;
  11397. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  11398. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  11399. return 0;
  11400. }
  11401. #endif
  11402. static int __devinit tg3_get_device_address(struct tg3 *tp)
  11403. {
  11404. struct net_device *dev = tp->dev;
  11405. u32 hi, lo, mac_offset;
  11406. int addr_ok = 0;
  11407. #ifdef CONFIG_SPARC
  11408. if (!tg3_get_macaddr_sparc(tp))
  11409. return 0;
  11410. #endif
  11411. mac_offset = 0x7c;
  11412. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  11413. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  11414. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  11415. mac_offset = 0xcc;
  11416. if (tg3_nvram_lock(tp))
  11417. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  11418. else
  11419. tg3_nvram_unlock(tp);
  11420. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
  11421. if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
  11422. mac_offset = 0xcc;
  11423. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  11424. mac_offset = 0x10;
  11425. /* First try to get it from MAC address mailbox. */
  11426. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  11427. if ((hi >> 16) == 0x484b) {
  11428. dev->dev_addr[0] = (hi >> 8) & 0xff;
  11429. dev->dev_addr[1] = (hi >> 0) & 0xff;
  11430. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  11431. dev->dev_addr[2] = (lo >> 24) & 0xff;
  11432. dev->dev_addr[3] = (lo >> 16) & 0xff;
  11433. dev->dev_addr[4] = (lo >> 8) & 0xff;
  11434. dev->dev_addr[5] = (lo >> 0) & 0xff;
  11435. /* Some old bootcode may report a 0 MAC address in SRAM */
  11436. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  11437. }
  11438. if (!addr_ok) {
  11439. /* Next, try NVRAM. */
  11440. if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
  11441. !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
  11442. !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
  11443. memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
  11444. memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
  11445. }
  11446. /* Finally just fetch it out of the MAC control regs. */
  11447. else {
  11448. hi = tr32(MAC_ADDR_0_HIGH);
  11449. lo = tr32(MAC_ADDR_0_LOW);
  11450. dev->dev_addr[5] = lo & 0xff;
  11451. dev->dev_addr[4] = (lo >> 8) & 0xff;
  11452. dev->dev_addr[3] = (lo >> 16) & 0xff;
  11453. dev->dev_addr[2] = (lo >> 24) & 0xff;
  11454. dev->dev_addr[1] = hi & 0xff;
  11455. dev->dev_addr[0] = (hi >> 8) & 0xff;
  11456. }
  11457. }
  11458. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  11459. #ifdef CONFIG_SPARC
  11460. if (!tg3_get_default_macaddr_sparc(tp))
  11461. return 0;
  11462. #endif
  11463. return -EINVAL;
  11464. }
  11465. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  11466. return 0;
  11467. }
  11468. #define BOUNDARY_SINGLE_CACHELINE 1
  11469. #define BOUNDARY_MULTI_CACHELINE 2
  11470. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  11471. {
  11472. int cacheline_size;
  11473. u8 byte;
  11474. int goal;
  11475. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  11476. if (byte == 0)
  11477. cacheline_size = 1024;
  11478. else
  11479. cacheline_size = (int) byte * 4;
  11480. /* On 5703 and later chips, the boundary bits have no
  11481. * effect.
  11482. */
  11483. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  11484. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  11485. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  11486. goto out;
  11487. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  11488. goal = BOUNDARY_MULTI_CACHELINE;
  11489. #else
  11490. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  11491. goal = BOUNDARY_SINGLE_CACHELINE;
  11492. #else
  11493. goal = 0;
  11494. #endif
  11495. #endif
  11496. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11497. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  11498. val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  11499. goto out;
  11500. }
  11501. if (!goal)
  11502. goto out;
  11503. /* PCI controllers on most RISC systems tend to disconnect
  11504. * when a device tries to burst across a cache-line boundary.
  11505. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  11506. *
  11507. * Unfortunately, for PCI-E there are only limited
  11508. * write-side controls for this, and thus for reads
  11509. * we will still get the disconnects. We'll also waste
  11510. * these PCI cycles for both read and write for chips
  11511. * other than 5700 and 5701 which do not implement the
  11512. * boundary bits.
  11513. */
  11514. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  11515. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  11516. switch (cacheline_size) {
  11517. case 16:
  11518. case 32:
  11519. case 64:
  11520. case 128:
  11521. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11522. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  11523. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  11524. } else {
  11525. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  11526. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  11527. }
  11528. break;
  11529. case 256:
  11530. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  11531. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  11532. break;
  11533. default:
  11534. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  11535. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  11536. break;
  11537. }
  11538. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11539. switch (cacheline_size) {
  11540. case 16:
  11541. case 32:
  11542. case 64:
  11543. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11544. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  11545. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  11546. break;
  11547. }
  11548. /* fallthrough */
  11549. case 128:
  11550. default:
  11551. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  11552. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  11553. break;
  11554. }
  11555. } else {
  11556. switch (cacheline_size) {
  11557. case 16:
  11558. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11559. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  11560. DMA_RWCTRL_WRITE_BNDRY_16);
  11561. break;
  11562. }
  11563. /* fallthrough */
  11564. case 32:
  11565. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11566. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  11567. DMA_RWCTRL_WRITE_BNDRY_32);
  11568. break;
  11569. }
  11570. /* fallthrough */
  11571. case 64:
  11572. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11573. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  11574. DMA_RWCTRL_WRITE_BNDRY_64);
  11575. break;
  11576. }
  11577. /* fallthrough */
  11578. case 128:
  11579. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  11580. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  11581. DMA_RWCTRL_WRITE_BNDRY_128);
  11582. break;
  11583. }
  11584. /* fallthrough */
  11585. case 256:
  11586. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  11587. DMA_RWCTRL_WRITE_BNDRY_256);
  11588. break;
  11589. case 512:
  11590. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  11591. DMA_RWCTRL_WRITE_BNDRY_512);
  11592. break;
  11593. case 1024:
  11594. default:
  11595. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  11596. DMA_RWCTRL_WRITE_BNDRY_1024);
  11597. break;
  11598. }
  11599. }
  11600. out:
  11601. return val;
  11602. }
  11603. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  11604. {
  11605. struct tg3_internal_buffer_desc test_desc;
  11606. u32 sram_dma_descs;
  11607. int i, ret;
  11608. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  11609. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  11610. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  11611. tw32(RDMAC_STATUS, 0);
  11612. tw32(WDMAC_STATUS, 0);
  11613. tw32(BUFMGR_MODE, 0);
  11614. tw32(FTQ_RESET, 0);
  11615. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  11616. test_desc.addr_lo = buf_dma & 0xffffffff;
  11617. test_desc.nic_mbuf = 0x00002100;
  11618. test_desc.len = size;
  11619. /*
  11620. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  11621. * the *second* time the tg3 driver was getting loaded after an
  11622. * initial scan.
  11623. *
  11624. * Broadcom tells me:
  11625. * ...the DMA engine is connected to the GRC block and a DMA
  11626. * reset may affect the GRC block in some unpredictable way...
  11627. * The behavior of resets to individual blocks has not been tested.
  11628. *
  11629. * Broadcom noted the GRC reset will also reset all sub-components.
  11630. */
  11631. if (to_device) {
  11632. test_desc.cqid_sqid = (13 << 8) | 2;
  11633. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  11634. udelay(40);
  11635. } else {
  11636. test_desc.cqid_sqid = (16 << 8) | 7;
  11637. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  11638. udelay(40);
  11639. }
  11640. test_desc.flags = 0x00000005;
  11641. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  11642. u32 val;
  11643. val = *(((u32 *)&test_desc) + i);
  11644. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  11645. sram_dma_descs + (i * sizeof(u32)));
  11646. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  11647. }
  11648. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  11649. if (to_device) {
  11650. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  11651. } else {
  11652. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  11653. }
  11654. ret = -ENODEV;
  11655. for (i = 0; i < 40; i++) {
  11656. u32 val;
  11657. if (to_device)
  11658. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  11659. else
  11660. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  11661. if ((val & 0xffff) == sram_dma_descs) {
  11662. ret = 0;
  11663. break;
  11664. }
  11665. udelay(100);
  11666. }
  11667. return ret;
  11668. }
  11669. #define TEST_BUFFER_SIZE 0x2000
  11670. static int __devinit tg3_test_dma(struct tg3 *tp)
  11671. {
  11672. dma_addr_t buf_dma;
  11673. u32 *buf, saved_dma_rwctrl;
  11674. int ret = 0;
  11675. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  11676. if (!buf) {
  11677. ret = -ENOMEM;
  11678. goto out_nofree;
  11679. }
  11680. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  11681. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  11682. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  11683. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11684. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
  11685. goto out;
  11686. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11687. /* DMA read watermark not used on PCIE */
  11688. tp->dma_rwctrl |= 0x00180000;
  11689. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  11690. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  11691. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  11692. tp->dma_rwctrl |= 0x003f0000;
  11693. else
  11694. tp->dma_rwctrl |= 0x003f000f;
  11695. } else {
  11696. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  11697. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  11698. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  11699. u32 read_water = 0x7;
  11700. /* If the 5704 is behind the EPB bridge, we can
  11701. * do the less restrictive ONE_DMA workaround for
  11702. * better performance.
  11703. */
  11704. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  11705. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  11706. tp->dma_rwctrl |= 0x8000;
  11707. else if (ccval == 0x6 || ccval == 0x7)
  11708. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  11709. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  11710. read_water = 4;
  11711. /* Set bit 23 to enable PCIX hw bug fix */
  11712. tp->dma_rwctrl |=
  11713. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  11714. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  11715. (1 << 23);
  11716. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  11717. /* 5780 always in PCIX mode */
  11718. tp->dma_rwctrl |= 0x00144000;
  11719. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  11720. /* 5714 always in PCIX mode */
  11721. tp->dma_rwctrl |= 0x00148000;
  11722. } else {
  11723. tp->dma_rwctrl |= 0x001b000f;
  11724. }
  11725. }
  11726. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  11727. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  11728. tp->dma_rwctrl &= 0xfffffff0;
  11729. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  11730. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  11731. /* Remove this if it causes problems for some boards. */
  11732. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  11733. /* On 5700/5701 chips, we need to set this bit.
  11734. * Otherwise the chip will issue cacheline transactions
  11735. * to streamable DMA memory with not all the byte
  11736. * enables turned on. This is an error on several
  11737. * RISC PCI controllers, in particular sparc64.
  11738. *
  11739. * On 5703/5704 chips, this bit has been reassigned
  11740. * a different meaning. In particular, it is used
  11741. * on those chips to enable a PCI-X workaround.
  11742. */
  11743. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  11744. }
  11745. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11746. #if 0
  11747. /* Unneeded, already done by tg3_get_invariants. */
  11748. tg3_switch_clocks(tp);
  11749. #endif
  11750. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  11751. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  11752. goto out;
  11753. /* It is best to perform DMA test with maximum write burst size
  11754. * to expose the 5700/5701 write DMA bug.
  11755. */
  11756. saved_dma_rwctrl = tp->dma_rwctrl;
  11757. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11758. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11759. while (1) {
  11760. u32 *p = buf, i;
  11761. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  11762. p[i] = i;
  11763. /* Send the buffer to the chip. */
  11764. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  11765. if (ret) {
  11766. printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
  11767. break;
  11768. }
  11769. #if 0
  11770. /* validate data reached card RAM correctly. */
  11771. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  11772. u32 val;
  11773. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  11774. if (le32_to_cpu(val) != p[i]) {
  11775. printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
  11776. /* ret = -ENODEV here? */
  11777. }
  11778. p[i] = 0;
  11779. }
  11780. #endif
  11781. /* Now read it back. */
  11782. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  11783. if (ret) {
  11784. printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
  11785. break;
  11786. }
  11787. /* Verify it. */
  11788. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  11789. if (p[i] == i)
  11790. continue;
  11791. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  11792. DMA_RWCTRL_WRITE_BNDRY_16) {
  11793. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11794. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  11795. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11796. break;
  11797. } else {
  11798. printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
  11799. ret = -ENODEV;
  11800. goto out;
  11801. }
  11802. }
  11803. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  11804. /* Success. */
  11805. ret = 0;
  11806. break;
  11807. }
  11808. }
  11809. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  11810. DMA_RWCTRL_WRITE_BNDRY_16) {
  11811. static struct pci_device_id dma_wait_state_chipsets[] = {
  11812. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  11813. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  11814. { },
  11815. };
  11816. /* DMA test passed without adjusting DMA boundary,
  11817. * now look for chipsets that are known to expose the
  11818. * DMA bug without failing the test.
  11819. */
  11820. if (pci_dev_present(dma_wait_state_chipsets)) {
  11821. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  11822. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  11823. }
  11824. else
  11825. /* Safe to use the calculated DMA boundary. */
  11826. tp->dma_rwctrl = saved_dma_rwctrl;
  11827. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  11828. }
  11829. out:
  11830. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  11831. out_nofree:
  11832. return ret;
  11833. }
  11834. static void __devinit tg3_init_link_config(struct tg3 *tp)
  11835. {
  11836. tp->link_config.advertising =
  11837. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  11838. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  11839. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  11840. ADVERTISED_Autoneg | ADVERTISED_MII);
  11841. tp->link_config.speed = SPEED_INVALID;
  11842. tp->link_config.duplex = DUPLEX_INVALID;
  11843. tp->link_config.autoneg = AUTONEG_ENABLE;
  11844. tp->link_config.active_speed = SPEED_INVALID;
  11845. tp->link_config.active_duplex = DUPLEX_INVALID;
  11846. tp->link_config.phy_is_low_power = 0;
  11847. tp->link_config.orig_speed = SPEED_INVALID;
  11848. tp->link_config.orig_duplex = DUPLEX_INVALID;
  11849. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  11850. }
  11851. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  11852. {
  11853. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
  11854. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
  11855. tp->bufmgr_config.mbuf_read_dma_low_water =
  11856. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11857. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11858. DEFAULT_MB_MACRX_LOW_WATER_57765;
  11859. tp->bufmgr_config.mbuf_high_water =
  11860. DEFAULT_MB_HIGH_WATER_57765;
  11861. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11862. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11863. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11864. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
  11865. tp->bufmgr_config.mbuf_high_water_jumbo =
  11866. DEFAULT_MB_HIGH_WATER_JUMBO_57765;
  11867. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  11868. tp->bufmgr_config.mbuf_read_dma_low_water =
  11869. DEFAULT_MB_RDMA_LOW_WATER_5705;
  11870. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11871. DEFAULT_MB_MACRX_LOW_WATER_5705;
  11872. tp->bufmgr_config.mbuf_high_water =
  11873. DEFAULT_MB_HIGH_WATER_5705;
  11874. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  11875. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11876. DEFAULT_MB_MACRX_LOW_WATER_5906;
  11877. tp->bufmgr_config.mbuf_high_water =
  11878. DEFAULT_MB_HIGH_WATER_5906;
  11879. }
  11880. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11881. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  11882. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11883. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  11884. tp->bufmgr_config.mbuf_high_water_jumbo =
  11885. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  11886. } else {
  11887. tp->bufmgr_config.mbuf_read_dma_low_water =
  11888. DEFAULT_MB_RDMA_LOW_WATER;
  11889. tp->bufmgr_config.mbuf_mac_rx_low_water =
  11890. DEFAULT_MB_MACRX_LOW_WATER;
  11891. tp->bufmgr_config.mbuf_high_water =
  11892. DEFAULT_MB_HIGH_WATER;
  11893. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  11894. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  11895. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  11896. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  11897. tp->bufmgr_config.mbuf_high_water_jumbo =
  11898. DEFAULT_MB_HIGH_WATER_JUMBO;
  11899. }
  11900. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  11901. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  11902. }
  11903. static char * __devinit tg3_phy_string(struct tg3 *tp)
  11904. {
  11905. switch (tp->phy_id & PHY_ID_MASK) {
  11906. case PHY_ID_BCM5400: return "5400";
  11907. case PHY_ID_BCM5401: return "5401";
  11908. case PHY_ID_BCM5411: return "5411";
  11909. case PHY_ID_BCM5701: return "5701";
  11910. case PHY_ID_BCM5703: return "5703";
  11911. case PHY_ID_BCM5704: return "5704";
  11912. case PHY_ID_BCM5705: return "5705";
  11913. case PHY_ID_BCM5750: return "5750";
  11914. case PHY_ID_BCM5752: return "5752";
  11915. case PHY_ID_BCM5714: return "5714";
  11916. case PHY_ID_BCM5780: return "5780";
  11917. case PHY_ID_BCM5755: return "5755";
  11918. case PHY_ID_BCM5787: return "5787";
  11919. case PHY_ID_BCM5784: return "5784";
  11920. case PHY_ID_BCM5756: return "5722/5756";
  11921. case PHY_ID_BCM5906: return "5906";
  11922. case PHY_ID_BCM5761: return "5761";
  11923. case PHY_ID_BCM5718C: return "5718C";
  11924. case PHY_ID_BCM5718S: return "5718S";
  11925. case PHY_ID_BCM57765: return "57765";
  11926. case PHY_ID_BCM8002: return "8002/serdes";
  11927. case 0: return "serdes";
  11928. default: return "unknown";
  11929. }
  11930. }
  11931. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  11932. {
  11933. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  11934. strcpy(str, "PCI Express");
  11935. return str;
  11936. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  11937. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  11938. strcpy(str, "PCIX:");
  11939. if ((clock_ctrl == 7) ||
  11940. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  11941. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  11942. strcat(str, "133MHz");
  11943. else if (clock_ctrl == 0)
  11944. strcat(str, "33MHz");
  11945. else if (clock_ctrl == 2)
  11946. strcat(str, "50MHz");
  11947. else if (clock_ctrl == 4)
  11948. strcat(str, "66MHz");
  11949. else if (clock_ctrl == 6)
  11950. strcat(str, "100MHz");
  11951. } else {
  11952. strcpy(str, "PCI:");
  11953. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  11954. strcat(str, "66MHz");
  11955. else
  11956. strcat(str, "33MHz");
  11957. }
  11958. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  11959. strcat(str, ":32-bit");
  11960. else
  11961. strcat(str, ":64-bit");
  11962. return str;
  11963. }
  11964. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  11965. {
  11966. struct pci_dev *peer;
  11967. unsigned int func, devnr = tp->pdev->devfn & ~7;
  11968. for (func = 0; func < 8; func++) {
  11969. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  11970. if (peer && peer != tp->pdev)
  11971. break;
  11972. pci_dev_put(peer);
  11973. }
  11974. /* 5704 can be configured in single-port mode, set peer to
  11975. * tp->pdev in that case.
  11976. */
  11977. if (!peer) {
  11978. peer = tp->pdev;
  11979. return peer;
  11980. }
  11981. /*
  11982. * We don't need to keep the refcount elevated; there's no way
  11983. * to remove one half of this device without removing the other
  11984. */
  11985. pci_dev_put(peer);
  11986. return peer;
  11987. }
  11988. static void __devinit tg3_init_coal(struct tg3 *tp)
  11989. {
  11990. struct ethtool_coalesce *ec = &tp->coal;
  11991. memset(ec, 0, sizeof(*ec));
  11992. ec->cmd = ETHTOOL_GCOALESCE;
  11993. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  11994. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  11995. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  11996. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  11997. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  11998. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  11999. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  12000. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  12001. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  12002. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  12003. HOSTCC_MODE_CLRTICK_TXBD)) {
  12004. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  12005. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  12006. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  12007. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  12008. }
  12009. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  12010. ec->rx_coalesce_usecs_irq = 0;
  12011. ec->tx_coalesce_usecs_irq = 0;
  12012. ec->stats_block_coalesce_usecs = 0;
  12013. }
  12014. }
  12015. static const struct net_device_ops tg3_netdev_ops = {
  12016. .ndo_open = tg3_open,
  12017. .ndo_stop = tg3_close,
  12018. .ndo_start_xmit = tg3_start_xmit,
  12019. .ndo_get_stats = tg3_get_stats,
  12020. .ndo_validate_addr = eth_validate_addr,
  12021. .ndo_set_multicast_list = tg3_set_rx_mode,
  12022. .ndo_set_mac_address = tg3_set_mac_addr,
  12023. .ndo_do_ioctl = tg3_ioctl,
  12024. .ndo_tx_timeout = tg3_tx_timeout,
  12025. .ndo_change_mtu = tg3_change_mtu,
  12026. #if TG3_VLAN_TAG_USED
  12027. .ndo_vlan_rx_register = tg3_vlan_rx_register,
  12028. #endif
  12029. #ifdef CONFIG_NET_POLL_CONTROLLER
  12030. .ndo_poll_controller = tg3_poll_controller,
  12031. #endif
  12032. };
  12033. static const struct net_device_ops tg3_netdev_ops_dma_bug = {
  12034. .ndo_open = tg3_open,
  12035. .ndo_stop = tg3_close,
  12036. .ndo_start_xmit = tg3_start_xmit_dma_bug,
  12037. .ndo_get_stats = tg3_get_stats,
  12038. .ndo_validate_addr = eth_validate_addr,
  12039. .ndo_set_multicast_list = tg3_set_rx_mode,
  12040. .ndo_set_mac_address = tg3_set_mac_addr,
  12041. .ndo_do_ioctl = tg3_ioctl,
  12042. .ndo_tx_timeout = tg3_tx_timeout,
  12043. .ndo_change_mtu = tg3_change_mtu,
  12044. #if TG3_VLAN_TAG_USED
  12045. .ndo_vlan_rx_register = tg3_vlan_rx_register,
  12046. #endif
  12047. #ifdef CONFIG_NET_POLL_CONTROLLER
  12048. .ndo_poll_controller = tg3_poll_controller,
  12049. #endif
  12050. };
  12051. static int __devinit tg3_init_one(struct pci_dev *pdev,
  12052. const struct pci_device_id *ent)
  12053. {
  12054. static int tg3_version_printed = 0;
  12055. struct net_device *dev;
  12056. struct tg3 *tp;
  12057. int i, err, pm_cap;
  12058. u32 sndmbx, rcvmbx, intmbx;
  12059. char str[40];
  12060. u64 dma_mask, persist_dma_mask;
  12061. if (tg3_version_printed++ == 0)
  12062. printk(KERN_INFO "%s", version);
  12063. err = pci_enable_device(pdev);
  12064. if (err) {
  12065. printk(KERN_ERR PFX "Cannot enable PCI device, "
  12066. "aborting.\n");
  12067. return err;
  12068. }
  12069. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  12070. if (err) {
  12071. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  12072. "aborting.\n");
  12073. goto err_out_disable_pdev;
  12074. }
  12075. pci_set_master(pdev);
  12076. /* Find power-management capability. */
  12077. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  12078. if (pm_cap == 0) {
  12079. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  12080. "aborting.\n");
  12081. err = -EIO;
  12082. goto err_out_free_res;
  12083. }
  12084. dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
  12085. if (!dev) {
  12086. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  12087. err = -ENOMEM;
  12088. goto err_out_free_res;
  12089. }
  12090. SET_NETDEV_DEV(dev, &pdev->dev);
  12091. #if TG3_VLAN_TAG_USED
  12092. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  12093. #endif
  12094. tp = netdev_priv(dev);
  12095. tp->pdev = pdev;
  12096. tp->dev = dev;
  12097. tp->pm_cap = pm_cap;
  12098. tp->rx_mode = TG3_DEF_RX_MODE;
  12099. tp->tx_mode = TG3_DEF_TX_MODE;
  12100. if (tg3_debug > 0)
  12101. tp->msg_enable = tg3_debug;
  12102. else
  12103. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  12104. /* The word/byte swap controls here control register access byte
  12105. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  12106. * setting below.
  12107. */
  12108. tp->misc_host_ctrl =
  12109. MISC_HOST_CTRL_MASK_PCI_INT |
  12110. MISC_HOST_CTRL_WORD_SWAP |
  12111. MISC_HOST_CTRL_INDIR_ACCESS |
  12112. MISC_HOST_CTRL_PCISTATE_RW;
  12113. /* The NONFRM (non-frame) byte/word swap controls take effect
  12114. * on descriptor entries, anything which isn't packet data.
  12115. *
  12116. * The StrongARM chips on the board (one for tx, one for rx)
  12117. * are running in big-endian mode.
  12118. */
  12119. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  12120. GRC_MODE_WSWAP_NONFRM_DATA);
  12121. #ifdef __BIG_ENDIAN
  12122. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  12123. #endif
  12124. spin_lock_init(&tp->lock);
  12125. spin_lock_init(&tp->indirect_lock);
  12126. INIT_WORK(&tp->reset_task, tg3_reset_task);
  12127. tp->regs = pci_ioremap_bar(pdev, BAR_0);
  12128. if (!tp->regs) {
  12129. printk(KERN_ERR PFX "Cannot map device registers, "
  12130. "aborting.\n");
  12131. err = -ENOMEM;
  12132. goto err_out_free_dev;
  12133. }
  12134. tg3_init_link_config(tp);
  12135. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  12136. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  12137. dev->ethtool_ops = &tg3_ethtool_ops;
  12138. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  12139. dev->irq = pdev->irq;
  12140. err = tg3_get_invariants(tp);
  12141. if (err) {
  12142. printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  12143. "aborting.\n");
  12144. goto err_out_iounmap;
  12145. }
  12146. if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
  12147. tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
  12148. dev->netdev_ops = &tg3_netdev_ops;
  12149. else
  12150. dev->netdev_ops = &tg3_netdev_ops_dma_bug;
  12151. /* The EPB bridge inside 5714, 5715, and 5780 and any
  12152. * device behind the EPB cannot support DMA addresses > 40-bit.
  12153. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  12154. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  12155. * do DMA address check in tg3_start_xmit().
  12156. */
  12157. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  12158. persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
  12159. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  12160. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  12161. #ifdef CONFIG_HIGHMEM
  12162. dma_mask = DMA_BIT_MASK(64);
  12163. #endif
  12164. } else
  12165. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  12166. /* Configure DMA attributes. */
  12167. if (dma_mask > DMA_BIT_MASK(32)) {
  12168. err = pci_set_dma_mask(pdev, dma_mask);
  12169. if (!err) {
  12170. dev->features |= NETIF_F_HIGHDMA;
  12171. err = pci_set_consistent_dma_mask(pdev,
  12172. persist_dma_mask);
  12173. if (err < 0) {
  12174. printk(KERN_ERR PFX "Unable to obtain 64 bit "
  12175. "DMA for consistent allocations\n");
  12176. goto err_out_iounmap;
  12177. }
  12178. }
  12179. }
  12180. if (err || dma_mask == DMA_BIT_MASK(32)) {
  12181. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  12182. if (err) {
  12183. printk(KERN_ERR PFX "No usable DMA configuration, "
  12184. "aborting.\n");
  12185. goto err_out_iounmap;
  12186. }
  12187. }
  12188. tg3_init_bufmgr_config(tp);
  12189. /* Selectively allow TSO based on operating conditions */
  12190. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  12191. (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
  12192. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  12193. else {
  12194. tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
  12195. tp->fw_needed = NULL;
  12196. }
  12197. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
  12198. tp->fw_needed = FIRMWARE_TG3;
  12199. /* TSO is on by default on chips that support hardware TSO.
  12200. * Firmware TSO on older chips gives lower performance, so it
  12201. * is off by default, but can be enabled using ethtool.
  12202. */
  12203. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
  12204. (dev->features & NETIF_F_IP_CSUM))
  12205. dev->features |= NETIF_F_TSO;
  12206. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
  12207. (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
  12208. if (dev->features & NETIF_F_IPV6_CSUM)
  12209. dev->features |= NETIF_F_TSO6;
  12210. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
  12211. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  12212. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  12213. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
  12214. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
  12215. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
  12216. dev->features |= NETIF_F_TSO_ECN;
  12217. }
  12218. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  12219. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  12220. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  12221. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  12222. tp->rx_pending = 63;
  12223. }
  12224. err = tg3_get_device_address(tp);
  12225. if (err) {
  12226. printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  12227. "aborting.\n");
  12228. goto err_out_iounmap;
  12229. }
  12230. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  12231. tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
  12232. if (!tp->aperegs) {
  12233. printk(KERN_ERR PFX "Cannot map APE registers, "
  12234. "aborting.\n");
  12235. err = -ENOMEM;
  12236. goto err_out_iounmap;
  12237. }
  12238. tg3_ape_lock_init(tp);
  12239. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  12240. tg3_read_dash_ver(tp);
  12241. }
  12242. /*
  12243. * Reset chip in case UNDI or EFI driver did not shutdown
  12244. * DMA self test will enable WDMAC and we'll see (spurious)
  12245. * pending DMA on the PCI bus at that point.
  12246. */
  12247. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  12248. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  12249. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  12250. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  12251. }
  12252. err = tg3_test_dma(tp);
  12253. if (err) {
  12254. printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  12255. goto err_out_apeunmap;
  12256. }
  12257. /* flow control autonegotiation is default behavior */
  12258. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  12259. tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  12260. intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
  12261. rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
  12262. sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  12263. for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
  12264. struct tg3_napi *tnapi = &tp->napi[i];
  12265. tnapi->tp = tp;
  12266. tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
  12267. tnapi->int_mbox = intmbx;
  12268. if (i < 4)
  12269. intmbx += 0x8;
  12270. else
  12271. intmbx += 0x4;
  12272. tnapi->consmbox = rcvmbx;
  12273. tnapi->prodmbox = sndmbx;
  12274. if (i) {
  12275. tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
  12276. netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
  12277. } else {
  12278. tnapi->coal_now = HOSTCC_MODE_NOW;
  12279. netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
  12280. }
  12281. if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
  12282. break;
  12283. /*
  12284. * If we support MSIX, we'll be using RSS. If we're using
  12285. * RSS, the first vector only handles link interrupts and the
  12286. * remaining vectors handle rx and tx interrupts. Reuse the
  12287. * mailbox values for the next iteration. The values we setup
  12288. * above are still useful for the single vectored mode.
  12289. */
  12290. if (!i)
  12291. continue;
  12292. rcvmbx += 0x8;
  12293. if (sndmbx & 0x4)
  12294. sndmbx -= 0x4;
  12295. else
  12296. sndmbx += 0xc;
  12297. }
  12298. tg3_init_coal(tp);
  12299. pci_set_drvdata(pdev, dev);
  12300. err = register_netdev(dev);
  12301. if (err) {
  12302. printk(KERN_ERR PFX "Cannot register net device, "
  12303. "aborting.\n");
  12304. goto err_out_apeunmap;
  12305. }
  12306. printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
  12307. dev->name,
  12308. tp->board_part_number,
  12309. tp->pci_chip_rev_id,
  12310. tg3_bus_string(tp, str),
  12311. dev->dev_addr);
  12312. if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
  12313. struct phy_device *phydev;
  12314. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  12315. printk(KERN_INFO
  12316. "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  12317. tp->dev->name, phydev->drv->name,
  12318. dev_name(&phydev->dev));
  12319. } else
  12320. printk(KERN_INFO
  12321. "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
  12322. tp->dev->name, tg3_phy_string(tp),
  12323. ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
  12324. ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
  12325. "10/100/1000Base-T")),
  12326. (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
  12327. printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
  12328. dev->name,
  12329. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  12330. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  12331. (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
  12332. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  12333. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  12334. printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  12335. dev->name, tp->dma_rwctrl,
  12336. (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
  12337. (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
  12338. return 0;
  12339. err_out_apeunmap:
  12340. if (tp->aperegs) {
  12341. iounmap(tp->aperegs);
  12342. tp->aperegs = NULL;
  12343. }
  12344. err_out_iounmap:
  12345. if (tp->regs) {
  12346. iounmap(tp->regs);
  12347. tp->regs = NULL;
  12348. }
  12349. err_out_free_dev:
  12350. free_netdev(dev);
  12351. err_out_free_res:
  12352. pci_release_regions(pdev);
  12353. err_out_disable_pdev:
  12354. pci_disable_device(pdev);
  12355. pci_set_drvdata(pdev, NULL);
  12356. return err;
  12357. }
  12358. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  12359. {
  12360. struct net_device *dev = pci_get_drvdata(pdev);
  12361. if (dev) {
  12362. struct tg3 *tp = netdev_priv(dev);
  12363. if (tp->fw)
  12364. release_firmware(tp->fw);
  12365. flush_scheduled_work();
  12366. if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
  12367. tg3_phy_fini(tp);
  12368. tg3_mdio_fini(tp);
  12369. }
  12370. unregister_netdev(dev);
  12371. if (tp->aperegs) {
  12372. iounmap(tp->aperegs);
  12373. tp->aperegs = NULL;
  12374. }
  12375. if (tp->regs) {
  12376. iounmap(tp->regs);
  12377. tp->regs = NULL;
  12378. }
  12379. free_netdev(dev);
  12380. pci_release_regions(pdev);
  12381. pci_disable_device(pdev);
  12382. pci_set_drvdata(pdev, NULL);
  12383. }
  12384. }
  12385. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  12386. {
  12387. struct net_device *dev = pci_get_drvdata(pdev);
  12388. struct tg3 *tp = netdev_priv(dev);
  12389. pci_power_t target_state;
  12390. int err;
  12391. /* PCI register 4 needs to be saved whether netif_running() or not.
  12392. * MSI address and data need to be saved if using MSI and
  12393. * netif_running().
  12394. */
  12395. pci_save_state(pdev);
  12396. if (!netif_running(dev))
  12397. return 0;
  12398. flush_scheduled_work();
  12399. tg3_phy_stop(tp);
  12400. tg3_netif_stop(tp);
  12401. del_timer_sync(&tp->timer);
  12402. tg3_full_lock(tp, 1);
  12403. tg3_disable_ints(tp);
  12404. tg3_full_unlock(tp);
  12405. netif_device_detach(dev);
  12406. tg3_full_lock(tp, 0);
  12407. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  12408. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  12409. tg3_full_unlock(tp);
  12410. target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
  12411. err = tg3_set_power_state(tp, target_state);
  12412. if (err) {
  12413. int err2;
  12414. tg3_full_lock(tp, 0);
  12415. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  12416. err2 = tg3_restart_hw(tp, 1);
  12417. if (err2)
  12418. goto out;
  12419. tp->timer.expires = jiffies + tp->timer_offset;
  12420. add_timer(&tp->timer);
  12421. netif_device_attach(dev);
  12422. tg3_netif_start(tp);
  12423. out:
  12424. tg3_full_unlock(tp);
  12425. if (!err2)
  12426. tg3_phy_start(tp);
  12427. }
  12428. return err;
  12429. }
  12430. static int tg3_resume(struct pci_dev *pdev)
  12431. {
  12432. struct net_device *dev = pci_get_drvdata(pdev);
  12433. struct tg3 *tp = netdev_priv(dev);
  12434. int err;
  12435. pci_restore_state(tp->pdev);
  12436. if (!netif_running(dev))
  12437. return 0;
  12438. err = tg3_set_power_state(tp, PCI_D0);
  12439. if (err)
  12440. return err;
  12441. netif_device_attach(dev);
  12442. tg3_full_lock(tp, 0);
  12443. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  12444. err = tg3_restart_hw(tp, 1);
  12445. if (err)
  12446. goto out;
  12447. tp->timer.expires = jiffies + tp->timer_offset;
  12448. add_timer(&tp->timer);
  12449. tg3_netif_start(tp);
  12450. out:
  12451. tg3_full_unlock(tp);
  12452. if (!err)
  12453. tg3_phy_start(tp);
  12454. return err;
  12455. }
  12456. static struct pci_driver tg3_driver = {
  12457. .name = DRV_MODULE_NAME,
  12458. .id_table = tg3_pci_tbl,
  12459. .probe = tg3_init_one,
  12460. .remove = __devexit_p(tg3_remove_one),
  12461. .suspend = tg3_suspend,
  12462. .resume = tg3_resume
  12463. };
  12464. static int __init tg3_init(void)
  12465. {
  12466. return pci_register_driver(&tg3_driver);
  12467. }
  12468. static void __exit tg3_cleanup(void)
  12469. {
  12470. pci_unregister_driver(&tg3_driver);
  12471. }
  12472. module_init(tg3_init);
  12473. module_exit(tg3_cleanup);