Kconfig 25 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. config ZONE_DMA
  24. bool
  25. default y
  26. config GENERIC_FIND_NEXT_BIT
  27. bool
  28. default y
  29. config GENERIC_HWEIGHT
  30. bool
  31. default y
  32. config GENERIC_HARDIRQS
  33. bool
  34. default y
  35. config GENERIC_IRQ_PROBE
  36. bool
  37. default y
  38. config GENERIC_GPIO
  39. bool
  40. default y
  41. config FORCE_MAX_ZONEORDER
  42. int
  43. default "14"
  44. config GENERIC_CALIBRATE_DELAY
  45. bool
  46. default y
  47. config HARDWARE_PM
  48. def_bool y
  49. depends on OPROFILE
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. source "kernel/Kconfig.freezer"
  53. menu "Blackfin Processor Options"
  54. comment "Processor and Board Settings"
  55. choice
  56. prompt "CPU"
  57. default BF533
  58. config BF522
  59. bool "BF522"
  60. help
  61. BF522 Processor Support.
  62. config BF523
  63. bool "BF523"
  64. help
  65. BF523 Processor Support.
  66. config BF524
  67. bool "BF524"
  68. help
  69. BF524 Processor Support.
  70. config BF525
  71. bool "BF525"
  72. help
  73. BF525 Processor Support.
  74. config BF526
  75. bool "BF526"
  76. help
  77. BF526 Processor Support.
  78. config BF527
  79. bool "BF527"
  80. help
  81. BF527 Processor Support.
  82. config BF531
  83. bool "BF531"
  84. help
  85. BF531 Processor Support.
  86. config BF532
  87. bool "BF532"
  88. help
  89. BF532 Processor Support.
  90. config BF533
  91. bool "BF533"
  92. help
  93. BF533 Processor Support.
  94. config BF534
  95. bool "BF534"
  96. help
  97. BF534 Processor Support.
  98. config BF536
  99. bool "BF536"
  100. help
  101. BF536 Processor Support.
  102. config BF537
  103. bool "BF537"
  104. help
  105. BF537 Processor Support.
  106. config BF538
  107. bool "BF538"
  108. help
  109. BF538 Processor Support.
  110. config BF539
  111. bool "BF539"
  112. help
  113. BF539 Processor Support.
  114. config BF542
  115. bool "BF542"
  116. help
  117. BF542 Processor Support.
  118. config BF544
  119. bool "BF544"
  120. help
  121. BF544 Processor Support.
  122. config BF547
  123. bool "BF547"
  124. help
  125. BF547 Processor Support.
  126. config BF548
  127. bool "BF548"
  128. help
  129. BF548 Processor Support.
  130. config BF549
  131. bool "BF549"
  132. help
  133. BF549 Processor Support.
  134. config BF561
  135. bool "BF561"
  136. help
  137. BF561 Processor Support.
  138. endchoice
  139. config BF_REV_MIN
  140. int
  141. default 0 if (BF52x || BF54x)
  142. default 2 if (BF537 || BF536 || BF534)
  143. default 3 if (BF561 ||BF533 || BF532 || BF531)
  144. default 4 if (BF538 || BF539)
  145. config BF_REV_MAX
  146. int
  147. default 2 if (BF52x || BF54x)
  148. default 3 if (BF537 || BF536 || BF534)
  149. default 5 if (BF561|| BF538 || BF539)
  150. default 6 if (BF533 || BF532 || BF531)
  151. choice
  152. prompt "Silicon Rev"
  153. default BF_REV_0_1 if (BF52x || BF54x)
  154. default BF_REV_0_2 if (BF534 || BF536 || BF537)
  155. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
  156. config BF_REV_0_0
  157. bool "0.0"
  158. depends on (BF52x || BF54x)
  159. config BF_REV_0_1
  160. bool "0.1"
  161. depends on (BF52x || BF54x)
  162. config BF_REV_0_2
  163. bool "0.2"
  164. depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
  165. config BF_REV_0_3
  166. bool "0.3"
  167. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  168. config BF_REV_0_4
  169. bool "0.4"
  170. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  171. config BF_REV_0_5
  172. bool "0.5"
  173. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  174. config BF_REV_0_6
  175. bool "0.6"
  176. depends on (BF533 || BF532 || BF531)
  177. config BF_REV_ANY
  178. bool "any"
  179. config BF_REV_NONE
  180. bool "none"
  181. endchoice
  182. config BF52x
  183. bool
  184. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  185. default y
  186. config BF53x
  187. bool
  188. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  189. default y
  190. config BF54x
  191. bool
  192. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  193. default y
  194. config MEM_GENERIC_BOARD
  195. bool
  196. depends on GENERIC_BOARD
  197. default y
  198. config MEM_MT48LC64M4A2FB_7E
  199. bool
  200. depends on (BFIN533_STAMP)
  201. default y
  202. config MEM_MT48LC16M16A2TG_75
  203. bool
  204. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  205. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  206. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  207. default y
  208. config MEM_MT48LC32M8A2_75
  209. bool
  210. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  211. default y
  212. config MEM_MT48LC8M32B2B5_7
  213. bool
  214. depends on (BFIN561_BLUETECHNIX_CM)
  215. default y
  216. config MEM_MT48LC32M16A2TG_75
  217. bool
  218. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
  219. default y
  220. source "arch/blackfin/mach-bf527/Kconfig"
  221. source "arch/blackfin/mach-bf533/Kconfig"
  222. source "arch/blackfin/mach-bf561/Kconfig"
  223. source "arch/blackfin/mach-bf537/Kconfig"
  224. source "arch/blackfin/mach-bf538/Kconfig"
  225. source "arch/blackfin/mach-bf548/Kconfig"
  226. menu "Board customizations"
  227. config CMDLINE_BOOL
  228. bool "Default bootloader kernel arguments"
  229. config CMDLINE
  230. string "Initial kernel command string"
  231. depends on CMDLINE_BOOL
  232. default "console=ttyBF0,57600"
  233. help
  234. If you don't have a boot loader capable of passing a command line string
  235. to the kernel, you may specify one here. As a minimum, you should specify
  236. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  237. config BOOT_LOAD
  238. hex "Kernel load address for booting"
  239. default "0x1000"
  240. range 0x1000 0x20000000
  241. help
  242. This option allows you to set the load address of the kernel.
  243. This can be useful if you are on a board which has a small amount
  244. of memory or you wish to reserve some memory at the beginning of
  245. the address space.
  246. Note that you need to keep this value above 4k (0x1000) as this
  247. memory region is used to capture NULL pointer references as well
  248. as some core kernel functions.
  249. config ROM_BASE
  250. hex "Kernel ROM Base"
  251. default "0x20040000"
  252. range 0x20000000 0x20400000 if !(BF54x || BF561)
  253. range 0x20000000 0x30000000 if (BF54x || BF561)
  254. help
  255. comment "Clock/PLL Setup"
  256. config CLKIN_HZ
  257. int "Frequency of the crystal on the board in Hz"
  258. default "11059200" if BFIN533_STAMP
  259. default "27000000" if BFIN533_EZKIT
  260. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT)
  261. default "30000000" if BFIN561_EZKIT
  262. default "24576000" if PNAV10
  263. default "10000000" if BFIN532_IP0X
  264. help
  265. The frequency of CLKIN crystal oscillator on the board in Hz.
  266. Warning: This value should match the crystal on the board. Otherwise,
  267. peripherals won't work properly.
  268. config BFIN_KERNEL_CLOCK
  269. bool "Re-program Clocks while Kernel boots?"
  270. default n
  271. help
  272. This option decides if kernel clocks are re-programed from the
  273. bootloader settings. If the clocks are not set, the SDRAM settings
  274. are also not changed, and the Bootloader does 100% of the hardware
  275. configuration.
  276. config PLL_BYPASS
  277. bool "Bypass PLL"
  278. depends on BFIN_KERNEL_CLOCK
  279. default n
  280. config CLKIN_HALF
  281. bool "Half Clock In"
  282. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  283. default n
  284. help
  285. If this is set the clock will be divided by 2, before it goes to the PLL.
  286. config VCO_MULT
  287. int "VCO Multiplier"
  288. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  289. range 1 64
  290. default "22" if BFIN533_EZKIT
  291. default "45" if BFIN533_STAMP
  292. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  293. default "22" if BFIN533_BLUETECHNIX_CM
  294. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  295. default "20" if BFIN561_EZKIT
  296. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
  297. help
  298. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  299. PLL Frequency = (Crystal Frequency) * (this setting)
  300. choice
  301. prompt "Core Clock Divider"
  302. depends on BFIN_KERNEL_CLOCK
  303. default CCLK_DIV_1
  304. help
  305. This sets the frequency of the core. It can be 1, 2, 4 or 8
  306. Core Frequency = (PLL frequency) / (this setting)
  307. config CCLK_DIV_1
  308. bool "1"
  309. config CCLK_DIV_2
  310. bool "2"
  311. config CCLK_DIV_4
  312. bool "4"
  313. config CCLK_DIV_8
  314. bool "8"
  315. endchoice
  316. config SCLK_DIV
  317. int "System Clock Divider"
  318. depends on BFIN_KERNEL_CLOCK
  319. range 1 15
  320. default 5
  321. help
  322. This sets the frequency of the system clock (including SDRAM or DDR).
  323. This can be between 1 and 15
  324. System Clock = (PLL frequency) / (this setting)
  325. choice
  326. prompt "DDR SDRAM Chip Type"
  327. depends on BFIN_KERNEL_CLOCK
  328. depends on BF54x
  329. default MEM_MT46V32M16_5B
  330. config MEM_MT46V32M16_6T
  331. bool "MT46V32M16_6T"
  332. config MEM_MT46V32M16_5B
  333. bool "MT46V32M16_5B"
  334. endchoice
  335. config MAX_MEM_SIZE
  336. int "Max SDRAM Memory Size in MBytes"
  337. depends on !MPU
  338. default 512
  339. help
  340. This is the max memory size that the kernel will create CPLB
  341. tables for. Your system will not be able to handle any more.
  342. #
  343. # Max & Min Speeds for various Chips
  344. #
  345. config MAX_VCO_HZ
  346. int
  347. default 600000000 if BF522
  348. default 400000000 if BF523
  349. default 400000000 if BF524
  350. default 600000000 if BF525
  351. default 400000000 if BF526
  352. default 600000000 if BF527
  353. default 400000000 if BF531
  354. default 400000000 if BF532
  355. default 750000000 if BF533
  356. default 500000000 if BF534
  357. default 400000000 if BF536
  358. default 600000000 if BF537
  359. default 533333333 if BF538
  360. default 533333333 if BF539
  361. default 600000000 if BF542
  362. default 533333333 if BF544
  363. default 600000000 if BF547
  364. default 600000000 if BF548
  365. default 533333333 if BF549
  366. default 600000000 if BF561
  367. config MIN_VCO_HZ
  368. int
  369. default 50000000
  370. config MAX_SCLK_HZ
  371. int
  372. default 133333333
  373. config MIN_SCLK_HZ
  374. int
  375. default 27000000
  376. comment "Kernel Timer/Scheduler"
  377. source kernel/Kconfig.hz
  378. config GENERIC_TIME
  379. bool "Generic time"
  380. default y
  381. config GENERIC_CLOCKEVENTS
  382. bool "Generic clock events"
  383. depends on GENERIC_TIME
  384. default y
  385. config CYCLES_CLOCKSOURCE
  386. bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
  387. depends on EXPERIMENTAL
  388. depends on GENERIC_CLOCKEVENTS
  389. depends on !BFIN_SCRATCH_REG_CYCLES
  390. default n
  391. help
  392. If you say Y here, you will enable support for using the 'cycles'
  393. registers as a clock source. Doing so means you will be unable to
  394. safely write to the 'cycles' register during runtime. You will
  395. still be able to read it (such as for performance monitoring), but
  396. writing the registers will most likely crash the kernel.
  397. source kernel/time/Kconfig
  398. comment "Misc"
  399. choice
  400. prompt "Blackfin Exception Scratch Register"
  401. default BFIN_SCRATCH_REG_RETN
  402. help
  403. Select the resource to reserve for the Exception handler:
  404. - RETN: Non-Maskable Interrupt (NMI)
  405. - RETE: Exception Return (JTAG/ICE)
  406. - CYCLES: Performance counter
  407. If you are unsure, please select "RETN".
  408. config BFIN_SCRATCH_REG_RETN
  409. bool "RETN"
  410. help
  411. Use the RETN register in the Blackfin exception handler
  412. as a stack scratch register. This means you cannot
  413. safely use NMI on the Blackfin while running Linux, but
  414. you can debug the system with a JTAG ICE and use the
  415. CYCLES performance registers.
  416. If you are unsure, please select "RETN".
  417. config BFIN_SCRATCH_REG_RETE
  418. bool "RETE"
  419. help
  420. Use the RETE register in the Blackfin exception handler
  421. as a stack scratch register. This means you cannot
  422. safely use a JTAG ICE while debugging a Blackfin board,
  423. but you can safely use the CYCLES performance registers
  424. and the NMI.
  425. If you are unsure, please select "RETN".
  426. config BFIN_SCRATCH_REG_CYCLES
  427. bool "CYCLES"
  428. help
  429. Use the CYCLES register in the Blackfin exception handler
  430. as a stack scratch register. This means you cannot
  431. safely use the CYCLES performance registers on a Blackfin
  432. board at anytime, but you can debug the system with a JTAG
  433. ICE and use the NMI.
  434. If you are unsure, please select "RETN".
  435. endchoice
  436. endmenu
  437. menu "Blackfin Kernel Optimizations"
  438. comment "Memory Optimizations"
  439. config I_ENTRY_L1
  440. bool "Locate interrupt entry code in L1 Memory"
  441. default y
  442. help
  443. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  444. into L1 instruction memory. (less latency)
  445. config EXCPT_IRQ_SYSC_L1
  446. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  447. default y
  448. help
  449. If enabled, the entire ASM lowlevel exception and interrupt entry code
  450. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  451. (less latency)
  452. config DO_IRQ_L1
  453. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  454. default y
  455. help
  456. If enabled, the frequently called do_irq dispatcher function is linked
  457. into L1 instruction memory. (less latency)
  458. config CORE_TIMER_IRQ_L1
  459. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  460. default y
  461. help
  462. If enabled, the frequently called timer_interrupt() function is linked
  463. into L1 instruction memory. (less latency)
  464. config IDLE_L1
  465. bool "Locate frequently idle function in L1 Memory"
  466. default y
  467. help
  468. If enabled, the frequently called idle function is linked
  469. into L1 instruction memory. (less latency)
  470. config SCHEDULE_L1
  471. bool "Locate kernel schedule function in L1 Memory"
  472. default y
  473. help
  474. If enabled, the frequently called kernel schedule is linked
  475. into L1 instruction memory. (less latency)
  476. config ARITHMETIC_OPS_L1
  477. bool "Locate kernel owned arithmetic functions in L1 Memory"
  478. default y
  479. help
  480. If enabled, arithmetic functions are linked
  481. into L1 instruction memory. (less latency)
  482. config ACCESS_OK_L1
  483. bool "Locate access_ok function in L1 Memory"
  484. default y
  485. help
  486. If enabled, the access_ok function is linked
  487. into L1 instruction memory. (less latency)
  488. config MEMSET_L1
  489. bool "Locate memset function in L1 Memory"
  490. default y
  491. help
  492. If enabled, the memset function is linked
  493. into L1 instruction memory. (less latency)
  494. config MEMCPY_L1
  495. bool "Locate memcpy function in L1 Memory"
  496. default y
  497. help
  498. If enabled, the memcpy function is linked
  499. into L1 instruction memory. (less latency)
  500. config SYS_BFIN_SPINLOCK_L1
  501. bool "Locate sys_bfin_spinlock function in L1 Memory"
  502. default y
  503. help
  504. If enabled, sys_bfin_spinlock function is linked
  505. into L1 instruction memory. (less latency)
  506. config IP_CHECKSUM_L1
  507. bool "Locate IP Checksum function in L1 Memory"
  508. default n
  509. help
  510. If enabled, the IP Checksum function is linked
  511. into L1 instruction memory. (less latency)
  512. config CACHELINE_ALIGNED_L1
  513. bool "Locate cacheline_aligned data to L1 Data Memory"
  514. default y if !BF54x
  515. default n if BF54x
  516. depends on !BF531
  517. help
  518. If enabled, cacheline_anligned data is linked
  519. into L1 data memory. (less latency)
  520. config SYSCALL_TAB_L1
  521. bool "Locate Syscall Table L1 Data Memory"
  522. default n
  523. depends on !BF531
  524. help
  525. If enabled, the Syscall LUT is linked
  526. into L1 data memory. (less latency)
  527. config CPLB_SWITCH_TAB_L1
  528. bool "Locate CPLB Switch Tables L1 Data Memory"
  529. default n
  530. depends on !BF531
  531. help
  532. If enabled, the CPLB Switch Tables are linked
  533. into L1 data memory. (less latency)
  534. config APP_STACK_L1
  535. bool "Support locating application stack in L1 Scratch Memory"
  536. default y
  537. help
  538. If enabled the application stack can be located in L1
  539. scratch memory (less latency).
  540. Currently only works with FLAT binaries.
  541. config EXCEPTION_L1_SCRATCH
  542. bool "Locate exception stack in L1 Scratch Memory"
  543. default n
  544. depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
  545. help
  546. Whenever an exception occurs, use the L1 Scratch memory for
  547. stack storage. You cannot place the stacks of FLAT binaries
  548. in L1 when using this option.
  549. If you don't use L1 Scratch, then you should say Y here.
  550. comment "Speed Optimizations"
  551. config BFIN_INS_LOWOVERHEAD
  552. bool "ins[bwl] low overhead, higher interrupt latency"
  553. default y
  554. help
  555. Reads on the Blackfin are speculative. In Blackfin terms, this means
  556. they can be interrupted at any time (even after they have been issued
  557. on to the external bus), and re-issued after the interrupt occurs.
  558. For memory - this is not a big deal, since memory does not change if
  559. it sees a read.
  560. If a FIFO is sitting on the end of the read, it will see two reads,
  561. when the core only sees one since the FIFO receives both the read
  562. which is cancelled (and not delivered to the core) and the one which
  563. is re-issued (which is delivered to the core).
  564. To solve this, interrupts are turned off before reads occur to
  565. I/O space. This option controls which the overhead/latency of
  566. controlling interrupts during this time
  567. "n" turns interrupts off every read
  568. (higher overhead, but lower interrupt latency)
  569. "y" turns interrupts off every loop
  570. (low overhead, but longer interrupt latency)
  571. default behavior is to leave this set to on (type "Y"). If you are experiencing
  572. interrupt latency issues, it is safe and OK to turn this off.
  573. endmenu
  574. choice
  575. prompt "Kernel executes from"
  576. help
  577. Choose the memory type that the kernel will be running in.
  578. config RAMKERNEL
  579. bool "RAM"
  580. help
  581. The kernel will be resident in RAM when running.
  582. config ROMKERNEL
  583. bool "ROM"
  584. help
  585. The kernel will be resident in FLASH/ROM when running.
  586. endchoice
  587. source "mm/Kconfig"
  588. config BFIN_GPTIMERS
  589. tristate "Enable Blackfin General Purpose Timers API"
  590. default n
  591. help
  592. Enable support for the General Purpose Timers API. If you
  593. are unsure, say N.
  594. To compile this driver as a module, choose M here: the module
  595. will be called gptimers.ko.
  596. config BFIN_DMA_5XX
  597. bool "Enable DMA Support"
  598. depends on (BF52x || BF53x || BF561 || BF54x || BF538 || BF539)
  599. default y
  600. help
  601. DMA driver for BF5xx.
  602. choice
  603. prompt "Uncached SDRAM region"
  604. default DMA_UNCACHED_1M
  605. depends on BFIN_DMA_5XX
  606. config DMA_UNCACHED_4M
  607. bool "Enable 4M DMA region"
  608. config DMA_UNCACHED_2M
  609. bool "Enable 2M DMA region"
  610. config DMA_UNCACHED_1M
  611. bool "Enable 1M DMA region"
  612. config DMA_UNCACHED_NONE
  613. bool "Disable DMA region"
  614. endchoice
  615. comment "Cache Support"
  616. config BFIN_ICACHE
  617. bool "Enable ICACHE"
  618. config BFIN_DCACHE
  619. bool "Enable DCACHE"
  620. config BFIN_DCACHE_BANKA
  621. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  622. depends on BFIN_DCACHE && !BF531
  623. default n
  624. config BFIN_ICACHE_LOCK
  625. bool "Enable Instruction Cache Locking"
  626. choice
  627. prompt "Policy"
  628. depends on BFIN_DCACHE
  629. default BFIN_WB
  630. config BFIN_WB
  631. bool "Write back"
  632. help
  633. Write Back Policy:
  634. Cached data will be written back to SDRAM only when needed.
  635. This can give a nice increase in performance, but beware of
  636. broken drivers that do not properly invalidate/flush their
  637. cache.
  638. Write Through Policy:
  639. Cached data will always be written back to SDRAM when the
  640. cache is updated. This is a completely safe setting, but
  641. performance is worse than Write Back.
  642. If you are unsure of the options and you want to be safe,
  643. then go with Write Through.
  644. config BFIN_WT
  645. bool "Write through"
  646. help
  647. Write Back Policy:
  648. Cached data will be written back to SDRAM only when needed.
  649. This can give a nice increase in performance, but beware of
  650. broken drivers that do not properly invalidate/flush their
  651. cache.
  652. Write Through Policy:
  653. Cached data will always be written back to SDRAM when the
  654. cache is updated. This is a completely safe setting, but
  655. performance is worse than Write Back.
  656. If you are unsure of the options and you want to be safe,
  657. then go with Write Through.
  658. endchoice
  659. config BFIN_L2_CACHEABLE
  660. bool "Cache L2 SRAM"
  661. depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
  662. default n
  663. help
  664. Select to make L2 SRAM cacheable in L1 data and instruction cache.
  665. config MPU
  666. bool "Enable the memory protection unit (EXPERIMENTAL)"
  667. default n
  668. help
  669. Use the processor's MPU to protect applications from accessing
  670. memory they do not own. This comes at a performance penalty
  671. and is recommended only for debugging.
  672. comment "Asynchonous Memory Configuration"
  673. menu "EBIU_AMGCTL Global Control"
  674. config C_AMCKEN
  675. bool "Enable CLKOUT"
  676. default y
  677. config C_CDPRIO
  678. bool "DMA has priority over core for ext. accesses"
  679. default n
  680. config C_B0PEN
  681. depends on BF561
  682. bool "Bank 0 16 bit packing enable"
  683. default y
  684. config C_B1PEN
  685. depends on BF561
  686. bool "Bank 1 16 bit packing enable"
  687. default y
  688. config C_B2PEN
  689. depends on BF561
  690. bool "Bank 2 16 bit packing enable"
  691. default y
  692. config C_B3PEN
  693. depends on BF561
  694. bool "Bank 3 16 bit packing enable"
  695. default n
  696. choice
  697. prompt"Enable Asynchonous Memory Banks"
  698. default C_AMBEN_ALL
  699. config C_AMBEN
  700. bool "Disable All Banks"
  701. config C_AMBEN_B0
  702. bool "Enable Bank 0"
  703. config C_AMBEN_B0_B1
  704. bool "Enable Bank 0 & 1"
  705. config C_AMBEN_B0_B1_B2
  706. bool "Enable Bank 0 & 1 & 2"
  707. config C_AMBEN_ALL
  708. bool "Enable All Banks"
  709. endchoice
  710. endmenu
  711. menu "EBIU_AMBCTL Control"
  712. config BANK_0
  713. hex "Bank 0"
  714. default 0x7BB0
  715. config BANK_1
  716. hex "Bank 1"
  717. default 0x7BB0
  718. default 0x5558 if BF54x
  719. config BANK_2
  720. hex "Bank 2"
  721. default 0x7BB0
  722. config BANK_3
  723. hex "Bank 3"
  724. default 0x99B3
  725. endmenu
  726. config EBIU_MBSCTLVAL
  727. hex "EBIU Bank Select Control Register"
  728. depends on BF54x
  729. default 0
  730. config EBIU_MODEVAL
  731. hex "Flash Memory Mode Control Register"
  732. depends on BF54x
  733. default 1
  734. config EBIU_FCTLVAL
  735. hex "Flash Memory Bank Control Register"
  736. depends on BF54x
  737. default 6
  738. endmenu
  739. #############################################################################
  740. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  741. config PCI
  742. bool "PCI support"
  743. depends on BROKEN
  744. help
  745. Support for PCI bus.
  746. source "drivers/pci/Kconfig"
  747. config HOTPLUG
  748. bool "Support for hot-pluggable device"
  749. help
  750. Say Y here if you want to plug devices into your computer while
  751. the system is running, and be able to use them quickly. In many
  752. cases, the devices can likewise be unplugged at any time too.
  753. One well known example of this is PCMCIA- or PC-cards, credit-card
  754. size devices such as network cards, modems or hard drives which are
  755. plugged into slots found on all modern laptop computers. Another
  756. example, used on modern desktops as well as laptops, is USB.
  757. Enable HOTPLUG and build a modular kernel. Get agent software
  758. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  759. Then your kernel will automatically call out to a user mode "policy
  760. agent" (/sbin/hotplug) to load modules and set up software needed
  761. to use devices as you hotplug them.
  762. source "drivers/pcmcia/Kconfig"
  763. source "drivers/pci/hotplug/Kconfig"
  764. endmenu
  765. menu "Executable file formats"
  766. source "fs/Kconfig.binfmt"
  767. endmenu
  768. menu "Power management options"
  769. source "kernel/power/Kconfig"
  770. config ARCH_SUSPEND_POSSIBLE
  771. def_bool y
  772. depends on !SMP
  773. choice
  774. prompt "Standby Power Saving Mode"
  775. depends on PM
  776. default PM_BFIN_SLEEP_DEEPER
  777. config PM_BFIN_SLEEP_DEEPER
  778. bool "Sleep Deeper"
  779. help
  780. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  781. power dissipation by disabling the clock to the processor core (CCLK).
  782. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  783. to 0.85 V to provide the greatest power savings, while preserving the
  784. processor state.
  785. The PLL and system clock (SCLK) continue to operate at a very low
  786. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  787. the SDRAM is put into Self Refresh Mode. Typically an external event
  788. such as GPIO interrupt or RTC activity wakes up the processor.
  789. Various Peripherals such as UART, SPORT, PPI may not function as
  790. normal during Sleep Deeper, due to the reduced SCLK frequency.
  791. When in the sleep mode, system DMA access to L1 memory is not supported.
  792. If unsure, select "Sleep Deeper".
  793. config PM_BFIN_SLEEP
  794. bool "Sleep"
  795. help
  796. Sleep Mode (High Power Savings) - The sleep mode reduces power
  797. dissipation by disabling the clock to the processor core (CCLK).
  798. The PLL and system clock (SCLK), however, continue to operate in
  799. this mode. Typically an external event or RTC activity will wake
  800. up the processor. When in the sleep mode, system DMA access to L1
  801. memory is not supported.
  802. If unsure, select "Sleep Deeper".
  803. endchoice
  804. config PM_WAKEUP_BY_GPIO
  805. bool "Allow Wakeup from Standby by GPIO"
  806. config PM_WAKEUP_GPIO_NUMBER
  807. int "GPIO number"
  808. range 0 47
  809. depends on PM_WAKEUP_BY_GPIO
  810. default 2 if BFIN537_STAMP
  811. choice
  812. prompt "GPIO Polarity"
  813. depends on PM_WAKEUP_BY_GPIO
  814. default PM_WAKEUP_GPIO_POLAR_H
  815. config PM_WAKEUP_GPIO_POLAR_H
  816. bool "Active High"
  817. config PM_WAKEUP_GPIO_POLAR_L
  818. bool "Active Low"
  819. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  820. bool "Falling EDGE"
  821. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  822. bool "Rising EDGE"
  823. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  824. bool "Both EDGE"
  825. endchoice
  826. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  827. depends on PM
  828. config PM_BFIN_WAKE_PH6
  829. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  830. depends on PM && (BF52x || BF534 || BF536 || BF537)
  831. default n
  832. help
  833. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  834. config PM_BFIN_WAKE_GP
  835. bool "Allow Wake-Up from GPIOs"
  836. depends on PM && BF54x
  837. default n
  838. help
  839. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  840. endmenu
  841. menu "CPU Frequency scaling"
  842. source "drivers/cpufreq/Kconfig"
  843. config CPU_VOLTAGE
  844. bool "CPU Voltage scaling"
  845. depends on EXPERIMENTAL
  846. depends on CPU_FREQ
  847. default n
  848. help
  849. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  850. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  851. manuals. There is a theoretical risk that during VDDINT transitions
  852. the PLL may unlock.
  853. endmenu
  854. source "net/Kconfig"
  855. source "drivers/Kconfig"
  856. source "fs/Kconfig"
  857. source "arch/blackfin/Kconfig.debug"
  858. source "security/Kconfig"
  859. source "crypto/Kconfig"
  860. source "lib/Kconfig"