ymfpci_main.c 71 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/firmware.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/sched.h>
  26. #include <linux/slab.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/mutex.h>
  29. #include <sound/core.h>
  30. #include <sound/control.h>
  31. #include <sound/info.h>
  32. #include <sound/tlv.h>
  33. #include <sound/ymfpci.h>
  34. #include <sound/asoundef.h>
  35. #include <sound/mpu401.h>
  36. #include <asm/io.h>
  37. #include <asm/byteorder.h>
  38. /*
  39. * common I/O routines
  40. */
  41. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  42. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  43. {
  44. return readb(chip->reg_area_virt + offset);
  45. }
  46. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  47. {
  48. writeb(val, chip->reg_area_virt + offset);
  49. }
  50. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  51. {
  52. return readw(chip->reg_area_virt + offset);
  53. }
  54. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  55. {
  56. writew(val, chip->reg_area_virt + offset);
  57. }
  58. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  59. {
  60. return readl(chip->reg_area_virt + offset);
  61. }
  62. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  63. {
  64. writel(val, chip->reg_area_virt + offset);
  65. }
  66. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  67. {
  68. unsigned long end_time;
  69. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  70. end_time = jiffies + msecs_to_jiffies(750);
  71. do {
  72. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  73. return 0;
  74. schedule_timeout_uninterruptible(1);
  75. } while (time_before(jiffies, end_time));
  76. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  77. return -EBUSY;
  78. }
  79. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  80. {
  81. struct snd_ymfpci *chip = ac97->private_data;
  82. u32 cmd;
  83. snd_ymfpci_codec_ready(chip, 0);
  84. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  85. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  86. }
  87. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  88. {
  89. struct snd_ymfpci *chip = ac97->private_data;
  90. if (snd_ymfpci_codec_ready(chip, 0))
  91. return ~0;
  92. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  93. if (snd_ymfpci_codec_ready(chip, 0))
  94. return ~0;
  95. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  96. int i;
  97. for (i = 0; i < 600; i++)
  98. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  99. }
  100. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  101. }
  102. /*
  103. * Misc routines
  104. */
  105. static u32 snd_ymfpci_calc_delta(u32 rate)
  106. {
  107. switch (rate) {
  108. case 8000: return 0x02aaab00;
  109. case 11025: return 0x03accd00;
  110. case 16000: return 0x05555500;
  111. case 22050: return 0x07599a00;
  112. case 32000: return 0x0aaaab00;
  113. case 44100: return 0x0eb33300;
  114. default: return ((rate << 16) / 375) << 5;
  115. }
  116. }
  117. static u32 def_rate[8] = {
  118. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  119. };
  120. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  121. {
  122. u32 i;
  123. static u32 val[8] = {
  124. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  125. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  126. };
  127. if (rate == 44100)
  128. return 0x40000000; /* FIXME: What's the right value? */
  129. for (i = 0; i < 8; i++)
  130. if (rate <= def_rate[i])
  131. return val[i];
  132. return val[0];
  133. }
  134. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  135. {
  136. u32 i;
  137. static u32 val[8] = {
  138. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  139. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  140. };
  141. if (rate == 44100)
  142. return 0x370A0000;
  143. for (i = 0; i < 8; i++)
  144. if (rate <= def_rate[i])
  145. return val[i];
  146. return val[0];
  147. }
  148. /*
  149. * Hardware start management
  150. */
  151. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  152. {
  153. unsigned long flags;
  154. spin_lock_irqsave(&chip->reg_lock, flags);
  155. if (chip->start_count++ > 0)
  156. goto __end;
  157. snd_ymfpci_writel(chip, YDSXGR_MODE,
  158. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  159. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  160. __end:
  161. spin_unlock_irqrestore(&chip->reg_lock, flags);
  162. }
  163. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  164. {
  165. unsigned long flags;
  166. long timeout = 1000;
  167. spin_lock_irqsave(&chip->reg_lock, flags);
  168. if (--chip->start_count > 0)
  169. goto __end;
  170. snd_ymfpci_writel(chip, YDSXGR_MODE,
  171. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  172. while (timeout-- > 0) {
  173. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  174. break;
  175. }
  176. if (atomic_read(&chip->interrupt_sleep_count)) {
  177. atomic_set(&chip->interrupt_sleep_count, 0);
  178. wake_up(&chip->interrupt_sleep);
  179. }
  180. __end:
  181. spin_unlock_irqrestore(&chip->reg_lock, flags);
  182. }
  183. /*
  184. * Playback voice management
  185. */
  186. static int voice_alloc(struct snd_ymfpci *chip,
  187. enum snd_ymfpci_voice_type type, int pair,
  188. struct snd_ymfpci_voice **rvoice)
  189. {
  190. struct snd_ymfpci_voice *voice, *voice2;
  191. int idx;
  192. *rvoice = NULL;
  193. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  194. voice = &chip->voices[idx];
  195. voice2 = pair ? &chip->voices[idx+1] : NULL;
  196. if (voice->use || (voice2 && voice2->use))
  197. continue;
  198. voice->use = 1;
  199. if (voice2)
  200. voice2->use = 1;
  201. switch (type) {
  202. case YMFPCI_PCM:
  203. voice->pcm = 1;
  204. if (voice2)
  205. voice2->pcm = 1;
  206. break;
  207. case YMFPCI_SYNTH:
  208. voice->synth = 1;
  209. break;
  210. case YMFPCI_MIDI:
  211. voice->midi = 1;
  212. break;
  213. }
  214. snd_ymfpci_hw_start(chip);
  215. if (voice2)
  216. snd_ymfpci_hw_start(chip);
  217. *rvoice = voice;
  218. return 0;
  219. }
  220. return -ENOMEM;
  221. }
  222. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  223. enum snd_ymfpci_voice_type type, int pair,
  224. struct snd_ymfpci_voice **rvoice)
  225. {
  226. unsigned long flags;
  227. int result;
  228. if (snd_BUG_ON(!rvoice))
  229. return -EINVAL;
  230. if (snd_BUG_ON(pair && type != YMFPCI_PCM))
  231. return -EINVAL;
  232. spin_lock_irqsave(&chip->voice_lock, flags);
  233. for (;;) {
  234. result = voice_alloc(chip, type, pair, rvoice);
  235. if (result == 0 || type != YMFPCI_PCM)
  236. break;
  237. /* TODO: synth/midi voice deallocation */
  238. break;
  239. }
  240. spin_unlock_irqrestore(&chip->voice_lock, flags);
  241. return result;
  242. }
  243. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  244. {
  245. unsigned long flags;
  246. if (snd_BUG_ON(!pvoice))
  247. return -EINVAL;
  248. snd_ymfpci_hw_stop(chip);
  249. spin_lock_irqsave(&chip->voice_lock, flags);
  250. if (pvoice->number == chip->src441_used) {
  251. chip->src441_used = -1;
  252. pvoice->ypcm->use_441_slot = 0;
  253. }
  254. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  255. pvoice->ypcm = NULL;
  256. pvoice->interrupt = NULL;
  257. spin_unlock_irqrestore(&chip->voice_lock, flags);
  258. return 0;
  259. }
  260. /*
  261. * PCM part
  262. */
  263. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  264. {
  265. struct snd_ymfpci_pcm *ypcm;
  266. u32 pos, delta;
  267. if ((ypcm = voice->ypcm) == NULL)
  268. return;
  269. if (ypcm->substream == NULL)
  270. return;
  271. spin_lock(&chip->reg_lock);
  272. if (ypcm->running) {
  273. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  274. if (pos < ypcm->last_pos)
  275. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  276. else
  277. delta = pos - ypcm->last_pos;
  278. ypcm->period_pos += delta;
  279. ypcm->last_pos = pos;
  280. if (ypcm->period_pos >= ypcm->period_size) {
  281. /*
  282. printk(KERN_DEBUG
  283. "done - active_bank = 0x%x, start = 0x%x\n",
  284. chip->active_bank,
  285. voice->bank[chip->active_bank].start);
  286. */
  287. ypcm->period_pos %= ypcm->period_size;
  288. spin_unlock(&chip->reg_lock);
  289. snd_pcm_period_elapsed(ypcm->substream);
  290. spin_lock(&chip->reg_lock);
  291. }
  292. if (unlikely(ypcm->update_pcm_vol)) {
  293. unsigned int subs = ypcm->substream->number;
  294. unsigned int next_bank = 1 - chip->active_bank;
  295. struct snd_ymfpci_playback_bank *bank;
  296. u32 volume;
  297. bank = &voice->bank[next_bank];
  298. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  299. bank->left_gain_end = volume;
  300. if (ypcm->output_rear)
  301. bank->eff2_gain_end = volume;
  302. if (ypcm->voices[1])
  303. bank = &ypcm->voices[1]->bank[next_bank];
  304. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  305. bank->right_gain_end = volume;
  306. if (ypcm->output_rear)
  307. bank->eff3_gain_end = volume;
  308. ypcm->update_pcm_vol--;
  309. }
  310. }
  311. spin_unlock(&chip->reg_lock);
  312. }
  313. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  314. {
  315. struct snd_pcm_runtime *runtime = substream->runtime;
  316. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  317. struct snd_ymfpci *chip = ypcm->chip;
  318. u32 pos, delta;
  319. spin_lock(&chip->reg_lock);
  320. if (ypcm->running) {
  321. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  322. if (pos < ypcm->last_pos)
  323. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  324. else
  325. delta = pos - ypcm->last_pos;
  326. ypcm->period_pos += delta;
  327. ypcm->last_pos = pos;
  328. if (ypcm->period_pos >= ypcm->period_size) {
  329. ypcm->period_pos %= ypcm->period_size;
  330. /*
  331. printk(KERN_DEBUG
  332. "done - active_bank = 0x%x, start = 0x%x\n",
  333. chip->active_bank,
  334. voice->bank[chip->active_bank].start);
  335. */
  336. spin_unlock(&chip->reg_lock);
  337. snd_pcm_period_elapsed(substream);
  338. spin_lock(&chip->reg_lock);
  339. }
  340. }
  341. spin_unlock(&chip->reg_lock);
  342. }
  343. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  344. int cmd)
  345. {
  346. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  347. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  348. struct snd_kcontrol *kctl = NULL;
  349. int result = 0;
  350. spin_lock(&chip->reg_lock);
  351. if (ypcm->voices[0] == NULL) {
  352. result = -EINVAL;
  353. goto __unlock;
  354. }
  355. switch (cmd) {
  356. case SNDRV_PCM_TRIGGER_START:
  357. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  358. case SNDRV_PCM_TRIGGER_RESUME:
  359. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  360. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  361. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  362. ypcm->running = 1;
  363. break;
  364. case SNDRV_PCM_TRIGGER_STOP:
  365. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  366. kctl = chip->pcm_mixer[substream->number].ctl;
  367. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  368. }
  369. /* fall through */
  370. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  371. case SNDRV_PCM_TRIGGER_SUSPEND:
  372. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  373. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  374. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  375. ypcm->running = 0;
  376. break;
  377. default:
  378. result = -EINVAL;
  379. break;
  380. }
  381. __unlock:
  382. spin_unlock(&chip->reg_lock);
  383. if (kctl)
  384. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  385. return result;
  386. }
  387. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  388. int cmd)
  389. {
  390. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  391. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  392. int result = 0;
  393. u32 tmp;
  394. spin_lock(&chip->reg_lock);
  395. switch (cmd) {
  396. case SNDRV_PCM_TRIGGER_START:
  397. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  398. case SNDRV_PCM_TRIGGER_RESUME:
  399. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  400. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  401. ypcm->running = 1;
  402. break;
  403. case SNDRV_PCM_TRIGGER_STOP:
  404. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  405. case SNDRV_PCM_TRIGGER_SUSPEND:
  406. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  407. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  408. ypcm->running = 0;
  409. break;
  410. default:
  411. result = -EINVAL;
  412. break;
  413. }
  414. spin_unlock(&chip->reg_lock);
  415. return result;
  416. }
  417. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  418. {
  419. int err;
  420. if (ypcm->voices[1] != NULL && voices < 2) {
  421. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  422. ypcm->voices[1] = NULL;
  423. }
  424. if (voices == 1 && ypcm->voices[0] != NULL)
  425. return 0; /* already allocated */
  426. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  427. return 0; /* already allocated */
  428. if (voices > 1) {
  429. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  430. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  431. ypcm->voices[0] = NULL;
  432. }
  433. }
  434. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  435. if (err < 0)
  436. return err;
  437. ypcm->voices[0]->ypcm = ypcm;
  438. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  439. if (voices > 1) {
  440. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  441. ypcm->voices[1]->ypcm = ypcm;
  442. }
  443. return 0;
  444. }
  445. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  446. struct snd_pcm_runtime *runtime,
  447. int has_pcm_volume)
  448. {
  449. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  450. u32 format;
  451. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  452. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  453. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  454. struct snd_ymfpci_playback_bank *bank;
  455. unsigned int nbank;
  456. u32 vol_left, vol_right;
  457. u8 use_left, use_right;
  458. unsigned long flags;
  459. if (snd_BUG_ON(!voice))
  460. return;
  461. if (runtime->channels == 1) {
  462. use_left = 1;
  463. use_right = 1;
  464. } else {
  465. use_left = (voiceidx & 1) == 0;
  466. use_right = !use_left;
  467. }
  468. if (has_pcm_volume) {
  469. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  470. [ypcm->substream->number].left << 15);
  471. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  472. [ypcm->substream->number].right << 15);
  473. } else {
  474. vol_left = cpu_to_le32(0x40000000);
  475. vol_right = cpu_to_le32(0x40000000);
  476. }
  477. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  478. format = runtime->channels == 2 ? 0x00010000 : 0;
  479. if (snd_pcm_format_width(runtime->format) == 8)
  480. format |= 0x80000000;
  481. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  482. runtime->rate == 44100 && runtime->channels == 2 &&
  483. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  484. ypcm->chip->src441_used == voice->number)) {
  485. ypcm->chip->src441_used = voice->number;
  486. ypcm->use_441_slot = 1;
  487. format |= 0x10000000;
  488. }
  489. if (ypcm->chip->src441_used == voice->number &&
  490. (format & 0x10000000) == 0) {
  491. ypcm->chip->src441_used = -1;
  492. ypcm->use_441_slot = 0;
  493. }
  494. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  495. format |= 1;
  496. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  497. for (nbank = 0; nbank < 2; nbank++) {
  498. bank = &voice->bank[nbank];
  499. memset(bank, 0, sizeof(*bank));
  500. bank->format = cpu_to_le32(format);
  501. bank->base = cpu_to_le32(runtime->dma_addr);
  502. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  503. bank->lpfQ = cpu_to_le32(lpfQ);
  504. bank->delta =
  505. bank->delta_end = cpu_to_le32(delta);
  506. bank->lpfK =
  507. bank->lpfK_end = cpu_to_le32(lpfK);
  508. bank->eg_gain =
  509. bank->eg_gain_end = cpu_to_le32(0x40000000);
  510. if (ypcm->output_front) {
  511. if (use_left) {
  512. bank->left_gain =
  513. bank->left_gain_end = vol_left;
  514. }
  515. if (use_right) {
  516. bank->right_gain =
  517. bank->right_gain_end = vol_right;
  518. }
  519. }
  520. if (ypcm->output_rear) {
  521. if (!ypcm->swap_rear) {
  522. if (use_left) {
  523. bank->eff2_gain =
  524. bank->eff2_gain_end = vol_left;
  525. }
  526. if (use_right) {
  527. bank->eff3_gain =
  528. bank->eff3_gain_end = vol_right;
  529. }
  530. } else {
  531. /* The SPDIF out channels seem to be swapped, so we have
  532. * to swap them here, too. The rear analog out channels
  533. * will be wrong, but otherwise AC3 would not work.
  534. */
  535. if (use_left) {
  536. bank->eff3_gain =
  537. bank->eff3_gain_end = vol_left;
  538. }
  539. if (use_right) {
  540. bank->eff2_gain =
  541. bank->eff2_gain_end = vol_right;
  542. }
  543. }
  544. }
  545. }
  546. }
  547. static int __devinit snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  548. {
  549. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  550. 4096, &chip->ac3_tmp_base) < 0)
  551. return -ENOMEM;
  552. chip->bank_effect[3][0]->base =
  553. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  554. chip->bank_effect[3][0]->loop_end =
  555. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  556. chip->bank_effect[4][0]->base =
  557. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  558. chip->bank_effect[4][0]->loop_end =
  559. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  560. spin_lock_irq(&chip->reg_lock);
  561. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  562. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  563. spin_unlock_irq(&chip->reg_lock);
  564. return 0;
  565. }
  566. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  567. {
  568. spin_lock_irq(&chip->reg_lock);
  569. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  570. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  571. spin_unlock_irq(&chip->reg_lock);
  572. // snd_ymfpci_irq_wait(chip);
  573. if (chip->ac3_tmp_base.area) {
  574. snd_dma_free_pages(&chip->ac3_tmp_base);
  575. chip->ac3_tmp_base.area = NULL;
  576. }
  577. return 0;
  578. }
  579. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  580. struct snd_pcm_hw_params *hw_params)
  581. {
  582. struct snd_pcm_runtime *runtime = substream->runtime;
  583. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  584. int err;
  585. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  586. return err;
  587. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  588. return err;
  589. return 0;
  590. }
  591. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  592. {
  593. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  594. struct snd_pcm_runtime *runtime = substream->runtime;
  595. struct snd_ymfpci_pcm *ypcm;
  596. if (runtime->private_data == NULL)
  597. return 0;
  598. ypcm = runtime->private_data;
  599. /* wait, until the PCI operations are not finished */
  600. snd_ymfpci_irq_wait(chip);
  601. snd_pcm_lib_free_pages(substream);
  602. if (ypcm->voices[1]) {
  603. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  604. ypcm->voices[1] = NULL;
  605. }
  606. if (ypcm->voices[0]) {
  607. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  608. ypcm->voices[0] = NULL;
  609. }
  610. return 0;
  611. }
  612. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  613. {
  614. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  615. struct snd_pcm_runtime *runtime = substream->runtime;
  616. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  617. struct snd_kcontrol *kctl;
  618. unsigned int nvoice;
  619. ypcm->period_size = runtime->period_size;
  620. ypcm->buffer_size = runtime->buffer_size;
  621. ypcm->period_pos = 0;
  622. ypcm->last_pos = 0;
  623. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  624. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  625. substream->pcm == chip->pcm);
  626. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  627. kctl = chip->pcm_mixer[substream->number].ctl;
  628. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  629. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  630. }
  631. return 0;
  632. }
  633. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  634. struct snd_pcm_hw_params *hw_params)
  635. {
  636. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  637. }
  638. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  639. {
  640. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  641. /* wait, until the PCI operations are not finished */
  642. snd_ymfpci_irq_wait(chip);
  643. return snd_pcm_lib_free_pages(substream);
  644. }
  645. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  646. {
  647. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  648. struct snd_pcm_runtime *runtime = substream->runtime;
  649. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  650. struct snd_ymfpci_capture_bank * bank;
  651. int nbank;
  652. u32 rate, format;
  653. ypcm->period_size = runtime->period_size;
  654. ypcm->buffer_size = runtime->buffer_size;
  655. ypcm->period_pos = 0;
  656. ypcm->last_pos = 0;
  657. ypcm->shift = 0;
  658. rate = ((48000 * 4096) / runtime->rate) - 1;
  659. format = 0;
  660. if (runtime->channels == 2) {
  661. format |= 2;
  662. ypcm->shift++;
  663. }
  664. if (snd_pcm_format_width(runtime->format) == 8)
  665. format |= 1;
  666. else
  667. ypcm->shift++;
  668. switch (ypcm->capture_bank_number) {
  669. case 0:
  670. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  671. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  672. break;
  673. case 1:
  674. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  675. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  676. break;
  677. }
  678. for (nbank = 0; nbank < 2; nbank++) {
  679. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  680. bank->base = cpu_to_le32(runtime->dma_addr);
  681. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  682. bank->start = 0;
  683. bank->num_of_loops = 0;
  684. }
  685. return 0;
  686. }
  687. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  688. {
  689. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  690. struct snd_pcm_runtime *runtime = substream->runtime;
  691. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  692. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  693. if (!(ypcm->running && voice))
  694. return 0;
  695. return le32_to_cpu(voice->bank[chip->active_bank].start);
  696. }
  697. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  698. {
  699. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  700. struct snd_pcm_runtime *runtime = substream->runtime;
  701. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  702. if (!ypcm->running)
  703. return 0;
  704. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  705. }
  706. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  707. {
  708. wait_queue_t wait;
  709. int loops = 4;
  710. while (loops-- > 0) {
  711. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  712. continue;
  713. init_waitqueue_entry(&wait, current);
  714. add_wait_queue(&chip->interrupt_sleep, &wait);
  715. atomic_inc(&chip->interrupt_sleep_count);
  716. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  717. remove_wait_queue(&chip->interrupt_sleep, &wait);
  718. }
  719. }
  720. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  721. {
  722. struct snd_ymfpci *chip = dev_id;
  723. u32 status, nvoice, mode;
  724. struct snd_ymfpci_voice *voice;
  725. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  726. if (status & 0x80000000) {
  727. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  728. spin_lock(&chip->voice_lock);
  729. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  730. voice = &chip->voices[nvoice];
  731. if (voice->interrupt)
  732. voice->interrupt(chip, voice);
  733. }
  734. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  735. if (chip->capture_substream[nvoice])
  736. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  737. }
  738. #if 0
  739. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  740. if (chip->effect_substream[nvoice])
  741. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  742. }
  743. #endif
  744. spin_unlock(&chip->voice_lock);
  745. spin_lock(&chip->reg_lock);
  746. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  747. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  748. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  749. spin_unlock(&chip->reg_lock);
  750. if (atomic_read(&chip->interrupt_sleep_count)) {
  751. atomic_set(&chip->interrupt_sleep_count, 0);
  752. wake_up(&chip->interrupt_sleep);
  753. }
  754. }
  755. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  756. if (status & 1) {
  757. if (chip->timer)
  758. snd_timer_interrupt(chip->timer, chip->timer_ticks);
  759. }
  760. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  761. if (chip->rawmidi)
  762. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  763. return IRQ_HANDLED;
  764. }
  765. static struct snd_pcm_hardware snd_ymfpci_playback =
  766. {
  767. .info = (SNDRV_PCM_INFO_MMAP |
  768. SNDRV_PCM_INFO_MMAP_VALID |
  769. SNDRV_PCM_INFO_INTERLEAVED |
  770. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  771. SNDRV_PCM_INFO_PAUSE |
  772. SNDRV_PCM_INFO_RESUME),
  773. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  774. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  775. .rate_min = 8000,
  776. .rate_max = 48000,
  777. .channels_min = 1,
  778. .channels_max = 2,
  779. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  780. .period_bytes_min = 64,
  781. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  782. .periods_min = 3,
  783. .periods_max = 1024,
  784. .fifo_size = 0,
  785. };
  786. static struct snd_pcm_hardware snd_ymfpci_capture =
  787. {
  788. .info = (SNDRV_PCM_INFO_MMAP |
  789. SNDRV_PCM_INFO_MMAP_VALID |
  790. SNDRV_PCM_INFO_INTERLEAVED |
  791. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  792. SNDRV_PCM_INFO_PAUSE |
  793. SNDRV_PCM_INFO_RESUME),
  794. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  795. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  796. .rate_min = 8000,
  797. .rate_max = 48000,
  798. .channels_min = 1,
  799. .channels_max = 2,
  800. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  801. .period_bytes_min = 64,
  802. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  803. .periods_min = 3,
  804. .periods_max = 1024,
  805. .fifo_size = 0,
  806. };
  807. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  808. {
  809. kfree(runtime->private_data);
  810. }
  811. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  812. {
  813. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  814. struct snd_pcm_runtime *runtime = substream->runtime;
  815. struct snd_ymfpci_pcm *ypcm;
  816. int err;
  817. runtime->hw = snd_ymfpci_playback;
  818. /* FIXME? True value is 256/48 = 5.33333 ms */
  819. err = snd_pcm_hw_constraint_minmax(runtime,
  820. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  821. 5334, UINT_MAX);
  822. if (err < 0)
  823. return err;
  824. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  825. if (err < 0)
  826. return err;
  827. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  828. if (ypcm == NULL)
  829. return -ENOMEM;
  830. ypcm->chip = chip;
  831. ypcm->type = PLAYBACK_VOICE;
  832. ypcm->substream = substream;
  833. runtime->private_data = ypcm;
  834. runtime->private_free = snd_ymfpci_pcm_free_substream;
  835. return 0;
  836. }
  837. /* call with spinlock held */
  838. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  839. {
  840. if (! chip->rear_opened) {
  841. if (! chip->spdif_opened) /* set AC3 */
  842. snd_ymfpci_writel(chip, YDSXGR_MODE,
  843. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  844. /* enable second codec (4CHEN) */
  845. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  846. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  847. }
  848. }
  849. /* call with spinlock held */
  850. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  851. {
  852. if (! chip->rear_opened) {
  853. if (! chip->spdif_opened)
  854. snd_ymfpci_writel(chip, YDSXGR_MODE,
  855. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  856. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  857. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  858. }
  859. }
  860. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  861. {
  862. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  863. struct snd_pcm_runtime *runtime = substream->runtime;
  864. struct snd_ymfpci_pcm *ypcm;
  865. int err;
  866. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  867. return err;
  868. ypcm = runtime->private_data;
  869. ypcm->output_front = 1;
  870. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  871. ypcm->swap_rear = 0;
  872. spin_lock_irq(&chip->reg_lock);
  873. if (ypcm->output_rear) {
  874. ymfpci_open_extension(chip);
  875. chip->rear_opened++;
  876. }
  877. spin_unlock_irq(&chip->reg_lock);
  878. return 0;
  879. }
  880. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  881. {
  882. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  883. struct snd_pcm_runtime *runtime = substream->runtime;
  884. struct snd_ymfpci_pcm *ypcm;
  885. int err;
  886. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  887. return err;
  888. ypcm = runtime->private_data;
  889. ypcm->output_front = 0;
  890. ypcm->output_rear = 1;
  891. ypcm->swap_rear = 1;
  892. spin_lock_irq(&chip->reg_lock);
  893. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  894. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  895. ymfpci_open_extension(chip);
  896. chip->spdif_pcm_bits = chip->spdif_bits;
  897. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  898. chip->spdif_opened++;
  899. spin_unlock_irq(&chip->reg_lock);
  900. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  901. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  902. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  903. return 0;
  904. }
  905. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  906. {
  907. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  908. struct snd_pcm_runtime *runtime = substream->runtime;
  909. struct snd_ymfpci_pcm *ypcm;
  910. int err;
  911. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  912. return err;
  913. ypcm = runtime->private_data;
  914. ypcm->output_front = 0;
  915. ypcm->output_rear = 1;
  916. ypcm->swap_rear = 0;
  917. spin_lock_irq(&chip->reg_lock);
  918. ymfpci_open_extension(chip);
  919. chip->rear_opened++;
  920. spin_unlock_irq(&chip->reg_lock);
  921. return 0;
  922. }
  923. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  924. u32 capture_bank_number)
  925. {
  926. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  927. struct snd_pcm_runtime *runtime = substream->runtime;
  928. struct snd_ymfpci_pcm *ypcm;
  929. int err;
  930. runtime->hw = snd_ymfpci_capture;
  931. /* FIXME? True value is 256/48 = 5.33333 ms */
  932. err = snd_pcm_hw_constraint_minmax(runtime,
  933. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  934. 5334, UINT_MAX);
  935. if (err < 0)
  936. return err;
  937. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  938. if (err < 0)
  939. return err;
  940. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  941. if (ypcm == NULL)
  942. return -ENOMEM;
  943. ypcm->chip = chip;
  944. ypcm->type = capture_bank_number + CAPTURE_REC;
  945. ypcm->substream = substream;
  946. ypcm->capture_bank_number = capture_bank_number;
  947. chip->capture_substream[capture_bank_number] = substream;
  948. runtime->private_data = ypcm;
  949. runtime->private_free = snd_ymfpci_pcm_free_substream;
  950. snd_ymfpci_hw_start(chip);
  951. return 0;
  952. }
  953. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  954. {
  955. return snd_ymfpci_capture_open(substream, 0);
  956. }
  957. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  958. {
  959. return snd_ymfpci_capture_open(substream, 1);
  960. }
  961. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  962. {
  963. return 0;
  964. }
  965. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  966. {
  967. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  968. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  969. spin_lock_irq(&chip->reg_lock);
  970. if (ypcm->output_rear && chip->rear_opened > 0) {
  971. chip->rear_opened--;
  972. ymfpci_close_extension(chip);
  973. }
  974. spin_unlock_irq(&chip->reg_lock);
  975. return snd_ymfpci_playback_close_1(substream);
  976. }
  977. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  978. {
  979. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  980. spin_lock_irq(&chip->reg_lock);
  981. chip->spdif_opened = 0;
  982. ymfpci_close_extension(chip);
  983. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  984. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  985. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  986. spin_unlock_irq(&chip->reg_lock);
  987. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  988. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  989. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  990. return snd_ymfpci_playback_close_1(substream);
  991. }
  992. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  993. {
  994. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  995. spin_lock_irq(&chip->reg_lock);
  996. if (chip->rear_opened > 0) {
  997. chip->rear_opened--;
  998. ymfpci_close_extension(chip);
  999. }
  1000. spin_unlock_irq(&chip->reg_lock);
  1001. return snd_ymfpci_playback_close_1(substream);
  1002. }
  1003. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  1004. {
  1005. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  1006. struct snd_pcm_runtime *runtime = substream->runtime;
  1007. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  1008. if (ypcm != NULL) {
  1009. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  1010. snd_ymfpci_hw_stop(chip);
  1011. }
  1012. return 0;
  1013. }
  1014. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  1015. .open = snd_ymfpci_playback_open,
  1016. .close = snd_ymfpci_playback_close,
  1017. .ioctl = snd_pcm_lib_ioctl,
  1018. .hw_params = snd_ymfpci_playback_hw_params,
  1019. .hw_free = snd_ymfpci_playback_hw_free,
  1020. .prepare = snd_ymfpci_playback_prepare,
  1021. .trigger = snd_ymfpci_playback_trigger,
  1022. .pointer = snd_ymfpci_playback_pointer,
  1023. };
  1024. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  1025. .open = snd_ymfpci_capture_rec_open,
  1026. .close = snd_ymfpci_capture_close,
  1027. .ioctl = snd_pcm_lib_ioctl,
  1028. .hw_params = snd_ymfpci_capture_hw_params,
  1029. .hw_free = snd_ymfpci_capture_hw_free,
  1030. .prepare = snd_ymfpci_capture_prepare,
  1031. .trigger = snd_ymfpci_capture_trigger,
  1032. .pointer = snd_ymfpci_capture_pointer,
  1033. };
  1034. int __devinit snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1035. {
  1036. struct snd_pcm *pcm;
  1037. int err;
  1038. if (rpcm)
  1039. *rpcm = NULL;
  1040. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  1041. return err;
  1042. pcm->private_data = chip;
  1043. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1044. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1045. /* global setup */
  1046. pcm->info_flags = 0;
  1047. strcpy(pcm->name, "YMFPCI");
  1048. chip->pcm = pcm;
  1049. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1050. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1051. if (rpcm)
  1052. *rpcm = pcm;
  1053. return 0;
  1054. }
  1055. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1056. .open = snd_ymfpci_capture_ac97_open,
  1057. .close = snd_ymfpci_capture_close,
  1058. .ioctl = snd_pcm_lib_ioctl,
  1059. .hw_params = snd_ymfpci_capture_hw_params,
  1060. .hw_free = snd_ymfpci_capture_hw_free,
  1061. .prepare = snd_ymfpci_capture_prepare,
  1062. .trigger = snd_ymfpci_capture_trigger,
  1063. .pointer = snd_ymfpci_capture_pointer,
  1064. };
  1065. int __devinit snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1066. {
  1067. struct snd_pcm *pcm;
  1068. int err;
  1069. if (rpcm)
  1070. *rpcm = NULL;
  1071. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1072. return err;
  1073. pcm->private_data = chip;
  1074. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1075. /* global setup */
  1076. pcm->info_flags = 0;
  1077. sprintf(pcm->name, "YMFPCI - %s",
  1078. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1079. chip->pcm2 = pcm;
  1080. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1081. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1082. if (rpcm)
  1083. *rpcm = pcm;
  1084. return 0;
  1085. }
  1086. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1087. .open = snd_ymfpci_playback_spdif_open,
  1088. .close = snd_ymfpci_playback_spdif_close,
  1089. .ioctl = snd_pcm_lib_ioctl,
  1090. .hw_params = snd_ymfpci_playback_hw_params,
  1091. .hw_free = snd_ymfpci_playback_hw_free,
  1092. .prepare = snd_ymfpci_playback_prepare,
  1093. .trigger = snd_ymfpci_playback_trigger,
  1094. .pointer = snd_ymfpci_playback_pointer,
  1095. };
  1096. int __devinit snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1097. {
  1098. struct snd_pcm *pcm;
  1099. int err;
  1100. if (rpcm)
  1101. *rpcm = NULL;
  1102. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1103. return err;
  1104. pcm->private_data = chip;
  1105. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1106. /* global setup */
  1107. pcm->info_flags = 0;
  1108. strcpy(pcm->name, "YMFPCI - IEC958");
  1109. chip->pcm_spdif = pcm;
  1110. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1111. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1112. if (rpcm)
  1113. *rpcm = pcm;
  1114. return 0;
  1115. }
  1116. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1117. .open = snd_ymfpci_playback_4ch_open,
  1118. .close = snd_ymfpci_playback_4ch_close,
  1119. .ioctl = snd_pcm_lib_ioctl,
  1120. .hw_params = snd_ymfpci_playback_hw_params,
  1121. .hw_free = snd_ymfpci_playback_hw_free,
  1122. .prepare = snd_ymfpci_playback_prepare,
  1123. .trigger = snd_ymfpci_playback_trigger,
  1124. .pointer = snd_ymfpci_playback_pointer,
  1125. };
  1126. int __devinit snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1127. {
  1128. struct snd_pcm *pcm;
  1129. int err;
  1130. if (rpcm)
  1131. *rpcm = NULL;
  1132. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1133. return err;
  1134. pcm->private_data = chip;
  1135. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1136. /* global setup */
  1137. pcm->info_flags = 0;
  1138. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1139. chip->pcm_4ch = pcm;
  1140. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1141. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1142. if (rpcm)
  1143. *rpcm = pcm;
  1144. return 0;
  1145. }
  1146. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1147. {
  1148. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1149. uinfo->count = 1;
  1150. return 0;
  1151. }
  1152. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1153. struct snd_ctl_elem_value *ucontrol)
  1154. {
  1155. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1156. spin_lock_irq(&chip->reg_lock);
  1157. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1158. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1159. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1160. spin_unlock_irq(&chip->reg_lock);
  1161. return 0;
  1162. }
  1163. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1164. struct snd_ctl_elem_value *ucontrol)
  1165. {
  1166. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1167. unsigned int val;
  1168. int change;
  1169. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1170. (ucontrol->value.iec958.status[1] << 8);
  1171. spin_lock_irq(&chip->reg_lock);
  1172. change = chip->spdif_bits != val;
  1173. chip->spdif_bits = val;
  1174. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1175. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1176. spin_unlock_irq(&chip->reg_lock);
  1177. return change;
  1178. }
  1179. static struct snd_kcontrol_new snd_ymfpci_spdif_default __devinitdata =
  1180. {
  1181. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1182. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1183. .info = snd_ymfpci_spdif_default_info,
  1184. .get = snd_ymfpci_spdif_default_get,
  1185. .put = snd_ymfpci_spdif_default_put
  1186. };
  1187. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1188. {
  1189. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1190. uinfo->count = 1;
  1191. return 0;
  1192. }
  1193. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1194. struct snd_ctl_elem_value *ucontrol)
  1195. {
  1196. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1197. spin_lock_irq(&chip->reg_lock);
  1198. ucontrol->value.iec958.status[0] = 0x3e;
  1199. ucontrol->value.iec958.status[1] = 0xff;
  1200. spin_unlock_irq(&chip->reg_lock);
  1201. return 0;
  1202. }
  1203. static struct snd_kcontrol_new snd_ymfpci_spdif_mask __devinitdata =
  1204. {
  1205. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1206. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1207. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1208. .info = snd_ymfpci_spdif_mask_info,
  1209. .get = snd_ymfpci_spdif_mask_get,
  1210. };
  1211. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1212. {
  1213. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1214. uinfo->count = 1;
  1215. return 0;
  1216. }
  1217. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1218. struct snd_ctl_elem_value *ucontrol)
  1219. {
  1220. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1221. spin_lock_irq(&chip->reg_lock);
  1222. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1223. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1224. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1225. spin_unlock_irq(&chip->reg_lock);
  1226. return 0;
  1227. }
  1228. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1229. struct snd_ctl_elem_value *ucontrol)
  1230. {
  1231. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1232. unsigned int val;
  1233. int change;
  1234. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1235. (ucontrol->value.iec958.status[1] << 8);
  1236. spin_lock_irq(&chip->reg_lock);
  1237. change = chip->spdif_pcm_bits != val;
  1238. chip->spdif_pcm_bits = val;
  1239. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1240. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1241. spin_unlock_irq(&chip->reg_lock);
  1242. return change;
  1243. }
  1244. static struct snd_kcontrol_new snd_ymfpci_spdif_stream __devinitdata =
  1245. {
  1246. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1247. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1248. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1249. .info = snd_ymfpci_spdif_stream_info,
  1250. .get = snd_ymfpci_spdif_stream_get,
  1251. .put = snd_ymfpci_spdif_stream_put
  1252. };
  1253. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1254. {
  1255. static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1256. return snd_ctl_enum_info(info, 1, 3, texts);
  1257. }
  1258. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1259. {
  1260. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1261. u16 reg;
  1262. spin_lock_irq(&chip->reg_lock);
  1263. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1264. spin_unlock_irq(&chip->reg_lock);
  1265. if (!(reg & 0x100))
  1266. value->value.enumerated.item[0] = 0;
  1267. else
  1268. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1269. return 0;
  1270. }
  1271. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1272. {
  1273. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1274. u16 reg, old_reg;
  1275. spin_lock_irq(&chip->reg_lock);
  1276. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1277. if (value->value.enumerated.item[0] == 0)
  1278. reg = old_reg & ~0x100;
  1279. else
  1280. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1281. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1282. spin_unlock_irq(&chip->reg_lock);
  1283. return reg != old_reg;
  1284. }
  1285. static struct snd_kcontrol_new snd_ymfpci_drec_source __devinitdata = {
  1286. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1287. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1288. .name = "Direct Recording Source",
  1289. .info = snd_ymfpci_drec_source_info,
  1290. .get = snd_ymfpci_drec_source_get,
  1291. .put = snd_ymfpci_drec_source_put
  1292. };
  1293. /*
  1294. * Mixer controls
  1295. */
  1296. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1297. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1298. .info = snd_ymfpci_info_single, \
  1299. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1300. .private_value = ((reg) | ((shift) << 16)) }
  1301. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1302. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1303. struct snd_ctl_elem_value *ucontrol)
  1304. {
  1305. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1306. int reg = kcontrol->private_value & 0xffff;
  1307. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1308. unsigned int mask = 1;
  1309. switch (reg) {
  1310. case YDSXGR_SPDIFOUTCTRL: break;
  1311. case YDSXGR_SPDIFINCTRL: break;
  1312. default: return -EINVAL;
  1313. }
  1314. ucontrol->value.integer.value[0] =
  1315. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1316. return 0;
  1317. }
  1318. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1319. struct snd_ctl_elem_value *ucontrol)
  1320. {
  1321. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1322. int reg = kcontrol->private_value & 0xffff;
  1323. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1324. unsigned int mask = 1;
  1325. int change;
  1326. unsigned int val, oval;
  1327. switch (reg) {
  1328. case YDSXGR_SPDIFOUTCTRL: break;
  1329. case YDSXGR_SPDIFINCTRL: break;
  1330. default: return -EINVAL;
  1331. }
  1332. val = (ucontrol->value.integer.value[0] & mask);
  1333. val <<= shift;
  1334. spin_lock_irq(&chip->reg_lock);
  1335. oval = snd_ymfpci_readl(chip, reg);
  1336. val = (oval & ~(mask << shift)) | val;
  1337. change = val != oval;
  1338. snd_ymfpci_writel(chip, reg, val);
  1339. spin_unlock_irq(&chip->reg_lock);
  1340. return change;
  1341. }
  1342. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1343. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1344. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1345. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1346. .info = snd_ymfpci_info_double, \
  1347. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1348. .private_value = reg, \
  1349. .tlv = { .p = db_scale_native } }
  1350. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1351. {
  1352. unsigned int reg = kcontrol->private_value;
  1353. if (reg < 0x80 || reg >= 0xc0)
  1354. return -EINVAL;
  1355. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1356. uinfo->count = 2;
  1357. uinfo->value.integer.min = 0;
  1358. uinfo->value.integer.max = 16383;
  1359. return 0;
  1360. }
  1361. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1362. {
  1363. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1364. unsigned int reg = kcontrol->private_value;
  1365. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1366. unsigned int val;
  1367. if (reg < 0x80 || reg >= 0xc0)
  1368. return -EINVAL;
  1369. spin_lock_irq(&chip->reg_lock);
  1370. val = snd_ymfpci_readl(chip, reg);
  1371. spin_unlock_irq(&chip->reg_lock);
  1372. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1373. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1374. return 0;
  1375. }
  1376. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1377. {
  1378. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1379. unsigned int reg = kcontrol->private_value;
  1380. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1381. int change;
  1382. unsigned int val1, val2, oval;
  1383. if (reg < 0x80 || reg >= 0xc0)
  1384. return -EINVAL;
  1385. val1 = ucontrol->value.integer.value[0] & mask;
  1386. val2 = ucontrol->value.integer.value[1] & mask;
  1387. val1 <<= shift_left;
  1388. val2 <<= shift_right;
  1389. spin_lock_irq(&chip->reg_lock);
  1390. oval = snd_ymfpci_readl(chip, reg);
  1391. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1392. change = val1 != oval;
  1393. snd_ymfpci_writel(chip, reg, val1);
  1394. spin_unlock_irq(&chip->reg_lock);
  1395. return change;
  1396. }
  1397. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1398. struct snd_ctl_elem_value *ucontrol)
  1399. {
  1400. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1401. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1402. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1403. int change;
  1404. unsigned int value, oval;
  1405. value = ucontrol->value.integer.value[0] & 0x3fff;
  1406. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1407. spin_lock_irq(&chip->reg_lock);
  1408. oval = snd_ymfpci_readl(chip, reg);
  1409. change = value != oval;
  1410. snd_ymfpci_writel(chip, reg, value);
  1411. snd_ymfpci_writel(chip, reg2, value);
  1412. spin_unlock_irq(&chip->reg_lock);
  1413. return change;
  1414. }
  1415. /*
  1416. * 4ch duplication
  1417. */
  1418. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1419. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1420. {
  1421. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1422. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1423. return 0;
  1424. }
  1425. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1426. {
  1427. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1428. int change;
  1429. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1430. if (change)
  1431. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1432. return change;
  1433. }
  1434. static struct snd_kcontrol_new snd_ymfpci_controls[] __devinitdata = {
  1435. {
  1436. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1437. .name = "Wave Playback Volume",
  1438. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1439. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1440. .info = snd_ymfpci_info_double,
  1441. .get = snd_ymfpci_get_double,
  1442. .put = snd_ymfpci_put_nativedacvol,
  1443. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1444. .tlv = { .p = db_scale_native },
  1445. },
  1446. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1447. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1448. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1449. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1450. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1451. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1452. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1453. YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
  1454. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1455. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1456. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1457. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1458. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1459. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1460. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1461. {
  1462. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1463. .name = "4ch Duplication",
  1464. .info = snd_ymfpci_info_dup4ch,
  1465. .get = snd_ymfpci_get_dup4ch,
  1466. .put = snd_ymfpci_put_dup4ch,
  1467. },
  1468. };
  1469. /*
  1470. * GPIO
  1471. */
  1472. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1473. {
  1474. u16 reg, mode;
  1475. unsigned long flags;
  1476. spin_lock_irqsave(&chip->reg_lock, flags);
  1477. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1478. reg &= ~(1 << (pin + 8));
  1479. reg |= (1 << pin);
  1480. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1481. /* set the level mode for input line */
  1482. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1483. mode &= ~(3 << (pin * 2));
  1484. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1485. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1486. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1487. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1488. return (mode >> pin) & 1;
  1489. }
  1490. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1491. {
  1492. u16 reg;
  1493. unsigned long flags;
  1494. spin_lock_irqsave(&chip->reg_lock, flags);
  1495. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1496. reg &= ~(1 << pin);
  1497. reg &= ~(1 << (pin + 8));
  1498. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1499. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1500. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1501. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1502. return 0;
  1503. }
  1504. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1505. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1506. {
  1507. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1508. int pin = (int)kcontrol->private_value;
  1509. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1510. return 0;
  1511. }
  1512. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1513. {
  1514. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1515. int pin = (int)kcontrol->private_value;
  1516. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1517. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1518. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1519. return 1;
  1520. }
  1521. return 0;
  1522. }
  1523. static struct snd_kcontrol_new snd_ymfpci_rear_shared __devinitdata = {
  1524. .name = "Shared Rear/Line-In Switch",
  1525. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1526. .info = snd_ymfpci_gpio_sw_info,
  1527. .get = snd_ymfpci_gpio_sw_get,
  1528. .put = snd_ymfpci_gpio_sw_put,
  1529. .private_value = 2,
  1530. };
  1531. /*
  1532. * PCM voice volume
  1533. */
  1534. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1535. struct snd_ctl_elem_info *uinfo)
  1536. {
  1537. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1538. uinfo->count = 2;
  1539. uinfo->value.integer.min = 0;
  1540. uinfo->value.integer.max = 0x8000;
  1541. return 0;
  1542. }
  1543. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1544. struct snd_ctl_elem_value *ucontrol)
  1545. {
  1546. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1547. unsigned int subs = kcontrol->id.subdevice;
  1548. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1549. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1550. return 0;
  1551. }
  1552. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1553. struct snd_ctl_elem_value *ucontrol)
  1554. {
  1555. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1556. unsigned int subs = kcontrol->id.subdevice;
  1557. struct snd_pcm_substream *substream;
  1558. unsigned long flags;
  1559. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1560. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1561. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1562. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1563. if (chip->pcm_mixer[subs].left > 0x8000)
  1564. chip->pcm_mixer[subs].left = 0x8000;
  1565. if (chip->pcm_mixer[subs].right > 0x8000)
  1566. chip->pcm_mixer[subs].right = 0x8000;
  1567. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1568. spin_lock_irqsave(&chip->voice_lock, flags);
  1569. if (substream->runtime && substream->runtime->private_data) {
  1570. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1571. if (!ypcm->use_441_slot)
  1572. ypcm->update_pcm_vol = 2;
  1573. }
  1574. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1575. return 1;
  1576. }
  1577. return 0;
  1578. }
  1579. static struct snd_kcontrol_new snd_ymfpci_pcm_volume __devinitdata = {
  1580. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1581. .name = "PCM Playback Volume",
  1582. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1583. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1584. .info = snd_ymfpci_pcm_vol_info,
  1585. .get = snd_ymfpci_pcm_vol_get,
  1586. .put = snd_ymfpci_pcm_vol_put,
  1587. };
  1588. /*
  1589. * Mixer routines
  1590. */
  1591. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1592. {
  1593. struct snd_ymfpci *chip = bus->private_data;
  1594. chip->ac97_bus = NULL;
  1595. }
  1596. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1597. {
  1598. struct snd_ymfpci *chip = ac97->private_data;
  1599. chip->ac97 = NULL;
  1600. }
  1601. int __devinit snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1602. {
  1603. struct snd_ac97_template ac97;
  1604. struct snd_kcontrol *kctl;
  1605. struct snd_pcm_substream *substream;
  1606. unsigned int idx;
  1607. int err;
  1608. static struct snd_ac97_bus_ops ops = {
  1609. .write = snd_ymfpci_codec_write,
  1610. .read = snd_ymfpci_codec_read,
  1611. };
  1612. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1613. return err;
  1614. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1615. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1616. memset(&ac97, 0, sizeof(ac97));
  1617. ac97.private_data = chip;
  1618. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1619. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1620. return err;
  1621. /* to be sure */
  1622. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1623. AC97_EA_VRA|AC97_EA_VRM, 0);
  1624. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1625. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1626. return err;
  1627. }
  1628. /* add S/PDIF control */
  1629. if (snd_BUG_ON(!chip->pcm_spdif))
  1630. return -ENXIO;
  1631. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1632. return err;
  1633. kctl->id.device = chip->pcm_spdif->device;
  1634. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1635. return err;
  1636. kctl->id.device = chip->pcm_spdif->device;
  1637. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1638. return err;
  1639. kctl->id.device = chip->pcm_spdif->device;
  1640. chip->spdif_pcm_ctl = kctl;
  1641. /* direct recording source */
  1642. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1643. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1644. return err;
  1645. /*
  1646. * shared rear/line-in
  1647. */
  1648. if (rear_switch) {
  1649. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1650. return err;
  1651. }
  1652. /* per-voice volume */
  1653. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1654. for (idx = 0; idx < 32; ++idx) {
  1655. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1656. if (!kctl)
  1657. return -ENOMEM;
  1658. kctl->id.device = chip->pcm->device;
  1659. kctl->id.subdevice = idx;
  1660. kctl->private_value = (unsigned long)substream;
  1661. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1662. return err;
  1663. chip->pcm_mixer[idx].left = 0x8000;
  1664. chip->pcm_mixer[idx].right = 0x8000;
  1665. chip->pcm_mixer[idx].ctl = kctl;
  1666. substream = substream->next;
  1667. }
  1668. return 0;
  1669. }
  1670. /*
  1671. * timer
  1672. */
  1673. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1674. {
  1675. struct snd_ymfpci *chip;
  1676. unsigned long flags;
  1677. unsigned int count;
  1678. chip = snd_timer_chip(timer);
  1679. spin_lock_irqsave(&chip->reg_lock, flags);
  1680. if (timer->sticks > 1) {
  1681. chip->timer_ticks = timer->sticks;
  1682. count = timer->sticks - 1;
  1683. } else {
  1684. /*
  1685. * Divisor 1 is not allowed; fake it by using divisor 2 and
  1686. * counting two ticks for each interrupt.
  1687. */
  1688. chip->timer_ticks = 2;
  1689. count = 2 - 1;
  1690. }
  1691. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1692. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1693. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1694. return 0;
  1695. }
  1696. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1697. {
  1698. struct snd_ymfpci *chip;
  1699. unsigned long flags;
  1700. chip = snd_timer_chip(timer);
  1701. spin_lock_irqsave(&chip->reg_lock, flags);
  1702. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1703. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1704. return 0;
  1705. }
  1706. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1707. unsigned long *num, unsigned long *den)
  1708. {
  1709. *num = 1;
  1710. *den = 96000;
  1711. return 0;
  1712. }
  1713. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1714. .flags = SNDRV_TIMER_HW_AUTO,
  1715. .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
  1716. .ticks = 0x10000,
  1717. .start = snd_ymfpci_timer_start,
  1718. .stop = snd_ymfpci_timer_stop,
  1719. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1720. };
  1721. int __devinit snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1722. {
  1723. struct snd_timer *timer = NULL;
  1724. struct snd_timer_id tid;
  1725. int err;
  1726. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1727. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1728. tid.card = chip->card->number;
  1729. tid.device = device;
  1730. tid.subdevice = 0;
  1731. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1732. strcpy(timer->name, "YMFPCI timer");
  1733. timer->private_data = chip;
  1734. timer->hw = snd_ymfpci_timer_hw;
  1735. }
  1736. chip->timer = timer;
  1737. return err;
  1738. }
  1739. /*
  1740. * proc interface
  1741. */
  1742. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1743. struct snd_info_buffer *buffer)
  1744. {
  1745. struct snd_ymfpci *chip = entry->private_data;
  1746. int i;
  1747. snd_iprintf(buffer, "YMFPCI\n\n");
  1748. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1749. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1750. }
  1751. static int __devinit snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1752. {
  1753. struct snd_info_entry *entry;
  1754. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1755. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1756. return 0;
  1757. }
  1758. /*
  1759. * initialization routines
  1760. */
  1761. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1762. {
  1763. u8 cmd;
  1764. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1765. #if 0 // force to reset
  1766. if (cmd & 0x03) {
  1767. #endif
  1768. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1769. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1770. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1771. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1772. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1773. #if 0
  1774. }
  1775. #endif
  1776. }
  1777. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1778. {
  1779. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1780. }
  1781. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1782. {
  1783. u32 val;
  1784. int timeout = 1000;
  1785. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1786. if (val)
  1787. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1788. while (timeout-- > 0) {
  1789. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1790. if ((val & 0x00000002) == 0)
  1791. break;
  1792. }
  1793. }
  1794. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1795. {
  1796. int err, is_1e;
  1797. const char *name;
  1798. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1799. &chip->pci->dev);
  1800. if (err >= 0) {
  1801. if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
  1802. snd_printk(KERN_ERR "DSP microcode has wrong size\n");
  1803. err = -EINVAL;
  1804. }
  1805. }
  1806. if (err < 0)
  1807. return err;
  1808. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1809. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1810. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1811. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1812. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1813. err = request_firmware(&chip->controller_microcode, name,
  1814. &chip->pci->dev);
  1815. if (err >= 0) {
  1816. if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
  1817. snd_printk(KERN_ERR "controller microcode"
  1818. " has wrong size\n");
  1819. err = -EINVAL;
  1820. }
  1821. }
  1822. if (err < 0)
  1823. return err;
  1824. return 0;
  1825. }
  1826. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1827. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1828. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1829. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1830. {
  1831. int i;
  1832. u16 ctrl;
  1833. const __le32 *inst;
  1834. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1835. snd_ymfpci_disable_dsp(chip);
  1836. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1837. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1838. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1839. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1840. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1841. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1842. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1843. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1844. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1845. /* setup DSP instruction code */
  1846. inst = (const __le32 *)chip->dsp_microcode->data;
  1847. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1848. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
  1849. le32_to_cpu(inst[i]));
  1850. /* setup control instruction code */
  1851. inst = (const __le32 *)chip->controller_microcode->data;
  1852. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1853. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
  1854. le32_to_cpu(inst[i]));
  1855. snd_ymfpci_enable_dsp(chip);
  1856. }
  1857. static int __devinit snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1858. {
  1859. long size, playback_ctrl_size;
  1860. int voice, bank, reg;
  1861. u8 *ptr;
  1862. dma_addr_t ptr_addr;
  1863. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1864. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1865. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1866. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1867. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1868. size = ALIGN(playback_ctrl_size, 0x100) +
  1869. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1870. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1871. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1872. chip->work_size;
  1873. /* work_ptr must be aligned to 256 bytes, but it's already
  1874. covered with the kernel page allocation mechanism */
  1875. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1876. size, &chip->work_ptr) < 0)
  1877. return -ENOMEM;
  1878. ptr = chip->work_ptr.area;
  1879. ptr_addr = chip->work_ptr.addr;
  1880. memset(ptr, 0, size); /* for sure */
  1881. chip->bank_base_playback = ptr;
  1882. chip->bank_base_playback_addr = ptr_addr;
  1883. chip->ctrl_playback = (u32 *)ptr;
  1884. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1885. ptr += ALIGN(playback_ctrl_size, 0x100);
  1886. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1887. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1888. chip->voices[voice].number = voice;
  1889. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1890. chip->voices[voice].bank_addr = ptr_addr;
  1891. for (bank = 0; bank < 2; bank++) {
  1892. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1893. ptr += chip->bank_size_playback;
  1894. ptr_addr += chip->bank_size_playback;
  1895. }
  1896. }
  1897. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1898. ptr_addr = ALIGN(ptr_addr, 0x100);
  1899. chip->bank_base_capture = ptr;
  1900. chip->bank_base_capture_addr = ptr_addr;
  1901. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1902. for (bank = 0; bank < 2; bank++) {
  1903. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1904. ptr += chip->bank_size_capture;
  1905. ptr_addr += chip->bank_size_capture;
  1906. }
  1907. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1908. ptr_addr = ALIGN(ptr_addr, 0x100);
  1909. chip->bank_base_effect = ptr;
  1910. chip->bank_base_effect_addr = ptr_addr;
  1911. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1912. for (bank = 0; bank < 2; bank++) {
  1913. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1914. ptr += chip->bank_size_effect;
  1915. ptr_addr += chip->bank_size_effect;
  1916. }
  1917. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1918. ptr_addr = ALIGN(ptr_addr, 0x100);
  1919. chip->work_base = ptr;
  1920. chip->work_base_addr = ptr_addr;
  1921. snd_BUG_ON(ptr + chip->work_size !=
  1922. chip->work_ptr.area + chip->work_ptr.bytes);
  1923. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1924. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1925. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1926. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1927. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1928. /* S/PDIF output initialization */
  1929. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1930. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1931. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1932. /* S/PDIF input initialization */
  1933. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1934. /* digital mixer setup */
  1935. for (reg = 0x80; reg < 0xc0; reg += 4)
  1936. snd_ymfpci_writel(chip, reg, 0);
  1937. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1938. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1939. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1940. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1941. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1942. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1943. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1944. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1945. return 0;
  1946. }
  1947. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1948. {
  1949. u16 ctrl;
  1950. if (snd_BUG_ON(!chip))
  1951. return -EINVAL;
  1952. if (chip->res_reg_area) { /* don't touch busy hardware */
  1953. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1954. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1955. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1956. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1957. snd_ymfpci_disable_dsp(chip);
  1958. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1959. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1960. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1961. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1962. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1963. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1964. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1965. }
  1966. snd_ymfpci_ac3_done(chip);
  1967. /* Set PCI device to D3 state */
  1968. #if 0
  1969. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1970. * the chip again unless reboot. ACPI bug?
  1971. */
  1972. pci_set_power_state(chip->pci, 3);
  1973. #endif
  1974. #ifdef CONFIG_PM
  1975. vfree(chip->saved_regs);
  1976. #endif
  1977. if (chip->irq >= 0)
  1978. free_irq(chip->irq, chip);
  1979. release_and_free_resource(chip->mpu_res);
  1980. release_and_free_resource(chip->fm_res);
  1981. snd_ymfpci_free_gameport(chip);
  1982. if (chip->reg_area_virt)
  1983. iounmap(chip->reg_area_virt);
  1984. if (chip->work_ptr.area)
  1985. snd_dma_free_pages(&chip->work_ptr);
  1986. release_and_free_resource(chip->res_reg_area);
  1987. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1988. pci_disable_device(chip->pci);
  1989. release_firmware(chip->dsp_microcode);
  1990. release_firmware(chip->controller_microcode);
  1991. kfree(chip);
  1992. return 0;
  1993. }
  1994. static int snd_ymfpci_dev_free(struct snd_device *device)
  1995. {
  1996. struct snd_ymfpci *chip = device->device_data;
  1997. return snd_ymfpci_free(chip);
  1998. }
  1999. #ifdef CONFIG_PM
  2000. static int saved_regs_index[] = {
  2001. /* spdif */
  2002. YDSXGR_SPDIFOUTCTRL,
  2003. YDSXGR_SPDIFOUTSTATUS,
  2004. YDSXGR_SPDIFINCTRL,
  2005. /* volumes */
  2006. YDSXGR_PRIADCLOOPVOL,
  2007. YDSXGR_NATIVEDACINVOL,
  2008. YDSXGR_NATIVEDACOUTVOL,
  2009. YDSXGR_BUF441OUTVOL,
  2010. YDSXGR_NATIVEADCINVOL,
  2011. YDSXGR_SPDIFLOOPVOL,
  2012. YDSXGR_SPDIFOUTVOL,
  2013. YDSXGR_ZVOUTVOL,
  2014. YDSXGR_LEGACYOUTVOL,
  2015. /* address bases */
  2016. YDSXGR_PLAYCTRLBASE,
  2017. YDSXGR_RECCTRLBASE,
  2018. YDSXGR_EFFCTRLBASE,
  2019. YDSXGR_WORKBASE,
  2020. /* capture set up */
  2021. YDSXGR_MAPOFREC,
  2022. YDSXGR_RECFORMAT,
  2023. YDSXGR_RECSLOTSR,
  2024. YDSXGR_ADCFORMAT,
  2025. YDSXGR_ADCSLOTSR,
  2026. };
  2027. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  2028. int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state)
  2029. {
  2030. struct snd_card *card = pci_get_drvdata(pci);
  2031. struct snd_ymfpci *chip = card->private_data;
  2032. unsigned int i;
  2033. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2034. snd_pcm_suspend_all(chip->pcm);
  2035. snd_pcm_suspend_all(chip->pcm2);
  2036. snd_pcm_suspend_all(chip->pcm_spdif);
  2037. snd_pcm_suspend_all(chip->pcm_4ch);
  2038. snd_ac97_suspend(chip->ac97);
  2039. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2040. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2041. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2042. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2043. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2044. snd_ymfpci_disable_dsp(chip);
  2045. pci_disable_device(pci);
  2046. pci_save_state(pci);
  2047. pci_set_power_state(pci, pci_choose_state(pci, state));
  2048. return 0;
  2049. }
  2050. int snd_ymfpci_resume(struct pci_dev *pci)
  2051. {
  2052. struct snd_card *card = pci_get_drvdata(pci);
  2053. struct snd_ymfpci *chip = card->private_data;
  2054. unsigned int i;
  2055. pci_set_power_state(pci, PCI_D0);
  2056. pci_restore_state(pci);
  2057. if (pci_enable_device(pci) < 0) {
  2058. printk(KERN_ERR "ymfpci: pci_enable_device failed, "
  2059. "disabling device\n");
  2060. snd_card_disconnect(card);
  2061. return -EIO;
  2062. }
  2063. pci_set_master(pci);
  2064. snd_ymfpci_aclink_reset(pci);
  2065. snd_ymfpci_codec_ready(chip, 0);
  2066. snd_ymfpci_download_image(chip);
  2067. udelay(100);
  2068. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2069. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2070. snd_ac97_resume(chip->ac97);
  2071. /* start hw again */
  2072. if (chip->start_count > 0) {
  2073. spin_lock_irq(&chip->reg_lock);
  2074. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2075. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2076. spin_unlock_irq(&chip->reg_lock);
  2077. }
  2078. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2079. return 0;
  2080. }
  2081. #endif /* CONFIG_PM */
  2082. int __devinit snd_ymfpci_create(struct snd_card *card,
  2083. struct pci_dev * pci,
  2084. unsigned short old_legacy_ctrl,
  2085. struct snd_ymfpci ** rchip)
  2086. {
  2087. struct snd_ymfpci *chip;
  2088. int err;
  2089. static struct snd_device_ops ops = {
  2090. .dev_free = snd_ymfpci_dev_free,
  2091. };
  2092. *rchip = NULL;
  2093. /* enable PCI device */
  2094. if ((err = pci_enable_device(pci)) < 0)
  2095. return err;
  2096. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2097. if (chip == NULL) {
  2098. pci_disable_device(pci);
  2099. return -ENOMEM;
  2100. }
  2101. chip->old_legacy_ctrl = old_legacy_ctrl;
  2102. spin_lock_init(&chip->reg_lock);
  2103. spin_lock_init(&chip->voice_lock);
  2104. init_waitqueue_head(&chip->interrupt_sleep);
  2105. atomic_set(&chip->interrupt_sleep_count, 0);
  2106. chip->card = card;
  2107. chip->pci = pci;
  2108. chip->irq = -1;
  2109. chip->device_id = pci->device;
  2110. chip->rev = pci->revision;
  2111. chip->reg_area_phys = pci_resource_start(pci, 0);
  2112. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2113. pci_set_master(pci);
  2114. chip->src441_used = -1;
  2115. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2116. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2117. snd_ymfpci_free(chip);
  2118. return -EBUSY;
  2119. }
  2120. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2121. KBUILD_MODNAME, chip)) {
  2122. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2123. snd_ymfpci_free(chip);
  2124. return -EBUSY;
  2125. }
  2126. chip->irq = pci->irq;
  2127. snd_ymfpci_aclink_reset(pci);
  2128. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2129. snd_ymfpci_free(chip);
  2130. return -EIO;
  2131. }
  2132. err = snd_ymfpci_request_firmware(chip);
  2133. if (err < 0) {
  2134. snd_printk(KERN_ERR "firmware request failed: %d\n", err);
  2135. snd_ymfpci_free(chip);
  2136. return err;
  2137. }
  2138. snd_ymfpci_download_image(chip);
  2139. udelay(100); /* seems we need a delay after downloading image.. */
  2140. if (snd_ymfpci_memalloc(chip) < 0) {
  2141. snd_ymfpci_free(chip);
  2142. return -EIO;
  2143. }
  2144. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2145. snd_ymfpci_free(chip);
  2146. return err;
  2147. }
  2148. #ifdef CONFIG_PM
  2149. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2150. if (chip->saved_regs == NULL) {
  2151. snd_ymfpci_free(chip);
  2152. return -ENOMEM;
  2153. }
  2154. #endif
  2155. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2156. snd_ymfpci_free(chip);
  2157. return err;
  2158. }
  2159. snd_ymfpci_proc_init(card, chip);
  2160. snd_card_set_dev(card, &pci->dev);
  2161. *rchip = chip;
  2162. return 0;
  2163. }