ql4_mbx.c 40 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine issue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. uint32_t dev_state;
  33. /* Make sure that pointers are valid */
  34. if (!mbx_cmd || !mbx_sts) {
  35. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  36. "pointer\n", ha->host_no, __func__));
  37. return status;
  38. }
  39. if (is_qla8022(ha)) {
  40. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  41. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  42. "prematurely completing mbx cmd as firmware "
  43. "recovery detected\n", ha->host_no, __func__));
  44. return status;
  45. }
  46. /* Do not send any mbx cmd if h/w is in failed state*/
  47. qla4_8xxx_idc_lock(ha);
  48. dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
  49. qla4_8xxx_idc_unlock(ha);
  50. if (dev_state == QLA82XX_DEV_FAILED) {
  51. ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: H/W is in "
  52. "failed state, do not send any mailbox commands\n",
  53. ha->host_no, __func__);
  54. return status;
  55. }
  56. }
  57. if ((is_aer_supported(ha)) &&
  58. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  59. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  60. "timeout MBX Exiting.\n", ha->host_no, __func__));
  61. return status;
  62. }
  63. /* Mailbox code active */
  64. wait_count = MBOX_TOV * 100;
  65. while (wait_count--) {
  66. mutex_lock(&ha->mbox_sem);
  67. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  68. set_bit(AF_MBOX_COMMAND, &ha->flags);
  69. mutex_unlock(&ha->mbox_sem);
  70. break;
  71. }
  72. mutex_unlock(&ha->mbox_sem);
  73. if (!wait_count) {
  74. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  75. ha->host_no, __func__));
  76. return status;
  77. }
  78. msleep(10);
  79. }
  80. spin_lock_irqsave(&ha->hardware_lock, flags);
  81. ha->mbox_status_count = outCount;
  82. for (i = 0; i < outCount; i++)
  83. ha->mbox_status[i] = 0;
  84. if (is_qla8022(ha)) {
  85. /* Load all mailbox registers, except mailbox 0. */
  86. DEBUG5(
  87. printk("scsi%ld: %s: Cmd ", ha->host_no, __func__);
  88. for (i = 0; i < inCount; i++)
  89. printk("mb%d=%04x ", i, mbx_cmd[i]);
  90. printk("\n"));
  91. for (i = 1; i < inCount; i++)
  92. writel(mbx_cmd[i], &ha->qla4_8xxx_reg->mailbox_in[i]);
  93. writel(mbx_cmd[0], &ha->qla4_8xxx_reg->mailbox_in[0]);
  94. readl(&ha->qla4_8xxx_reg->mailbox_in[0]);
  95. writel(HINT_MBX_INT_PENDING, &ha->qla4_8xxx_reg->hint);
  96. } else {
  97. /* Load all mailbox registers, except mailbox 0. */
  98. for (i = 1; i < inCount; i++)
  99. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  100. /* Wakeup firmware */
  101. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  102. readl(&ha->reg->mailbox[0]);
  103. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  104. readl(&ha->reg->ctrl_status);
  105. }
  106. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  107. /* Wait for completion */
  108. /*
  109. * If we don't want status, don't wait for the mailbox command to
  110. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  111. * you must poll the inbound Interrupt Mask for completion.
  112. */
  113. if (outCount == 0) {
  114. status = QLA_SUCCESS;
  115. goto mbox_exit;
  116. }
  117. /*
  118. * Wait for completion: Poll or completion queue
  119. */
  120. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  121. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  122. test_bit(AF_ONLINE, &ha->flags) &&
  123. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  124. /* Do not poll for completion. Use completion queue */
  125. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  127. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  128. } else {
  129. /* Poll for command to complete */
  130. wait_count = jiffies + MBOX_TOV * HZ;
  131. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  132. if (time_after_eq(jiffies, wait_count))
  133. break;
  134. /*
  135. * Service the interrupt.
  136. * The ISR will save the mailbox status registers
  137. * to a temporary storage location in the adapter
  138. * structure.
  139. */
  140. spin_lock_irqsave(&ha->hardware_lock, flags);
  141. if (is_qla8022(ha)) {
  142. intr_status =
  143. readl(&ha->qla4_8xxx_reg->host_int);
  144. if (intr_status & ISRX_82XX_RISC_INT) {
  145. ha->mbox_status_count = outCount;
  146. intr_status =
  147. readl(&ha->qla4_8xxx_reg->host_status);
  148. ha->isp_ops->interrupt_service_routine(
  149. ha, intr_status);
  150. if (test_bit(AF_INTERRUPTS_ON,
  151. &ha->flags) &&
  152. test_bit(AF_INTx_ENABLED,
  153. &ha->flags))
  154. qla4_8xxx_wr_32(ha,
  155. ha->nx_legacy_intr.tgt_mask_reg,
  156. 0xfbff);
  157. }
  158. } else {
  159. intr_status = readl(&ha->reg->ctrl_status);
  160. if (intr_status & INTR_PENDING) {
  161. /*
  162. * Service the interrupt.
  163. * The ISR will save the mailbox status
  164. * registers to a temporary storage
  165. * location in the adapter structure.
  166. */
  167. ha->mbox_status_count = outCount;
  168. ha->isp_ops->interrupt_service_routine(
  169. ha, intr_status);
  170. }
  171. }
  172. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  173. msleep(10);
  174. }
  175. }
  176. /* Check for mailbox timeout. */
  177. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  178. if (is_qla8022(ha) &&
  179. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  180. DEBUG2(ql4_printk(KERN_INFO, ha,
  181. "scsi%ld: %s: prematurely completing mbx cmd as "
  182. "firmware recovery detected\n",
  183. ha->host_no, __func__));
  184. goto mbox_exit;
  185. }
  186. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  187. " Scheduling Adapter Reset\n", ha->host_no,
  188. mbx_cmd[0]));
  189. ha->mailbox_timeout_count++;
  190. mbx_sts[0] = (-1);
  191. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  192. goto mbox_exit;
  193. }
  194. /*
  195. * Copy the mailbox out registers to the caller's mailbox in/out
  196. * structure.
  197. */
  198. spin_lock_irqsave(&ha->hardware_lock, flags);
  199. for (i = 0; i < outCount; i++)
  200. mbx_sts[i] = ha->mbox_status[i];
  201. /* Set return status and error flags (if applicable). */
  202. switch (ha->mbox_status[0]) {
  203. case MBOX_STS_COMMAND_COMPLETE:
  204. status = QLA_SUCCESS;
  205. break;
  206. case MBOX_STS_INTERMEDIATE_COMPLETION:
  207. status = QLA_SUCCESS;
  208. break;
  209. case MBOX_STS_BUSY:
  210. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  211. ha->host_no, __func__, mbx_cmd[0]));
  212. ha->mailbox_timeout_count++;
  213. break;
  214. default:
  215. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  216. "sts = %08X ****\n", ha->host_no, __func__,
  217. mbx_cmd[0], mbx_sts[0]));
  218. break;
  219. }
  220. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  221. mbox_exit:
  222. mutex_lock(&ha->mbox_sem);
  223. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  224. mutex_unlock(&ha->mbox_sem);
  225. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  226. return status;
  227. }
  228. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  229. {
  230. set_bit(AF_FW_RECOVERY, &ha->flags);
  231. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  232. ha->host_no, __func__);
  233. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  234. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  235. complete(&ha->mbx_intr_comp);
  236. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  237. "recovery, doing premature completion of "
  238. "mbx cmd\n", ha->host_no, __func__);
  239. } else {
  240. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  241. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  242. "recovery, doing premature completion of "
  243. "polling mbx cmd\n", ha->host_no, __func__);
  244. }
  245. }
  246. }
  247. static uint8_t
  248. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  249. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  250. {
  251. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  252. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  253. if (is_qla8022(ha))
  254. qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  255. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  256. mbox_cmd[1] = 0;
  257. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  258. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  259. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  260. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  261. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  262. QLA_SUCCESS) {
  263. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  264. "MBOX_CMD_INITIALIZE_FIRMWARE"
  265. " failed w/ status %04X\n",
  266. ha->host_no, __func__, mbox_sts[0]));
  267. return QLA_ERROR;
  268. }
  269. return QLA_SUCCESS;
  270. }
  271. uint8_t
  272. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  273. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  274. {
  275. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  276. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  277. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  278. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  279. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  280. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  281. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  282. QLA_SUCCESS) {
  283. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  284. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  285. " failed w/ status %04X\n",
  286. ha->host_no, __func__, mbox_sts[0]));
  287. return QLA_ERROR;
  288. }
  289. return QLA_SUCCESS;
  290. }
  291. static void
  292. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  293. struct addr_ctrl_blk *init_fw_cb)
  294. {
  295. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  296. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  297. ha->ip_config.ipv4_addr_state =
  298. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  299. if (ha->acb_version == ACB_SUPPORTED) {
  300. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  301. ha->ip_config.ipv6_addl_options =
  302. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  303. }
  304. /* Save IPv4 Address Info */
  305. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  306. min(sizeof(ha->ip_config.ip_address),
  307. sizeof(init_fw_cb->ipv4_addr)));
  308. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  309. min(sizeof(ha->ip_config.subnet_mask),
  310. sizeof(init_fw_cb->ipv4_subnet)));
  311. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  312. min(sizeof(ha->ip_config.gateway),
  313. sizeof(init_fw_cb->ipv4_gw_addr)));
  314. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  315. if (is_ipv6_enabled(ha)) {
  316. /* Save IPv6 Address */
  317. ha->ip_config.ipv6_link_local_state =
  318. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  319. ha->ip_config.ipv6_addr0_state =
  320. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  321. ha->ip_config.ipv6_addr1_state =
  322. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  323. ha->ip_config.ipv6_default_router_state =
  324. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  325. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  326. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  327. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  328. init_fw_cb->ipv6_if_id,
  329. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  330. sizeof(init_fw_cb->ipv6_if_id)));
  331. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  332. min(sizeof(ha->ip_config.ipv6_addr0),
  333. sizeof(init_fw_cb->ipv6_addr0)));
  334. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  335. min(sizeof(ha->ip_config.ipv6_addr1),
  336. sizeof(init_fw_cb->ipv6_addr1)));
  337. memcpy(&ha->ip_config.ipv6_default_router_addr,
  338. init_fw_cb->ipv6_dflt_rtr_addr,
  339. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  340. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  341. ha->ip_config.ipv6_vlan_tag =
  342. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  343. }
  344. }
  345. uint8_t
  346. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  347. uint32_t *mbox_cmd,
  348. uint32_t *mbox_sts,
  349. struct addr_ctrl_blk *init_fw_cb,
  350. dma_addr_t init_fw_cb_dma)
  351. {
  352. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  353. != QLA_SUCCESS) {
  354. DEBUG2(printk(KERN_WARNING
  355. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  356. ha->host_no, __func__));
  357. return QLA_ERROR;
  358. }
  359. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  360. /* Save some info in adapter structure. */
  361. ha->acb_version = init_fw_cb->acb_version;
  362. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  363. ha->heartbeat_interval = init_fw_cb->hb_interval;
  364. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  365. min(sizeof(ha->name_string),
  366. sizeof(init_fw_cb->iscsi_name)));
  367. /*memcpy(ha->alias, init_fw_cb->Alias,
  368. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  369. qla4xxx_update_local_ip(ha, init_fw_cb);
  370. return QLA_SUCCESS;
  371. }
  372. /**
  373. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  374. * @ha: Pointer to host adapter structure.
  375. **/
  376. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  377. {
  378. struct addr_ctrl_blk *init_fw_cb;
  379. dma_addr_t init_fw_cb_dma;
  380. uint32_t mbox_cmd[MBOX_REG_COUNT];
  381. uint32_t mbox_sts[MBOX_REG_COUNT];
  382. int status = QLA_ERROR;
  383. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  384. sizeof(struct addr_ctrl_blk),
  385. &init_fw_cb_dma, GFP_KERNEL);
  386. if (init_fw_cb == NULL) {
  387. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  388. ha->host_no, __func__));
  389. goto exit_init_fw_cb_no_free;
  390. }
  391. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  392. /* Get Initialize Firmware Control Block. */
  393. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  394. memset(&mbox_sts, 0, sizeof(mbox_sts));
  395. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  396. QLA_SUCCESS) {
  397. dma_free_coherent(&ha->pdev->dev,
  398. sizeof(struct addr_ctrl_blk),
  399. init_fw_cb, init_fw_cb_dma);
  400. goto exit_init_fw_cb;
  401. }
  402. /* Initialize request and response queues. */
  403. qla4xxx_init_rings(ha);
  404. /* Fill in the request and response queue information. */
  405. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  406. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  407. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  408. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  409. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  410. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  411. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  412. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  413. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  414. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  415. /* Set up required options. */
  416. init_fw_cb->fw_options |=
  417. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  418. FWOPT_INITIATOR_MODE);
  419. if (is_qla8022(ha))
  420. init_fw_cb->fw_options |=
  421. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  422. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  423. /* Set bit for "serialize task mgmt" all other bits need to be zero */
  424. init_fw_cb->add_fw_options = 0;
  425. init_fw_cb->add_fw_options |=
  426. __constant_cpu_to_le16(SERIALIZE_TASK_MGMT);
  427. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  428. != QLA_SUCCESS) {
  429. DEBUG2(printk(KERN_WARNING
  430. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  431. ha->host_no, __func__));
  432. goto exit_init_fw_cb;
  433. }
  434. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  435. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  436. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  437. ha->host_no, __func__));
  438. goto exit_init_fw_cb;
  439. }
  440. status = QLA_SUCCESS;
  441. exit_init_fw_cb:
  442. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  443. init_fw_cb, init_fw_cb_dma);
  444. exit_init_fw_cb_no_free:
  445. return status;
  446. }
  447. /**
  448. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  449. * @ha: Pointer to host adapter structure.
  450. **/
  451. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  452. {
  453. struct addr_ctrl_blk *init_fw_cb;
  454. dma_addr_t init_fw_cb_dma;
  455. uint32_t mbox_cmd[MBOX_REG_COUNT];
  456. uint32_t mbox_sts[MBOX_REG_COUNT];
  457. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  458. sizeof(struct addr_ctrl_blk),
  459. &init_fw_cb_dma, GFP_KERNEL);
  460. if (init_fw_cb == NULL) {
  461. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  462. __func__);
  463. return QLA_ERROR;
  464. }
  465. /* Get Initialize Firmware Control Block. */
  466. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  467. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  468. QLA_SUCCESS) {
  469. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  470. ha->host_no, __func__));
  471. dma_free_coherent(&ha->pdev->dev,
  472. sizeof(struct addr_ctrl_blk),
  473. init_fw_cb, init_fw_cb_dma);
  474. return QLA_ERROR;
  475. }
  476. /* Save IP Address. */
  477. qla4xxx_update_local_ip(ha, init_fw_cb);
  478. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  479. init_fw_cb, init_fw_cb_dma);
  480. return QLA_SUCCESS;
  481. }
  482. /**
  483. * qla4xxx_get_firmware_state - gets firmware state of HBA
  484. * @ha: Pointer to host adapter structure.
  485. **/
  486. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  487. {
  488. uint32_t mbox_cmd[MBOX_REG_COUNT];
  489. uint32_t mbox_sts[MBOX_REG_COUNT];
  490. /* Get firmware version */
  491. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  492. memset(&mbox_sts, 0, sizeof(mbox_sts));
  493. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  494. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  495. QLA_SUCCESS) {
  496. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  497. "status %04X\n", ha->host_no, __func__,
  498. mbox_sts[0]));
  499. return QLA_ERROR;
  500. }
  501. ha->firmware_state = mbox_sts[1];
  502. ha->board_id = mbox_sts[2];
  503. ha->addl_fw_state = mbox_sts[3];
  504. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  505. ha->host_no, __func__, ha->firmware_state);)
  506. return QLA_SUCCESS;
  507. }
  508. /**
  509. * qla4xxx_get_firmware_status - retrieves firmware status
  510. * @ha: Pointer to host adapter structure.
  511. **/
  512. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  513. {
  514. uint32_t mbox_cmd[MBOX_REG_COUNT];
  515. uint32_t mbox_sts[MBOX_REG_COUNT];
  516. /* Get firmware version */
  517. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  518. memset(&mbox_sts, 0, sizeof(mbox_sts));
  519. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  520. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  521. QLA_SUCCESS) {
  522. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  523. "status %04X\n", ha->host_no, __func__,
  524. mbox_sts[0]));
  525. return QLA_ERROR;
  526. }
  527. ql4_printk(KERN_INFO, ha, "%ld firmare IOCBs available (%d).\n",
  528. ha->host_no, mbox_sts[2]);
  529. return QLA_SUCCESS;
  530. }
  531. /**
  532. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  533. * @ha: Pointer to host adapter structure.
  534. * @fw_ddb_index: Firmware's device database index
  535. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  536. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  537. * @next_ddb_index: Pointer to next valid device database index
  538. * @fw_ddb_device_state: Pointer to device state
  539. **/
  540. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  541. uint16_t fw_ddb_index,
  542. struct dev_db_entry *fw_ddb_entry,
  543. dma_addr_t fw_ddb_entry_dma,
  544. uint32_t *num_valid_ddb_entries,
  545. uint32_t *next_ddb_index,
  546. uint32_t *fw_ddb_device_state,
  547. uint32_t *conn_err_detail,
  548. uint16_t *tcp_source_port_num,
  549. uint16_t *connection_id)
  550. {
  551. int status = QLA_ERROR;
  552. uint16_t options;
  553. uint32_t mbox_cmd[MBOX_REG_COUNT];
  554. uint32_t mbox_sts[MBOX_REG_COUNT];
  555. /* Make sure the device index is valid */
  556. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  557. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  558. ha->host_no, __func__, fw_ddb_index));
  559. goto exit_get_fwddb;
  560. }
  561. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  562. memset(&mbox_sts, 0, sizeof(mbox_sts));
  563. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  564. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  565. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  566. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  567. mbox_cmd[4] = sizeof(struct dev_db_entry);
  568. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  569. QLA_ERROR) {
  570. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  571. " with status 0x%04X\n", ha->host_no, __func__,
  572. mbox_sts[0]));
  573. goto exit_get_fwddb;
  574. }
  575. if (fw_ddb_index != mbox_sts[1]) {
  576. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  577. ha->host_no, __func__, fw_ddb_index,
  578. mbox_sts[1]));
  579. goto exit_get_fwddb;
  580. }
  581. if (fw_ddb_entry) {
  582. options = le16_to_cpu(fw_ddb_entry->options);
  583. if (options & DDB_OPT_IPV6_DEVICE) {
  584. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  585. "Next %d State %04x ConnErr %08x %pI6 "
  586. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  587. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  588. mbox_sts[4], mbox_sts[5],
  589. fw_ddb_entry->ip_addr,
  590. le16_to_cpu(fw_ddb_entry->port),
  591. fw_ddb_entry->iscsi_name);
  592. } else {
  593. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  594. "Next %d State %04x ConnErr %08x %pI4 "
  595. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  596. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  597. mbox_sts[4], mbox_sts[5],
  598. fw_ddb_entry->ip_addr,
  599. le16_to_cpu(fw_ddb_entry->port),
  600. fw_ddb_entry->iscsi_name);
  601. }
  602. }
  603. if (num_valid_ddb_entries)
  604. *num_valid_ddb_entries = mbox_sts[2];
  605. if (next_ddb_index)
  606. *next_ddb_index = mbox_sts[3];
  607. if (fw_ddb_device_state)
  608. *fw_ddb_device_state = mbox_sts[4];
  609. /*
  610. * RA: This mailbox has been changed to pass connection error and
  611. * details. Its true for ISP4010 as per Version E - Not sure when it
  612. * was changed. Get the time2wait from the fw_dd_entry field :
  613. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  614. * struct.
  615. */
  616. if (conn_err_detail)
  617. *conn_err_detail = mbox_sts[5];
  618. if (tcp_source_port_num)
  619. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  620. if (connection_id)
  621. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  622. status = QLA_SUCCESS;
  623. exit_get_fwddb:
  624. return status;
  625. }
  626. /**
  627. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  628. * @ha: Pointer to host adapter structure.
  629. * @fw_ddb_index: Firmware's device database index
  630. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  631. *
  632. * This routine initializes or updates the adapter's device database
  633. * entry for the specified device. It also triggers a login for the
  634. * specified device. Therefore, it may also be used as a secondary
  635. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  636. **/
  637. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  638. dma_addr_t fw_ddb_entry_dma)
  639. {
  640. uint32_t mbox_cmd[MBOX_REG_COUNT];
  641. uint32_t mbox_sts[MBOX_REG_COUNT];
  642. int status;
  643. /* Do not wait for completion. The firmware will send us an
  644. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  645. */
  646. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  647. memset(&mbox_sts, 0, sizeof(mbox_sts));
  648. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  649. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  650. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  651. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  652. mbox_cmd[4] = sizeof(struct dev_db_entry);
  653. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  654. &mbox_sts[0]);
  655. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  656. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  657. return status;
  658. }
  659. /**
  660. * qla4xxx_get_crash_record - retrieves crash record.
  661. * @ha: Pointer to host adapter structure.
  662. *
  663. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  664. **/
  665. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  666. {
  667. uint32_t mbox_cmd[MBOX_REG_COUNT];
  668. uint32_t mbox_sts[MBOX_REG_COUNT];
  669. struct crash_record *crash_record = NULL;
  670. dma_addr_t crash_record_dma = 0;
  671. uint32_t crash_record_size = 0;
  672. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  673. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  674. /* Get size of crash record. */
  675. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  676. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  677. QLA_SUCCESS) {
  678. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  679. ha->host_no, __func__));
  680. goto exit_get_crash_record;
  681. }
  682. crash_record_size = mbox_sts[4];
  683. if (crash_record_size == 0) {
  684. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  685. ha->host_no, __func__));
  686. goto exit_get_crash_record;
  687. }
  688. /* Alloc Memory for Crash Record. */
  689. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  690. &crash_record_dma, GFP_KERNEL);
  691. if (crash_record == NULL)
  692. goto exit_get_crash_record;
  693. /* Get Crash Record. */
  694. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  695. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  696. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  697. mbox_cmd[2] = LSDW(crash_record_dma);
  698. mbox_cmd[3] = MSDW(crash_record_dma);
  699. mbox_cmd[4] = crash_record_size;
  700. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  701. QLA_SUCCESS)
  702. goto exit_get_crash_record;
  703. /* Dump Crash Record. */
  704. exit_get_crash_record:
  705. if (crash_record)
  706. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  707. crash_record, crash_record_dma);
  708. }
  709. /**
  710. * qla4xxx_get_conn_event_log - retrieves connection event log
  711. * @ha: Pointer to host adapter structure.
  712. **/
  713. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  714. {
  715. uint32_t mbox_cmd[MBOX_REG_COUNT];
  716. uint32_t mbox_sts[MBOX_REG_COUNT];
  717. struct conn_event_log_entry *event_log = NULL;
  718. dma_addr_t event_log_dma = 0;
  719. uint32_t event_log_size = 0;
  720. uint32_t num_valid_entries;
  721. uint32_t oldest_entry = 0;
  722. uint32_t max_event_log_entries;
  723. uint8_t i;
  724. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  725. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  726. /* Get size of crash record. */
  727. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  728. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  729. QLA_SUCCESS)
  730. goto exit_get_event_log;
  731. event_log_size = mbox_sts[4];
  732. if (event_log_size == 0)
  733. goto exit_get_event_log;
  734. /* Alloc Memory for Crash Record. */
  735. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  736. &event_log_dma, GFP_KERNEL);
  737. if (event_log == NULL)
  738. goto exit_get_event_log;
  739. /* Get Crash Record. */
  740. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  741. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  742. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  743. mbox_cmd[2] = LSDW(event_log_dma);
  744. mbox_cmd[3] = MSDW(event_log_dma);
  745. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  746. QLA_SUCCESS) {
  747. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  748. "log!\n", ha->host_no, __func__));
  749. goto exit_get_event_log;
  750. }
  751. /* Dump Event Log. */
  752. num_valid_entries = mbox_sts[1];
  753. max_event_log_entries = event_log_size /
  754. sizeof(struct conn_event_log_entry);
  755. if (num_valid_entries > max_event_log_entries)
  756. oldest_entry = num_valid_entries % max_event_log_entries;
  757. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  758. ha->host_no, num_valid_entries));
  759. if (ql4xextended_error_logging == 3) {
  760. if (oldest_entry == 0) {
  761. /* Circular Buffer has not wrapped around */
  762. for (i=0; i < num_valid_entries; i++) {
  763. qla4xxx_dump_buffer((uint8_t *)event_log+
  764. (i*sizeof(*event_log)),
  765. sizeof(*event_log));
  766. }
  767. }
  768. else {
  769. /* Circular Buffer has wrapped around -
  770. * display accordingly*/
  771. for (i=oldest_entry; i < max_event_log_entries; i++) {
  772. qla4xxx_dump_buffer((uint8_t *)event_log+
  773. (i*sizeof(*event_log)),
  774. sizeof(*event_log));
  775. }
  776. for (i=0; i < oldest_entry; i++) {
  777. qla4xxx_dump_buffer((uint8_t *)event_log+
  778. (i*sizeof(*event_log)),
  779. sizeof(*event_log));
  780. }
  781. }
  782. }
  783. exit_get_event_log:
  784. if (event_log)
  785. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  786. event_log_dma);
  787. }
  788. /**
  789. * qla4xxx_abort_task - issues Abort Task
  790. * @ha: Pointer to host adapter structure.
  791. * @srb: Pointer to srb entry
  792. *
  793. * This routine performs a LUN RESET on the specified target/lun.
  794. * The caller must ensure that the ddb_entry and lun_entry pointers
  795. * are valid before calling this routine.
  796. **/
  797. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  798. {
  799. uint32_t mbox_cmd[MBOX_REG_COUNT];
  800. uint32_t mbox_sts[MBOX_REG_COUNT];
  801. struct scsi_cmnd *cmd = srb->cmd;
  802. int status = QLA_SUCCESS;
  803. unsigned long flags = 0;
  804. uint32_t index;
  805. /*
  806. * Send abort task command to ISP, so that the ISP will return
  807. * request with ABORT status
  808. */
  809. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  810. memset(&mbox_sts, 0, sizeof(mbox_sts));
  811. spin_lock_irqsave(&ha->hardware_lock, flags);
  812. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  813. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  814. /* Firmware already posted completion on response queue */
  815. if (index == MAX_SRBS)
  816. return status;
  817. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  818. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  819. mbox_cmd[2] = index;
  820. /* Immediate Command Enable */
  821. mbox_cmd[5] = 0x01;
  822. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  823. &mbox_sts[0]);
  824. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  825. status = QLA_ERROR;
  826. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  827. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  828. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  829. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  830. }
  831. return status;
  832. }
  833. /**
  834. * qla4xxx_reset_lun - issues LUN Reset
  835. * @ha: Pointer to host adapter structure.
  836. * @ddb_entry: Pointer to device database entry
  837. * @lun: lun number
  838. *
  839. * This routine performs a LUN RESET on the specified target/lun.
  840. * The caller must ensure that the ddb_entry and lun_entry pointers
  841. * are valid before calling this routine.
  842. **/
  843. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  844. int lun)
  845. {
  846. uint32_t mbox_cmd[MBOX_REG_COUNT];
  847. uint32_t mbox_sts[MBOX_REG_COUNT];
  848. int status = QLA_SUCCESS;
  849. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  850. ddb_entry->fw_ddb_index, lun));
  851. /*
  852. * Send lun reset command to ISP, so that the ISP will return all
  853. * outstanding requests with RESET status
  854. */
  855. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  856. memset(&mbox_sts, 0, sizeof(mbox_sts));
  857. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  858. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  859. mbox_cmd[2] = lun << 8;
  860. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  861. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  862. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  863. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  864. status = QLA_ERROR;
  865. return status;
  866. }
  867. /**
  868. * qla4xxx_reset_target - issues target Reset
  869. * @ha: Pointer to host adapter structure.
  870. * @db_entry: Pointer to device database entry
  871. * @un_entry: Pointer to lun entry structure
  872. *
  873. * This routine performs a TARGET RESET on the specified target.
  874. * The caller must ensure that the ddb_entry pointers
  875. * are valid before calling this routine.
  876. **/
  877. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  878. struct ddb_entry *ddb_entry)
  879. {
  880. uint32_t mbox_cmd[MBOX_REG_COUNT];
  881. uint32_t mbox_sts[MBOX_REG_COUNT];
  882. int status = QLA_SUCCESS;
  883. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  884. ddb_entry->fw_ddb_index));
  885. /*
  886. * Send target reset command to ISP, so that the ISP will return all
  887. * outstanding requests with RESET status
  888. */
  889. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  890. memset(&mbox_sts, 0, sizeof(mbox_sts));
  891. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  892. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  893. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  894. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  895. &mbox_sts[0]);
  896. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  897. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  898. status = QLA_ERROR;
  899. return status;
  900. }
  901. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  902. uint32_t offset, uint32_t len)
  903. {
  904. uint32_t mbox_cmd[MBOX_REG_COUNT];
  905. uint32_t mbox_sts[MBOX_REG_COUNT];
  906. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  907. memset(&mbox_sts, 0, sizeof(mbox_sts));
  908. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  909. mbox_cmd[1] = LSDW(dma_addr);
  910. mbox_cmd[2] = MSDW(dma_addr);
  911. mbox_cmd[3] = offset;
  912. mbox_cmd[4] = len;
  913. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  914. QLA_SUCCESS) {
  915. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  916. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  917. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  918. return QLA_ERROR;
  919. }
  920. return QLA_SUCCESS;
  921. }
  922. /**
  923. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  924. * @ha: Pointer to host adapter structure.
  925. *
  926. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  927. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  928. * those mailboxes, if unused.
  929. **/
  930. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  931. {
  932. struct about_fw_info *about_fw = NULL;
  933. dma_addr_t about_fw_dma;
  934. uint32_t mbox_cmd[MBOX_REG_COUNT];
  935. uint32_t mbox_sts[MBOX_REG_COUNT];
  936. int status = QLA_ERROR;
  937. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  938. sizeof(struct about_fw_info),
  939. &about_fw_dma, GFP_KERNEL);
  940. if (!about_fw) {
  941. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  942. "for about_fw\n", __func__));
  943. return status;
  944. }
  945. memset(about_fw, 0, sizeof(struct about_fw_info));
  946. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  947. memset(&mbox_sts, 0, sizeof(mbox_sts));
  948. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  949. mbox_cmd[2] = LSDW(about_fw_dma);
  950. mbox_cmd[3] = MSDW(about_fw_dma);
  951. mbox_cmd[4] = sizeof(struct about_fw_info);
  952. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  953. &mbox_cmd[0], &mbox_sts[0]);
  954. if (status != QLA_SUCCESS) {
  955. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  956. "failed w/ status %04X\n", __func__,
  957. mbox_sts[0]));
  958. goto exit_about_fw;
  959. }
  960. /* Save version information. */
  961. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  962. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  963. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  964. ha->build_number = le16_to_cpu(about_fw->fw_build);
  965. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  966. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  967. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  968. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  969. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  970. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  971. status = QLA_SUCCESS;
  972. exit_about_fw:
  973. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  974. about_fw, about_fw_dma);
  975. return status;
  976. }
  977. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  978. dma_addr_t dma_addr)
  979. {
  980. uint32_t mbox_cmd[MBOX_REG_COUNT];
  981. uint32_t mbox_sts[MBOX_REG_COUNT];
  982. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  983. memset(&mbox_sts, 0, sizeof(mbox_sts));
  984. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  985. mbox_cmd[2] = LSDW(dma_addr);
  986. mbox_cmd[3] = MSDW(dma_addr);
  987. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  988. QLA_SUCCESS) {
  989. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  990. ha->host_no, __func__, mbox_sts[0]));
  991. return QLA_ERROR;
  992. }
  993. return QLA_SUCCESS;
  994. }
  995. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  996. {
  997. uint32_t mbox_cmd[MBOX_REG_COUNT];
  998. uint32_t mbox_sts[MBOX_REG_COUNT];
  999. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1000. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1001. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1002. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  1003. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  1004. QLA_SUCCESS) {
  1005. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  1006. *ddb_index = mbox_sts[2];
  1007. } else {
  1008. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1009. ha->host_no, __func__, mbox_sts[0]));
  1010. return QLA_ERROR;
  1011. }
  1012. } else {
  1013. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  1014. }
  1015. return QLA_SUCCESS;
  1016. }
  1017. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  1018. {
  1019. struct dev_db_entry *fw_ddb_entry;
  1020. dma_addr_t fw_ddb_entry_dma;
  1021. uint32_t ddb_index;
  1022. int ret_val = QLA_SUCCESS;
  1023. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  1024. sizeof(*fw_ddb_entry),
  1025. &fw_ddb_entry_dma, GFP_KERNEL);
  1026. if (!fw_ddb_entry) {
  1027. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  1028. ha->host_no, __func__));
  1029. ret_val = QLA_ERROR;
  1030. goto exit_send_tgts_no_free;
  1031. }
  1032. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  1033. if (ret_val != QLA_SUCCESS)
  1034. goto exit_send_tgts;
  1035. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  1036. if (ret_val != QLA_SUCCESS)
  1037. goto exit_send_tgts;
  1038. memset(fw_ddb_entry->iscsi_alias, 0,
  1039. sizeof(fw_ddb_entry->iscsi_alias));
  1040. memset(fw_ddb_entry->iscsi_name, 0,
  1041. sizeof(fw_ddb_entry->iscsi_name));
  1042. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1043. memset(fw_ddb_entry->tgt_addr, 0,
  1044. sizeof(fw_ddb_entry->tgt_addr));
  1045. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  1046. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  1047. fw_ddb_entry->ip_addr[0] = *ip;
  1048. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  1049. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  1050. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  1051. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  1052. exit_send_tgts:
  1053. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1054. fw_ddb_entry, fw_ddb_entry_dma);
  1055. exit_send_tgts_no_free:
  1056. return ret_val;
  1057. }
  1058. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1059. uint32_t offset, uint32_t length, uint32_t options)
  1060. {
  1061. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1062. uint32_t mbox_sts[MBOX_REG_COUNT];
  1063. int status = QLA_SUCCESS;
  1064. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1065. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1066. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1067. mbox_cmd[1] = LSDW(dma_addr);
  1068. mbox_cmd[2] = MSDW(dma_addr);
  1069. mbox_cmd[3] = offset;
  1070. mbox_cmd[4] = length;
  1071. mbox_cmd[5] = options;
  1072. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1073. if (status != QLA_SUCCESS) {
  1074. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1075. "failed w/ status %04X, mbx1 %04X\n",
  1076. __func__, mbox_sts[0], mbox_sts[1]));
  1077. }
  1078. return status;
  1079. }
  1080. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1081. uint16_t fw_ddb_index,
  1082. uint16_t connection_id,
  1083. uint16_t option)
  1084. {
  1085. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1086. uint32_t mbox_sts[MBOX_REG_COUNT];
  1087. int status = QLA_SUCCESS;
  1088. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1089. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1090. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1091. mbox_cmd[1] = fw_ddb_index;
  1092. mbox_cmd[2] = connection_id;
  1093. mbox_cmd[3] = option;
  1094. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1095. if (status != QLA_SUCCESS) {
  1096. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1097. "option %04x failed w/ status %04X %04X\n",
  1098. __func__, option, mbox_sts[0], mbox_sts[1]));
  1099. }
  1100. return status;
  1101. }
  1102. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1103. {
  1104. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1105. uint32_t mbox_sts[MBOX_REG_COUNT];
  1106. int status = QLA_SUCCESS;
  1107. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1108. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1109. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1110. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1111. if (status != QLA_SUCCESS) {
  1112. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1113. "failed w/ status %04X %04X %04X", __func__,
  1114. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1115. }
  1116. return status;
  1117. }
  1118. int qla4xxx_get_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1119. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1120. {
  1121. int status = QLA_SUCCESS;
  1122. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1123. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1124. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1125. mbox_cmd[1] = 0; /* Primary ACB */
  1126. mbox_cmd[2] = LSDW(acb_dma);
  1127. mbox_cmd[3] = MSDW(acb_dma);
  1128. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1129. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1130. if (status != QLA_SUCCESS) {
  1131. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1132. "failed w/ status %04X\n", __func__,
  1133. mbox_sts[0]));
  1134. }
  1135. return status;
  1136. }
  1137. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1138. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1139. {
  1140. int status = QLA_SUCCESS;
  1141. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1142. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1143. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1144. mbox_cmd[1] = 0; /* Primary ACB */
  1145. mbox_cmd[2] = LSDW(acb_dma);
  1146. mbox_cmd[3] = MSDW(acb_dma);
  1147. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1148. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1149. if (status != QLA_SUCCESS) {
  1150. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1151. "failed w/ status %04X\n", __func__,
  1152. mbox_sts[0]));
  1153. }
  1154. return status;
  1155. }