vmwgfx_kms.c 50 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. int vmw_cursor_update_dmabuf(struct vmw_private *dev_priv,
  72. struct vmw_dma_buffer *dmabuf,
  73. u32 width, u32 height,
  74. u32 hotspotX, u32 hotspotY)
  75. {
  76. struct ttm_bo_kmap_obj map;
  77. unsigned long kmap_offset;
  78. unsigned long kmap_num;
  79. void *virtual;
  80. bool dummy;
  81. int ret;
  82. kmap_offset = 0;
  83. kmap_num = (width*height*4 + PAGE_SIZE - 1) >> PAGE_SHIFT;
  84. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  85. if (unlikely(ret != 0)) {
  86. DRM_ERROR("reserve failed\n");
  87. return -EINVAL;
  88. }
  89. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  90. if (unlikely(ret != 0))
  91. goto err_unreserve;
  92. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  93. ret = vmw_cursor_update_image(dev_priv, virtual, width, height,
  94. hotspotX, hotspotY);
  95. ttm_bo_kunmap(&map);
  96. err_unreserve:
  97. ttm_bo_unreserve(&dmabuf->base);
  98. return ret;
  99. }
  100. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  101. bool show, int x, int y)
  102. {
  103. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  104. uint32_t count;
  105. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  106. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  107. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  108. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  109. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  110. }
  111. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  112. uint32_t handle, uint32_t width, uint32_t height)
  113. {
  114. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  115. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  116. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  117. struct vmw_surface *surface = NULL;
  118. struct vmw_dma_buffer *dmabuf = NULL;
  119. int ret;
  120. /* A lot of the code assumes this */
  121. if (handle && (width != 64 || height != 64))
  122. return -EINVAL;
  123. if (handle) {
  124. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  125. handle, &surface);
  126. if (!ret) {
  127. if (!surface->snooper.image) {
  128. DRM_ERROR("surface not suitable for cursor\n");
  129. vmw_surface_unreference(&surface);
  130. return -EINVAL;
  131. }
  132. } else {
  133. ret = vmw_user_dmabuf_lookup(tfile,
  134. handle, &dmabuf);
  135. if (ret) {
  136. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  137. return -EINVAL;
  138. }
  139. }
  140. }
  141. /* takedown old cursor */
  142. if (du->cursor_surface) {
  143. du->cursor_surface->snooper.crtc = NULL;
  144. vmw_surface_unreference(&du->cursor_surface);
  145. }
  146. if (du->cursor_dmabuf)
  147. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  148. /* setup new image */
  149. if (surface) {
  150. /* vmw_user_surface_lookup takes one reference */
  151. du->cursor_surface = surface;
  152. du->cursor_surface->snooper.crtc = crtc;
  153. du->cursor_age = du->cursor_surface->snooper.age;
  154. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  155. 64, 64, du->hotspot_x, du->hotspot_y);
  156. } else if (dmabuf) {
  157. /* vmw_user_surface_lookup takes one reference */
  158. du->cursor_dmabuf = dmabuf;
  159. ret = vmw_cursor_update_dmabuf(dev_priv, dmabuf, width, height,
  160. du->hotspot_x, du->hotspot_y);
  161. } else {
  162. vmw_cursor_update_position(dev_priv, false, 0, 0);
  163. return 0;
  164. }
  165. vmw_cursor_update_position(dev_priv, true,
  166. du->cursor_x + du->hotspot_x,
  167. du->cursor_y + du->hotspot_y);
  168. return 0;
  169. }
  170. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  171. {
  172. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  173. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  174. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  175. du->cursor_x = x + crtc->x;
  176. du->cursor_y = y + crtc->y;
  177. vmw_cursor_update_position(dev_priv, shown,
  178. du->cursor_x + du->hotspot_x,
  179. du->cursor_y + du->hotspot_y);
  180. return 0;
  181. }
  182. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  183. struct ttm_object_file *tfile,
  184. struct ttm_buffer_object *bo,
  185. SVGA3dCmdHeader *header)
  186. {
  187. struct ttm_bo_kmap_obj map;
  188. unsigned long kmap_offset;
  189. unsigned long kmap_num;
  190. SVGA3dCopyBox *box;
  191. unsigned box_count;
  192. void *virtual;
  193. bool dummy;
  194. struct vmw_dma_cmd {
  195. SVGA3dCmdHeader header;
  196. SVGA3dCmdSurfaceDMA dma;
  197. } *cmd;
  198. int i, ret;
  199. cmd = container_of(header, struct vmw_dma_cmd, header);
  200. /* No snooper installed */
  201. if (!srf->snooper.image)
  202. return;
  203. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  204. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  205. return;
  206. }
  207. if (cmd->header.size < 64) {
  208. DRM_ERROR("at least one full copy box must be given\n");
  209. return;
  210. }
  211. box = (SVGA3dCopyBox *)&cmd[1];
  212. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  213. sizeof(SVGA3dCopyBox);
  214. if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  215. box->x != 0 || box->y != 0 || box->z != 0 ||
  216. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  217. box->d != 1 || box_count != 1) {
  218. /* TODO handle none page aligned offsets */
  219. /* TODO handle more dst & src != 0 */
  220. /* TODO handle more then one copy */
  221. DRM_ERROR("Cant snoop dma request for cursor!\n");
  222. DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
  223. box->srcx, box->srcy, box->srcz,
  224. box->x, box->y, box->z,
  225. box->w, box->h, box->d, box_count,
  226. cmd->dma.guest.ptr.offset);
  227. return;
  228. }
  229. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  230. kmap_num = (64*64*4) >> PAGE_SHIFT;
  231. ret = ttm_bo_reserve(bo, true, false, false, 0);
  232. if (unlikely(ret != 0)) {
  233. DRM_ERROR("reserve failed\n");
  234. return;
  235. }
  236. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  237. if (unlikely(ret != 0))
  238. goto err_unreserve;
  239. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  240. if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
  241. memcpy(srf->snooper.image, virtual, 64*64*4);
  242. } else {
  243. /* Image is unsigned pointer. */
  244. for (i = 0; i < box->h; i++)
  245. memcpy(srf->snooper.image + i * 64,
  246. virtual + i * cmd->dma.guest.pitch,
  247. box->w * 4);
  248. }
  249. srf->snooper.age++;
  250. /* we can't call this function from this function since execbuf has
  251. * reserved fifo space.
  252. *
  253. * if (srf->snooper.crtc)
  254. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  255. * srf->snooper.image, 64, 64,
  256. * du->hotspot_x, du->hotspot_y);
  257. */
  258. ttm_bo_kunmap(&map);
  259. err_unreserve:
  260. ttm_bo_unreserve(bo);
  261. }
  262. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  263. {
  264. struct drm_device *dev = dev_priv->dev;
  265. struct vmw_display_unit *du;
  266. struct drm_crtc *crtc;
  267. mutex_lock(&dev->mode_config.mutex);
  268. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  269. du = vmw_crtc_to_du(crtc);
  270. if (!du->cursor_surface ||
  271. du->cursor_age == du->cursor_surface->snooper.age)
  272. continue;
  273. du->cursor_age = du->cursor_surface->snooper.age;
  274. vmw_cursor_update_image(dev_priv,
  275. du->cursor_surface->snooper.image,
  276. 64, 64, du->hotspot_x, du->hotspot_y);
  277. }
  278. mutex_unlock(&dev->mode_config.mutex);
  279. }
  280. /*
  281. * Generic framebuffer code
  282. */
  283. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  284. struct drm_file *file_priv,
  285. unsigned int *handle)
  286. {
  287. if (handle)
  288. handle = 0;
  289. return 0;
  290. }
  291. /*
  292. * Surface framebuffer code
  293. */
  294. #define vmw_framebuffer_to_vfbs(x) \
  295. container_of(x, struct vmw_framebuffer_surface, base.base)
  296. struct vmw_framebuffer_surface {
  297. struct vmw_framebuffer base;
  298. struct vmw_surface *surface;
  299. struct vmw_dma_buffer *buffer;
  300. struct list_head head;
  301. struct drm_master *master;
  302. };
  303. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  304. {
  305. struct vmw_framebuffer_surface *vfbs =
  306. vmw_framebuffer_to_vfbs(framebuffer);
  307. struct vmw_master *vmaster = vmw_master(vfbs->master);
  308. mutex_lock(&vmaster->fb_surf_mutex);
  309. list_del(&vfbs->head);
  310. mutex_unlock(&vmaster->fb_surf_mutex);
  311. drm_master_put(&vfbs->master);
  312. drm_framebuffer_cleanup(framebuffer);
  313. vmw_surface_unreference(&vfbs->surface);
  314. ttm_base_object_unref(&vfbs->base.user_obj);
  315. kfree(vfbs);
  316. }
  317. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  318. struct drm_file *file_priv,
  319. struct vmw_framebuffer *framebuffer,
  320. unsigned flags, unsigned color,
  321. struct drm_clip_rect *clips,
  322. unsigned num_clips, int inc)
  323. {
  324. struct drm_clip_rect *clips_ptr;
  325. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  326. struct drm_crtc *crtc;
  327. size_t fifo_size;
  328. int i, num_units;
  329. int ret = 0; /* silence warning */
  330. int left, right, top, bottom;
  331. struct {
  332. SVGA3dCmdHeader header;
  333. SVGA3dCmdBlitSurfaceToScreen body;
  334. } *cmd;
  335. SVGASignedRect *blits;
  336. num_units = 0;
  337. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  338. head) {
  339. if (crtc->fb != &framebuffer->base)
  340. continue;
  341. units[num_units++] = vmw_crtc_to_du(crtc);
  342. }
  343. BUG_ON(!clips || !num_clips);
  344. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  345. cmd = kzalloc(fifo_size, GFP_KERNEL);
  346. if (unlikely(cmd == NULL)) {
  347. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  348. return -ENOMEM;
  349. }
  350. left = clips->x1;
  351. right = clips->x2;
  352. top = clips->y1;
  353. bottom = clips->y2;
  354. /* skip the first clip rect */
  355. for (i = 1, clips_ptr = clips + inc;
  356. i < num_clips; i++, clips_ptr += inc) {
  357. left = min_t(int, left, (int)clips_ptr->x1);
  358. right = max_t(int, right, (int)clips_ptr->x2);
  359. top = min_t(int, top, (int)clips_ptr->y1);
  360. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  361. }
  362. /* only need to do this once */
  363. memset(cmd, 0, fifo_size);
  364. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  365. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  366. cmd->body.srcRect.left = left;
  367. cmd->body.srcRect.right = right;
  368. cmd->body.srcRect.top = top;
  369. cmd->body.srcRect.bottom = bottom;
  370. clips_ptr = clips;
  371. blits = (SVGASignedRect *)&cmd[1];
  372. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  373. blits[i].left = clips_ptr->x1 - left;
  374. blits[i].right = clips_ptr->x2 - left;
  375. blits[i].top = clips_ptr->y1 - top;
  376. blits[i].bottom = clips_ptr->y2 - top;
  377. }
  378. /* do per unit writing, reuse fifo for each */
  379. for (i = 0; i < num_units; i++) {
  380. struct vmw_display_unit *unit = units[i];
  381. int clip_x1 = left - unit->crtc.x;
  382. int clip_y1 = top - unit->crtc.y;
  383. int clip_x2 = right - unit->crtc.x;
  384. int clip_y2 = bottom - unit->crtc.y;
  385. /* skip any crtcs that misses the clip region */
  386. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  387. clip_y1 >= unit->crtc.mode.vdisplay ||
  388. clip_x2 <= 0 || clip_y2 <= 0)
  389. continue;
  390. /* need to reset sid as it is changed by execbuf */
  391. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  392. cmd->body.destScreenId = unit->unit;
  393. /*
  394. * The blit command is a lot more resilient then the
  395. * readback command when it comes to clip rects. So its
  396. * okay to go out of bounds.
  397. */
  398. cmd->body.destRect.left = clip_x1;
  399. cmd->body.destRect.right = clip_x2;
  400. cmd->body.destRect.top = clip_y1;
  401. cmd->body.destRect.bottom = clip_y2;
  402. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  403. fifo_size, 0, NULL);
  404. if (unlikely(ret != 0))
  405. break;
  406. }
  407. kfree(cmd);
  408. return ret;
  409. }
  410. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  411. struct drm_file *file_priv,
  412. unsigned flags, unsigned color,
  413. struct drm_clip_rect *clips,
  414. unsigned num_clips)
  415. {
  416. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  417. struct vmw_master *vmaster = vmw_master(file_priv->master);
  418. struct vmw_framebuffer_surface *vfbs =
  419. vmw_framebuffer_to_vfbs(framebuffer);
  420. struct drm_clip_rect norect;
  421. int ret, inc = 1;
  422. if (unlikely(vfbs->master != file_priv->master))
  423. return -EINVAL;
  424. /* Require ScreenObject support for 3D */
  425. if (!dev_priv->sou_priv)
  426. return -EINVAL;
  427. ret = ttm_read_lock(&vmaster->lock, true);
  428. if (unlikely(ret != 0))
  429. return ret;
  430. if (!num_clips) {
  431. num_clips = 1;
  432. clips = &norect;
  433. norect.x1 = norect.y1 = 0;
  434. norect.x2 = framebuffer->width;
  435. norect.y2 = framebuffer->height;
  436. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  437. num_clips /= 2;
  438. inc = 2; /* skip source rects */
  439. }
  440. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  441. flags, color,
  442. clips, num_clips, inc);
  443. ttm_read_unlock(&vmaster->lock);
  444. return 0;
  445. }
  446. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  447. .destroy = vmw_framebuffer_surface_destroy,
  448. .dirty = vmw_framebuffer_surface_dirty,
  449. .create_handle = vmw_framebuffer_create_handle,
  450. };
  451. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  452. struct drm_file *file_priv,
  453. struct vmw_surface *surface,
  454. struct vmw_framebuffer **out,
  455. const struct drm_mode_fb_cmd
  456. *mode_cmd)
  457. {
  458. struct drm_device *dev = dev_priv->dev;
  459. struct vmw_framebuffer_surface *vfbs;
  460. enum SVGA3dSurfaceFormat format;
  461. struct vmw_master *vmaster = vmw_master(file_priv->master);
  462. int ret;
  463. /* 3D is only supported on HWv8 hosts which supports screen objects */
  464. if (!dev_priv->sou_priv)
  465. return -ENOSYS;
  466. /*
  467. * Sanity checks.
  468. */
  469. if (unlikely(surface->mip_levels[0] != 1 ||
  470. surface->num_sizes != 1 ||
  471. surface->sizes[0].width < mode_cmd->width ||
  472. surface->sizes[0].height < mode_cmd->height ||
  473. surface->sizes[0].depth != 1)) {
  474. DRM_ERROR("Incompatible surface dimensions "
  475. "for requested mode.\n");
  476. return -EINVAL;
  477. }
  478. switch (mode_cmd->depth) {
  479. case 32:
  480. format = SVGA3D_A8R8G8B8;
  481. break;
  482. case 24:
  483. format = SVGA3D_X8R8G8B8;
  484. break;
  485. case 16:
  486. format = SVGA3D_R5G6B5;
  487. break;
  488. case 15:
  489. format = SVGA3D_A1R5G5B5;
  490. break;
  491. case 8:
  492. format = SVGA3D_LUMINANCE8;
  493. break;
  494. default:
  495. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  496. return -EINVAL;
  497. }
  498. if (unlikely(format != surface->format)) {
  499. DRM_ERROR("Invalid surface format for requested mode.\n");
  500. return -EINVAL;
  501. }
  502. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  503. if (!vfbs) {
  504. ret = -ENOMEM;
  505. goto out_err1;
  506. }
  507. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  508. &vmw_framebuffer_surface_funcs);
  509. if (ret)
  510. goto out_err2;
  511. if (!vmw_surface_reference(surface)) {
  512. DRM_ERROR("failed to reference surface %p\n", surface);
  513. goto out_err3;
  514. }
  515. /* XXX get the first 3 from the surface info */
  516. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  517. vfbs->base.base.pitch = mode_cmd->pitch;
  518. vfbs->base.base.depth = mode_cmd->depth;
  519. vfbs->base.base.width = mode_cmd->width;
  520. vfbs->base.base.height = mode_cmd->height;
  521. vfbs->surface = surface;
  522. vfbs->base.user_handle = mode_cmd->handle;
  523. vfbs->master = drm_master_get(file_priv->master);
  524. mutex_lock(&vmaster->fb_surf_mutex);
  525. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  526. mutex_unlock(&vmaster->fb_surf_mutex);
  527. *out = &vfbs->base;
  528. return 0;
  529. out_err3:
  530. drm_framebuffer_cleanup(&vfbs->base.base);
  531. out_err2:
  532. kfree(vfbs);
  533. out_err1:
  534. return ret;
  535. }
  536. /*
  537. * Dmabuf framebuffer code
  538. */
  539. #define vmw_framebuffer_to_vfbd(x) \
  540. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  541. struct vmw_framebuffer_dmabuf {
  542. struct vmw_framebuffer base;
  543. struct vmw_dma_buffer *buffer;
  544. };
  545. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  546. {
  547. struct vmw_framebuffer_dmabuf *vfbd =
  548. vmw_framebuffer_to_vfbd(framebuffer);
  549. drm_framebuffer_cleanup(framebuffer);
  550. vmw_dmabuf_unreference(&vfbd->buffer);
  551. ttm_base_object_unref(&vfbd->base.user_obj);
  552. kfree(vfbd);
  553. }
  554. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  555. struct vmw_framebuffer *framebuffer,
  556. unsigned flags, unsigned color,
  557. struct drm_clip_rect *clips,
  558. unsigned num_clips, int increment)
  559. {
  560. size_t fifo_size;
  561. int i;
  562. struct {
  563. uint32_t header;
  564. SVGAFifoCmdUpdate body;
  565. } *cmd;
  566. fifo_size = sizeof(*cmd) * num_clips;
  567. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  568. if (unlikely(cmd == NULL)) {
  569. DRM_ERROR("Fifo reserve failed.\n");
  570. return -ENOMEM;
  571. }
  572. memset(cmd, 0, fifo_size);
  573. for (i = 0; i < num_clips; i++, clips += increment) {
  574. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  575. cmd[i].body.x = cpu_to_le32(clips->x1);
  576. cmd[i].body.y = cpu_to_le32(clips->y1);
  577. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  578. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  579. }
  580. vmw_fifo_commit(dev_priv, fifo_size);
  581. return 0;
  582. }
  583. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  584. struct vmw_private *dev_priv,
  585. struct vmw_framebuffer *framebuffer)
  586. {
  587. int depth = framebuffer->base.depth;
  588. size_t fifo_size;
  589. int ret;
  590. struct {
  591. uint32_t header;
  592. SVGAFifoCmdDefineGMRFB body;
  593. } *cmd;
  594. /* Emulate RGBA support, contrary to svga_reg.h this is not
  595. * supported by hosts. This is only a problem if we are reading
  596. * this value later and expecting what we uploaded back.
  597. */
  598. if (depth == 32)
  599. depth = 24;
  600. fifo_size = sizeof(*cmd);
  601. cmd = kmalloc(fifo_size, GFP_KERNEL);
  602. if (unlikely(cmd == NULL)) {
  603. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  604. return -ENOMEM;
  605. }
  606. memset(cmd, 0, fifo_size);
  607. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  608. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  609. cmd->body.format.colorDepth = depth;
  610. cmd->body.format.reserved = 0;
  611. cmd->body.bytesPerLine = framebuffer->base.pitch;
  612. cmd->body.ptr.gmrId = framebuffer->user_handle;
  613. cmd->body.ptr.offset = 0;
  614. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  615. fifo_size, 0, NULL);
  616. kfree(cmd);
  617. return ret;
  618. }
  619. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  620. struct vmw_private *dev_priv,
  621. struct vmw_framebuffer *framebuffer,
  622. unsigned flags, unsigned color,
  623. struct drm_clip_rect *clips,
  624. unsigned num_clips, int increment)
  625. {
  626. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  627. struct drm_clip_rect *clips_ptr;
  628. int i, k, num_units, ret;
  629. struct drm_crtc *crtc;
  630. size_t fifo_size;
  631. struct {
  632. uint32_t header;
  633. SVGAFifoCmdBlitGMRFBToScreen body;
  634. } *blits;
  635. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  636. if (unlikely(ret != 0))
  637. return ret; /* define_gmrfb prints warnings */
  638. fifo_size = sizeof(*blits) * num_clips;
  639. blits = kmalloc(fifo_size, GFP_KERNEL);
  640. if (unlikely(blits == NULL)) {
  641. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  642. return -ENOMEM;
  643. }
  644. num_units = 0;
  645. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  646. if (crtc->fb != &framebuffer->base)
  647. continue;
  648. units[num_units++] = vmw_crtc_to_du(crtc);
  649. }
  650. for (k = 0; k < num_units; k++) {
  651. struct vmw_display_unit *unit = units[k];
  652. int hit_num = 0;
  653. clips_ptr = clips;
  654. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  655. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  656. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  657. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  658. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  659. /* skip any crtcs that misses the clip region */
  660. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  661. clip_y1 >= unit->crtc.mode.vdisplay ||
  662. clip_x2 <= 0 || clip_y2 <= 0)
  663. continue;
  664. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  665. blits[hit_num].body.destScreenId = unit->unit;
  666. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  667. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  668. blits[hit_num].body.destRect.left = clip_x1;
  669. blits[hit_num].body.destRect.top = clip_y1;
  670. blits[hit_num].body.destRect.right = clip_x2;
  671. blits[hit_num].body.destRect.bottom = clip_y2;
  672. hit_num++;
  673. }
  674. /* no clips hit the crtc */
  675. if (hit_num == 0)
  676. continue;
  677. fifo_size = sizeof(*blits) * hit_num;
  678. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  679. fifo_size, 0, NULL);
  680. if (unlikely(ret != 0))
  681. break;
  682. }
  683. kfree(blits);
  684. return ret;
  685. }
  686. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  687. struct drm_file *file_priv,
  688. unsigned flags, unsigned color,
  689. struct drm_clip_rect *clips,
  690. unsigned num_clips)
  691. {
  692. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  693. struct vmw_master *vmaster = vmw_master(file_priv->master);
  694. struct vmw_framebuffer_dmabuf *vfbd =
  695. vmw_framebuffer_to_vfbd(framebuffer);
  696. struct drm_clip_rect norect;
  697. int ret, increment = 1;
  698. ret = ttm_read_lock(&vmaster->lock, true);
  699. if (unlikely(ret != 0))
  700. return ret;
  701. if (!num_clips) {
  702. num_clips = 1;
  703. clips = &norect;
  704. norect.x1 = norect.y1 = 0;
  705. norect.x2 = framebuffer->width;
  706. norect.y2 = framebuffer->height;
  707. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  708. num_clips /= 2;
  709. increment = 2;
  710. }
  711. if (dev_priv->ldu_priv) {
  712. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  713. flags, color,
  714. clips, num_clips, increment);
  715. } else {
  716. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  717. flags, color,
  718. clips, num_clips, increment);
  719. }
  720. ttm_read_unlock(&vmaster->lock);
  721. return ret;
  722. }
  723. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  724. .destroy = vmw_framebuffer_dmabuf_destroy,
  725. .dirty = vmw_framebuffer_dmabuf_dirty,
  726. .create_handle = vmw_framebuffer_create_handle,
  727. };
  728. /**
  729. * Pin the dmabuffer to the start of vram.
  730. */
  731. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  732. {
  733. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  734. struct vmw_framebuffer_dmabuf *vfbd =
  735. vmw_framebuffer_to_vfbd(&vfb->base);
  736. int ret;
  737. /* This code should not be used with screen objects */
  738. BUG_ON(dev_priv->sou_priv);
  739. vmw_overlay_pause_all(dev_priv);
  740. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  741. vmw_overlay_resume_all(dev_priv);
  742. WARN_ON(ret != 0);
  743. return 0;
  744. }
  745. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  746. {
  747. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  748. struct vmw_framebuffer_dmabuf *vfbd =
  749. vmw_framebuffer_to_vfbd(&vfb->base);
  750. if (!vfbd->buffer) {
  751. WARN_ON(!vfbd->buffer);
  752. return 0;
  753. }
  754. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  755. }
  756. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  757. struct vmw_dma_buffer *dmabuf,
  758. struct vmw_framebuffer **out,
  759. const struct drm_mode_fb_cmd
  760. *mode_cmd)
  761. {
  762. struct drm_device *dev = dev_priv->dev;
  763. struct vmw_framebuffer_dmabuf *vfbd;
  764. unsigned int requested_size;
  765. int ret;
  766. requested_size = mode_cmd->height * mode_cmd->pitch;
  767. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  768. DRM_ERROR("Screen buffer object size is too small "
  769. "for requested mode.\n");
  770. return -EINVAL;
  771. }
  772. /* Limited framebuffer color depth support for screen objects */
  773. if (dev_priv->sou_priv) {
  774. switch (mode_cmd->depth) {
  775. case 32:
  776. case 24:
  777. /* Only support 32 bpp for 32 and 24 depth fbs */
  778. if (mode_cmd->bpp == 32)
  779. break;
  780. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  781. mode_cmd->depth, mode_cmd->bpp);
  782. return -EINVAL;
  783. case 16:
  784. case 15:
  785. /* Only support 16 bpp for 16 and 15 depth fbs */
  786. if (mode_cmd->bpp == 16)
  787. break;
  788. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  789. mode_cmd->depth, mode_cmd->bpp);
  790. return -EINVAL;
  791. default:
  792. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  793. return -EINVAL;
  794. }
  795. }
  796. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  797. if (!vfbd) {
  798. ret = -ENOMEM;
  799. goto out_err1;
  800. }
  801. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  802. &vmw_framebuffer_dmabuf_funcs);
  803. if (ret)
  804. goto out_err2;
  805. if (!vmw_dmabuf_reference(dmabuf)) {
  806. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  807. goto out_err3;
  808. }
  809. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  810. vfbd->base.base.pitch = mode_cmd->pitch;
  811. vfbd->base.base.depth = mode_cmd->depth;
  812. vfbd->base.base.width = mode_cmd->width;
  813. vfbd->base.base.height = mode_cmd->height;
  814. if (!dev_priv->sou_priv) {
  815. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  816. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  817. }
  818. vfbd->base.dmabuf = true;
  819. vfbd->buffer = dmabuf;
  820. vfbd->base.user_handle = mode_cmd->handle;
  821. *out = &vfbd->base;
  822. return 0;
  823. out_err3:
  824. drm_framebuffer_cleanup(&vfbd->base.base);
  825. out_err2:
  826. kfree(vfbd);
  827. out_err1:
  828. return ret;
  829. }
  830. /*
  831. * Generic Kernel modesetting functions
  832. */
  833. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  834. struct drm_file *file_priv,
  835. struct drm_mode_fb_cmd *mode_cmd)
  836. {
  837. struct vmw_private *dev_priv = vmw_priv(dev);
  838. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  839. struct vmw_framebuffer *vfb = NULL;
  840. struct vmw_surface *surface = NULL;
  841. struct vmw_dma_buffer *bo = NULL;
  842. struct ttm_base_object *user_obj;
  843. u64 required_size;
  844. int ret;
  845. /**
  846. * This code should be conditioned on Screen Objects not being used.
  847. * If screen objects are used, we can allocate a GMR to hold the
  848. * requested framebuffer.
  849. */
  850. required_size = mode_cmd->pitch * mode_cmd->height;
  851. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  852. DRM_ERROR("VRAM size is too small for requested mode.\n");
  853. return ERR_PTR(-ENOMEM);
  854. }
  855. /*
  856. * Take a reference on the user object of the resource
  857. * backing the kms fb. This ensures that user-space handle
  858. * lookups on that resource will always work as long as
  859. * it's registered with a kms framebuffer. This is important,
  860. * since vmw_execbuf_process identifies resources in the
  861. * command stream using user-space handles.
  862. */
  863. user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
  864. if (unlikely(user_obj == NULL)) {
  865. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  866. return ERR_PTR(-ENOENT);
  867. }
  868. /**
  869. * End conditioned code.
  870. */
  871. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  872. mode_cmd->handle, &surface);
  873. if (ret)
  874. goto try_dmabuf;
  875. if (!surface->scanout)
  876. goto err_not_scanout;
  877. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  878. &vfb, mode_cmd);
  879. /* vmw_user_surface_lookup takes one ref so does new_fb */
  880. vmw_surface_unreference(&surface);
  881. if (ret) {
  882. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  883. ttm_base_object_unref(&user_obj);
  884. return ERR_PTR(ret);
  885. } else
  886. vfb->user_obj = user_obj;
  887. return &vfb->base;
  888. try_dmabuf:
  889. DRM_INFO("%s: trying buffer\n", __func__);
  890. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
  891. if (ret) {
  892. DRM_ERROR("failed to find buffer: %i\n", ret);
  893. return ERR_PTR(-ENOENT);
  894. }
  895. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  896. mode_cmd);
  897. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  898. vmw_dmabuf_unreference(&bo);
  899. if (ret) {
  900. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  901. ttm_base_object_unref(&user_obj);
  902. return ERR_PTR(ret);
  903. } else
  904. vfb->user_obj = user_obj;
  905. return &vfb->base;
  906. err_not_scanout:
  907. DRM_ERROR("surface not marked as scanout\n");
  908. /* vmw_user_surface_lookup takes one ref */
  909. vmw_surface_unreference(&surface);
  910. ttm_base_object_unref(&user_obj);
  911. return ERR_PTR(-EINVAL);
  912. }
  913. static struct drm_mode_config_funcs vmw_kms_funcs = {
  914. .fb_create = vmw_kms_fb_create,
  915. };
  916. int vmw_kms_present(struct vmw_private *dev_priv,
  917. struct drm_file *file_priv,
  918. struct vmw_framebuffer *vfb,
  919. struct vmw_surface *surface,
  920. uint32_t sid,
  921. int32_t destX, int32_t destY,
  922. struct drm_vmw_rect *clips,
  923. uint32_t num_clips)
  924. {
  925. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  926. struct drm_crtc *crtc;
  927. size_t fifo_size;
  928. int i, k, num_units;
  929. int ret = 0; /* silence warning */
  930. struct {
  931. SVGA3dCmdHeader header;
  932. SVGA3dCmdBlitSurfaceToScreen body;
  933. } *cmd;
  934. SVGASignedRect *blits;
  935. num_units = 0;
  936. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  937. if (crtc->fb != &vfb->base)
  938. continue;
  939. units[num_units++] = vmw_crtc_to_du(crtc);
  940. }
  941. BUG_ON(surface == NULL);
  942. BUG_ON(!clips || !num_clips);
  943. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  944. cmd = kmalloc(fifo_size, GFP_KERNEL);
  945. if (unlikely(cmd == NULL)) {
  946. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  947. return -ENOMEM;
  948. }
  949. /* only need to do this once */
  950. memset(cmd, 0, fifo_size);
  951. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  952. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  953. cmd->body.srcRect.left = 0;
  954. cmd->body.srcRect.right = surface->sizes[0].width;
  955. cmd->body.srcRect.top = 0;
  956. cmd->body.srcRect.bottom = surface->sizes[0].height;
  957. blits = (SVGASignedRect *)&cmd[1];
  958. for (i = 0; i < num_clips; i++) {
  959. blits[i].left = clips[i].x;
  960. blits[i].right = clips[i].x + clips[i].w;
  961. blits[i].top = clips[i].y;
  962. blits[i].bottom = clips[i].y + clips[i].h;
  963. }
  964. for (k = 0; k < num_units; k++) {
  965. struct vmw_display_unit *unit = units[k];
  966. int clip_x1 = destX - unit->crtc.x;
  967. int clip_y1 = destY - unit->crtc.y;
  968. int clip_x2 = clip_x1 + surface->sizes[0].width;
  969. int clip_y2 = clip_y1 + surface->sizes[0].height;
  970. /* skip any crtcs that misses the clip region */
  971. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  972. clip_y1 >= unit->crtc.mode.vdisplay ||
  973. clip_x2 <= 0 || clip_y2 <= 0)
  974. continue;
  975. /* need to reset sid as it is changed by execbuf */
  976. cmd->body.srcImage.sid = sid;
  977. cmd->body.destScreenId = unit->unit;
  978. /*
  979. * The blit command is a lot more resilient then the
  980. * readback command when it comes to clip rects. So its
  981. * okay to go out of bounds.
  982. */
  983. cmd->body.destRect.left = clip_x1;
  984. cmd->body.destRect.right = clip_x2;
  985. cmd->body.destRect.top = clip_y1;
  986. cmd->body.destRect.bottom = clip_y2;
  987. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  988. fifo_size, 0, NULL);
  989. if (unlikely(ret != 0))
  990. break;
  991. }
  992. kfree(cmd);
  993. return ret;
  994. }
  995. int vmw_kms_readback(struct vmw_private *dev_priv,
  996. struct drm_file *file_priv,
  997. struct vmw_framebuffer *vfb,
  998. struct drm_vmw_fence_rep __user *user_fence_rep,
  999. struct drm_vmw_rect *clips,
  1000. uint32_t num_clips)
  1001. {
  1002. struct vmw_framebuffer_dmabuf *vfbd =
  1003. vmw_framebuffer_to_vfbd(&vfb->base);
  1004. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  1005. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  1006. struct drm_crtc *crtc;
  1007. size_t fifo_size;
  1008. int i, k, ret, num_units, blits_pos;
  1009. struct {
  1010. uint32_t header;
  1011. SVGAFifoCmdDefineGMRFB body;
  1012. } *cmd;
  1013. struct {
  1014. uint32_t header;
  1015. SVGAFifoCmdBlitScreenToGMRFB body;
  1016. } *blits;
  1017. num_units = 0;
  1018. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1019. if (crtc->fb != &vfb->base)
  1020. continue;
  1021. units[num_units++] = vmw_crtc_to_du(crtc);
  1022. }
  1023. BUG_ON(dmabuf == NULL);
  1024. BUG_ON(!clips || !num_clips);
  1025. /* take a safe guess at fifo size */
  1026. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1027. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1028. if (unlikely(cmd == NULL)) {
  1029. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1030. return -ENOMEM;
  1031. }
  1032. memset(cmd, 0, fifo_size);
  1033. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1034. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1035. cmd->body.format.colorDepth = vfb->base.depth;
  1036. cmd->body.format.reserved = 0;
  1037. cmd->body.bytesPerLine = vfb->base.pitch;
  1038. cmd->body.ptr.gmrId = vfb->user_handle;
  1039. cmd->body.ptr.offset = 0;
  1040. blits = (void *)&cmd[1];
  1041. blits_pos = 0;
  1042. for (i = 0; i < num_units; i++) {
  1043. struct drm_vmw_rect *c = clips;
  1044. for (k = 0; k < num_clips; k++, c++) {
  1045. /* transform clip coords to crtc origin based coords */
  1046. int clip_x1 = c->x - units[i]->crtc.x;
  1047. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1048. int clip_y1 = c->y - units[i]->crtc.y;
  1049. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1050. int dest_x = c->x;
  1051. int dest_y = c->y;
  1052. /* compensate for clipping, we negate
  1053. * a negative number and add that.
  1054. */
  1055. if (clip_x1 < 0)
  1056. dest_x += -clip_x1;
  1057. if (clip_y1 < 0)
  1058. dest_y += -clip_y1;
  1059. /* clip */
  1060. clip_x1 = max(clip_x1, 0);
  1061. clip_y1 = max(clip_y1, 0);
  1062. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1063. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1064. /* and cull any rects that misses the crtc */
  1065. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1066. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1067. clip_x2 <= 0 || clip_y2 <= 0)
  1068. continue;
  1069. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1070. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1071. blits[blits_pos].body.destOrigin.x = dest_x;
  1072. blits[blits_pos].body.destOrigin.y = dest_y;
  1073. blits[blits_pos].body.srcRect.left = clip_x1;
  1074. blits[blits_pos].body.srcRect.top = clip_y1;
  1075. blits[blits_pos].body.srcRect.right = clip_x2;
  1076. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1077. blits_pos++;
  1078. }
  1079. }
  1080. /* reset size here and use calculated exact size from loops */
  1081. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1082. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1083. 0, user_fence_rep);
  1084. kfree(cmd);
  1085. return ret;
  1086. }
  1087. int vmw_kms_init(struct vmw_private *dev_priv)
  1088. {
  1089. struct drm_device *dev = dev_priv->dev;
  1090. int ret;
  1091. drm_mode_config_init(dev);
  1092. dev->mode_config.funcs = &vmw_kms_funcs;
  1093. dev->mode_config.min_width = 1;
  1094. dev->mode_config.min_height = 1;
  1095. /* assumed largest fb size */
  1096. dev->mode_config.max_width = 8192;
  1097. dev->mode_config.max_height = 8192;
  1098. ret = vmw_kms_init_screen_object_display(dev_priv);
  1099. if (ret) /* Fallback */
  1100. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1101. return 0;
  1102. }
  1103. int vmw_kms_close(struct vmw_private *dev_priv)
  1104. {
  1105. /*
  1106. * Docs says we should take the lock before calling this function
  1107. * but since it destroys encoders and our destructor calls
  1108. * drm_encoder_cleanup which takes the lock we deadlock.
  1109. */
  1110. drm_mode_config_cleanup(dev_priv->dev);
  1111. if (dev_priv->sou_priv)
  1112. vmw_kms_close_screen_object_display(dev_priv);
  1113. else
  1114. vmw_kms_close_legacy_display_system(dev_priv);
  1115. return 0;
  1116. }
  1117. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1118. struct drm_file *file_priv)
  1119. {
  1120. struct drm_vmw_cursor_bypass_arg *arg = data;
  1121. struct vmw_display_unit *du;
  1122. struct drm_mode_object *obj;
  1123. struct drm_crtc *crtc;
  1124. int ret = 0;
  1125. mutex_lock(&dev->mode_config.mutex);
  1126. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1127. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1128. du = vmw_crtc_to_du(crtc);
  1129. du->hotspot_x = arg->xhot;
  1130. du->hotspot_y = arg->yhot;
  1131. }
  1132. mutex_unlock(&dev->mode_config.mutex);
  1133. return 0;
  1134. }
  1135. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1136. if (!obj) {
  1137. ret = -EINVAL;
  1138. goto out;
  1139. }
  1140. crtc = obj_to_crtc(obj);
  1141. du = vmw_crtc_to_du(crtc);
  1142. du->hotspot_x = arg->xhot;
  1143. du->hotspot_y = arg->yhot;
  1144. out:
  1145. mutex_unlock(&dev->mode_config.mutex);
  1146. return ret;
  1147. }
  1148. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1149. unsigned width, unsigned height, unsigned pitch,
  1150. unsigned bpp, unsigned depth)
  1151. {
  1152. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1153. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1154. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1155. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1156. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1157. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1158. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1159. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1160. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1161. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1162. return -EINVAL;
  1163. }
  1164. return 0;
  1165. }
  1166. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1167. {
  1168. struct vmw_vga_topology_state *save;
  1169. uint32_t i;
  1170. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1171. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1172. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1173. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1174. vmw_priv->vga_pitchlock =
  1175. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1176. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1177. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1178. SVGA_FIFO_PITCHLOCK);
  1179. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1180. return 0;
  1181. vmw_priv->num_displays = vmw_read(vmw_priv,
  1182. SVGA_REG_NUM_GUEST_DISPLAYS);
  1183. if (vmw_priv->num_displays == 0)
  1184. vmw_priv->num_displays = 1;
  1185. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1186. save = &vmw_priv->vga_save[i];
  1187. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1188. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1189. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1190. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1191. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1192. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1193. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1194. if (i == 0 && vmw_priv->num_displays == 1 &&
  1195. save->width == 0 && save->height == 0) {
  1196. /*
  1197. * It should be fairly safe to assume that these
  1198. * values are uninitialized.
  1199. */
  1200. save->width = vmw_priv->vga_width - save->pos_x;
  1201. save->height = vmw_priv->vga_height - save->pos_y;
  1202. }
  1203. }
  1204. return 0;
  1205. }
  1206. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1207. {
  1208. struct vmw_vga_topology_state *save;
  1209. uint32_t i;
  1210. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1211. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1212. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1213. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1214. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1215. vmw_priv->vga_pitchlock);
  1216. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1217. iowrite32(vmw_priv->vga_pitchlock,
  1218. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1219. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1220. return 0;
  1221. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1222. save = &vmw_priv->vga_save[i];
  1223. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1224. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1225. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1226. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1227. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1228. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1229. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1230. }
  1231. return 0;
  1232. }
  1233. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1234. uint32_t pitch,
  1235. uint32_t height)
  1236. {
  1237. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1238. }
  1239. /**
  1240. * Function called by DRM code called with vbl_lock held.
  1241. */
  1242. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1243. {
  1244. return 0;
  1245. }
  1246. /**
  1247. * Function called by DRM code called with vbl_lock held.
  1248. */
  1249. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1250. {
  1251. return -ENOSYS;
  1252. }
  1253. /**
  1254. * Function called by DRM code called with vbl_lock held.
  1255. */
  1256. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1257. {
  1258. }
  1259. /*
  1260. * Small shared kms functions.
  1261. */
  1262. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1263. struct drm_vmw_rect *rects)
  1264. {
  1265. struct drm_device *dev = dev_priv->dev;
  1266. struct vmw_display_unit *du;
  1267. struct drm_connector *con;
  1268. mutex_lock(&dev->mode_config.mutex);
  1269. #if 0
  1270. {
  1271. unsigned int i;
  1272. DRM_INFO("%s: new layout ", __func__);
  1273. for (i = 0; i < num; i++)
  1274. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1275. rects[i].w, rects[i].h);
  1276. DRM_INFO("\n");
  1277. }
  1278. #endif
  1279. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1280. du = vmw_connector_to_du(con);
  1281. if (num > du->unit) {
  1282. du->pref_width = rects[du->unit].w;
  1283. du->pref_height = rects[du->unit].h;
  1284. du->pref_active = true;
  1285. du->gui_x = rects[du->unit].x;
  1286. du->gui_y = rects[du->unit].y;
  1287. } else {
  1288. du->pref_width = 800;
  1289. du->pref_height = 600;
  1290. du->pref_active = false;
  1291. }
  1292. con->status = vmw_du_connector_detect(con, true);
  1293. }
  1294. mutex_unlock(&dev->mode_config.mutex);
  1295. return 0;
  1296. }
  1297. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1298. {
  1299. }
  1300. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1301. {
  1302. }
  1303. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1304. u16 *r, u16 *g, u16 *b,
  1305. uint32_t start, uint32_t size)
  1306. {
  1307. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1308. int i;
  1309. for (i = 0; i < size; i++) {
  1310. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1311. r[i], g[i], b[i]);
  1312. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1313. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1314. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1315. }
  1316. }
  1317. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1318. {
  1319. }
  1320. void vmw_du_connector_save(struct drm_connector *connector)
  1321. {
  1322. }
  1323. void vmw_du_connector_restore(struct drm_connector *connector)
  1324. {
  1325. }
  1326. enum drm_connector_status
  1327. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1328. {
  1329. uint32_t num_displays;
  1330. struct drm_device *dev = connector->dev;
  1331. struct vmw_private *dev_priv = vmw_priv(dev);
  1332. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1333. mutex_lock(&dev_priv->hw_mutex);
  1334. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1335. mutex_unlock(&dev_priv->hw_mutex);
  1336. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1337. du->pref_active) ?
  1338. connector_status_connected : connector_status_disconnected);
  1339. }
  1340. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1341. /* 640x480@60Hz */
  1342. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1343. 752, 800, 0, 480, 489, 492, 525, 0,
  1344. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1345. /* 800x600@60Hz */
  1346. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1347. 968, 1056, 0, 600, 601, 605, 628, 0,
  1348. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1349. /* 1024x768@60Hz */
  1350. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1351. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1352. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1353. /* 1152x864@75Hz */
  1354. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1355. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1356. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1357. /* 1280x768@60Hz */
  1358. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1359. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1360. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1361. /* 1280x800@60Hz */
  1362. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1363. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1364. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1365. /* 1280x960@60Hz */
  1366. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1367. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1368. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1369. /* 1280x1024@60Hz */
  1370. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1371. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1372. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1373. /* 1360x768@60Hz */
  1374. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1375. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1376. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1377. /* 1440x1050@60Hz */
  1378. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1379. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1380. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1381. /* 1440x900@60Hz */
  1382. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1383. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1384. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1385. /* 1600x1200@60Hz */
  1386. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1387. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1388. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1389. /* 1680x1050@60Hz */
  1390. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1391. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1392. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1393. /* 1792x1344@60Hz */
  1394. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1395. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1396. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1397. /* 1853x1392@60Hz */
  1398. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1399. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1400. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1401. /* 1920x1200@60Hz */
  1402. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1403. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1404. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1405. /* 1920x1440@60Hz */
  1406. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1407. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1408. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1409. /* 2560x1600@60Hz */
  1410. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1411. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1412. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1413. /* Terminate */
  1414. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1415. };
  1416. /**
  1417. * vmw_guess_mode_timing - Provide fake timings for a
  1418. * 60Hz vrefresh mode.
  1419. *
  1420. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1421. * members filled in.
  1422. */
  1423. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1424. {
  1425. mode->hsync_start = mode->hdisplay + 50;
  1426. mode->hsync_end = mode->hsync_start + 50;
  1427. mode->htotal = mode->hsync_end + 50;
  1428. mode->vsync_start = mode->vdisplay + 50;
  1429. mode->vsync_end = mode->vsync_start + 50;
  1430. mode->vtotal = mode->vsync_end + 50;
  1431. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1432. mode->vrefresh = drm_mode_vrefresh(mode);
  1433. }
  1434. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1435. uint32_t max_width, uint32_t max_height)
  1436. {
  1437. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1438. struct drm_device *dev = connector->dev;
  1439. struct vmw_private *dev_priv = vmw_priv(dev);
  1440. struct drm_display_mode *mode = NULL;
  1441. struct drm_display_mode *bmode;
  1442. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1443. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1444. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1445. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1446. };
  1447. int i;
  1448. /* Add preferred mode */
  1449. {
  1450. mode = drm_mode_duplicate(dev, &prefmode);
  1451. if (!mode)
  1452. return 0;
  1453. mode->hdisplay = du->pref_width;
  1454. mode->vdisplay = du->pref_height;
  1455. vmw_guess_mode_timing(mode);
  1456. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1457. mode->vdisplay)) {
  1458. drm_mode_probed_add(connector, mode);
  1459. } else {
  1460. drm_mode_destroy(dev, mode);
  1461. mode = NULL;
  1462. }
  1463. if (du->pref_mode) {
  1464. list_del_init(&du->pref_mode->head);
  1465. drm_mode_destroy(dev, du->pref_mode);
  1466. }
  1467. /* mode might be null here, this is intended */
  1468. du->pref_mode = mode;
  1469. }
  1470. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1471. bmode = &vmw_kms_connector_builtin[i];
  1472. if (bmode->hdisplay > max_width ||
  1473. bmode->vdisplay > max_height)
  1474. continue;
  1475. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1476. bmode->vdisplay))
  1477. continue;
  1478. mode = drm_mode_duplicate(dev, bmode);
  1479. if (!mode)
  1480. return 0;
  1481. mode->vrefresh = drm_mode_vrefresh(mode);
  1482. drm_mode_probed_add(connector, mode);
  1483. }
  1484. /* Move the prefered mode first, help apps pick the right mode. */
  1485. if (du->pref_mode)
  1486. list_move(&du->pref_mode->head, &connector->probed_modes);
  1487. drm_mode_connector_list_update(connector);
  1488. return 1;
  1489. }
  1490. int vmw_du_connector_set_property(struct drm_connector *connector,
  1491. struct drm_property *property,
  1492. uint64_t val)
  1493. {
  1494. return 0;
  1495. }
  1496. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1497. struct drm_file *file_priv)
  1498. {
  1499. struct vmw_private *dev_priv = vmw_priv(dev);
  1500. struct drm_vmw_update_layout_arg *arg =
  1501. (struct drm_vmw_update_layout_arg *)data;
  1502. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1503. void __user *user_rects;
  1504. struct drm_vmw_rect *rects;
  1505. unsigned rects_size;
  1506. int ret;
  1507. int i;
  1508. struct drm_mode_config *mode_config = &dev->mode_config;
  1509. ret = ttm_read_lock(&vmaster->lock, true);
  1510. if (unlikely(ret != 0))
  1511. return ret;
  1512. if (!arg->num_outputs) {
  1513. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1514. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1515. goto out_unlock;
  1516. }
  1517. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1518. rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect),
  1519. GFP_KERNEL);
  1520. if (unlikely(!rects)) {
  1521. ret = -ENOMEM;
  1522. goto out_unlock;
  1523. }
  1524. user_rects = (void __user *)(unsigned long)arg->rects;
  1525. ret = copy_from_user(rects, user_rects, rects_size);
  1526. if (unlikely(ret != 0)) {
  1527. DRM_ERROR("Failed to get rects.\n");
  1528. ret = -EFAULT;
  1529. goto out_free;
  1530. }
  1531. for (i = 0; i < arg->num_outputs; ++i) {
  1532. if (rects[i].x < 0 ||
  1533. rects[i].y < 0 ||
  1534. rects[i].x + rects[i].w > mode_config->max_width ||
  1535. rects[i].y + rects[i].h > mode_config->max_height) {
  1536. DRM_ERROR("Invalid GUI layout.\n");
  1537. ret = -EINVAL;
  1538. goto out_free;
  1539. }
  1540. }
  1541. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1542. out_free:
  1543. kfree(rects);
  1544. out_unlock:
  1545. ttm_read_unlock(&vmaster->lock);
  1546. return ret;
  1547. }