mach-mxs.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. * Copyright 2012 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/clocksource.h>
  15. #include <linux/can/platform/flexcan.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/gpio.h>
  19. #include <linux/init.h>
  20. #include <linux/irqchip.h>
  21. #include <linux/irqchip/mxs.h>
  22. #include <linux/micrel_phy.h>
  23. #include <linux/mxsfb.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/phy.h>
  26. #include <linux/pinctrl/consumer.h>
  27. #include <asm/mach/arch.h>
  28. #include <asm/mach/time.h>
  29. #include <mach/common.h>
  30. #include <mach/digctl.h>
  31. #include <mach/mxs.h>
  32. static struct fb_videomode mx23evk_video_modes[] = {
  33. {
  34. .name = "Samsung-LMS430HF02",
  35. .refresh = 60,
  36. .xres = 480,
  37. .yres = 272,
  38. .pixclock = 108096, /* picosecond (9.2 MHz) */
  39. .left_margin = 15,
  40. .right_margin = 8,
  41. .upper_margin = 12,
  42. .lower_margin = 4,
  43. .hsync_len = 1,
  44. .vsync_len = 1,
  45. },
  46. };
  47. static struct fb_videomode mx28evk_video_modes[] = {
  48. {
  49. .name = "Seiko-43WVF1G",
  50. .refresh = 60,
  51. .xres = 800,
  52. .yres = 480,
  53. .pixclock = 29851, /* picosecond (33.5 MHz) */
  54. .left_margin = 89,
  55. .right_margin = 164,
  56. .upper_margin = 23,
  57. .lower_margin = 10,
  58. .hsync_len = 10,
  59. .vsync_len = 10,
  60. },
  61. };
  62. static struct fb_videomode m28evk_video_modes[] = {
  63. {
  64. .name = "Ampire AM-800480R2TMQW-T01H",
  65. .refresh = 60,
  66. .xres = 800,
  67. .yres = 480,
  68. .pixclock = 30066, /* picosecond (33.26 MHz) */
  69. .left_margin = 0,
  70. .right_margin = 256,
  71. .upper_margin = 0,
  72. .lower_margin = 45,
  73. .hsync_len = 1,
  74. .vsync_len = 1,
  75. },
  76. };
  77. static struct fb_videomode apx4devkit_video_modes[] = {
  78. {
  79. .name = "HannStar PJ70112A",
  80. .refresh = 60,
  81. .xres = 800,
  82. .yres = 480,
  83. .pixclock = 33333, /* picosecond (30.00 MHz) */
  84. .left_margin = 88,
  85. .right_margin = 40,
  86. .upper_margin = 32,
  87. .lower_margin = 13,
  88. .hsync_len = 48,
  89. .vsync_len = 3,
  90. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  91. },
  92. };
  93. static struct fb_videomode apf28dev_video_modes[] = {
  94. {
  95. .name = "LW700",
  96. .refresh = 60,
  97. .xres = 800,
  98. .yres = 480,
  99. .pixclock = 30303, /* picosecond */
  100. .left_margin = 96,
  101. .right_margin = 96, /* at least 3 & 1 */
  102. .upper_margin = 0x14,
  103. .lower_margin = 0x15,
  104. .hsync_len = 64,
  105. .vsync_len = 4,
  106. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  107. },
  108. };
  109. static struct fb_videomode cfa10049_video_modes[] = {
  110. {
  111. .name = "Himax HX8357-B",
  112. .refresh = 60,
  113. .xres = 320,
  114. .yres = 480,
  115. .pixclock = 108506, /* picosecond (9.216 MHz) */
  116. .left_margin = 2,
  117. .right_margin = 2,
  118. .upper_margin = 2,
  119. .lower_margin = 2,
  120. .hsync_len = 15,
  121. .vsync_len = 15,
  122. },
  123. };
  124. static struct mxsfb_platform_data mxsfb_pdata __initdata;
  125. /*
  126. * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
  127. */
  128. #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
  129. static int flexcan0_en, flexcan1_en;
  130. static void mx28evk_flexcan_switch(void)
  131. {
  132. if (flexcan0_en || flexcan1_en)
  133. gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
  134. else
  135. gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
  136. }
  137. static void mx28evk_flexcan0_switch(int enable)
  138. {
  139. flexcan0_en = enable;
  140. mx28evk_flexcan_switch();
  141. }
  142. static void mx28evk_flexcan1_switch(int enable)
  143. {
  144. flexcan1_en = enable;
  145. mx28evk_flexcan_switch();
  146. }
  147. static struct flexcan_platform_data flexcan_pdata[2];
  148. static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
  149. OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
  150. OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
  151. OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
  152. OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
  153. { /* sentinel */ }
  154. };
  155. static void __init imx23_timer_init(void)
  156. {
  157. mx23_clocks_init();
  158. clocksource_of_init();
  159. }
  160. static void __init imx28_timer_init(void)
  161. {
  162. mx28_clocks_init();
  163. clocksource_of_init();
  164. }
  165. enum mac_oui {
  166. OUI_FSL,
  167. OUI_DENX,
  168. OUI_CRYSTALFONTZ,
  169. };
  170. static void __init update_fec_mac_prop(enum mac_oui oui)
  171. {
  172. struct device_node *np, *from = NULL;
  173. struct property *newmac;
  174. const u32 *ocotp = mxs_get_ocotp();
  175. u8 *macaddr;
  176. u32 val;
  177. int i;
  178. for (i = 0; i < 2; i++) {
  179. np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
  180. if (!np)
  181. return;
  182. from = np;
  183. if (of_get_property(np, "local-mac-address", NULL))
  184. continue;
  185. newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
  186. if (!newmac)
  187. return;
  188. newmac->value = newmac + 1;
  189. newmac->length = 6;
  190. newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
  191. if (!newmac->name) {
  192. kfree(newmac);
  193. return;
  194. }
  195. /*
  196. * OCOTP only stores the last 4 octets for each mac address,
  197. * so hard-code OUI here.
  198. */
  199. macaddr = newmac->value;
  200. switch (oui) {
  201. case OUI_FSL:
  202. macaddr[0] = 0x00;
  203. macaddr[1] = 0x04;
  204. macaddr[2] = 0x9f;
  205. break;
  206. case OUI_DENX:
  207. macaddr[0] = 0xc0;
  208. macaddr[1] = 0xe5;
  209. macaddr[2] = 0x4e;
  210. break;
  211. case OUI_CRYSTALFONTZ:
  212. macaddr[0] = 0x58;
  213. macaddr[1] = 0xb9;
  214. macaddr[2] = 0xe1;
  215. break;
  216. }
  217. val = ocotp[i];
  218. macaddr[3] = (val >> 16) & 0xff;
  219. macaddr[4] = (val >> 8) & 0xff;
  220. macaddr[5] = (val >> 0) & 0xff;
  221. of_update_property(np, newmac);
  222. }
  223. }
  224. static void __init imx23_evk_init(void)
  225. {
  226. mxsfb_pdata.mode_list = mx23evk_video_modes;
  227. mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
  228. mxsfb_pdata.default_bpp = 32;
  229. mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
  230. mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
  231. MXSFB_SYNC_DOTCLK_FAILING_ACT;
  232. }
  233. static inline void enable_clk_enet_out(void)
  234. {
  235. struct clk *clk = clk_get_sys("enet_out", NULL);
  236. if (!IS_ERR(clk))
  237. clk_prepare_enable(clk);
  238. }
  239. static void __init imx28_evk_init(void)
  240. {
  241. enable_clk_enet_out();
  242. update_fec_mac_prop(OUI_FSL);
  243. mxsfb_pdata.mode_list = mx28evk_video_modes;
  244. mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
  245. mxsfb_pdata.default_bpp = 32;
  246. mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
  247. mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
  248. MXSFB_SYNC_DOTCLK_FAILING_ACT;
  249. mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
  250. }
  251. static void __init imx28_evk_post_init(void)
  252. {
  253. if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
  254. "flexcan-switch")) {
  255. flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
  256. flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
  257. }
  258. }
  259. static void __init m28evk_init(void)
  260. {
  261. mxsfb_pdata.mode_list = m28evk_video_modes;
  262. mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
  263. mxsfb_pdata.default_bpp = 16;
  264. mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
  265. mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
  266. }
  267. static void __init sc_sps1_init(void)
  268. {
  269. enable_clk_enet_out();
  270. }
  271. static int apx4devkit_phy_fixup(struct phy_device *phy)
  272. {
  273. phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
  274. return 0;
  275. }
  276. static void __init apx4devkit_init(void)
  277. {
  278. enable_clk_enet_out();
  279. if (IS_BUILTIN(CONFIG_PHYLIB))
  280. phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
  281. apx4devkit_phy_fixup);
  282. mxsfb_pdata.mode_list = apx4devkit_video_modes;
  283. mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
  284. mxsfb_pdata.default_bpp = 32;
  285. mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
  286. mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
  287. MXSFB_SYNC_DOTCLK_FAILING_ACT;
  288. }
  289. #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
  290. #define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1)
  291. #define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2)
  292. #define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3)
  293. #define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4)
  294. #define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6)
  295. #define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7)
  296. #define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8)
  297. #define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16)
  298. #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
  299. #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
  300. #define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
  301. static const struct gpio tx28_gpios[] __initconst = {
  302. { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
  303. { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
  304. { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
  305. { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
  306. { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
  307. { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
  308. { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
  309. { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
  310. { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
  311. { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
  312. { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
  313. { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
  314. };
  315. static void __init tx28_post_init(void)
  316. {
  317. struct device_node *np;
  318. struct platform_device *pdev;
  319. struct pinctrl *pctl;
  320. int ret;
  321. enable_clk_enet_out();
  322. np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
  323. pdev = of_find_device_by_node(np);
  324. if (!pdev) {
  325. pr_err("%s: failed to find fec device\n", __func__);
  326. return;
  327. }
  328. pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
  329. if (IS_ERR(pctl)) {
  330. pr_err("%s: failed to get pinctrl state\n", __func__);
  331. return;
  332. }
  333. ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
  334. if (ret) {
  335. pr_err("%s: failed to request gpios: %d\n", __func__, ret);
  336. return;
  337. }
  338. /* Power up fec phy */
  339. gpio_set_value(TX28_FEC_PHY_POWER, 1);
  340. msleep(26); /* 25ms according to data sheet */
  341. /* Mode strap pins */
  342. gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
  343. gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
  344. gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
  345. udelay(100); /* minimum assertion time for nRST */
  346. /* Deasserting FEC PHY RESET */
  347. gpio_set_value(TX28_FEC_PHY_RESET, 1);
  348. pinctrl_put(pctl);
  349. }
  350. static void __init cfa10049_init(void)
  351. {
  352. enable_clk_enet_out();
  353. update_fec_mac_prop(OUI_CRYSTALFONTZ);
  354. mxsfb_pdata.mode_list = cfa10049_video_modes;
  355. mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
  356. mxsfb_pdata.default_bpp = 32;
  357. mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
  358. mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
  359. }
  360. static void __init cfa10037_init(void)
  361. {
  362. enable_clk_enet_out();
  363. update_fec_mac_prop(OUI_CRYSTALFONTZ);
  364. }
  365. static void __init apf28_init(void)
  366. {
  367. enable_clk_enet_out();
  368. mxsfb_pdata.mode_list = apf28dev_video_modes;
  369. mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
  370. mxsfb_pdata.default_bpp = 16;
  371. mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
  372. mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
  373. MXSFB_SYNC_DOTCLK_FAILING_ACT;
  374. }
  375. static void __init mxs_machine_init(void)
  376. {
  377. if (of_machine_is_compatible("fsl,imx28-evk"))
  378. imx28_evk_init();
  379. else if (of_machine_is_compatible("fsl,imx23-evk"))
  380. imx23_evk_init();
  381. else if (of_machine_is_compatible("denx,m28evk"))
  382. m28evk_init();
  383. else if (of_machine_is_compatible("bluegiga,apx4devkit"))
  384. apx4devkit_init();
  385. else if (of_machine_is_compatible("crystalfontz,cfa10037"))
  386. cfa10037_init();
  387. else if (of_machine_is_compatible("crystalfontz,cfa10049"))
  388. cfa10049_init();
  389. else if (of_machine_is_compatible("armadeus,imx28-apf28"))
  390. apf28_init();
  391. else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
  392. sc_sps1_init();
  393. of_platform_populate(NULL, of_default_bus_match_table,
  394. mxs_auxdata_lookup, NULL);
  395. if (of_machine_is_compatible("karo,tx28"))
  396. tx28_post_init();
  397. if (of_machine_is_compatible("fsl,imx28-evk"))
  398. imx28_evk_post_init();
  399. }
  400. static const char *imx23_dt_compat[] __initdata = {
  401. "fsl,imx23",
  402. NULL,
  403. };
  404. static const char *imx28_dt_compat[] __initdata = {
  405. "fsl,imx28",
  406. NULL,
  407. };
  408. DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
  409. .map_io = mx23_map_io,
  410. .init_irq = irqchip_init,
  411. .handle_irq = icoll_handle_irq,
  412. .init_time = imx23_timer_init,
  413. .init_machine = mxs_machine_init,
  414. .dt_compat = imx23_dt_compat,
  415. .restart = mxs_restart,
  416. MACHINE_END
  417. DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
  418. .map_io = mx28_map_io,
  419. .init_irq = irqchip_init,
  420. .handle_irq = icoll_handle_irq,
  421. .init_time = imx28_timer_init,
  422. .init_machine = mxs_machine_init,
  423. .dt_compat = imx28_dt_compat,
  424. .restart = mxs_restart,
  425. MACHINE_END