netxen_nic_init.c 42 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include "netxen_nic.h"
  28. #include "netxen_nic_hw.h"
  29. struct crb_addr_pair {
  30. u32 addr;
  31. u32 data;
  32. };
  33. #define NETXEN_MAX_CRB_XFORM 60
  34. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  35. #define NETXEN_ADDR_ERROR (0xffffffff)
  36. #define crb_addr_transform(name) \
  37. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  38. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  39. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  40. static void
  41. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  42. struct nx_host_rds_ring *rds_ring);
  43. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  44. static void crb_addr_transform_setup(void)
  45. {
  46. crb_addr_transform(XDMA);
  47. crb_addr_transform(TIMR);
  48. crb_addr_transform(SRE);
  49. crb_addr_transform(SQN3);
  50. crb_addr_transform(SQN2);
  51. crb_addr_transform(SQN1);
  52. crb_addr_transform(SQN0);
  53. crb_addr_transform(SQS3);
  54. crb_addr_transform(SQS2);
  55. crb_addr_transform(SQS1);
  56. crb_addr_transform(SQS0);
  57. crb_addr_transform(RPMX7);
  58. crb_addr_transform(RPMX6);
  59. crb_addr_transform(RPMX5);
  60. crb_addr_transform(RPMX4);
  61. crb_addr_transform(RPMX3);
  62. crb_addr_transform(RPMX2);
  63. crb_addr_transform(RPMX1);
  64. crb_addr_transform(RPMX0);
  65. crb_addr_transform(ROMUSB);
  66. crb_addr_transform(SN);
  67. crb_addr_transform(QMN);
  68. crb_addr_transform(QMS);
  69. crb_addr_transform(PGNI);
  70. crb_addr_transform(PGND);
  71. crb_addr_transform(PGN3);
  72. crb_addr_transform(PGN2);
  73. crb_addr_transform(PGN1);
  74. crb_addr_transform(PGN0);
  75. crb_addr_transform(PGSI);
  76. crb_addr_transform(PGSD);
  77. crb_addr_transform(PGS3);
  78. crb_addr_transform(PGS2);
  79. crb_addr_transform(PGS1);
  80. crb_addr_transform(PGS0);
  81. crb_addr_transform(PS);
  82. crb_addr_transform(PH);
  83. crb_addr_transform(NIU);
  84. crb_addr_transform(I2Q);
  85. crb_addr_transform(EG);
  86. crb_addr_transform(MN);
  87. crb_addr_transform(MS);
  88. crb_addr_transform(CAS2);
  89. crb_addr_transform(CAS1);
  90. crb_addr_transform(CAS0);
  91. crb_addr_transform(CAM);
  92. crb_addr_transform(C2C1);
  93. crb_addr_transform(C2C0);
  94. crb_addr_transform(SMB);
  95. crb_addr_transform(OCM0);
  96. crb_addr_transform(I2C0);
  97. }
  98. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  99. {
  100. struct netxen_recv_context *recv_ctx;
  101. struct nx_host_rds_ring *rds_ring;
  102. struct netxen_rx_buffer *rx_buf;
  103. int i, ring;
  104. recv_ctx = &adapter->recv_ctx;
  105. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  106. rds_ring = &recv_ctx->rds_rings[ring];
  107. for (i = 0; i < rds_ring->num_desc; ++i) {
  108. rx_buf = &(rds_ring->rx_buf_arr[i]);
  109. if (rx_buf->state == NETXEN_BUFFER_FREE)
  110. continue;
  111. pci_unmap_single(adapter->pdev,
  112. rx_buf->dma,
  113. rds_ring->dma_size,
  114. PCI_DMA_FROMDEVICE);
  115. if (rx_buf->skb != NULL)
  116. dev_kfree_skb_any(rx_buf->skb);
  117. }
  118. }
  119. }
  120. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  121. {
  122. struct netxen_cmd_buffer *cmd_buf;
  123. struct netxen_skb_frag *buffrag;
  124. int i, j;
  125. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  126. cmd_buf = tx_ring->cmd_buf_arr;
  127. for (i = 0; i < tx_ring->num_desc; i++) {
  128. buffrag = cmd_buf->frag_array;
  129. if (buffrag->dma) {
  130. pci_unmap_single(adapter->pdev, buffrag->dma,
  131. buffrag->length, PCI_DMA_TODEVICE);
  132. buffrag->dma = 0ULL;
  133. }
  134. for (j = 0; j < cmd_buf->frag_count; j++) {
  135. buffrag++;
  136. if (buffrag->dma) {
  137. pci_unmap_page(adapter->pdev, buffrag->dma,
  138. buffrag->length,
  139. PCI_DMA_TODEVICE);
  140. buffrag->dma = 0ULL;
  141. }
  142. }
  143. if (cmd_buf->skb) {
  144. dev_kfree_skb_any(cmd_buf->skb);
  145. cmd_buf->skb = NULL;
  146. }
  147. cmd_buf++;
  148. }
  149. }
  150. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  151. {
  152. struct netxen_recv_context *recv_ctx;
  153. struct nx_host_rds_ring *rds_ring;
  154. struct nx_host_tx_ring *tx_ring;
  155. int ring;
  156. recv_ctx = &adapter->recv_ctx;
  157. if (recv_ctx->rds_rings == NULL)
  158. goto skip_rds;
  159. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  160. rds_ring = &recv_ctx->rds_rings[ring];
  161. vfree(rds_ring->rx_buf_arr);
  162. rds_ring->rx_buf_arr = NULL;
  163. }
  164. kfree(recv_ctx->rds_rings);
  165. skip_rds:
  166. if (adapter->tx_ring == NULL)
  167. return;
  168. tx_ring = adapter->tx_ring;
  169. vfree(tx_ring->cmd_buf_arr);
  170. }
  171. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  172. {
  173. struct netxen_recv_context *recv_ctx;
  174. struct nx_host_rds_ring *rds_ring;
  175. struct nx_host_sds_ring *sds_ring;
  176. struct nx_host_tx_ring *tx_ring;
  177. struct netxen_rx_buffer *rx_buf;
  178. int ring, i, size;
  179. struct netxen_cmd_buffer *cmd_buf_arr;
  180. struct net_device *netdev = adapter->netdev;
  181. struct pci_dev *pdev = adapter->pdev;
  182. size = sizeof(struct nx_host_tx_ring);
  183. tx_ring = kzalloc(size, GFP_KERNEL);
  184. if (tx_ring == NULL) {
  185. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  186. netdev->name);
  187. return -ENOMEM;
  188. }
  189. adapter->tx_ring = tx_ring;
  190. tx_ring->num_desc = adapter->num_txd;
  191. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  192. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  193. if (cmd_buf_arr == NULL) {
  194. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  195. netdev->name);
  196. return -ENOMEM;
  197. }
  198. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  199. tx_ring->cmd_buf_arr = cmd_buf_arr;
  200. recv_ctx = &adapter->recv_ctx;
  201. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  202. rds_ring = kzalloc(size, GFP_KERNEL);
  203. if (rds_ring == NULL) {
  204. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  205. netdev->name);
  206. return -ENOMEM;
  207. }
  208. recv_ctx->rds_rings = rds_ring;
  209. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  210. rds_ring = &recv_ctx->rds_rings[ring];
  211. switch (ring) {
  212. case RCV_RING_NORMAL:
  213. rds_ring->num_desc = adapter->num_rxd;
  214. if (adapter->ahw.cut_through) {
  215. rds_ring->dma_size =
  216. NX_CT_DEFAULT_RX_BUF_LEN;
  217. rds_ring->skb_size =
  218. NX_CT_DEFAULT_RX_BUF_LEN;
  219. } else {
  220. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  221. rds_ring->dma_size =
  222. NX_P3_RX_BUF_MAX_LEN;
  223. else
  224. rds_ring->dma_size =
  225. NX_P2_RX_BUF_MAX_LEN;
  226. rds_ring->skb_size =
  227. rds_ring->dma_size + NET_IP_ALIGN;
  228. }
  229. break;
  230. case RCV_RING_JUMBO:
  231. rds_ring->num_desc = adapter->num_jumbo_rxd;
  232. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  233. rds_ring->dma_size =
  234. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  235. else
  236. rds_ring->dma_size =
  237. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  238. if (adapter->capabilities & NX_CAP0_HW_LRO)
  239. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  240. rds_ring->skb_size =
  241. rds_ring->dma_size + NET_IP_ALIGN;
  242. break;
  243. case RCV_RING_LRO:
  244. rds_ring->num_desc = adapter->num_lro_rxd;
  245. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  246. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  247. break;
  248. }
  249. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  250. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  251. if (rds_ring->rx_buf_arr == NULL) {
  252. printk(KERN_ERR "%s: Failed to allocate "
  253. "rx buffer ring %d\n",
  254. netdev->name, ring);
  255. /* free whatever was already allocated */
  256. goto err_out;
  257. }
  258. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  259. INIT_LIST_HEAD(&rds_ring->free_list);
  260. /*
  261. * Now go through all of them, set reference handles
  262. * and put them in the queues.
  263. */
  264. rx_buf = rds_ring->rx_buf_arr;
  265. for (i = 0; i < rds_ring->num_desc; i++) {
  266. list_add_tail(&rx_buf->list,
  267. &rds_ring->free_list);
  268. rx_buf->ref_handle = i;
  269. rx_buf->state = NETXEN_BUFFER_FREE;
  270. rx_buf++;
  271. }
  272. spin_lock_init(&rds_ring->lock);
  273. }
  274. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  275. sds_ring = &recv_ctx->sds_rings[ring];
  276. sds_ring->irq = adapter->msix_entries[ring].vector;
  277. sds_ring->adapter = adapter;
  278. sds_ring->num_desc = adapter->num_rxd;
  279. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  280. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  281. }
  282. return 0;
  283. err_out:
  284. netxen_free_sw_resources(adapter);
  285. return -ENOMEM;
  286. }
  287. /*
  288. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  289. * address to external PCI CRB address.
  290. */
  291. static u32 netxen_decode_crb_addr(u32 addr)
  292. {
  293. int i;
  294. u32 base_addr, offset, pci_base;
  295. crb_addr_transform_setup();
  296. pci_base = NETXEN_ADDR_ERROR;
  297. base_addr = addr & 0xfff00000;
  298. offset = addr & 0x000fffff;
  299. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  300. if (crb_addr_xform[i] == base_addr) {
  301. pci_base = i << 20;
  302. break;
  303. }
  304. }
  305. if (pci_base == NETXEN_ADDR_ERROR)
  306. return pci_base;
  307. else
  308. return (pci_base + offset);
  309. }
  310. #define NETXEN_MAX_ROM_WAIT_USEC 100
  311. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  312. {
  313. long timeout = 0;
  314. long done = 0;
  315. cond_resched();
  316. while (done == 0) {
  317. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  318. done &= 2;
  319. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  320. dev_err(&adapter->pdev->dev,
  321. "Timeout reached waiting for rom done");
  322. return -EIO;
  323. }
  324. udelay(1);
  325. }
  326. return 0;
  327. }
  328. static int do_rom_fast_read(struct netxen_adapter *adapter,
  329. int addr, int *valp)
  330. {
  331. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  332. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  335. if (netxen_wait_rom_done(adapter)) {
  336. printk("Error waiting for rom done\n");
  337. return -EIO;
  338. }
  339. /* reset abyte_cnt and dummy_byte_cnt */
  340. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  341. udelay(10);
  342. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  343. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  344. return 0;
  345. }
  346. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  347. u8 *bytes, size_t size)
  348. {
  349. int addridx;
  350. int ret = 0;
  351. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  352. int v;
  353. ret = do_rom_fast_read(adapter, addridx, &v);
  354. if (ret != 0)
  355. break;
  356. *(__le32 *)bytes = cpu_to_le32(v);
  357. bytes += 4;
  358. }
  359. return ret;
  360. }
  361. int
  362. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  363. u8 *bytes, size_t size)
  364. {
  365. int ret;
  366. ret = netxen_rom_lock(adapter);
  367. if (ret < 0)
  368. return ret;
  369. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  370. netxen_rom_unlock(adapter);
  371. return ret;
  372. }
  373. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  374. {
  375. int ret;
  376. if (netxen_rom_lock(adapter) != 0)
  377. return -EIO;
  378. ret = do_rom_fast_read(adapter, addr, valp);
  379. netxen_rom_unlock(adapter);
  380. return ret;
  381. }
  382. #define NETXEN_BOARDTYPE 0x4008
  383. #define NETXEN_BOARDNUM 0x400c
  384. #define NETXEN_CHIPNUM 0x4010
  385. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  386. {
  387. int addr, val;
  388. int i, n, init_delay = 0;
  389. struct crb_addr_pair *buf;
  390. unsigned offset;
  391. u32 off;
  392. /* resetall */
  393. netxen_rom_lock(adapter);
  394. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  395. netxen_rom_unlock(adapter);
  396. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  397. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  398. (n != 0xcafecafe) ||
  399. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  400. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  401. "n: %08x\n", netxen_nic_driver_name, n);
  402. return -EIO;
  403. }
  404. offset = n & 0xffffU;
  405. n = (n >> 16) & 0xffffU;
  406. } else {
  407. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  408. !(n & 0x80000000)) {
  409. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  410. "n: %08x\n", netxen_nic_driver_name, n);
  411. return -EIO;
  412. }
  413. offset = 1;
  414. n &= ~0x80000000;
  415. }
  416. if (n >= 1024) {
  417. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  418. " initialized.\n", __func__, n);
  419. return -EIO;
  420. }
  421. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  422. if (buf == NULL) {
  423. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  424. netxen_nic_driver_name);
  425. return -ENOMEM;
  426. }
  427. for (i = 0; i < n; i++) {
  428. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  429. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  430. kfree(buf);
  431. return -EIO;
  432. }
  433. buf[i].addr = addr;
  434. buf[i].data = val;
  435. }
  436. for (i = 0; i < n; i++) {
  437. off = netxen_decode_crb_addr(buf[i].addr);
  438. if (off == NETXEN_ADDR_ERROR) {
  439. printk(KERN_ERR"CRB init value out of range %x\n",
  440. buf[i].addr);
  441. continue;
  442. }
  443. off += NETXEN_PCI_CRBSPACE;
  444. if (off & 1)
  445. continue;
  446. /* skipping cold reboot MAGIC */
  447. if (off == NETXEN_CAM_RAM(0x1fc))
  448. continue;
  449. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  450. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  451. continue;
  452. /* do not reset PCI */
  453. if (off == (ROMUSB_GLB + 0xbc))
  454. continue;
  455. if (off == (ROMUSB_GLB + 0xa8))
  456. continue;
  457. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  458. continue;
  459. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  460. continue;
  461. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  462. continue;
  463. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  464. continue;
  465. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  466. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  467. buf[i].data = 0x1020;
  468. /* skip the function enable register */
  469. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  470. continue;
  471. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  472. continue;
  473. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  474. continue;
  475. }
  476. init_delay = 1;
  477. /* After writing this register, HW needs time for CRB */
  478. /* to quiet down (else crb_window returns 0xffffffff) */
  479. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  480. init_delay = 1000;
  481. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  482. /* hold xdma in reset also */
  483. buf[i].data = NETXEN_NIC_XDMA_RESET;
  484. buf[i].data = 0x8000ff;
  485. }
  486. }
  487. NXWR32(adapter, off, buf[i].data);
  488. msleep(init_delay);
  489. }
  490. kfree(buf);
  491. /* disable_peg_cache_all */
  492. /* unreset_net_cache */
  493. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  494. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  495. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  496. }
  497. /* p2dn replyCount */
  498. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  499. /* disable_peg_cache 0 */
  500. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  501. /* disable_peg_cache 1 */
  502. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  503. /* peg_clr_all */
  504. /* peg_clr 0 */
  505. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  506. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  507. /* peg_clr 1 */
  508. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  510. /* peg_clr 2 */
  511. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  512. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  513. /* peg_clr 3 */
  514. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  515. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  516. return 0;
  517. }
  518. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  519. {
  520. uint32_t i;
  521. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  522. __le32 entries = cpu_to_le32(directory->num_entries);
  523. for (i = 0; i < entries; i++) {
  524. __le32 offs = cpu_to_le32(directory->findex) +
  525. (i * cpu_to_le32(directory->entry_size));
  526. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  527. if (tab_type == section)
  528. return (struct uni_table_desc *) &unirom[offs];
  529. }
  530. return NULL;
  531. }
  532. static int
  533. nx_set_product_offs(struct netxen_adapter *adapter)
  534. {
  535. struct uni_table_desc *ptab_descr;
  536. const u8 *unirom = adapter->fw->data;
  537. uint32_t i;
  538. __le32 entries;
  539. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  540. 1 : netxen_p3_has_mn(adapter);
  541. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  542. if (ptab_descr == NULL)
  543. return -1;
  544. entries = cpu_to_le32(ptab_descr->num_entries);
  545. nomn:
  546. for (i = 0; i < entries; i++) {
  547. __le32 flags, file_chiprev, offs;
  548. u8 chiprev = adapter->ahw.revision_id;
  549. uint32_t flagbit;
  550. offs = cpu_to_le32(ptab_descr->findex) +
  551. (i * cpu_to_le32(ptab_descr->entry_size));
  552. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  553. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  554. NX_UNI_CHIP_REV_OFF));
  555. flagbit = mn_present ? 1 : 2;
  556. if ((chiprev == file_chiprev) &&
  557. ((1ULL << flagbit) & flags)) {
  558. adapter->file_prd_off = offs;
  559. return 0;
  560. }
  561. }
  562. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  563. mn_present = 0;
  564. goto nomn;
  565. }
  566. return -1;
  567. }
  568. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  569. u32 section, u32 idx_offset)
  570. {
  571. const u8 *unirom = adapter->fw->data;
  572. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  573. idx_offset));
  574. struct uni_table_desc *tab_desc;
  575. __le32 offs;
  576. tab_desc = nx_get_table_desc(unirom, section);
  577. if (tab_desc == NULL)
  578. return NULL;
  579. offs = cpu_to_le32(tab_desc->findex) +
  580. (cpu_to_le32(tab_desc->entry_size) * idx);
  581. return (struct uni_data_desc *)&unirom[offs];
  582. }
  583. static u8 *
  584. nx_get_bootld_offs(struct netxen_adapter *adapter)
  585. {
  586. u32 offs = NETXEN_BOOTLD_START;
  587. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  588. offs = cpu_to_le32((nx_get_data_desc(adapter,
  589. NX_UNI_DIR_SECT_BOOTLD,
  590. NX_UNI_BOOTLD_IDX_OFF))->findex);
  591. return (u8 *)&adapter->fw->data[offs];
  592. }
  593. static u8 *
  594. nx_get_fw_offs(struct netxen_adapter *adapter)
  595. {
  596. u32 offs = NETXEN_IMAGE_START;
  597. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  598. offs = cpu_to_le32((nx_get_data_desc(adapter,
  599. NX_UNI_DIR_SECT_FW,
  600. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  601. return (u8 *)&adapter->fw->data[offs];
  602. }
  603. static __le32
  604. nx_get_fw_size(struct netxen_adapter *adapter)
  605. {
  606. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  607. return cpu_to_le32((nx_get_data_desc(adapter,
  608. NX_UNI_DIR_SECT_FW,
  609. NX_UNI_FIRMWARE_IDX_OFF))->size);
  610. else
  611. return cpu_to_le32(
  612. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  613. }
  614. static __le32
  615. nx_get_fw_version(struct netxen_adapter *adapter)
  616. {
  617. struct uni_data_desc *fw_data_desc;
  618. const struct firmware *fw = adapter->fw;
  619. __le32 major, minor, sub;
  620. const u8 *ver_str;
  621. int i, ret = 0;
  622. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  623. fw_data_desc = nx_get_data_desc(adapter,
  624. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  625. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  626. cpu_to_le32(fw_data_desc->size) - 17;
  627. for (i = 0; i < 12; i++) {
  628. if (!strncmp(&ver_str[i], "REV=", 4)) {
  629. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  630. &major, &minor, &sub);
  631. break;
  632. }
  633. }
  634. if (ret != 3)
  635. return 0;
  636. return major + (minor << 8) + (sub << 16);
  637. } else
  638. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  639. }
  640. static __le32
  641. nx_get_bios_version(struct netxen_adapter *adapter)
  642. {
  643. const struct firmware *fw = adapter->fw;
  644. __le32 bios_ver, prd_off = adapter->file_prd_off;
  645. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  646. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  647. + NX_UNI_BIOS_VERSION_OFF));
  648. return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) +
  649. (bios_ver >> 24);
  650. } else
  651. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  652. }
  653. int
  654. netxen_need_fw_reset(struct netxen_adapter *adapter)
  655. {
  656. u32 count, old_count;
  657. u32 val, version, major, minor, build;
  658. int i, timeout;
  659. u8 fw_type;
  660. /* NX2031 firmware doesn't support heartbit */
  661. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  662. return 1;
  663. if (adapter->need_fw_reset)
  664. return 1;
  665. /* last attempt had failed */
  666. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  667. return 1;
  668. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  669. for (i = 0; i < 10; i++) {
  670. timeout = msleep_interruptible(200);
  671. if (timeout) {
  672. NXWR32(adapter, CRB_CMDPEG_STATE,
  673. PHAN_INITIALIZE_FAILED);
  674. return -EINTR;
  675. }
  676. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  677. if (count != old_count)
  678. break;
  679. }
  680. /* firmware is dead */
  681. if (count == old_count)
  682. return 1;
  683. /* check if we have got newer or different file firmware */
  684. if (adapter->fw) {
  685. val = nx_get_fw_version(adapter);
  686. version = NETXEN_DECODE_VERSION(val);
  687. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  688. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  689. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  690. if (version > NETXEN_VERSION_CODE(major, minor, build))
  691. return 1;
  692. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  693. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  694. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  695. fw_type = (val & 0x4) ?
  696. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  697. if (adapter->fw_type != fw_type)
  698. return 1;
  699. }
  700. }
  701. return 0;
  702. }
  703. static char *fw_name[] = {
  704. NX_P2_MN_ROMIMAGE_NAME,
  705. NX_P3_CT_ROMIMAGE_NAME,
  706. NX_P3_MN_ROMIMAGE_NAME,
  707. NX_UNIFIED_ROMIMAGE_NAME,
  708. NX_FLASH_ROMIMAGE_NAME,
  709. };
  710. int
  711. netxen_load_firmware(struct netxen_adapter *adapter)
  712. {
  713. u64 *ptr64;
  714. u32 i, flashaddr, size;
  715. const struct firmware *fw = adapter->fw;
  716. struct pci_dev *pdev = adapter->pdev;
  717. dev_info(&pdev->dev, "loading firmware from %s\n",
  718. fw_name[adapter->fw_type]);
  719. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  720. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  721. if (fw) {
  722. __le64 data;
  723. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  724. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  725. flashaddr = NETXEN_BOOTLD_START;
  726. for (i = 0; i < size; i++) {
  727. data = cpu_to_le64(ptr64[i]);
  728. if (adapter->pci_mem_write(adapter, flashaddr, data))
  729. return -EIO;
  730. flashaddr += 8;
  731. }
  732. size = (__force u32)nx_get_fw_size(adapter) / 8;
  733. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  734. flashaddr = NETXEN_IMAGE_START;
  735. for (i = 0; i < size; i++) {
  736. data = cpu_to_le64(ptr64[i]);
  737. if (adapter->pci_mem_write(adapter,
  738. flashaddr, data))
  739. return -EIO;
  740. flashaddr += 8;
  741. }
  742. } else {
  743. u64 data;
  744. u32 hi, lo;
  745. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  746. flashaddr = NETXEN_BOOTLD_START;
  747. for (i = 0; i < size; i++) {
  748. if (netxen_rom_fast_read(adapter,
  749. flashaddr, (int *)&lo) != 0)
  750. return -EIO;
  751. if (netxen_rom_fast_read(adapter,
  752. flashaddr + 4, (int *)&hi) != 0)
  753. return -EIO;
  754. /* hi, lo are already in host endian byteorder */
  755. data = (((u64)hi << 32) | lo);
  756. if (adapter->pci_mem_write(adapter,
  757. flashaddr, data))
  758. return -EIO;
  759. flashaddr += 8;
  760. }
  761. }
  762. msleep(1);
  763. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  764. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  765. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  766. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  767. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  768. else {
  769. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  770. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  771. }
  772. return 0;
  773. }
  774. static int
  775. netxen_validate_firmware(struct netxen_adapter *adapter)
  776. {
  777. __le32 val;
  778. u32 ver, min_ver, bios, min_size;
  779. struct pci_dev *pdev = adapter->pdev;
  780. const struct firmware *fw = adapter->fw;
  781. u8 fw_type = adapter->fw_type;
  782. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  783. if (nx_set_product_offs(adapter))
  784. return -EINVAL;
  785. min_size = NX_UNI_FW_MIN_SIZE;
  786. } else {
  787. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  788. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  789. return -EINVAL;
  790. min_size = NX_FW_MIN_SIZE;
  791. }
  792. if (fw->size < min_size)
  793. return -EINVAL;
  794. val = nx_get_fw_version(adapter);
  795. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  796. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  797. else
  798. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  799. ver = NETXEN_DECODE_VERSION(val);
  800. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  801. dev_err(&pdev->dev,
  802. "%s: firmware version %d.%d.%d unsupported\n",
  803. fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
  804. return -EINVAL;
  805. }
  806. val = nx_get_bios_version(adapter);
  807. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  808. if ((__force u32)val != bios) {
  809. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  810. fw_name[fw_type]);
  811. return -EINVAL;
  812. }
  813. /* check if flashed firmware is newer */
  814. if (netxen_rom_fast_read(adapter,
  815. NX_FW_VERSION_OFFSET, (int *)&val))
  816. return -EIO;
  817. val = NETXEN_DECODE_VERSION(val);
  818. if (val > ver) {
  819. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  820. fw_name[fw_type]);
  821. return -EINVAL;
  822. }
  823. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  824. return 0;
  825. }
  826. static void
  827. nx_get_next_fwtype(struct netxen_adapter *adapter)
  828. {
  829. u8 fw_type;
  830. switch (adapter->fw_type) {
  831. case NX_UNKNOWN_ROMIMAGE:
  832. fw_type = NX_UNIFIED_ROMIMAGE;
  833. break;
  834. case NX_UNIFIED_ROMIMAGE:
  835. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  836. fw_type = NX_FLASH_ROMIMAGE;
  837. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  838. fw_type = NX_P2_MN_ROMIMAGE;
  839. else if (netxen_p3_has_mn(adapter))
  840. fw_type = NX_P3_MN_ROMIMAGE;
  841. else
  842. fw_type = NX_P3_CT_ROMIMAGE;
  843. break;
  844. case NX_P3_MN_ROMIMAGE:
  845. fw_type = NX_P3_CT_ROMIMAGE;
  846. break;
  847. case NX_P2_MN_ROMIMAGE:
  848. case NX_P3_CT_ROMIMAGE:
  849. default:
  850. fw_type = NX_FLASH_ROMIMAGE;
  851. break;
  852. }
  853. adapter->fw_type = fw_type;
  854. }
  855. static int
  856. netxen_p3_has_mn(struct netxen_adapter *adapter)
  857. {
  858. u32 capability, flashed_ver;
  859. capability = 0;
  860. /* NX2031 always had MN */
  861. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  862. return 1;
  863. netxen_rom_fast_read(adapter,
  864. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  865. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  866. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  867. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  868. if (capability & NX_PEG_TUNE_MN_PRESENT)
  869. return 1;
  870. }
  871. return 0;
  872. }
  873. void netxen_request_firmware(struct netxen_adapter *adapter)
  874. {
  875. struct pci_dev *pdev = adapter->pdev;
  876. int rc = 0;
  877. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  878. next:
  879. nx_get_next_fwtype(adapter);
  880. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  881. adapter->fw = NULL;
  882. } else {
  883. rc = request_firmware(&adapter->fw,
  884. fw_name[adapter->fw_type], &pdev->dev);
  885. if (rc != 0)
  886. goto next;
  887. rc = netxen_validate_firmware(adapter);
  888. if (rc != 0) {
  889. release_firmware(adapter->fw);
  890. msleep(1);
  891. goto next;
  892. }
  893. }
  894. }
  895. void
  896. netxen_release_firmware(struct netxen_adapter *adapter)
  897. {
  898. if (adapter->fw)
  899. release_firmware(adapter->fw);
  900. adapter->fw = NULL;
  901. }
  902. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  903. {
  904. u64 addr;
  905. u32 hi, lo;
  906. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  907. return 0;
  908. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  909. NETXEN_HOST_DUMMY_DMA_SIZE,
  910. &adapter->dummy_dma.phys_addr);
  911. if (adapter->dummy_dma.addr == NULL) {
  912. dev_err(&adapter->pdev->dev,
  913. "ERROR: Could not allocate dummy DMA memory\n");
  914. return -ENOMEM;
  915. }
  916. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  917. hi = (addr >> 32) & 0xffffffff;
  918. lo = addr & 0xffffffff;
  919. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  920. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  921. return 0;
  922. }
  923. /*
  924. * NetXen DMA watchdog control:
  925. *
  926. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  927. * Bit 1 : disable_request => 1 req disable dma watchdog
  928. * Bit 2 : enable_request => 1 req enable dma watchdog
  929. * Bit 3-31 : unused
  930. */
  931. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  932. {
  933. int i = 100;
  934. u32 ctrl;
  935. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  936. return;
  937. if (!adapter->dummy_dma.addr)
  938. return;
  939. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  940. if ((ctrl & 0x1) != 0) {
  941. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  942. while ((ctrl & 0x1) != 0) {
  943. msleep(50);
  944. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  945. if (--i == 0)
  946. break;
  947. };
  948. }
  949. if (i) {
  950. pci_free_consistent(adapter->pdev,
  951. NETXEN_HOST_DUMMY_DMA_SIZE,
  952. adapter->dummy_dma.addr,
  953. adapter->dummy_dma.phys_addr);
  954. adapter->dummy_dma.addr = NULL;
  955. } else
  956. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  957. }
  958. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  959. {
  960. u32 val = 0;
  961. int retries = 60;
  962. if (pegtune_val)
  963. return 0;
  964. do {
  965. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  966. switch (val) {
  967. case PHAN_INITIALIZE_COMPLETE:
  968. case PHAN_INITIALIZE_ACK:
  969. return 0;
  970. case PHAN_INITIALIZE_FAILED:
  971. goto out_err;
  972. default:
  973. break;
  974. }
  975. msleep(500);
  976. } while (--retries);
  977. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  978. out_err:
  979. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  980. return -EIO;
  981. }
  982. static int
  983. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  984. {
  985. u32 val = 0;
  986. int retries = 2000;
  987. do {
  988. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  989. if (val == PHAN_PEG_RCV_INITIALIZED)
  990. return 0;
  991. msleep(10);
  992. } while (--retries);
  993. if (!retries) {
  994. printk(KERN_ERR "Receive Peg initialization not "
  995. "complete, state: 0x%x.\n", val);
  996. return -EIO;
  997. }
  998. return 0;
  999. }
  1000. int netxen_init_firmware(struct netxen_adapter *adapter)
  1001. {
  1002. int err;
  1003. err = netxen_receive_peg_ready(adapter);
  1004. if (err)
  1005. return err;
  1006. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1007. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1008. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1009. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1010. return err;
  1011. }
  1012. static void
  1013. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1014. {
  1015. u32 cable_OUI;
  1016. u16 cable_len;
  1017. u16 link_speed;
  1018. u8 link_status, module, duplex, autoneg;
  1019. struct net_device *netdev = adapter->netdev;
  1020. adapter->has_link_events = 1;
  1021. cable_OUI = msg->body[1] & 0xffffffff;
  1022. cable_len = (msg->body[1] >> 32) & 0xffff;
  1023. link_speed = (msg->body[1] >> 48) & 0xffff;
  1024. link_status = msg->body[2] & 0xff;
  1025. duplex = (msg->body[2] >> 16) & 0xff;
  1026. autoneg = (msg->body[2] >> 24) & 0xff;
  1027. module = (msg->body[2] >> 8) & 0xff;
  1028. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1029. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1030. netdev->name, cable_OUI, cable_len);
  1031. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1032. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1033. netdev->name, cable_len);
  1034. }
  1035. netxen_advert_link_change(adapter, link_status);
  1036. /* update link parameters */
  1037. if (duplex == LINKEVENT_FULL_DUPLEX)
  1038. adapter->link_duplex = DUPLEX_FULL;
  1039. else
  1040. adapter->link_duplex = DUPLEX_HALF;
  1041. adapter->module_type = module;
  1042. adapter->link_autoneg = autoneg;
  1043. adapter->link_speed = link_speed;
  1044. }
  1045. static void
  1046. netxen_handle_fw_message(int desc_cnt, int index,
  1047. struct nx_host_sds_ring *sds_ring)
  1048. {
  1049. nx_fw_msg_t msg;
  1050. struct status_desc *desc;
  1051. int i = 0, opcode;
  1052. while (desc_cnt > 0 && i < 8) {
  1053. desc = &sds_ring->desc_head[index];
  1054. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1055. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1056. index = get_next_index(index, sds_ring->num_desc);
  1057. desc_cnt--;
  1058. }
  1059. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1060. switch (opcode) {
  1061. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1062. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1063. break;
  1064. default:
  1065. break;
  1066. }
  1067. }
  1068. static int
  1069. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1070. struct nx_host_rds_ring *rds_ring,
  1071. struct netxen_rx_buffer *buffer)
  1072. {
  1073. struct sk_buff *skb;
  1074. dma_addr_t dma;
  1075. struct pci_dev *pdev = adapter->pdev;
  1076. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1077. if (!buffer->skb)
  1078. return 1;
  1079. skb = buffer->skb;
  1080. if (!adapter->ahw.cut_through)
  1081. skb_reserve(skb, 2);
  1082. dma = pci_map_single(pdev, skb->data,
  1083. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1084. if (pci_dma_mapping_error(pdev, dma)) {
  1085. dev_kfree_skb_any(skb);
  1086. buffer->skb = NULL;
  1087. return 1;
  1088. }
  1089. buffer->skb = skb;
  1090. buffer->dma = dma;
  1091. buffer->state = NETXEN_BUFFER_BUSY;
  1092. return 0;
  1093. }
  1094. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1095. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1096. {
  1097. struct netxen_rx_buffer *buffer;
  1098. struct sk_buff *skb;
  1099. buffer = &rds_ring->rx_buf_arr[index];
  1100. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1101. PCI_DMA_FROMDEVICE);
  1102. skb = buffer->skb;
  1103. if (!skb)
  1104. goto no_skb;
  1105. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1106. adapter->stats.csummed++;
  1107. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1108. } else
  1109. skb->ip_summed = CHECKSUM_NONE;
  1110. skb->dev = adapter->netdev;
  1111. buffer->skb = NULL;
  1112. no_skb:
  1113. buffer->state = NETXEN_BUFFER_FREE;
  1114. return skb;
  1115. }
  1116. static struct netxen_rx_buffer *
  1117. netxen_process_rcv(struct netxen_adapter *adapter,
  1118. struct nx_host_sds_ring *sds_ring,
  1119. int ring, u64 sts_data0)
  1120. {
  1121. struct net_device *netdev = adapter->netdev;
  1122. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1123. struct netxen_rx_buffer *buffer;
  1124. struct sk_buff *skb;
  1125. struct nx_host_rds_ring *rds_ring;
  1126. int index, length, cksum, pkt_offset;
  1127. if (unlikely(ring >= adapter->max_rds_rings))
  1128. return NULL;
  1129. rds_ring = &recv_ctx->rds_rings[ring];
  1130. index = netxen_get_sts_refhandle(sts_data0);
  1131. if (unlikely(index >= rds_ring->num_desc))
  1132. return NULL;
  1133. buffer = &rds_ring->rx_buf_arr[index];
  1134. length = netxen_get_sts_totallength(sts_data0);
  1135. cksum = netxen_get_sts_status(sts_data0);
  1136. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1137. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1138. if (!skb)
  1139. return buffer;
  1140. if (length > rds_ring->skb_size)
  1141. skb_put(skb, rds_ring->skb_size);
  1142. else
  1143. skb_put(skb, length);
  1144. if (pkt_offset)
  1145. skb_pull(skb, pkt_offset);
  1146. skb->truesize = skb->len + sizeof(struct sk_buff);
  1147. skb->protocol = eth_type_trans(skb, netdev);
  1148. napi_gro_receive(&sds_ring->napi, skb);
  1149. adapter->stats.rx_pkts++;
  1150. adapter->stats.rxbytes += length;
  1151. return buffer;
  1152. }
  1153. #define TCP_HDR_SIZE 20
  1154. #define TCP_TS_OPTION_SIZE 12
  1155. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1156. static struct netxen_rx_buffer *
  1157. netxen_process_lro(struct netxen_adapter *adapter,
  1158. struct nx_host_sds_ring *sds_ring,
  1159. int ring, u64 sts_data0, u64 sts_data1)
  1160. {
  1161. struct net_device *netdev = adapter->netdev;
  1162. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1163. struct netxen_rx_buffer *buffer;
  1164. struct sk_buff *skb;
  1165. struct nx_host_rds_ring *rds_ring;
  1166. struct iphdr *iph;
  1167. struct tcphdr *th;
  1168. bool push, timestamp;
  1169. int l2_hdr_offset, l4_hdr_offset;
  1170. int index;
  1171. u16 lro_length, length, data_offset;
  1172. u32 seq_number;
  1173. if (unlikely(ring > adapter->max_rds_rings))
  1174. return NULL;
  1175. rds_ring = &recv_ctx->rds_rings[ring];
  1176. index = netxen_get_lro_sts_refhandle(sts_data0);
  1177. if (unlikely(index > rds_ring->num_desc))
  1178. return NULL;
  1179. buffer = &rds_ring->rx_buf_arr[index];
  1180. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1181. lro_length = netxen_get_lro_sts_length(sts_data0);
  1182. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1183. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1184. push = netxen_get_lro_sts_push_flag(sts_data0);
  1185. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1186. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1187. if (!skb)
  1188. return buffer;
  1189. if (timestamp)
  1190. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1191. else
  1192. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1193. skb_put(skb, lro_length + data_offset);
  1194. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1195. skb_pull(skb, l2_hdr_offset);
  1196. skb->protocol = eth_type_trans(skb, netdev);
  1197. iph = (struct iphdr *)skb->data;
  1198. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1199. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1200. iph->tot_len = htons(length);
  1201. iph->check = 0;
  1202. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1203. th->psh = push;
  1204. th->seq = htonl(seq_number);
  1205. length = skb->len;
  1206. netif_receive_skb(skb);
  1207. adapter->stats.lro_pkts++;
  1208. adapter->stats.rxbytes += length;
  1209. return buffer;
  1210. }
  1211. #define netxen_merge_rx_buffers(list, head) \
  1212. do { list_splice_tail_init(list, head); } while (0);
  1213. int
  1214. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1215. {
  1216. struct netxen_adapter *adapter = sds_ring->adapter;
  1217. struct list_head *cur;
  1218. struct status_desc *desc;
  1219. struct netxen_rx_buffer *rxbuf;
  1220. u32 consumer = sds_ring->consumer;
  1221. int count = 0;
  1222. u64 sts_data0, sts_data1;
  1223. int opcode, ring = 0, desc_cnt;
  1224. while (count < max) {
  1225. desc = &sds_ring->desc_head[consumer];
  1226. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1227. if (!(sts_data0 & STATUS_OWNER_HOST))
  1228. break;
  1229. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1230. opcode = netxen_get_sts_opcode(sts_data0);
  1231. switch (opcode) {
  1232. case NETXEN_NIC_RXPKT_DESC:
  1233. case NETXEN_OLD_RXPKT_DESC:
  1234. case NETXEN_NIC_SYN_OFFLOAD:
  1235. ring = netxen_get_sts_type(sts_data0);
  1236. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1237. ring, sts_data0);
  1238. break;
  1239. case NETXEN_NIC_LRO_DESC:
  1240. ring = netxen_get_lro_sts_type(sts_data0);
  1241. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1242. rxbuf = netxen_process_lro(adapter, sds_ring,
  1243. ring, sts_data0, sts_data1);
  1244. break;
  1245. case NETXEN_NIC_RESPONSE_DESC:
  1246. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1247. default:
  1248. goto skip;
  1249. }
  1250. WARN_ON(desc_cnt > 1);
  1251. if (rxbuf)
  1252. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1253. skip:
  1254. for (; desc_cnt > 0; desc_cnt--) {
  1255. desc = &sds_ring->desc_head[consumer];
  1256. desc->status_desc_data[0] =
  1257. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1258. consumer = get_next_index(consumer, sds_ring->num_desc);
  1259. }
  1260. count++;
  1261. }
  1262. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1263. struct nx_host_rds_ring *rds_ring =
  1264. &adapter->recv_ctx.rds_rings[ring];
  1265. if (!list_empty(&sds_ring->free_list[ring])) {
  1266. list_for_each(cur, &sds_ring->free_list[ring]) {
  1267. rxbuf = list_entry(cur,
  1268. struct netxen_rx_buffer, list);
  1269. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1270. }
  1271. spin_lock(&rds_ring->lock);
  1272. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1273. &rds_ring->free_list);
  1274. spin_unlock(&rds_ring->lock);
  1275. }
  1276. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1277. }
  1278. if (count) {
  1279. sds_ring->consumer = consumer;
  1280. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1281. }
  1282. return count;
  1283. }
  1284. /* Process Command status ring */
  1285. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1286. {
  1287. u32 sw_consumer, hw_consumer;
  1288. int count = 0, i;
  1289. struct netxen_cmd_buffer *buffer;
  1290. struct pci_dev *pdev = adapter->pdev;
  1291. struct net_device *netdev = adapter->netdev;
  1292. struct netxen_skb_frag *frag;
  1293. int done = 0;
  1294. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1295. if (!spin_trylock(&adapter->tx_clean_lock))
  1296. return 1;
  1297. sw_consumer = tx_ring->sw_consumer;
  1298. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1299. while (sw_consumer != hw_consumer) {
  1300. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1301. if (buffer->skb) {
  1302. frag = &buffer->frag_array[0];
  1303. pci_unmap_single(pdev, frag->dma, frag->length,
  1304. PCI_DMA_TODEVICE);
  1305. frag->dma = 0ULL;
  1306. for (i = 1; i < buffer->frag_count; i++) {
  1307. frag++; /* Get the next frag */
  1308. pci_unmap_page(pdev, frag->dma, frag->length,
  1309. PCI_DMA_TODEVICE);
  1310. frag->dma = 0ULL;
  1311. }
  1312. adapter->stats.xmitfinished++;
  1313. dev_kfree_skb_any(buffer->skb);
  1314. buffer->skb = NULL;
  1315. }
  1316. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1317. if (++count >= MAX_STATUS_HANDLE)
  1318. break;
  1319. }
  1320. if (count && netif_running(netdev)) {
  1321. tx_ring->sw_consumer = sw_consumer;
  1322. smp_mb();
  1323. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1324. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1325. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
  1326. netif_wake_queue(netdev);
  1327. adapter->tx_timeo_cnt = 0;
  1328. }
  1329. __netif_tx_unlock(tx_ring->txq);
  1330. }
  1331. }
  1332. /*
  1333. * If everything is freed up to consumer then check if the ring is full
  1334. * If the ring is full then check if more needs to be freed and
  1335. * schedule the call back again.
  1336. *
  1337. * This happens when there are 2 CPUs. One could be freeing and the
  1338. * other filling it. If the ring is full when we get out of here and
  1339. * the card has already interrupted the host then the host can miss the
  1340. * interrupt.
  1341. *
  1342. * There is still a possible race condition and the host could miss an
  1343. * interrupt. The card has to take care of this.
  1344. */
  1345. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1346. done = (sw_consumer == hw_consumer);
  1347. spin_unlock(&adapter->tx_clean_lock);
  1348. return (done);
  1349. }
  1350. void
  1351. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1352. struct nx_host_rds_ring *rds_ring)
  1353. {
  1354. struct rcv_desc *pdesc;
  1355. struct netxen_rx_buffer *buffer;
  1356. int producer, count = 0;
  1357. netxen_ctx_msg msg = 0;
  1358. struct list_head *head;
  1359. producer = rds_ring->producer;
  1360. spin_lock(&rds_ring->lock);
  1361. head = &rds_ring->free_list;
  1362. while (!list_empty(head)) {
  1363. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1364. if (!buffer->skb) {
  1365. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1366. break;
  1367. }
  1368. count++;
  1369. list_del(&buffer->list);
  1370. /* make a rcv descriptor */
  1371. pdesc = &rds_ring->desc_head[producer];
  1372. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1373. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1374. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1375. producer = get_next_index(producer, rds_ring->num_desc);
  1376. }
  1377. spin_unlock(&rds_ring->lock);
  1378. if (count) {
  1379. rds_ring->producer = producer;
  1380. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1381. (producer-1) & (rds_ring->num_desc-1));
  1382. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1383. /*
  1384. * Write a doorbell msg to tell phanmon of change in
  1385. * receive ring producer
  1386. * Only for firmware version < 4.0.0
  1387. */
  1388. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1389. netxen_set_msg_privid(msg);
  1390. netxen_set_msg_count(msg,
  1391. ((producer - 1) &
  1392. (rds_ring->num_desc - 1)));
  1393. netxen_set_msg_ctxid(msg, adapter->portnum);
  1394. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1395. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1396. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1397. }
  1398. }
  1399. }
  1400. static void
  1401. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1402. struct nx_host_rds_ring *rds_ring)
  1403. {
  1404. struct rcv_desc *pdesc;
  1405. struct netxen_rx_buffer *buffer;
  1406. int producer, count = 0;
  1407. struct list_head *head;
  1408. producer = rds_ring->producer;
  1409. if (!spin_trylock(&rds_ring->lock))
  1410. return;
  1411. head = &rds_ring->free_list;
  1412. while (!list_empty(head)) {
  1413. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1414. if (!buffer->skb) {
  1415. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1416. break;
  1417. }
  1418. count++;
  1419. list_del(&buffer->list);
  1420. /* make a rcv descriptor */
  1421. pdesc = &rds_ring->desc_head[producer];
  1422. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1423. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1424. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1425. producer = get_next_index(producer, rds_ring->num_desc);
  1426. }
  1427. if (count) {
  1428. rds_ring->producer = producer;
  1429. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1430. (producer - 1) & (rds_ring->num_desc - 1));
  1431. }
  1432. spin_unlock(&rds_ring->lock);
  1433. }
  1434. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1435. {
  1436. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1437. return;
  1438. }