mci.c 16 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  40. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  41. return false;
  42. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  43. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  44. return false;
  45. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  46. if (!entry)
  47. return false;
  48. memcpy(entry, info, 10);
  49. INC_PROF(mci, info);
  50. list_add_tail(&entry->list, &mci->info);
  51. return true;
  52. }
  53. static void ath_mci_del_profile(struct ath_common *common,
  54. struct ath_mci_profile *mci,
  55. struct ath_mci_profile_info *entry)
  56. {
  57. if (!entry)
  58. return;
  59. DEC_PROF(mci, entry);
  60. list_del(&entry->list);
  61. kfree(entry);
  62. }
  63. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  64. {
  65. struct ath_mci_profile_info *info, *tinfo;
  66. mci->aggr_limit = 0;
  67. mci->num_mgmt = 0;
  68. if (list_empty(&mci->info))
  69. return;
  70. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  71. list_del(&info->list);
  72. DEC_PROF(mci, info);
  73. kfree(info);
  74. }
  75. }
  76. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  77. {
  78. struct ath_mci_profile *mci = &btcoex->mci;
  79. u32 wlan_airtime = btcoex->btcoex_period *
  80. (100 - btcoex->duty_cycle) / 100;
  81. /*
  82. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  83. * When wlan_airtime is less than 4ms, aggregation limit has to be
  84. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  85. * without collision with BT traffic.
  86. */
  87. if ((wlan_airtime <= 4) &&
  88. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  89. mci->aggr_limit = 2 * wlan_airtime;
  90. }
  91. static void ath_mci_update_scheme(struct ath_softc *sc)
  92. {
  93. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  94. struct ath_btcoex *btcoex = &sc->btcoex;
  95. struct ath_mci_profile *mci = &btcoex->mci;
  96. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  97. struct ath_mci_profile_info *info;
  98. u32 num_profile = NUM_PROF(mci);
  99. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  100. goto skip_tuning;
  101. mci->aggr_limit = 0;
  102. btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
  103. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  104. if (NUM_PROF(mci))
  105. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  106. else
  107. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  108. ATH_BTCOEX_STOMP_LOW;
  109. if (num_profile == 1) {
  110. info = list_first_entry(&mci->info,
  111. struct ath_mci_profile_info,
  112. list);
  113. if (mci->num_sco) {
  114. if (info->T == 12)
  115. mci->aggr_limit = 8;
  116. else if (info->T == 6) {
  117. mci->aggr_limit = 6;
  118. btcoex->duty_cycle = 30;
  119. } else
  120. mci->aggr_limit = 6;
  121. ath_dbg(common, MCI,
  122. "Single SCO, aggregation limit %d 1/4 ms\n",
  123. mci->aggr_limit);
  124. } else if (mci->num_pan || mci->num_other_acl) {
  125. /*
  126. * For single PAN/FTP profile, allocate 35% for BT
  127. * to improve WLAN throughput.
  128. */
  129. btcoex->duty_cycle = 35;
  130. btcoex->btcoex_period = 53;
  131. ath_dbg(common, MCI,
  132. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  133. btcoex->duty_cycle, btcoex->btcoex_period);
  134. } else if (mci->num_hid) {
  135. btcoex->duty_cycle = 30;
  136. mci->aggr_limit = 6;
  137. ath_dbg(common, MCI,
  138. "Multiple attempt/timeout single HID "
  139. "aggregation limit 1.5 ms dutycycle 30%%\n");
  140. }
  141. } else if (num_profile == 2) {
  142. if (mci->num_hid == 2)
  143. btcoex->duty_cycle = 30;
  144. mci->aggr_limit = 6;
  145. ath_dbg(common, MCI,
  146. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  147. btcoex->duty_cycle);
  148. } else if (num_profile >= 3) {
  149. mci->aggr_limit = 4;
  150. ath_dbg(common, MCI,
  151. "Three or more profiles aggregation limit 1 ms\n");
  152. }
  153. skip_tuning:
  154. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  155. if (IS_CHAN_HT(sc->sc_ah->curchan))
  156. ath_mci_adjust_aggr_limit(btcoex);
  157. else
  158. btcoex->btcoex_period >>= 1;
  159. }
  160. ath9k_btcoex_timer_pause(sc);
  161. ath9k_hw_btcoex_disable(sc->sc_ah);
  162. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  163. return;
  164. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
  165. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  166. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  167. btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
  168. (100 - btcoex->duty_cycle) / 100;
  169. ath9k_hw_btcoex_enable(sc->sc_ah);
  170. ath9k_btcoex_timer_resume(sc);
  171. }
  172. static void ath_mci_wait_btcal_done(struct ath_softc *sc)
  173. {
  174. struct ath_hw *ah = sc->sc_ah;
  175. /* Stop tx & rx */
  176. ieee80211_stop_queues(sc->hw);
  177. ath_stoprecv(sc);
  178. ath_drain_all_txq(sc, false);
  179. /* Wait for cal done */
  180. ar9003_mci_start_reset(ah, ah->curchan);
  181. /* Resume tx & rx */
  182. ath_startrecv(sc);
  183. ieee80211_wake_queues(sc->hw);
  184. }
  185. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  186. {
  187. struct ath_hw *ah = sc->sc_ah;
  188. struct ath_common *common = ath9k_hw_common(ah);
  189. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  190. u32 payload[4] = {0, 0, 0, 0};
  191. switch (opcode) {
  192. case MCI_GPM_BT_CAL_REQ:
  193. if (mci_hw->bt_state == MCI_BT_AWAKE) {
  194. mci_hw->bt_state = MCI_BT_CAL_START;
  195. ath_mci_wait_btcal_done(sc);
  196. }
  197. ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
  198. break;
  199. case MCI_GPM_BT_CAL_GRANT:
  200. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  201. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  202. 16, false, true);
  203. break;
  204. default:
  205. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  206. break;
  207. }
  208. }
  209. static void ath9k_mci_work(struct work_struct *work)
  210. {
  211. struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
  212. ath_mci_update_scheme(sc);
  213. }
  214. static u8 ath_mci_process_profile(struct ath_softc *sc,
  215. struct ath_mci_profile_info *info)
  216. {
  217. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  218. struct ath_btcoex *btcoex = &sc->btcoex;
  219. struct ath_mci_profile *mci = &btcoex->mci;
  220. struct ath_mci_profile_info *entry = NULL;
  221. entry = ath_mci_find_profile(mci, info);
  222. if (entry) {
  223. /*
  224. * Two MCI interrupts are generated while connecting to
  225. * headset and A2DP profile, but only one MCI interrupt
  226. * is generated with last added profile type while disconnecting
  227. * both profiles.
  228. * So while adding second profile type decrement
  229. * the first one.
  230. */
  231. if (entry->type != info->type) {
  232. DEC_PROF(mci, entry);
  233. INC_PROF(mci, info);
  234. }
  235. memcpy(entry, info, 10);
  236. }
  237. if (info->start) {
  238. if (!entry && !ath_mci_add_profile(common, mci, info))
  239. return 0;
  240. } else
  241. ath_mci_del_profile(common, mci, entry);
  242. return 1;
  243. }
  244. static u8 ath_mci_process_status(struct ath_softc *sc,
  245. struct ath_mci_profile_status *status)
  246. {
  247. struct ath_btcoex *btcoex = &sc->btcoex;
  248. struct ath_mci_profile *mci = &btcoex->mci;
  249. struct ath_mci_profile_info info;
  250. int i = 0, old_num_mgmt = mci->num_mgmt;
  251. /* Link status type are not handled */
  252. if (status->is_link)
  253. return 0;
  254. info.conn_handle = status->conn_handle;
  255. if (ath_mci_find_profile(mci, &info))
  256. return 0;
  257. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  258. return 0;
  259. if (status->is_critical)
  260. __set_bit(status->conn_handle, mci->status);
  261. else
  262. __clear_bit(status->conn_handle, mci->status);
  263. mci->num_mgmt = 0;
  264. do {
  265. if (test_bit(i, mci->status))
  266. mci->num_mgmt++;
  267. } while (++i < ATH_MCI_MAX_PROFILE);
  268. if (old_num_mgmt != mci->num_mgmt)
  269. return 1;
  270. return 0;
  271. }
  272. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  273. {
  274. struct ath_hw *ah = sc->sc_ah;
  275. struct ath_mci_profile_info profile_info;
  276. struct ath_mci_profile_status profile_status;
  277. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  278. u8 major, minor, update_scheme = 0;
  279. u32 seq_num;
  280. if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
  281. ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
  282. ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
  283. ath_mci_flush_profile(&sc->btcoex.mci);
  284. ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
  285. }
  286. switch (opcode) {
  287. case MCI_GPM_COEX_VERSION_QUERY:
  288. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
  289. break;
  290. case MCI_GPM_COEX_VERSION_RESPONSE:
  291. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  292. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  293. ar9003_mci_set_bt_version(ah, major, minor);
  294. break;
  295. case MCI_GPM_COEX_STATUS_QUERY:
  296. ar9003_mci_send_wlan_channels(ah);
  297. break;
  298. case MCI_GPM_COEX_BT_PROFILE_INFO:
  299. memcpy(&profile_info,
  300. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  301. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  302. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  303. ath_dbg(common, MCI,
  304. "Illegal profile type = %d, state = %d\n",
  305. profile_info.type,
  306. profile_info.start);
  307. break;
  308. }
  309. update_scheme += ath_mci_process_profile(sc, &profile_info);
  310. break;
  311. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  312. profile_status.is_link = *(rx_payload +
  313. MCI_GPM_COEX_B_STATUS_TYPE);
  314. profile_status.conn_handle = *(rx_payload +
  315. MCI_GPM_COEX_B_STATUS_LINKID);
  316. profile_status.is_critical = *(rx_payload +
  317. MCI_GPM_COEX_B_STATUS_STATE);
  318. seq_num = *((u32 *)(rx_payload + 12));
  319. ath_dbg(common, MCI,
  320. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
  321. profile_status.is_link, profile_status.conn_handle,
  322. profile_status.is_critical, seq_num);
  323. update_scheme += ath_mci_process_status(sc, &profile_status);
  324. break;
  325. default:
  326. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  327. break;
  328. }
  329. if (update_scheme)
  330. ieee80211_queue_work(sc->hw, &sc->mci_work);
  331. }
  332. int ath_mci_setup(struct ath_softc *sc)
  333. {
  334. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  335. struct ath_mci_coex *mci = &sc->mci_coex;
  336. struct ath_mci_buf *buf = &mci->sched_buf;
  337. int ret;
  338. buf->bf_addr = dma_alloc_coherent(sc->dev,
  339. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  340. &buf->bf_paddr, GFP_KERNEL);
  341. if (buf->bf_addr == NULL) {
  342. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  343. return -ENOMEM;
  344. }
  345. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  346. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  347. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  348. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  349. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  350. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  351. ret = ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  352. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  353. mci->sched_buf.bf_paddr);
  354. if (ret) {
  355. ath_err(common, "Failed to initialize MCI\n");
  356. return ret;
  357. }
  358. INIT_WORK(&sc->mci_work, ath9k_mci_work);
  359. ath_dbg(common, MCI, "MCI Initialized\n");
  360. return 0;
  361. }
  362. void ath_mci_cleanup(struct ath_softc *sc)
  363. {
  364. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  365. struct ath_hw *ah = sc->sc_ah;
  366. struct ath_mci_coex *mci = &sc->mci_coex;
  367. struct ath_mci_buf *buf = &mci->sched_buf;
  368. if (buf->bf_addr)
  369. dma_free_coherent(sc->dev,
  370. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  371. buf->bf_addr, buf->bf_paddr);
  372. ar9003_mci_cleanup(ah);
  373. ath_dbg(common, MCI, "MCI De-Initialized\n");
  374. }
  375. void ath_mci_intr(struct ath_softc *sc)
  376. {
  377. struct ath_mci_coex *mci = &sc->mci_coex;
  378. struct ath_hw *ah = sc->sc_ah;
  379. struct ath_common *common = ath9k_hw_common(ah);
  380. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  381. u32 mci_int, mci_int_rxmsg;
  382. u32 offset, subtype, opcode;
  383. u32 *pgpm;
  384. u32 more_data = MCI_GPM_MORE;
  385. bool skip_gpm = false;
  386. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  387. if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
  388. ar9003_mci_get_next_gpm_offset(ah, true, NULL);
  389. return;
  390. }
  391. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  392. u32 payload[4] = { 0xffffffff, 0xffffffff,
  393. 0xffffffff, 0xffffff00};
  394. /*
  395. * The following REMOTE_RESET and SYS_WAKING used to sent
  396. * only when BT wake up. Now they are always sent, as a
  397. * recovery method to reset BT MCI's RX alignment.
  398. */
  399. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  400. payload, 16, true, false);
  401. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  402. NULL, 0, true, false);
  403. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  404. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
  405. /*
  406. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  407. */
  408. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  409. }
  410. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  411. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  412. if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
  413. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  414. MCI_BT_SLEEP))
  415. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  416. }
  417. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  418. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  419. if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
  420. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  421. MCI_BT_AWAKE))
  422. mci_hw->bt_state = MCI_BT_SLEEP;
  423. }
  424. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  425. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  426. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
  427. skip_gpm = true;
  428. }
  429. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  430. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  431. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
  432. }
  433. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  434. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  435. while (more_data == MCI_GPM_MORE) {
  436. pgpm = mci->gpm_buf.bf_addr;
  437. offset = ar9003_mci_get_next_gpm_offset(ah, false,
  438. &more_data);
  439. if (offset == MCI_GPM_INVALID)
  440. break;
  441. pgpm += (offset >> 2);
  442. /*
  443. * The first dword is timer.
  444. * The real data starts from 2nd dword.
  445. */
  446. subtype = MCI_GPM_TYPE(pgpm);
  447. opcode = MCI_GPM_OPCODE(pgpm);
  448. if (skip_gpm)
  449. goto recycle;
  450. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  451. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  452. } else {
  453. switch (subtype) {
  454. case MCI_GPM_COEX_AGENT:
  455. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  456. break;
  457. default:
  458. break;
  459. }
  460. }
  461. recycle:
  462. MCI_GPM_RECYCLE(pgpm);
  463. }
  464. }
  465. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  466. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  467. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  468. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  469. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  470. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  471. int value_dbm = MS(mci_hw->cont_status,
  472. AR_MCI_CONT_RSSI_POWER);
  473. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  474. ath_dbg(common, MCI,
  475. "MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
  476. MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
  477. "tx" : "rx",
  478. MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
  479. value_dbm);
  480. }
  481. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  482. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  483. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  484. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  485. }
  486. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  487. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  488. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  489. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  490. ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
  491. }
  492. }
  493. void ath_mci_enable(struct ath_softc *sc)
  494. {
  495. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  496. if (!common->btcoex_enabled)
  497. return;
  498. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  499. sc->sc_ah->imask |= ATH9K_INT_MCI;
  500. }