main.c 59 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. spin_unlock(&common->cc_lock);
  92. }
  93. unlock:
  94. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  95. }
  96. void ath9k_ps_restore(struct ath_softc *sc)
  97. {
  98. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  99. enum ath9k_power_mode mode;
  100. unsigned long flags;
  101. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  102. if (--sc->ps_usecount != 0)
  103. goto unlock;
  104. if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK))
  105. mode = ATH9K_PM_FULL_SLEEP;
  106. else if (sc->ps_enabled &&
  107. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  108. PS_WAIT_FOR_CAB |
  109. PS_WAIT_FOR_PSPOLL_DATA |
  110. PS_WAIT_FOR_TX_ACK)))
  111. mode = ATH9K_PM_NETWORK_SLEEP;
  112. else
  113. goto unlock;
  114. spin_lock(&common->cc_lock);
  115. ath_hw_cycle_counters_update(common);
  116. spin_unlock(&common->cc_lock);
  117. ath9k_hw_setpower(sc->sc_ah, mode);
  118. unlock:
  119. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  120. }
  121. void ath_start_ani(struct ath_common *common)
  122. {
  123. struct ath_hw *ah = common->ah;
  124. unsigned long timestamp = jiffies_to_msecs(jiffies);
  125. struct ath_softc *sc = (struct ath_softc *) common->priv;
  126. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  127. return;
  128. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  129. return;
  130. common->ani.longcal_timer = timestamp;
  131. common->ani.shortcal_timer = timestamp;
  132. common->ani.checkani_timer = timestamp;
  133. mod_timer(&common->ani.timer,
  134. jiffies +
  135. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  136. }
  137. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  138. {
  139. struct ath_hw *ah = sc->sc_ah;
  140. struct ath9k_channel *chan = &ah->channels[channel];
  141. struct survey_info *survey = &sc->survey[channel];
  142. if (chan->noisefloor) {
  143. survey->filled |= SURVEY_INFO_NOISE_DBM;
  144. survey->noise = ath9k_hw_getchan_noise(ah, chan);
  145. }
  146. }
  147. /*
  148. * Updates the survey statistics and returns the busy time since last
  149. * update in %, if the measurement duration was long enough for the
  150. * result to be useful, -1 otherwise.
  151. */
  152. static int ath_update_survey_stats(struct ath_softc *sc)
  153. {
  154. struct ath_hw *ah = sc->sc_ah;
  155. struct ath_common *common = ath9k_hw_common(ah);
  156. int pos = ah->curchan - &ah->channels[0];
  157. struct survey_info *survey = &sc->survey[pos];
  158. struct ath_cycle_counters *cc = &common->cc_survey;
  159. unsigned int div = common->clockrate * 1000;
  160. int ret = 0;
  161. if (!ah->curchan)
  162. return -1;
  163. if (ah->power_mode == ATH9K_PM_AWAKE)
  164. ath_hw_cycle_counters_update(common);
  165. if (cc->cycles > 0) {
  166. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  167. SURVEY_INFO_CHANNEL_TIME_BUSY |
  168. SURVEY_INFO_CHANNEL_TIME_RX |
  169. SURVEY_INFO_CHANNEL_TIME_TX;
  170. survey->channel_time += cc->cycles / div;
  171. survey->channel_time_busy += cc->rx_busy / div;
  172. survey->channel_time_rx += cc->rx_frame / div;
  173. survey->channel_time_tx += cc->tx_frame / div;
  174. }
  175. if (cc->cycles < div)
  176. return -1;
  177. if (cc->cycles > 0)
  178. ret = cc->rx_busy * 100 / cc->cycles;
  179. memset(cc, 0, sizeof(*cc));
  180. ath_update_survey_nf(sc, pos);
  181. return ret;
  182. }
  183. static void __ath_cancel_work(struct ath_softc *sc)
  184. {
  185. cancel_work_sync(&sc->paprd_work);
  186. cancel_work_sync(&sc->hw_check_work);
  187. cancel_delayed_work_sync(&sc->tx_complete_work);
  188. cancel_delayed_work_sync(&sc->hw_pll_work);
  189. }
  190. static void ath_cancel_work(struct ath_softc *sc)
  191. {
  192. __ath_cancel_work(sc);
  193. cancel_work_sync(&sc->hw_reset_work);
  194. }
  195. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  196. {
  197. struct ath_hw *ah = sc->sc_ah;
  198. struct ath_common *common = ath9k_hw_common(ah);
  199. bool ret;
  200. ieee80211_stop_queues(sc->hw);
  201. sc->hw_busy_count = 0;
  202. del_timer_sync(&common->ani.timer);
  203. ath9k_debug_samp_bb_mac(sc);
  204. ath9k_hw_disable_interrupts(ah);
  205. ret = ath_drain_all_txq(sc, retry_tx);
  206. if (!ath_stoprecv(sc))
  207. ret = false;
  208. if (!flush) {
  209. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  210. ath_rx_tasklet(sc, 1, true);
  211. ath_rx_tasklet(sc, 1, false);
  212. } else {
  213. ath_flushrecv(sc);
  214. }
  215. return ret;
  216. }
  217. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  218. {
  219. struct ath_hw *ah = sc->sc_ah;
  220. struct ath_common *common = ath9k_hw_common(ah);
  221. if (ath_startrecv(sc) != 0) {
  222. ath_err(common, "Unable to restart recv logic\n");
  223. return false;
  224. }
  225. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  226. sc->config.txpowlimit, &sc->curtxpow);
  227. ath9k_hw_set_interrupts(ah);
  228. ath9k_hw_enable_interrupts(ah);
  229. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
  230. if (sc->sc_flags & SC_OP_BEACONS)
  231. ath_set_beacon(sc);
  232. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  233. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  234. if (!common->disable_ani)
  235. ath_start_ani(common);
  236. }
  237. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
  238. struct ath_hw_antcomb_conf div_ant_conf;
  239. u8 lna_conf;
  240. ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
  241. if (sc->ant_rx == 1)
  242. lna_conf = ATH_ANT_DIV_COMB_LNA1;
  243. else
  244. lna_conf = ATH_ANT_DIV_COMB_LNA2;
  245. div_ant_conf.main_lna_conf = lna_conf;
  246. div_ant_conf.alt_lna_conf = lna_conf;
  247. ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
  248. }
  249. ieee80211_wake_queues(sc->hw);
  250. return true;
  251. }
  252. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  253. bool retry_tx)
  254. {
  255. struct ath_hw *ah = sc->sc_ah;
  256. struct ath_common *common = ath9k_hw_common(ah);
  257. struct ath9k_hw_cal_data *caldata = NULL;
  258. bool fastcc = true;
  259. bool flush = false;
  260. int r;
  261. __ath_cancel_work(sc);
  262. spin_lock_bh(&sc->sc_pcu_lock);
  263. if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
  264. fastcc = false;
  265. caldata = &sc->caldata;
  266. }
  267. if (!hchan) {
  268. fastcc = false;
  269. flush = true;
  270. hchan = ah->curchan;
  271. }
  272. if (fastcc && (ah->chip_fullsleep ||
  273. !ath9k_hw_check_alive(ah)))
  274. fastcc = false;
  275. if (!ath_prepare_reset(sc, retry_tx, flush))
  276. fastcc = false;
  277. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  278. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  279. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  280. if (r) {
  281. ath_err(common,
  282. "Unable to reset channel, reset status %d\n", r);
  283. goto out;
  284. }
  285. if (!ath_complete_reset(sc, true))
  286. r = -EIO;
  287. out:
  288. spin_unlock_bh(&sc->sc_pcu_lock);
  289. return r;
  290. }
  291. /*
  292. * Set/change channels. If the channel is really being changed, it's done
  293. * by reseting the chip. To accomplish this we must first cleanup any pending
  294. * DMA, then restart stuff.
  295. */
  296. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  297. struct ath9k_channel *hchan)
  298. {
  299. int r;
  300. if (sc->sc_flags & SC_OP_INVALID)
  301. return -EIO;
  302. r = ath_reset_internal(sc, hchan, false);
  303. return r;
  304. }
  305. static void ath_paprd_activate(struct ath_softc *sc)
  306. {
  307. struct ath_hw *ah = sc->sc_ah;
  308. struct ath9k_hw_cal_data *caldata = ah->caldata;
  309. int chain;
  310. if (!caldata || !caldata->paprd_done)
  311. return;
  312. ath9k_ps_wakeup(sc);
  313. ar9003_paprd_enable(ah, false);
  314. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  315. if (!(ah->txchainmask & BIT(chain)))
  316. continue;
  317. ar9003_paprd_populate_single_table(ah, caldata, chain);
  318. }
  319. ar9003_paprd_enable(ah, true);
  320. ath9k_ps_restore(sc);
  321. }
  322. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  323. {
  324. struct ieee80211_hw *hw = sc->hw;
  325. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  326. struct ath_hw *ah = sc->sc_ah;
  327. struct ath_common *common = ath9k_hw_common(ah);
  328. struct ath_tx_control txctl;
  329. int time_left;
  330. memset(&txctl, 0, sizeof(txctl));
  331. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  332. memset(tx_info, 0, sizeof(*tx_info));
  333. tx_info->band = hw->conf.channel->band;
  334. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  335. tx_info->control.rates[0].idx = 0;
  336. tx_info->control.rates[0].count = 1;
  337. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  338. tx_info->control.rates[1].idx = -1;
  339. init_completion(&sc->paprd_complete);
  340. txctl.paprd = BIT(chain);
  341. if (ath_tx_start(hw, skb, &txctl) != 0) {
  342. ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
  343. dev_kfree_skb_any(skb);
  344. return false;
  345. }
  346. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  347. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  348. if (!time_left)
  349. ath_dbg(common, CALIBRATE,
  350. "Timeout waiting for paprd training on TX chain %d\n",
  351. chain);
  352. return !!time_left;
  353. }
  354. void ath_paprd_calibrate(struct work_struct *work)
  355. {
  356. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  357. struct ieee80211_hw *hw = sc->hw;
  358. struct ath_hw *ah = sc->sc_ah;
  359. struct ieee80211_hdr *hdr;
  360. struct sk_buff *skb = NULL;
  361. struct ath9k_hw_cal_data *caldata = ah->caldata;
  362. struct ath_common *common = ath9k_hw_common(ah);
  363. int ftype;
  364. int chain_ok = 0;
  365. int chain;
  366. int len = 1800;
  367. if (!caldata)
  368. return;
  369. ath9k_ps_wakeup(sc);
  370. if (ar9003_paprd_init_table(ah) < 0)
  371. goto fail_paprd;
  372. skb = alloc_skb(len, GFP_KERNEL);
  373. if (!skb)
  374. goto fail_paprd;
  375. skb_put(skb, len);
  376. memset(skb->data, 0, len);
  377. hdr = (struct ieee80211_hdr *)skb->data;
  378. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  379. hdr->frame_control = cpu_to_le16(ftype);
  380. hdr->duration_id = cpu_to_le16(10);
  381. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  382. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  383. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  384. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  385. if (!(ah->txchainmask & BIT(chain)))
  386. continue;
  387. chain_ok = 0;
  388. ath_dbg(common, CALIBRATE,
  389. "Sending PAPRD frame for thermal measurement on chain %d\n",
  390. chain);
  391. if (!ath_paprd_send_frame(sc, skb, chain))
  392. goto fail_paprd;
  393. ar9003_paprd_setup_gain_table(ah, chain);
  394. ath_dbg(common, CALIBRATE,
  395. "Sending PAPRD training frame on chain %d\n", chain);
  396. if (!ath_paprd_send_frame(sc, skb, chain))
  397. goto fail_paprd;
  398. if (!ar9003_paprd_is_done(ah)) {
  399. ath_dbg(common, CALIBRATE,
  400. "PAPRD not yet done on chain %d\n", chain);
  401. break;
  402. }
  403. if (ar9003_paprd_create_curve(ah, caldata, chain)) {
  404. ath_dbg(common, CALIBRATE,
  405. "PAPRD create curve failed on chain %d\n",
  406. chain);
  407. break;
  408. }
  409. chain_ok = 1;
  410. }
  411. kfree_skb(skb);
  412. if (chain_ok) {
  413. caldata->paprd_done = true;
  414. ath_paprd_activate(sc);
  415. }
  416. fail_paprd:
  417. ath9k_ps_restore(sc);
  418. }
  419. /*
  420. * This routine performs the periodic noise floor calibration function
  421. * that is used to adjust and optimize the chip performance. This
  422. * takes environmental changes (location, temperature) into account.
  423. * When the task is complete, it reschedules itself depending on the
  424. * appropriate interval that was calculated.
  425. */
  426. void ath_ani_calibrate(unsigned long data)
  427. {
  428. struct ath_softc *sc = (struct ath_softc *)data;
  429. struct ath_hw *ah = sc->sc_ah;
  430. struct ath_common *common = ath9k_hw_common(ah);
  431. bool longcal = false;
  432. bool shortcal = false;
  433. bool aniflag = false;
  434. unsigned int timestamp = jiffies_to_msecs(jiffies);
  435. u32 cal_interval, short_cal_interval, long_cal_interval;
  436. unsigned long flags;
  437. if (ah->caldata && ah->caldata->nfcal_interference)
  438. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  439. else
  440. long_cal_interval = ATH_LONG_CALINTERVAL;
  441. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  442. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  443. /* Only calibrate if awake */
  444. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  445. goto set_timer;
  446. ath9k_ps_wakeup(sc);
  447. /* Long calibration runs independently of short calibration. */
  448. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  449. longcal = true;
  450. common->ani.longcal_timer = timestamp;
  451. }
  452. /* Short calibration applies only while caldone is false */
  453. if (!common->ani.caldone) {
  454. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  455. shortcal = true;
  456. common->ani.shortcal_timer = timestamp;
  457. common->ani.resetcal_timer = timestamp;
  458. }
  459. } else {
  460. if ((timestamp - common->ani.resetcal_timer) >=
  461. ATH_RESTART_CALINTERVAL) {
  462. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  463. if (common->ani.caldone)
  464. common->ani.resetcal_timer = timestamp;
  465. }
  466. }
  467. /* Verify whether we must check ANI */
  468. if (sc->sc_ah->config.enable_ani
  469. && (timestamp - common->ani.checkani_timer) >=
  470. ah->config.ani_poll_interval) {
  471. aniflag = true;
  472. common->ani.checkani_timer = timestamp;
  473. }
  474. /* Call ANI routine if necessary */
  475. if (aniflag) {
  476. spin_lock_irqsave(&common->cc_lock, flags);
  477. ath9k_hw_ani_monitor(ah, ah->curchan);
  478. ath_update_survey_stats(sc);
  479. spin_unlock_irqrestore(&common->cc_lock, flags);
  480. }
  481. /* Perform calibration if necessary */
  482. if (longcal || shortcal) {
  483. common->ani.caldone =
  484. ath9k_hw_calibrate(ah, ah->curchan,
  485. ah->rxchainmask, longcal);
  486. }
  487. ath_dbg(common, ANI,
  488. "Calibration @%lu finished: %s %s %s, caldone: %s\n",
  489. jiffies,
  490. longcal ? "long" : "", shortcal ? "short" : "",
  491. aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
  492. ath9k_ps_restore(sc);
  493. set_timer:
  494. /*
  495. * Set timer interval based on previous results.
  496. * The interval must be the shortest necessary to satisfy ANI,
  497. * short calibration and long calibration.
  498. */
  499. ath9k_debug_samp_bb_mac(sc);
  500. cal_interval = ATH_LONG_CALINTERVAL;
  501. if (sc->sc_ah->config.enable_ani)
  502. cal_interval = min(cal_interval,
  503. (u32)ah->config.ani_poll_interval);
  504. if (!common->ani.caldone)
  505. cal_interval = min(cal_interval, (u32)short_cal_interval);
  506. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  507. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  508. if (!ah->caldata->paprd_done)
  509. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  510. else if (!ah->paprd_table_write_done)
  511. ath_paprd_activate(sc);
  512. }
  513. }
  514. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  515. struct ieee80211_vif *vif)
  516. {
  517. struct ath_node *an;
  518. an = (struct ath_node *)sta->drv_priv;
  519. #ifdef CONFIG_ATH9K_DEBUGFS
  520. spin_lock(&sc->nodes_lock);
  521. list_add(&an->list, &sc->nodes);
  522. spin_unlock(&sc->nodes_lock);
  523. #endif
  524. an->sta = sta;
  525. an->vif = vif;
  526. if (sc->sc_flags & SC_OP_TXAGGR) {
  527. ath_tx_node_init(sc, an);
  528. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  529. sta->ht_cap.ampdu_factor);
  530. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  531. }
  532. }
  533. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  534. {
  535. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  536. #ifdef CONFIG_ATH9K_DEBUGFS
  537. spin_lock(&sc->nodes_lock);
  538. list_del(&an->list);
  539. spin_unlock(&sc->nodes_lock);
  540. an->sta = NULL;
  541. #endif
  542. if (sc->sc_flags & SC_OP_TXAGGR)
  543. ath_tx_node_cleanup(sc, an);
  544. }
  545. void ath9k_tasklet(unsigned long data)
  546. {
  547. struct ath_softc *sc = (struct ath_softc *)data;
  548. struct ath_hw *ah = sc->sc_ah;
  549. struct ath_common *common = ath9k_hw_common(ah);
  550. u32 status = sc->intrstatus;
  551. u32 rxmask;
  552. ath9k_ps_wakeup(sc);
  553. spin_lock(&sc->sc_pcu_lock);
  554. if ((status & ATH9K_INT_FATAL) ||
  555. (status & ATH9K_INT_BB_WATCHDOG)) {
  556. #ifdef CONFIG_ATH9K_DEBUGFS
  557. enum ath_reset_type type;
  558. if (status & ATH9K_INT_FATAL)
  559. type = RESET_TYPE_FATAL_INT;
  560. else
  561. type = RESET_TYPE_BB_WATCHDOG;
  562. RESET_STAT_INC(sc, type);
  563. #endif
  564. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  565. goto out;
  566. }
  567. /*
  568. * Only run the baseband hang check if beacons stop working in AP or
  569. * IBSS mode, because it has a high false positive rate. For station
  570. * mode it should not be necessary, since the upper layers will detect
  571. * this through a beacon miss automatically and the following channel
  572. * change will trigger a hardware reset anyway
  573. */
  574. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  575. !ath9k_hw_check_alive(ah))
  576. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  577. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  578. /*
  579. * TSF sync does not look correct; remain awake to sync with
  580. * the next Beacon.
  581. */
  582. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  583. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  584. }
  585. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  586. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  587. ATH9K_INT_RXORN);
  588. else
  589. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  590. if (status & rxmask) {
  591. /* Check for high priority Rx first */
  592. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  593. (status & ATH9K_INT_RXHP))
  594. ath_rx_tasklet(sc, 0, true);
  595. ath_rx_tasklet(sc, 0, false);
  596. }
  597. if (status & ATH9K_INT_TX) {
  598. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  599. ath_tx_edma_tasklet(sc);
  600. else
  601. ath_tx_tasklet(sc);
  602. }
  603. ath9k_btcoex_handle_interrupt(sc, status);
  604. out:
  605. /* re-enable hardware interrupt */
  606. ath9k_hw_enable_interrupts(ah);
  607. spin_unlock(&sc->sc_pcu_lock);
  608. ath9k_ps_restore(sc);
  609. }
  610. irqreturn_t ath_isr(int irq, void *dev)
  611. {
  612. #define SCHED_INTR ( \
  613. ATH9K_INT_FATAL | \
  614. ATH9K_INT_BB_WATCHDOG | \
  615. ATH9K_INT_RXORN | \
  616. ATH9K_INT_RXEOL | \
  617. ATH9K_INT_RX | \
  618. ATH9K_INT_RXLP | \
  619. ATH9K_INT_RXHP | \
  620. ATH9K_INT_TX | \
  621. ATH9K_INT_BMISS | \
  622. ATH9K_INT_CST | \
  623. ATH9K_INT_TSFOOR | \
  624. ATH9K_INT_GENTIMER | \
  625. ATH9K_INT_MCI)
  626. struct ath_softc *sc = dev;
  627. struct ath_hw *ah = sc->sc_ah;
  628. struct ath_common *common = ath9k_hw_common(ah);
  629. enum ath9k_int status;
  630. bool sched = false;
  631. /*
  632. * The hardware is not ready/present, don't
  633. * touch anything. Note this can happen early
  634. * on if the IRQ is shared.
  635. */
  636. if (sc->sc_flags & SC_OP_INVALID)
  637. return IRQ_NONE;
  638. /* shared irq, not for us */
  639. if (!ath9k_hw_intrpend(ah))
  640. return IRQ_NONE;
  641. /*
  642. * Figure out the reason(s) for the interrupt. Note
  643. * that the hal returns a pseudo-ISR that may include
  644. * bits we haven't explicitly enabled so we mask the
  645. * value to insure we only process bits we requested.
  646. */
  647. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  648. status &= ah->imask; /* discard unasked-for bits */
  649. /*
  650. * If there are no status bits set, then this interrupt was not
  651. * for me (should have been caught above).
  652. */
  653. if (!status)
  654. return IRQ_NONE;
  655. /* Cache the status */
  656. sc->intrstatus = status;
  657. if (status & SCHED_INTR)
  658. sched = true;
  659. /*
  660. * If a FATAL or RXORN interrupt is received, we have to reset the
  661. * chip immediately.
  662. */
  663. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  664. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  665. goto chip_reset;
  666. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  667. (status & ATH9K_INT_BB_WATCHDOG)) {
  668. spin_lock(&common->cc_lock);
  669. ath_hw_cycle_counters_update(common);
  670. ar9003_hw_bb_watchdog_dbg_info(ah);
  671. spin_unlock(&common->cc_lock);
  672. goto chip_reset;
  673. }
  674. if (status & ATH9K_INT_SWBA)
  675. tasklet_schedule(&sc->bcon_tasklet);
  676. if (status & ATH9K_INT_TXURN)
  677. ath9k_hw_updatetxtriglevel(ah, true);
  678. if (status & ATH9K_INT_RXEOL) {
  679. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  680. ath9k_hw_set_interrupts(ah);
  681. }
  682. if (status & ATH9K_INT_MIB) {
  683. /*
  684. * Disable interrupts until we service the MIB
  685. * interrupt; otherwise it will continue to
  686. * fire.
  687. */
  688. ath9k_hw_disable_interrupts(ah);
  689. /*
  690. * Let the hal handle the event. We assume
  691. * it will clear whatever condition caused
  692. * the interrupt.
  693. */
  694. spin_lock(&common->cc_lock);
  695. ath9k_hw_proc_mib_event(ah);
  696. spin_unlock(&common->cc_lock);
  697. ath9k_hw_enable_interrupts(ah);
  698. }
  699. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  700. if (status & ATH9K_INT_TIM_TIMER) {
  701. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  702. goto chip_reset;
  703. /* Clear RxAbort bit so that we can
  704. * receive frames */
  705. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  706. ath9k_hw_setrxabort(sc->sc_ah, 0);
  707. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  708. }
  709. chip_reset:
  710. ath_debug_stat_interrupt(sc, status);
  711. if (sched) {
  712. /* turn off every interrupt */
  713. ath9k_hw_disable_interrupts(ah);
  714. tasklet_schedule(&sc->intr_tq);
  715. }
  716. return IRQ_HANDLED;
  717. #undef SCHED_INTR
  718. }
  719. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  720. {
  721. int r;
  722. ath9k_ps_wakeup(sc);
  723. r = ath_reset_internal(sc, NULL, retry_tx);
  724. if (retry_tx) {
  725. int i;
  726. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  727. if (ATH_TXQ_SETUP(sc, i)) {
  728. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  729. ath_txq_schedule(sc, &sc->tx.txq[i]);
  730. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  731. }
  732. }
  733. }
  734. ath9k_ps_restore(sc);
  735. return r;
  736. }
  737. void ath_reset_work(struct work_struct *work)
  738. {
  739. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  740. ath_reset(sc, true);
  741. }
  742. void ath_hw_check(struct work_struct *work)
  743. {
  744. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  745. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  746. unsigned long flags;
  747. int busy;
  748. ath9k_ps_wakeup(sc);
  749. if (ath9k_hw_check_alive(sc->sc_ah))
  750. goto out;
  751. spin_lock_irqsave(&common->cc_lock, flags);
  752. busy = ath_update_survey_stats(sc);
  753. spin_unlock_irqrestore(&common->cc_lock, flags);
  754. ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
  755. busy, sc->hw_busy_count + 1);
  756. if (busy >= 99) {
  757. if (++sc->hw_busy_count >= 3) {
  758. RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
  759. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  760. }
  761. } else if (busy >= 0)
  762. sc->hw_busy_count = 0;
  763. out:
  764. ath9k_ps_restore(sc);
  765. }
  766. static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
  767. {
  768. static int count;
  769. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  770. if (pll_sqsum >= 0x40000) {
  771. count++;
  772. if (count == 3) {
  773. /* Rx is hung for more than 500ms. Reset it */
  774. ath_dbg(common, RESET, "Possible RX hang, resetting\n");
  775. RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
  776. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  777. count = 0;
  778. }
  779. } else
  780. count = 0;
  781. }
  782. void ath_hw_pll_work(struct work_struct *work)
  783. {
  784. struct ath_softc *sc = container_of(work, struct ath_softc,
  785. hw_pll_work.work);
  786. u32 pll_sqsum;
  787. if (AR_SREV_9485(sc->sc_ah)) {
  788. ath9k_ps_wakeup(sc);
  789. pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
  790. ath9k_ps_restore(sc);
  791. ath_hw_pll_rx_hang_check(sc, pll_sqsum);
  792. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
  793. }
  794. }
  795. /**********************/
  796. /* mac80211 callbacks */
  797. /**********************/
  798. static int ath9k_start(struct ieee80211_hw *hw)
  799. {
  800. struct ath_softc *sc = hw->priv;
  801. struct ath_hw *ah = sc->sc_ah;
  802. struct ath_common *common = ath9k_hw_common(ah);
  803. struct ieee80211_channel *curchan = hw->conf.channel;
  804. struct ath9k_channel *init_channel;
  805. int r;
  806. ath_dbg(common, CONFIG,
  807. "Starting driver with initial channel: %d MHz\n",
  808. curchan->center_freq);
  809. ath9k_ps_wakeup(sc);
  810. mutex_lock(&sc->mutex);
  811. /* setup initial channel */
  812. sc->chan_idx = curchan->hw_value;
  813. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  814. /* Reset SERDES registers */
  815. ath9k_hw_configpcipowersave(ah, false);
  816. /*
  817. * The basic interface to setting the hardware in a good
  818. * state is ``reset''. On return the hardware is known to
  819. * be powered up and with interrupts disabled. This must
  820. * be followed by initialization of the appropriate bits
  821. * and then setup of the interrupt mask.
  822. */
  823. spin_lock_bh(&sc->sc_pcu_lock);
  824. atomic_set(&ah->intr_ref_cnt, -1);
  825. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  826. if (r) {
  827. ath_err(common,
  828. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  829. r, curchan->center_freq);
  830. spin_unlock_bh(&sc->sc_pcu_lock);
  831. goto mutex_unlock;
  832. }
  833. /* Setup our intr mask. */
  834. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  835. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  836. ATH9K_INT_GLOBAL;
  837. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  838. ah->imask |= ATH9K_INT_RXHP |
  839. ATH9K_INT_RXLP |
  840. ATH9K_INT_BB_WATCHDOG;
  841. else
  842. ah->imask |= ATH9K_INT_RX;
  843. ah->imask |= ATH9K_INT_GTT;
  844. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  845. ah->imask |= ATH9K_INT_CST;
  846. if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  847. ah->imask |= ATH9K_INT_MCI;
  848. sc->sc_flags &= ~SC_OP_INVALID;
  849. sc->sc_ah->is_monitoring = false;
  850. /* Disable BMISS interrupt when we're not associated */
  851. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  852. if (!ath_complete_reset(sc, false)) {
  853. r = -EIO;
  854. spin_unlock_bh(&sc->sc_pcu_lock);
  855. goto mutex_unlock;
  856. }
  857. if (ah->led_pin >= 0) {
  858. ath9k_hw_cfg_output(ah, ah->led_pin,
  859. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  860. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  861. }
  862. /*
  863. * Reset key cache to sane defaults (all entries cleared) instead of
  864. * semi-random values after suspend/resume.
  865. */
  866. ath9k_cmn_init_crypto(sc->sc_ah);
  867. spin_unlock_bh(&sc->sc_pcu_lock);
  868. ath9k_start_btcoex(sc);
  869. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  870. common->bus_ops->extn_synch_en(common);
  871. mutex_unlock:
  872. mutex_unlock(&sc->mutex);
  873. ath9k_ps_restore(sc);
  874. return r;
  875. }
  876. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  877. {
  878. struct ath_softc *sc = hw->priv;
  879. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  880. struct ath_tx_control txctl;
  881. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  882. if (sc->ps_enabled) {
  883. /*
  884. * mac80211 does not set PM field for normal data frames, so we
  885. * need to update that based on the current PS mode.
  886. */
  887. if (ieee80211_is_data(hdr->frame_control) &&
  888. !ieee80211_is_nullfunc(hdr->frame_control) &&
  889. !ieee80211_has_pm(hdr->frame_control)) {
  890. ath_dbg(common, PS,
  891. "Add PM=1 for a TX frame while in PS mode\n");
  892. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  893. }
  894. }
  895. /*
  896. * Cannot tx while the hardware is in full sleep, it first needs a full
  897. * chip reset to recover from that
  898. */
  899. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
  900. goto exit;
  901. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  902. /*
  903. * We are using PS-Poll and mac80211 can request TX while in
  904. * power save mode. Need to wake up hardware for the TX to be
  905. * completed and if needed, also for RX of buffered frames.
  906. */
  907. ath9k_ps_wakeup(sc);
  908. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  909. ath9k_hw_setrxabort(sc->sc_ah, 0);
  910. if (ieee80211_is_pspoll(hdr->frame_control)) {
  911. ath_dbg(common, PS,
  912. "Sending PS-Poll to pick a buffered frame\n");
  913. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  914. } else {
  915. ath_dbg(common, PS, "Wake up to complete TX\n");
  916. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  917. }
  918. /*
  919. * The actual restore operation will happen only after
  920. * the sc_flags bit is cleared. We are just dropping
  921. * the ps_usecount here.
  922. */
  923. ath9k_ps_restore(sc);
  924. }
  925. memset(&txctl, 0, sizeof(struct ath_tx_control));
  926. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  927. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  928. if (ath_tx_start(hw, skb, &txctl) != 0) {
  929. ath_dbg(common, XMIT, "TX failed\n");
  930. goto exit;
  931. }
  932. return;
  933. exit:
  934. dev_kfree_skb_any(skb);
  935. }
  936. static void ath9k_stop(struct ieee80211_hw *hw)
  937. {
  938. struct ath_softc *sc = hw->priv;
  939. struct ath_hw *ah = sc->sc_ah;
  940. struct ath_common *common = ath9k_hw_common(ah);
  941. bool prev_idle;
  942. mutex_lock(&sc->mutex);
  943. ath_cancel_work(sc);
  944. if (sc->sc_flags & SC_OP_INVALID) {
  945. ath_dbg(common, ANY, "Device not present\n");
  946. mutex_unlock(&sc->mutex);
  947. return;
  948. }
  949. /* Ensure HW is awake when we try to shut it down. */
  950. ath9k_ps_wakeup(sc);
  951. ath9k_stop_btcoex(sc);
  952. spin_lock_bh(&sc->sc_pcu_lock);
  953. /* prevent tasklets to enable interrupts once we disable them */
  954. ah->imask &= ~ATH9K_INT_GLOBAL;
  955. /* make sure h/w will not generate any interrupt
  956. * before setting the invalid flag. */
  957. ath9k_hw_disable_interrupts(ah);
  958. spin_unlock_bh(&sc->sc_pcu_lock);
  959. /* we can now sync irq and kill any running tasklets, since we already
  960. * disabled interrupts and not holding a spin lock */
  961. synchronize_irq(sc->irq);
  962. tasklet_kill(&sc->intr_tq);
  963. tasklet_kill(&sc->bcon_tasklet);
  964. prev_idle = sc->ps_idle;
  965. sc->ps_idle = true;
  966. spin_lock_bh(&sc->sc_pcu_lock);
  967. if (ah->led_pin >= 0) {
  968. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  969. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  970. }
  971. ath_prepare_reset(sc, false, true);
  972. if (sc->rx.frag) {
  973. dev_kfree_skb_any(sc->rx.frag);
  974. sc->rx.frag = NULL;
  975. }
  976. if (!ah->curchan)
  977. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  978. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  979. ath9k_hw_phy_disable(ah);
  980. ath9k_hw_configpcipowersave(ah, true);
  981. spin_unlock_bh(&sc->sc_pcu_lock);
  982. ath9k_ps_restore(sc);
  983. sc->sc_flags |= SC_OP_INVALID;
  984. sc->ps_idle = prev_idle;
  985. mutex_unlock(&sc->mutex);
  986. ath_dbg(common, CONFIG, "Driver halt\n");
  987. }
  988. bool ath9k_uses_beacons(int type)
  989. {
  990. switch (type) {
  991. case NL80211_IFTYPE_AP:
  992. case NL80211_IFTYPE_ADHOC:
  993. case NL80211_IFTYPE_MESH_POINT:
  994. return true;
  995. default:
  996. return false;
  997. }
  998. }
  999. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1000. struct ieee80211_vif *vif)
  1001. {
  1002. struct ath_vif *avp = (void *)vif->drv_priv;
  1003. ath9k_set_beaconing_status(sc, false);
  1004. ath_beacon_return(sc, avp);
  1005. ath9k_set_beaconing_status(sc, true);
  1006. sc->sc_flags &= ~SC_OP_BEACONS;
  1007. }
  1008. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1009. {
  1010. struct ath9k_vif_iter_data *iter_data = data;
  1011. int i;
  1012. if (iter_data->hw_macaddr)
  1013. for (i = 0; i < ETH_ALEN; i++)
  1014. iter_data->mask[i] &=
  1015. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1016. switch (vif->type) {
  1017. case NL80211_IFTYPE_AP:
  1018. iter_data->naps++;
  1019. break;
  1020. case NL80211_IFTYPE_STATION:
  1021. iter_data->nstations++;
  1022. break;
  1023. case NL80211_IFTYPE_ADHOC:
  1024. iter_data->nadhocs++;
  1025. break;
  1026. case NL80211_IFTYPE_MESH_POINT:
  1027. iter_data->nmeshes++;
  1028. break;
  1029. case NL80211_IFTYPE_WDS:
  1030. iter_data->nwds++;
  1031. break;
  1032. default:
  1033. iter_data->nothers++;
  1034. break;
  1035. }
  1036. }
  1037. /* Called with sc->mutex held. */
  1038. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1039. struct ieee80211_vif *vif,
  1040. struct ath9k_vif_iter_data *iter_data)
  1041. {
  1042. struct ath_softc *sc = hw->priv;
  1043. struct ath_hw *ah = sc->sc_ah;
  1044. struct ath_common *common = ath9k_hw_common(ah);
  1045. /*
  1046. * Use the hardware MAC address as reference, the hardware uses it
  1047. * together with the BSSID mask when matching addresses.
  1048. */
  1049. memset(iter_data, 0, sizeof(*iter_data));
  1050. iter_data->hw_macaddr = common->macaddr;
  1051. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1052. if (vif)
  1053. ath9k_vif_iter(iter_data, vif->addr, vif);
  1054. /* Get list of all active MAC addresses */
  1055. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1056. iter_data);
  1057. }
  1058. /* Called with sc->mutex held. */
  1059. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1060. struct ieee80211_vif *vif)
  1061. {
  1062. struct ath_softc *sc = hw->priv;
  1063. struct ath_hw *ah = sc->sc_ah;
  1064. struct ath_common *common = ath9k_hw_common(ah);
  1065. struct ath9k_vif_iter_data iter_data;
  1066. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1067. /* Set BSSID mask. */
  1068. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1069. ath_hw_setbssidmask(common);
  1070. /* Set op-mode & TSF */
  1071. if (iter_data.naps > 0) {
  1072. ath9k_hw_set_tsfadjust(ah, 1);
  1073. sc->sc_flags |= SC_OP_TSF_RESET;
  1074. ah->opmode = NL80211_IFTYPE_AP;
  1075. } else {
  1076. ath9k_hw_set_tsfadjust(ah, 0);
  1077. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1078. if (iter_data.nmeshes)
  1079. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  1080. else if (iter_data.nwds)
  1081. ah->opmode = NL80211_IFTYPE_AP;
  1082. else if (iter_data.nadhocs)
  1083. ah->opmode = NL80211_IFTYPE_ADHOC;
  1084. else
  1085. ah->opmode = NL80211_IFTYPE_STATION;
  1086. }
  1087. /*
  1088. * Enable MIB interrupts when there are hardware phy counters.
  1089. */
  1090. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1091. if (ah->config.enable_ani)
  1092. ah->imask |= ATH9K_INT_MIB;
  1093. ah->imask |= ATH9K_INT_TSFOOR;
  1094. } else {
  1095. ah->imask &= ~ATH9K_INT_MIB;
  1096. ah->imask &= ~ATH9K_INT_TSFOOR;
  1097. }
  1098. ath9k_hw_set_interrupts(ah);
  1099. /* Set up ANI */
  1100. if (iter_data.naps > 0) {
  1101. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1102. if (!common->disable_ani) {
  1103. sc->sc_flags |= SC_OP_ANI_RUN;
  1104. ath_start_ani(common);
  1105. }
  1106. } else {
  1107. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1108. del_timer_sync(&common->ani.timer);
  1109. }
  1110. }
  1111. /* Called with sc->mutex held, vif counts set up properly. */
  1112. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1113. struct ieee80211_vif *vif)
  1114. {
  1115. struct ath_softc *sc = hw->priv;
  1116. ath9k_calculate_summary_state(hw, vif);
  1117. if (ath9k_uses_beacons(vif->type)) {
  1118. int error;
  1119. /* This may fail because upper levels do not have beacons
  1120. * properly configured yet. That's OK, we assume it
  1121. * will be properly configured and then we will be notified
  1122. * in the info_changed method and set up beacons properly
  1123. * there.
  1124. */
  1125. ath9k_set_beaconing_status(sc, false);
  1126. error = ath_beacon_alloc(sc, vif);
  1127. if (!error)
  1128. ath_beacon_config(sc, vif);
  1129. ath9k_set_beaconing_status(sc, true);
  1130. }
  1131. }
  1132. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1133. struct ieee80211_vif *vif)
  1134. {
  1135. struct ath_softc *sc = hw->priv;
  1136. struct ath_hw *ah = sc->sc_ah;
  1137. struct ath_common *common = ath9k_hw_common(ah);
  1138. int ret = 0;
  1139. ath9k_ps_wakeup(sc);
  1140. mutex_lock(&sc->mutex);
  1141. switch (vif->type) {
  1142. case NL80211_IFTYPE_STATION:
  1143. case NL80211_IFTYPE_WDS:
  1144. case NL80211_IFTYPE_ADHOC:
  1145. case NL80211_IFTYPE_AP:
  1146. case NL80211_IFTYPE_MESH_POINT:
  1147. break;
  1148. default:
  1149. ath_err(common, "Interface type %d not yet supported\n",
  1150. vif->type);
  1151. ret = -EOPNOTSUPP;
  1152. goto out;
  1153. }
  1154. if (ath9k_uses_beacons(vif->type)) {
  1155. if (sc->nbcnvifs >= ATH_BCBUF) {
  1156. ath_err(common, "Not enough beacon buffers when adding"
  1157. " new interface of type: %i\n",
  1158. vif->type);
  1159. ret = -ENOBUFS;
  1160. goto out;
  1161. }
  1162. }
  1163. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1164. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1165. sc->nvifs > 0)) {
  1166. ath_err(common, "Cannot create ADHOC interface when other"
  1167. " interfaces already exist.\n");
  1168. ret = -EINVAL;
  1169. goto out;
  1170. }
  1171. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  1172. sc->nvifs++;
  1173. ath9k_do_vif_add_setup(hw, vif);
  1174. out:
  1175. mutex_unlock(&sc->mutex);
  1176. ath9k_ps_restore(sc);
  1177. return ret;
  1178. }
  1179. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1180. struct ieee80211_vif *vif,
  1181. enum nl80211_iftype new_type,
  1182. bool p2p)
  1183. {
  1184. struct ath_softc *sc = hw->priv;
  1185. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1186. int ret = 0;
  1187. ath_dbg(common, CONFIG, "Change Interface\n");
  1188. mutex_lock(&sc->mutex);
  1189. ath9k_ps_wakeup(sc);
  1190. /* See if new interface type is valid. */
  1191. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1192. (sc->nvifs > 1)) {
  1193. ath_err(common, "When using ADHOC, it must be the only"
  1194. " interface.\n");
  1195. ret = -EINVAL;
  1196. goto out;
  1197. }
  1198. if (ath9k_uses_beacons(new_type) &&
  1199. !ath9k_uses_beacons(vif->type)) {
  1200. if (sc->nbcnvifs >= ATH_BCBUF) {
  1201. ath_err(common, "No beacon slot available\n");
  1202. ret = -ENOBUFS;
  1203. goto out;
  1204. }
  1205. }
  1206. /* Clean up old vif stuff */
  1207. if (ath9k_uses_beacons(vif->type))
  1208. ath9k_reclaim_beacon(sc, vif);
  1209. /* Add new settings */
  1210. vif->type = new_type;
  1211. vif->p2p = p2p;
  1212. ath9k_do_vif_add_setup(hw, vif);
  1213. out:
  1214. ath9k_ps_restore(sc);
  1215. mutex_unlock(&sc->mutex);
  1216. return ret;
  1217. }
  1218. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1219. struct ieee80211_vif *vif)
  1220. {
  1221. struct ath_softc *sc = hw->priv;
  1222. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1223. ath_dbg(common, CONFIG, "Detach Interface\n");
  1224. ath9k_ps_wakeup(sc);
  1225. mutex_lock(&sc->mutex);
  1226. sc->nvifs--;
  1227. /* Reclaim beacon resources */
  1228. if (ath9k_uses_beacons(vif->type))
  1229. ath9k_reclaim_beacon(sc, vif);
  1230. ath9k_calculate_summary_state(hw, NULL);
  1231. mutex_unlock(&sc->mutex);
  1232. ath9k_ps_restore(sc);
  1233. }
  1234. static void ath9k_enable_ps(struct ath_softc *sc)
  1235. {
  1236. struct ath_hw *ah = sc->sc_ah;
  1237. sc->ps_enabled = true;
  1238. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1239. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1240. ah->imask |= ATH9K_INT_TIM_TIMER;
  1241. ath9k_hw_set_interrupts(ah);
  1242. }
  1243. ath9k_hw_setrxabort(ah, 1);
  1244. }
  1245. }
  1246. static void ath9k_disable_ps(struct ath_softc *sc)
  1247. {
  1248. struct ath_hw *ah = sc->sc_ah;
  1249. sc->ps_enabled = false;
  1250. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1251. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1252. ath9k_hw_setrxabort(ah, 0);
  1253. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1254. PS_WAIT_FOR_CAB |
  1255. PS_WAIT_FOR_PSPOLL_DATA |
  1256. PS_WAIT_FOR_TX_ACK);
  1257. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1258. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1259. ath9k_hw_set_interrupts(ah);
  1260. }
  1261. }
  1262. }
  1263. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1264. {
  1265. struct ath_softc *sc = hw->priv;
  1266. struct ath_hw *ah = sc->sc_ah;
  1267. struct ath_common *common = ath9k_hw_common(ah);
  1268. struct ieee80211_conf *conf = &hw->conf;
  1269. ath9k_ps_wakeup(sc);
  1270. mutex_lock(&sc->mutex);
  1271. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1272. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1273. if (sc->ps_idle)
  1274. ath_cancel_work(sc);
  1275. }
  1276. /*
  1277. * We just prepare to enable PS. We have to wait until our AP has
  1278. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1279. * those ACKs and end up retransmitting the same null data frames.
  1280. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1281. */
  1282. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1283. unsigned long flags;
  1284. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1285. if (conf->flags & IEEE80211_CONF_PS)
  1286. ath9k_enable_ps(sc);
  1287. else
  1288. ath9k_disable_ps(sc);
  1289. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1290. }
  1291. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1292. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1293. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  1294. sc->sc_ah->is_monitoring = true;
  1295. } else {
  1296. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  1297. sc->sc_ah->is_monitoring = false;
  1298. }
  1299. }
  1300. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1301. struct ieee80211_channel *curchan = hw->conf.channel;
  1302. int pos = curchan->hw_value;
  1303. int old_pos = -1;
  1304. unsigned long flags;
  1305. if (ah->curchan)
  1306. old_pos = ah->curchan - &ah->channels[0];
  1307. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1308. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1309. else
  1310. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1311. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  1312. curchan->center_freq, conf->channel_type);
  1313. /* update survey stats for the old channel before switching */
  1314. spin_lock_irqsave(&common->cc_lock, flags);
  1315. ath_update_survey_stats(sc);
  1316. spin_unlock_irqrestore(&common->cc_lock, flags);
  1317. /*
  1318. * Preserve the current channel values, before updating
  1319. * the same channel
  1320. */
  1321. if (ah->curchan && (old_pos == pos))
  1322. ath9k_hw_getnf(ah, ah->curchan);
  1323. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1324. curchan, conf->channel_type);
  1325. /*
  1326. * If the operating channel changes, change the survey in-use flags
  1327. * along with it.
  1328. * Reset the survey data for the new channel, unless we're switching
  1329. * back to the operating channel from an off-channel operation.
  1330. */
  1331. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1332. sc->cur_survey != &sc->survey[pos]) {
  1333. if (sc->cur_survey)
  1334. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1335. sc->cur_survey = &sc->survey[pos];
  1336. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1337. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1338. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1339. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1340. }
  1341. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1342. ath_err(common, "Unable to set channel\n");
  1343. mutex_unlock(&sc->mutex);
  1344. return -EINVAL;
  1345. }
  1346. /*
  1347. * The most recent snapshot of channel->noisefloor for the old
  1348. * channel is only available after the hardware reset. Copy it to
  1349. * the survey stats now.
  1350. */
  1351. if (old_pos >= 0)
  1352. ath_update_survey_nf(sc, old_pos);
  1353. }
  1354. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1355. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1356. sc->config.txpowlimit = 2 * conf->power_level;
  1357. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1358. sc->config.txpowlimit, &sc->curtxpow);
  1359. }
  1360. mutex_unlock(&sc->mutex);
  1361. ath9k_ps_restore(sc);
  1362. return 0;
  1363. }
  1364. #define SUPPORTED_FILTERS \
  1365. (FIF_PROMISC_IN_BSS | \
  1366. FIF_ALLMULTI | \
  1367. FIF_CONTROL | \
  1368. FIF_PSPOLL | \
  1369. FIF_OTHER_BSS | \
  1370. FIF_BCN_PRBRESP_PROMISC | \
  1371. FIF_PROBE_REQ | \
  1372. FIF_FCSFAIL)
  1373. /* FIXME: sc->sc_full_reset ? */
  1374. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1375. unsigned int changed_flags,
  1376. unsigned int *total_flags,
  1377. u64 multicast)
  1378. {
  1379. struct ath_softc *sc = hw->priv;
  1380. u32 rfilt;
  1381. changed_flags &= SUPPORTED_FILTERS;
  1382. *total_flags &= SUPPORTED_FILTERS;
  1383. sc->rx.rxfilter = *total_flags;
  1384. ath9k_ps_wakeup(sc);
  1385. rfilt = ath_calcrxfilter(sc);
  1386. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1387. ath9k_ps_restore(sc);
  1388. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1389. rfilt);
  1390. }
  1391. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1392. struct ieee80211_vif *vif,
  1393. struct ieee80211_sta *sta)
  1394. {
  1395. struct ath_softc *sc = hw->priv;
  1396. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1397. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1398. struct ieee80211_key_conf ps_key = { };
  1399. ath_node_attach(sc, sta, vif);
  1400. if (vif->type != NL80211_IFTYPE_AP &&
  1401. vif->type != NL80211_IFTYPE_AP_VLAN)
  1402. return 0;
  1403. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1404. return 0;
  1405. }
  1406. static void ath9k_del_ps_key(struct ath_softc *sc,
  1407. struct ieee80211_vif *vif,
  1408. struct ieee80211_sta *sta)
  1409. {
  1410. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1411. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1412. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1413. if (!an->ps_key)
  1414. return;
  1415. ath_key_delete(common, &ps_key);
  1416. }
  1417. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1418. struct ieee80211_vif *vif,
  1419. struct ieee80211_sta *sta)
  1420. {
  1421. struct ath_softc *sc = hw->priv;
  1422. ath9k_del_ps_key(sc, vif, sta);
  1423. ath_node_detach(sc, sta);
  1424. return 0;
  1425. }
  1426. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1427. struct ieee80211_vif *vif,
  1428. enum sta_notify_cmd cmd,
  1429. struct ieee80211_sta *sta)
  1430. {
  1431. struct ath_softc *sc = hw->priv;
  1432. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1433. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1434. return;
  1435. switch (cmd) {
  1436. case STA_NOTIFY_SLEEP:
  1437. an->sleeping = true;
  1438. ath_tx_aggr_sleep(sta, sc, an);
  1439. break;
  1440. case STA_NOTIFY_AWAKE:
  1441. an->sleeping = false;
  1442. ath_tx_aggr_wakeup(sc, an);
  1443. break;
  1444. }
  1445. }
  1446. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1447. struct ieee80211_vif *vif, u16 queue,
  1448. const struct ieee80211_tx_queue_params *params)
  1449. {
  1450. struct ath_softc *sc = hw->priv;
  1451. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1452. struct ath_txq *txq;
  1453. struct ath9k_tx_queue_info qi;
  1454. int ret = 0;
  1455. if (queue >= WME_NUM_AC)
  1456. return 0;
  1457. txq = sc->tx.txq_map[queue];
  1458. ath9k_ps_wakeup(sc);
  1459. mutex_lock(&sc->mutex);
  1460. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1461. qi.tqi_aifs = params->aifs;
  1462. qi.tqi_cwmin = params->cw_min;
  1463. qi.tqi_cwmax = params->cw_max;
  1464. qi.tqi_burstTime = params->txop;
  1465. ath_dbg(common, CONFIG,
  1466. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1467. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1468. params->cw_max, params->txop);
  1469. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1470. if (ret)
  1471. ath_err(common, "TXQ Update failed\n");
  1472. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1473. if (queue == WME_AC_BE && !ret)
  1474. ath_beaconq_config(sc);
  1475. mutex_unlock(&sc->mutex);
  1476. ath9k_ps_restore(sc);
  1477. return ret;
  1478. }
  1479. static int ath9k_set_key(struct ieee80211_hw *hw,
  1480. enum set_key_cmd cmd,
  1481. struct ieee80211_vif *vif,
  1482. struct ieee80211_sta *sta,
  1483. struct ieee80211_key_conf *key)
  1484. {
  1485. struct ath_softc *sc = hw->priv;
  1486. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1487. int ret = 0;
  1488. if (ath9k_modparam_nohwcrypt)
  1489. return -ENOSPC;
  1490. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1491. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1492. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1493. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1494. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1495. /*
  1496. * For now, disable hw crypto for the RSN IBSS group keys. This
  1497. * could be optimized in the future to use a modified key cache
  1498. * design to support per-STA RX GTK, but until that gets
  1499. * implemented, use of software crypto for group addressed
  1500. * frames is a acceptable to allow RSN IBSS to be used.
  1501. */
  1502. return -EOPNOTSUPP;
  1503. }
  1504. mutex_lock(&sc->mutex);
  1505. ath9k_ps_wakeup(sc);
  1506. ath_dbg(common, CONFIG, "Set HW Key\n");
  1507. switch (cmd) {
  1508. case SET_KEY:
  1509. if (sta)
  1510. ath9k_del_ps_key(sc, vif, sta);
  1511. ret = ath_key_config(common, vif, sta, key);
  1512. if (ret >= 0) {
  1513. key->hw_key_idx = ret;
  1514. /* push IV and Michael MIC generation to stack */
  1515. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1516. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1517. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1518. if (sc->sc_ah->sw_mgmt_crypto &&
  1519. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1520. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1521. ret = 0;
  1522. }
  1523. break;
  1524. case DISABLE_KEY:
  1525. ath_key_delete(common, key);
  1526. break;
  1527. default:
  1528. ret = -EINVAL;
  1529. }
  1530. ath9k_ps_restore(sc);
  1531. mutex_unlock(&sc->mutex);
  1532. return ret;
  1533. }
  1534. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1535. {
  1536. struct ath_softc *sc = data;
  1537. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1538. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1539. struct ath_vif *avp = (void *)vif->drv_priv;
  1540. /*
  1541. * Skip iteration if primary station vif's bss info
  1542. * was not changed
  1543. */
  1544. if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
  1545. return;
  1546. if (bss_conf->assoc) {
  1547. sc->sc_flags |= SC_OP_PRIM_STA_VIF;
  1548. avp->primary_sta_vif = true;
  1549. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1550. common->curaid = bss_conf->aid;
  1551. ath9k_hw_write_associd(sc->sc_ah);
  1552. ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
  1553. bss_conf->aid, common->curbssid);
  1554. ath_beacon_config(sc, vif);
  1555. /*
  1556. * Request a re-configuration of Beacon related timers
  1557. * on the receipt of the first Beacon frame (i.e.,
  1558. * after time sync with the AP).
  1559. */
  1560. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1561. /* Reset rssi stats */
  1562. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1563. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1564. if (!common->disable_ani) {
  1565. sc->sc_flags |= SC_OP_ANI_RUN;
  1566. ath_start_ani(common);
  1567. }
  1568. }
  1569. }
  1570. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1571. {
  1572. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1573. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1574. struct ath_vif *avp = (void *)vif->drv_priv;
  1575. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1576. return;
  1577. /* Reconfigure bss info */
  1578. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1579. ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
  1580. common->curaid, common->curbssid);
  1581. sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
  1582. avp->primary_sta_vif = false;
  1583. memset(common->curbssid, 0, ETH_ALEN);
  1584. common->curaid = 0;
  1585. }
  1586. ieee80211_iterate_active_interfaces_atomic(
  1587. sc->hw, ath9k_bss_iter, sc);
  1588. /*
  1589. * None of station vifs are associated.
  1590. * Clear bssid & aid
  1591. */
  1592. if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
  1593. ath9k_hw_write_associd(sc->sc_ah);
  1594. /* Stop ANI */
  1595. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1596. del_timer_sync(&common->ani.timer);
  1597. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1598. }
  1599. }
  1600. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1601. struct ieee80211_vif *vif,
  1602. struct ieee80211_bss_conf *bss_conf,
  1603. u32 changed)
  1604. {
  1605. struct ath_softc *sc = hw->priv;
  1606. struct ath_hw *ah = sc->sc_ah;
  1607. struct ath_common *common = ath9k_hw_common(ah);
  1608. struct ath_vif *avp = (void *)vif->drv_priv;
  1609. int slottime;
  1610. int error;
  1611. ath9k_ps_wakeup(sc);
  1612. mutex_lock(&sc->mutex);
  1613. if (changed & BSS_CHANGED_BSSID) {
  1614. ath9k_config_bss(sc, vif);
  1615. ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
  1616. common->curbssid, common->curaid);
  1617. }
  1618. if (changed & BSS_CHANGED_IBSS) {
  1619. /* There can be only one vif available */
  1620. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1621. common->curaid = bss_conf->aid;
  1622. ath9k_hw_write_associd(sc->sc_ah);
  1623. if (bss_conf->ibss_joined) {
  1624. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1625. if (!common->disable_ani) {
  1626. sc->sc_flags |= SC_OP_ANI_RUN;
  1627. ath_start_ani(common);
  1628. }
  1629. } else {
  1630. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1631. del_timer_sync(&common->ani.timer);
  1632. }
  1633. }
  1634. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1635. if ((changed & BSS_CHANGED_BEACON) ||
  1636. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1637. ath9k_set_beaconing_status(sc, false);
  1638. error = ath_beacon_alloc(sc, vif);
  1639. if (!error)
  1640. ath_beacon_config(sc, vif);
  1641. ath9k_set_beaconing_status(sc, true);
  1642. }
  1643. if (changed & BSS_CHANGED_ERP_SLOT) {
  1644. if (bss_conf->use_short_slot)
  1645. slottime = 9;
  1646. else
  1647. slottime = 20;
  1648. if (vif->type == NL80211_IFTYPE_AP) {
  1649. /*
  1650. * Defer update, so that connected stations can adjust
  1651. * their settings at the same time.
  1652. * See beacon.c for more details
  1653. */
  1654. sc->beacon.slottime = slottime;
  1655. sc->beacon.updateslot = UPDATE;
  1656. } else {
  1657. ah->slottime = slottime;
  1658. ath9k_hw_init_global_settings(ah);
  1659. }
  1660. }
  1661. /* Disable transmission of beacons */
  1662. if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
  1663. !bss_conf->enable_beacon) {
  1664. ath9k_set_beaconing_status(sc, false);
  1665. avp->is_bslot_active = false;
  1666. ath9k_set_beaconing_status(sc, true);
  1667. }
  1668. if (changed & BSS_CHANGED_BEACON_INT) {
  1669. /*
  1670. * In case of AP mode, the HW TSF has to be reset
  1671. * when the beacon interval changes.
  1672. */
  1673. if (vif->type == NL80211_IFTYPE_AP) {
  1674. sc->sc_flags |= SC_OP_TSF_RESET;
  1675. ath9k_set_beaconing_status(sc, false);
  1676. error = ath_beacon_alloc(sc, vif);
  1677. if (!error)
  1678. ath_beacon_config(sc, vif);
  1679. ath9k_set_beaconing_status(sc, true);
  1680. } else
  1681. ath_beacon_config(sc, vif);
  1682. }
  1683. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1684. ath_dbg(common, CONFIG, "BSS Changed PREAMBLE %d\n",
  1685. bss_conf->use_short_preamble);
  1686. if (bss_conf->use_short_preamble)
  1687. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1688. else
  1689. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1690. }
  1691. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1692. ath_dbg(common, CONFIG, "BSS Changed CTS PROT %d\n",
  1693. bss_conf->use_cts_prot);
  1694. if (bss_conf->use_cts_prot &&
  1695. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1696. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1697. else
  1698. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1699. }
  1700. mutex_unlock(&sc->mutex);
  1701. ath9k_ps_restore(sc);
  1702. }
  1703. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1704. {
  1705. struct ath_softc *sc = hw->priv;
  1706. u64 tsf;
  1707. mutex_lock(&sc->mutex);
  1708. ath9k_ps_wakeup(sc);
  1709. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1710. ath9k_ps_restore(sc);
  1711. mutex_unlock(&sc->mutex);
  1712. return tsf;
  1713. }
  1714. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1715. struct ieee80211_vif *vif,
  1716. u64 tsf)
  1717. {
  1718. struct ath_softc *sc = hw->priv;
  1719. mutex_lock(&sc->mutex);
  1720. ath9k_ps_wakeup(sc);
  1721. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1722. ath9k_ps_restore(sc);
  1723. mutex_unlock(&sc->mutex);
  1724. }
  1725. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1726. {
  1727. struct ath_softc *sc = hw->priv;
  1728. mutex_lock(&sc->mutex);
  1729. ath9k_ps_wakeup(sc);
  1730. ath9k_hw_reset_tsf(sc->sc_ah);
  1731. ath9k_ps_restore(sc);
  1732. mutex_unlock(&sc->mutex);
  1733. }
  1734. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1735. struct ieee80211_vif *vif,
  1736. enum ieee80211_ampdu_mlme_action action,
  1737. struct ieee80211_sta *sta,
  1738. u16 tid, u16 *ssn, u8 buf_size)
  1739. {
  1740. struct ath_softc *sc = hw->priv;
  1741. int ret = 0;
  1742. local_bh_disable();
  1743. switch (action) {
  1744. case IEEE80211_AMPDU_RX_START:
  1745. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1746. ret = -ENOTSUPP;
  1747. break;
  1748. case IEEE80211_AMPDU_RX_STOP:
  1749. break;
  1750. case IEEE80211_AMPDU_TX_START:
  1751. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1752. return -EOPNOTSUPP;
  1753. ath9k_ps_wakeup(sc);
  1754. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1755. if (!ret)
  1756. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1757. ath9k_ps_restore(sc);
  1758. break;
  1759. case IEEE80211_AMPDU_TX_STOP:
  1760. ath9k_ps_wakeup(sc);
  1761. ath_tx_aggr_stop(sc, sta, tid);
  1762. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1763. ath9k_ps_restore(sc);
  1764. break;
  1765. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1766. ath9k_ps_wakeup(sc);
  1767. ath_tx_aggr_resume(sc, sta, tid);
  1768. ath9k_ps_restore(sc);
  1769. break;
  1770. default:
  1771. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1772. }
  1773. local_bh_enable();
  1774. return ret;
  1775. }
  1776. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1777. struct survey_info *survey)
  1778. {
  1779. struct ath_softc *sc = hw->priv;
  1780. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1781. struct ieee80211_supported_band *sband;
  1782. struct ieee80211_channel *chan;
  1783. unsigned long flags;
  1784. int pos;
  1785. spin_lock_irqsave(&common->cc_lock, flags);
  1786. if (idx == 0)
  1787. ath_update_survey_stats(sc);
  1788. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1789. if (sband && idx >= sband->n_channels) {
  1790. idx -= sband->n_channels;
  1791. sband = NULL;
  1792. }
  1793. if (!sband)
  1794. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1795. if (!sband || idx >= sband->n_channels) {
  1796. spin_unlock_irqrestore(&common->cc_lock, flags);
  1797. return -ENOENT;
  1798. }
  1799. chan = &sband->channels[idx];
  1800. pos = chan->hw_value;
  1801. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1802. survey->channel = chan;
  1803. spin_unlock_irqrestore(&common->cc_lock, flags);
  1804. return 0;
  1805. }
  1806. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1807. {
  1808. struct ath_softc *sc = hw->priv;
  1809. struct ath_hw *ah = sc->sc_ah;
  1810. mutex_lock(&sc->mutex);
  1811. ah->coverage_class = coverage_class;
  1812. ath9k_ps_wakeup(sc);
  1813. ath9k_hw_init_global_settings(ah);
  1814. ath9k_ps_restore(sc);
  1815. mutex_unlock(&sc->mutex);
  1816. }
  1817. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1818. {
  1819. struct ath_softc *sc = hw->priv;
  1820. struct ath_hw *ah = sc->sc_ah;
  1821. struct ath_common *common = ath9k_hw_common(ah);
  1822. int timeout = 200; /* ms */
  1823. int i, j;
  1824. bool drain_txq;
  1825. mutex_lock(&sc->mutex);
  1826. cancel_delayed_work_sync(&sc->tx_complete_work);
  1827. if (ah->ah_flags & AH_UNPLUGGED) {
  1828. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1829. mutex_unlock(&sc->mutex);
  1830. return;
  1831. }
  1832. if (sc->sc_flags & SC_OP_INVALID) {
  1833. ath_dbg(common, ANY, "Device not present\n");
  1834. mutex_unlock(&sc->mutex);
  1835. return;
  1836. }
  1837. for (j = 0; j < timeout; j++) {
  1838. bool npend = false;
  1839. if (j)
  1840. usleep_range(1000, 2000);
  1841. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1842. if (!ATH_TXQ_SETUP(sc, i))
  1843. continue;
  1844. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1845. if (npend)
  1846. break;
  1847. }
  1848. if (!npend)
  1849. break;
  1850. }
  1851. if (drop) {
  1852. ath9k_ps_wakeup(sc);
  1853. spin_lock_bh(&sc->sc_pcu_lock);
  1854. drain_txq = ath_drain_all_txq(sc, false);
  1855. spin_unlock_bh(&sc->sc_pcu_lock);
  1856. if (!drain_txq)
  1857. ath_reset(sc, false);
  1858. ath9k_ps_restore(sc);
  1859. ieee80211_wake_queues(hw);
  1860. }
  1861. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1862. mutex_unlock(&sc->mutex);
  1863. }
  1864. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1865. {
  1866. struct ath_softc *sc = hw->priv;
  1867. int i;
  1868. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1869. if (!ATH_TXQ_SETUP(sc, i))
  1870. continue;
  1871. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1872. return true;
  1873. }
  1874. return false;
  1875. }
  1876. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1877. {
  1878. struct ath_softc *sc = hw->priv;
  1879. struct ath_hw *ah = sc->sc_ah;
  1880. struct ieee80211_vif *vif;
  1881. struct ath_vif *avp;
  1882. struct ath_buf *bf;
  1883. struct ath_tx_status ts;
  1884. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1885. int status;
  1886. vif = sc->beacon.bslot[0];
  1887. if (!vif)
  1888. return 0;
  1889. avp = (void *)vif->drv_priv;
  1890. if (!avp->is_bslot_active)
  1891. return 0;
  1892. if (!sc->beacon.tx_processed && !edma) {
  1893. tasklet_disable(&sc->bcon_tasklet);
  1894. bf = avp->av_bcbuf;
  1895. if (!bf || !bf->bf_mpdu)
  1896. goto skip;
  1897. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1898. if (status == -EINPROGRESS)
  1899. goto skip;
  1900. sc->beacon.tx_processed = true;
  1901. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1902. skip:
  1903. tasklet_enable(&sc->bcon_tasklet);
  1904. }
  1905. return sc->beacon.tx_last;
  1906. }
  1907. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1908. struct ieee80211_low_level_stats *stats)
  1909. {
  1910. struct ath_softc *sc = hw->priv;
  1911. struct ath_hw *ah = sc->sc_ah;
  1912. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1913. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1914. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1915. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1916. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1917. return 0;
  1918. }
  1919. static u32 fill_chainmask(u32 cap, u32 new)
  1920. {
  1921. u32 filled = 0;
  1922. int i;
  1923. for (i = 0; cap && new; i++, cap >>= 1) {
  1924. if (!(cap & BIT(0)))
  1925. continue;
  1926. if (new & BIT(0))
  1927. filled |= BIT(i);
  1928. new >>= 1;
  1929. }
  1930. return filled;
  1931. }
  1932. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1933. {
  1934. struct ath_softc *sc = hw->priv;
  1935. struct ath_hw *ah = sc->sc_ah;
  1936. if (!rx_ant || !tx_ant)
  1937. return -EINVAL;
  1938. sc->ant_rx = rx_ant;
  1939. sc->ant_tx = tx_ant;
  1940. if (ah->caps.rx_chainmask == 1)
  1941. return 0;
  1942. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1943. if (AR_SREV_9100(ah))
  1944. ah->rxchainmask = 0x7;
  1945. else
  1946. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1947. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1948. ath9k_reload_chainmask_settings(sc);
  1949. return 0;
  1950. }
  1951. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1952. {
  1953. struct ath_softc *sc = hw->priv;
  1954. *tx_ant = sc->ant_tx;
  1955. *rx_ant = sc->ant_rx;
  1956. return 0;
  1957. }
  1958. struct ieee80211_ops ath9k_ops = {
  1959. .tx = ath9k_tx,
  1960. .start = ath9k_start,
  1961. .stop = ath9k_stop,
  1962. .add_interface = ath9k_add_interface,
  1963. .change_interface = ath9k_change_interface,
  1964. .remove_interface = ath9k_remove_interface,
  1965. .config = ath9k_config,
  1966. .configure_filter = ath9k_configure_filter,
  1967. .sta_add = ath9k_sta_add,
  1968. .sta_remove = ath9k_sta_remove,
  1969. .sta_notify = ath9k_sta_notify,
  1970. .conf_tx = ath9k_conf_tx,
  1971. .bss_info_changed = ath9k_bss_info_changed,
  1972. .set_key = ath9k_set_key,
  1973. .get_tsf = ath9k_get_tsf,
  1974. .set_tsf = ath9k_set_tsf,
  1975. .reset_tsf = ath9k_reset_tsf,
  1976. .ampdu_action = ath9k_ampdu_action,
  1977. .get_survey = ath9k_get_survey,
  1978. .rfkill_poll = ath9k_rfkill_poll_state,
  1979. .set_coverage_class = ath9k_set_coverage_class,
  1980. .flush = ath9k_flush,
  1981. .tx_frames_pending = ath9k_tx_frames_pending,
  1982. .tx_last_beacon = ath9k_tx_last_beacon,
  1983. .get_stats = ath9k_get_stats,
  1984. .set_antenna = ath9k_set_antenna,
  1985. .get_antenna = ath9k_get_antenna,
  1986. };