qla_init.c 147 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_device_resync(scsi_qla_host_t *);
  29. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  30. uint16_t *);
  31. static int qla2x00_restart_isp(scsi_qla_host_t *);
  32. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  33. static int qla84xx_init_chip(scsi_qla_host_t *);
  34. static int qla25xx_init_queues(struct qla_hw_data *);
  35. /* SRB Extensions ---------------------------------------------------------- */
  36. static void
  37. qla2x00_ctx_sp_timeout(unsigned long __data)
  38. {
  39. srb_t *sp = (srb_t *)__data;
  40. struct srb_ctx *ctx;
  41. struct srb_iocb *iocb;
  42. fc_port_t *fcport = sp->fcport;
  43. struct qla_hw_data *ha = fcport->vha->hw;
  44. struct req_que *req;
  45. unsigned long flags;
  46. spin_lock_irqsave(&ha->hardware_lock, flags);
  47. req = ha->req_q_map[0];
  48. req->outstanding_cmds[sp->handle] = NULL;
  49. ctx = sp->ctx;
  50. iocb = ctx->u.iocb_cmd;
  51. iocb->timeout(sp);
  52. iocb->free(sp);
  53. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  54. }
  55. static void
  56. qla2x00_ctx_sp_free(srb_t *sp)
  57. {
  58. struct srb_ctx *ctx = sp->ctx;
  59. struct srb_iocb *iocb = ctx->u.iocb_cmd;
  60. struct scsi_qla_host *vha = sp->fcport->vha;
  61. del_timer(&iocb->timer);
  62. kfree(iocb);
  63. kfree(ctx);
  64. mempool_free(sp, sp->fcport->vha->hw->srb_mempool);
  65. QLA_VHA_MARK_NOT_BUSY(vha);
  66. }
  67. inline srb_t *
  68. qla2x00_get_ctx_sp(scsi_qla_host_t *vha, fc_port_t *fcport, size_t size,
  69. unsigned long tmo)
  70. {
  71. srb_t *sp = NULL;
  72. struct qla_hw_data *ha = vha->hw;
  73. struct srb_ctx *ctx;
  74. struct srb_iocb *iocb;
  75. uint8_t bail;
  76. QLA_VHA_MARK_BUSY(vha, bail);
  77. if (bail)
  78. return NULL;
  79. sp = mempool_alloc(ha->srb_mempool, GFP_KERNEL);
  80. if (!sp)
  81. goto done;
  82. ctx = kzalloc(size, GFP_KERNEL);
  83. if (!ctx) {
  84. mempool_free(sp, ha->srb_mempool);
  85. sp = NULL;
  86. goto done;
  87. }
  88. iocb = kzalloc(sizeof(struct srb_iocb), GFP_KERNEL);
  89. if (!iocb) {
  90. mempool_free(sp, ha->srb_mempool);
  91. sp = NULL;
  92. kfree(ctx);
  93. goto done;
  94. }
  95. memset(sp, 0, sizeof(*sp));
  96. sp->fcport = fcport;
  97. sp->ctx = ctx;
  98. ctx->iocbs = 1;
  99. ctx->u.iocb_cmd = iocb;
  100. iocb->free = qla2x00_ctx_sp_free;
  101. init_timer(&iocb->timer);
  102. if (!tmo)
  103. goto done;
  104. iocb->timer.expires = jiffies + tmo * HZ;
  105. iocb->timer.data = (unsigned long)sp;
  106. iocb->timer.function = qla2x00_ctx_sp_timeout;
  107. add_timer(&iocb->timer);
  108. done:
  109. if (!sp)
  110. QLA_VHA_MARK_NOT_BUSY(vha);
  111. return sp;
  112. }
  113. /* Asynchronous Login/Logout Routines -------------------------------------- */
  114. static inline unsigned long
  115. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  116. {
  117. unsigned long tmo;
  118. struct qla_hw_data *ha = vha->hw;
  119. /* Firmware should use switch negotiated r_a_tov for timeout. */
  120. tmo = ha->r_a_tov / 10 * 2;
  121. if (!IS_FWI2_CAPABLE(ha)) {
  122. /*
  123. * Except for earlier ISPs where the timeout is seeded from the
  124. * initialization control block.
  125. */
  126. tmo = ha->login_timeout;
  127. }
  128. return tmo;
  129. }
  130. static void
  131. qla2x00_async_iocb_timeout(srb_t *sp)
  132. {
  133. fc_port_t *fcport = sp->fcport;
  134. struct srb_ctx *ctx = sp->ctx;
  135. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  136. "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
  137. ctx->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
  138. fcport->d_id.b.al_pa);
  139. fcport->flags &= ~FCF_ASYNC_SENT;
  140. if (ctx->type == SRB_LOGIN_CMD) {
  141. struct srb_iocb *lio = ctx->u.iocb_cmd;
  142. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  143. /* Retry as needed. */
  144. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  145. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  146. QLA_LOGIO_LOGIN_RETRIED : 0;
  147. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  148. lio->u.logio.data);
  149. }
  150. }
  151. static void
  152. qla2x00_async_login_ctx_done(srb_t *sp)
  153. {
  154. struct srb_ctx *ctx = sp->ctx;
  155. struct srb_iocb *lio = ctx->u.iocb_cmd;
  156. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  157. lio->u.logio.data);
  158. lio->free(sp);
  159. }
  160. int
  161. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  162. uint16_t *data)
  163. {
  164. srb_t *sp;
  165. struct srb_ctx *ctx;
  166. struct srb_iocb *lio;
  167. int rval;
  168. rval = QLA_FUNCTION_FAILED;
  169. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  170. qla2x00_get_async_timeout(vha) + 2);
  171. if (!sp)
  172. goto done;
  173. ctx = sp->ctx;
  174. ctx->type = SRB_LOGIN_CMD;
  175. ctx->name = "login";
  176. lio = ctx->u.iocb_cmd;
  177. lio->timeout = qla2x00_async_iocb_timeout;
  178. lio->done = qla2x00_async_login_ctx_done;
  179. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  180. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  181. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  182. rval = qla2x00_start_sp(sp);
  183. if (rval != QLA_SUCCESS)
  184. goto done_free_sp;
  185. ql_dbg(ql_dbg_disc, vha, 0x2072,
  186. "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
  187. "retries=%d.\n", sp->handle, fcport->loop_id,
  188. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  189. fcport->login_retry);
  190. return rval;
  191. done_free_sp:
  192. lio->free(sp);
  193. done:
  194. return rval;
  195. }
  196. static void
  197. qla2x00_async_logout_ctx_done(srb_t *sp)
  198. {
  199. struct srb_ctx *ctx = sp->ctx;
  200. struct srb_iocb *lio = ctx->u.iocb_cmd;
  201. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  202. lio->u.logio.data);
  203. lio->free(sp);
  204. }
  205. int
  206. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  207. {
  208. srb_t *sp;
  209. struct srb_ctx *ctx;
  210. struct srb_iocb *lio;
  211. int rval;
  212. rval = QLA_FUNCTION_FAILED;
  213. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  214. qla2x00_get_async_timeout(vha) + 2);
  215. if (!sp)
  216. goto done;
  217. ctx = sp->ctx;
  218. ctx->type = SRB_LOGOUT_CMD;
  219. ctx->name = "logout";
  220. lio = ctx->u.iocb_cmd;
  221. lio->timeout = qla2x00_async_iocb_timeout;
  222. lio->done = qla2x00_async_logout_ctx_done;
  223. rval = qla2x00_start_sp(sp);
  224. if (rval != QLA_SUCCESS)
  225. goto done_free_sp;
  226. ql_dbg(ql_dbg_disc, vha, 0x2070,
  227. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  228. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  229. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  230. return rval;
  231. done_free_sp:
  232. lio->free(sp);
  233. done:
  234. return rval;
  235. }
  236. static void
  237. qla2x00_async_adisc_ctx_done(srb_t *sp)
  238. {
  239. struct srb_ctx *ctx = sp->ctx;
  240. struct srb_iocb *lio = ctx->u.iocb_cmd;
  241. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  242. lio->u.logio.data);
  243. lio->free(sp);
  244. }
  245. int
  246. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  247. uint16_t *data)
  248. {
  249. srb_t *sp;
  250. struct srb_ctx *ctx;
  251. struct srb_iocb *lio;
  252. int rval;
  253. rval = QLA_FUNCTION_FAILED;
  254. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  255. qla2x00_get_async_timeout(vha) + 2);
  256. if (!sp)
  257. goto done;
  258. ctx = sp->ctx;
  259. ctx->type = SRB_ADISC_CMD;
  260. ctx->name = "adisc";
  261. lio = ctx->u.iocb_cmd;
  262. lio->timeout = qla2x00_async_iocb_timeout;
  263. lio->done = qla2x00_async_adisc_ctx_done;
  264. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  265. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  266. rval = qla2x00_start_sp(sp);
  267. if (rval != QLA_SUCCESS)
  268. goto done_free_sp;
  269. ql_dbg(ql_dbg_disc, vha, 0x206f,
  270. "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
  271. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  272. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  273. return rval;
  274. done_free_sp:
  275. lio->free(sp);
  276. done:
  277. return rval;
  278. }
  279. static void
  280. qla2x00_async_tm_cmd_ctx_done(srb_t *sp)
  281. {
  282. struct srb_ctx *ctx = sp->ctx;
  283. struct srb_iocb *iocb = (struct srb_iocb *)ctx->u.iocb_cmd;
  284. qla2x00_async_tm_cmd_done(sp->fcport->vha, sp->fcport, iocb);
  285. iocb->free(sp);
  286. }
  287. int
  288. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
  289. uint32_t tag)
  290. {
  291. struct scsi_qla_host *vha = fcport->vha;
  292. srb_t *sp;
  293. struct srb_ctx *ctx;
  294. struct srb_iocb *tcf;
  295. int rval;
  296. rval = QLA_FUNCTION_FAILED;
  297. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  298. qla2x00_get_async_timeout(vha) + 2);
  299. if (!sp)
  300. goto done;
  301. ctx = sp->ctx;
  302. ctx->type = SRB_TM_CMD;
  303. ctx->name = "tmf";
  304. tcf = ctx->u.iocb_cmd;
  305. tcf->u.tmf.flags = flags;
  306. tcf->u.tmf.lun = lun;
  307. tcf->u.tmf.data = tag;
  308. tcf->timeout = qla2x00_async_iocb_timeout;
  309. tcf->done = qla2x00_async_tm_cmd_ctx_done;
  310. rval = qla2x00_start_sp(sp);
  311. if (rval != QLA_SUCCESS)
  312. goto done_free_sp;
  313. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  314. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  315. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  316. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  317. return rval;
  318. done_free_sp:
  319. tcf->free(sp);
  320. done:
  321. return rval;
  322. }
  323. void
  324. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  325. uint16_t *data)
  326. {
  327. int rval;
  328. switch (data[0]) {
  329. case MBS_COMMAND_COMPLETE:
  330. /*
  331. * Driver must validate login state - If PRLI not complete,
  332. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  333. * requests.
  334. */
  335. rval = qla2x00_get_port_database(vha, fcport, 0);
  336. if (rval != QLA_SUCCESS) {
  337. qla2x00_post_async_logout_work(vha, fcport, NULL);
  338. qla2x00_post_async_login_work(vha, fcport, NULL);
  339. break;
  340. }
  341. if (fcport->flags & FCF_FCP2_DEVICE) {
  342. qla2x00_post_async_adisc_work(vha, fcport, data);
  343. break;
  344. }
  345. qla2x00_update_fcport(vha, fcport);
  346. break;
  347. case MBS_COMMAND_ERROR:
  348. fcport->flags &= ~FCF_ASYNC_SENT;
  349. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  350. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  351. else
  352. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  353. break;
  354. case MBS_PORT_ID_USED:
  355. fcport->loop_id = data[1];
  356. qla2x00_post_async_logout_work(vha, fcport, NULL);
  357. qla2x00_post_async_login_work(vha, fcport, NULL);
  358. break;
  359. case MBS_LOOP_ID_USED:
  360. fcport->loop_id++;
  361. rval = qla2x00_find_new_loop_id(vha, fcport);
  362. if (rval != QLA_SUCCESS) {
  363. fcport->flags &= ~FCF_ASYNC_SENT;
  364. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  365. break;
  366. }
  367. qla2x00_post_async_login_work(vha, fcport, NULL);
  368. break;
  369. }
  370. return;
  371. }
  372. void
  373. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  374. uint16_t *data)
  375. {
  376. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  377. return;
  378. }
  379. void
  380. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  381. uint16_t *data)
  382. {
  383. if (data[0] == MBS_COMMAND_COMPLETE) {
  384. qla2x00_update_fcport(vha, fcport);
  385. return;
  386. }
  387. /* Retry login. */
  388. fcport->flags &= ~FCF_ASYNC_SENT;
  389. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  390. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  391. else
  392. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  393. return;
  394. }
  395. void
  396. qla2x00_async_tm_cmd_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  397. struct srb_iocb *iocb)
  398. {
  399. int rval;
  400. uint32_t flags;
  401. uint16_t lun;
  402. flags = iocb->u.tmf.flags;
  403. lun = (uint16_t)iocb->u.tmf.lun;
  404. /* Issue Marker IOCB */
  405. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  406. vha->hw->rsp_q_map[0], fcport->loop_id, lun,
  407. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  408. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  409. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  410. "TM IOCB failed (%x).\n", rval);
  411. }
  412. return;
  413. }
  414. /****************************************************************************/
  415. /* QLogic ISP2x00 Hardware Support Functions. */
  416. /****************************************************************************/
  417. /*
  418. * qla2x00_initialize_adapter
  419. * Initialize board.
  420. *
  421. * Input:
  422. * ha = adapter block pointer.
  423. *
  424. * Returns:
  425. * 0 = success
  426. */
  427. int
  428. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  429. {
  430. int rval;
  431. struct qla_hw_data *ha = vha->hw;
  432. struct req_que *req = ha->req_q_map[0];
  433. /* Clear adapter flags. */
  434. vha->flags.online = 0;
  435. ha->flags.chip_reset_done = 0;
  436. vha->flags.reset_active = 0;
  437. ha->flags.pci_channel_io_perm_failure = 0;
  438. ha->flags.eeh_busy = 0;
  439. ha->flags.thermal_supported = 1;
  440. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  441. atomic_set(&vha->loop_state, LOOP_DOWN);
  442. vha->device_flags = DFLG_NO_CABLE;
  443. vha->dpc_flags = 0;
  444. vha->flags.management_server_logged_in = 0;
  445. vha->marker_needed = 0;
  446. ha->isp_abort_cnt = 0;
  447. ha->beacon_blink_led = 0;
  448. set_bit(0, ha->req_qid_map);
  449. set_bit(0, ha->rsp_qid_map);
  450. ql_dbg(ql_dbg_init, vha, 0x0040,
  451. "Configuring PCI space...\n");
  452. rval = ha->isp_ops->pci_config(vha);
  453. if (rval) {
  454. ql_log(ql_log_warn, vha, 0x0044,
  455. "Unable to configure PCI space.\n");
  456. return (rval);
  457. }
  458. ha->isp_ops->reset_chip(vha);
  459. rval = qla2xxx_get_flash_info(vha);
  460. if (rval) {
  461. ql_log(ql_log_fatal, vha, 0x004f,
  462. "Unable to validate FLASH data.\n");
  463. return (rval);
  464. }
  465. ha->isp_ops->get_flash_version(vha, req->ring);
  466. ql_dbg(ql_dbg_init, vha, 0x0061,
  467. "Configure NVRAM parameters...\n");
  468. ha->isp_ops->nvram_config(vha);
  469. if (ha->flags.disable_serdes) {
  470. /* Mask HBA via NVRAM settings? */
  471. ql_log(ql_log_info, vha, 0x0077,
  472. "Masking HBA WWPN "
  473. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  474. vha->port_name[0], vha->port_name[1],
  475. vha->port_name[2], vha->port_name[3],
  476. vha->port_name[4], vha->port_name[5],
  477. vha->port_name[6], vha->port_name[7]);
  478. return QLA_FUNCTION_FAILED;
  479. }
  480. ql_dbg(ql_dbg_init, vha, 0x0078,
  481. "Verifying loaded RISC code...\n");
  482. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  483. rval = ha->isp_ops->chip_diag(vha);
  484. if (rval)
  485. return (rval);
  486. rval = qla2x00_setup_chip(vha);
  487. if (rval)
  488. return (rval);
  489. }
  490. if (IS_QLA84XX(ha)) {
  491. ha->cs84xx = qla84xx_get_chip(vha);
  492. if (!ha->cs84xx) {
  493. ql_log(ql_log_warn, vha, 0x00d0,
  494. "Unable to configure ISP84XX.\n");
  495. return QLA_FUNCTION_FAILED;
  496. }
  497. }
  498. rval = qla2x00_init_rings(vha);
  499. ha->flags.chip_reset_done = 1;
  500. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  501. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  502. rval = qla84xx_init_chip(vha);
  503. if (rval != QLA_SUCCESS) {
  504. ql_log(ql_log_warn, vha, 0x00d4,
  505. "Unable to initialize ISP84XX.\n");
  506. qla84xx_put_chip(vha);
  507. }
  508. }
  509. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  510. qla24xx_read_fcp_prio_cfg(vha);
  511. return (rval);
  512. }
  513. /**
  514. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  515. * @ha: HA context
  516. *
  517. * Returns 0 on success.
  518. */
  519. int
  520. qla2100_pci_config(scsi_qla_host_t *vha)
  521. {
  522. uint16_t w;
  523. unsigned long flags;
  524. struct qla_hw_data *ha = vha->hw;
  525. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  526. pci_set_master(ha->pdev);
  527. pci_try_set_mwi(ha->pdev);
  528. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  529. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  530. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  531. pci_disable_rom(ha->pdev);
  532. /* Get PCI bus information. */
  533. spin_lock_irqsave(&ha->hardware_lock, flags);
  534. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  535. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  536. return QLA_SUCCESS;
  537. }
  538. /**
  539. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  540. * @ha: HA context
  541. *
  542. * Returns 0 on success.
  543. */
  544. int
  545. qla2300_pci_config(scsi_qla_host_t *vha)
  546. {
  547. uint16_t w;
  548. unsigned long flags = 0;
  549. uint32_t cnt;
  550. struct qla_hw_data *ha = vha->hw;
  551. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  552. pci_set_master(ha->pdev);
  553. pci_try_set_mwi(ha->pdev);
  554. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  555. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  556. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  557. w &= ~PCI_COMMAND_INTX_DISABLE;
  558. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  559. /*
  560. * If this is a 2300 card and not 2312, reset the
  561. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  562. * the 2310 also reports itself as a 2300 so we need to get the
  563. * fb revision level -- a 6 indicates it really is a 2300 and
  564. * not a 2310.
  565. */
  566. if (IS_QLA2300(ha)) {
  567. spin_lock_irqsave(&ha->hardware_lock, flags);
  568. /* Pause RISC. */
  569. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  570. for (cnt = 0; cnt < 30000; cnt++) {
  571. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  572. break;
  573. udelay(10);
  574. }
  575. /* Select FPM registers. */
  576. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  577. RD_REG_WORD(&reg->ctrl_status);
  578. /* Get the fb rev level */
  579. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  580. if (ha->fb_rev == FPM_2300)
  581. pci_clear_mwi(ha->pdev);
  582. /* Deselect FPM registers. */
  583. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  584. RD_REG_WORD(&reg->ctrl_status);
  585. /* Release RISC module. */
  586. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  587. for (cnt = 0; cnt < 30000; cnt++) {
  588. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  589. break;
  590. udelay(10);
  591. }
  592. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  593. }
  594. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  595. pci_disable_rom(ha->pdev);
  596. /* Get PCI bus information. */
  597. spin_lock_irqsave(&ha->hardware_lock, flags);
  598. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  599. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  600. return QLA_SUCCESS;
  601. }
  602. /**
  603. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  604. * @ha: HA context
  605. *
  606. * Returns 0 on success.
  607. */
  608. int
  609. qla24xx_pci_config(scsi_qla_host_t *vha)
  610. {
  611. uint16_t w;
  612. unsigned long flags = 0;
  613. struct qla_hw_data *ha = vha->hw;
  614. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  615. pci_set_master(ha->pdev);
  616. pci_try_set_mwi(ha->pdev);
  617. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  618. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  619. w &= ~PCI_COMMAND_INTX_DISABLE;
  620. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  621. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  622. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  623. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  624. pcix_set_mmrbc(ha->pdev, 2048);
  625. /* PCIe -- adjust Maximum Read Request Size (2048). */
  626. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  627. pcie_set_readrq(ha->pdev, 2048);
  628. pci_disable_rom(ha->pdev);
  629. ha->chip_revision = ha->pdev->revision;
  630. /* Get PCI bus information. */
  631. spin_lock_irqsave(&ha->hardware_lock, flags);
  632. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  633. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  634. return QLA_SUCCESS;
  635. }
  636. /**
  637. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  638. * @ha: HA context
  639. *
  640. * Returns 0 on success.
  641. */
  642. int
  643. qla25xx_pci_config(scsi_qla_host_t *vha)
  644. {
  645. uint16_t w;
  646. struct qla_hw_data *ha = vha->hw;
  647. pci_set_master(ha->pdev);
  648. pci_try_set_mwi(ha->pdev);
  649. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  650. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  651. w &= ~PCI_COMMAND_INTX_DISABLE;
  652. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  653. /* PCIe -- adjust Maximum Read Request Size (2048). */
  654. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  655. pcie_set_readrq(ha->pdev, 2048);
  656. pci_disable_rom(ha->pdev);
  657. ha->chip_revision = ha->pdev->revision;
  658. return QLA_SUCCESS;
  659. }
  660. /**
  661. * qla2x00_isp_firmware() - Choose firmware image.
  662. * @ha: HA context
  663. *
  664. * Returns 0 on success.
  665. */
  666. static int
  667. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  668. {
  669. int rval;
  670. uint16_t loop_id, topo, sw_cap;
  671. uint8_t domain, area, al_pa;
  672. struct qla_hw_data *ha = vha->hw;
  673. /* Assume loading risc code */
  674. rval = QLA_FUNCTION_FAILED;
  675. if (ha->flags.disable_risc_code_load) {
  676. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  677. /* Verify checksum of loaded RISC code. */
  678. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  679. if (rval == QLA_SUCCESS) {
  680. /* And, verify we are not in ROM code. */
  681. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  682. &area, &domain, &topo, &sw_cap);
  683. }
  684. }
  685. if (rval)
  686. ql_dbg(ql_dbg_init, vha, 0x007a,
  687. "**** Load RISC code ****.\n");
  688. return (rval);
  689. }
  690. /**
  691. * qla2x00_reset_chip() - Reset ISP chip.
  692. * @ha: HA context
  693. *
  694. * Returns 0 on success.
  695. */
  696. void
  697. qla2x00_reset_chip(scsi_qla_host_t *vha)
  698. {
  699. unsigned long flags = 0;
  700. struct qla_hw_data *ha = vha->hw;
  701. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  702. uint32_t cnt;
  703. uint16_t cmd;
  704. if (unlikely(pci_channel_offline(ha->pdev)))
  705. return;
  706. ha->isp_ops->disable_intrs(ha);
  707. spin_lock_irqsave(&ha->hardware_lock, flags);
  708. /* Turn off master enable */
  709. cmd = 0;
  710. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  711. cmd &= ~PCI_COMMAND_MASTER;
  712. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  713. if (!IS_QLA2100(ha)) {
  714. /* Pause RISC. */
  715. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  716. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  717. for (cnt = 0; cnt < 30000; cnt++) {
  718. if ((RD_REG_WORD(&reg->hccr) &
  719. HCCR_RISC_PAUSE) != 0)
  720. break;
  721. udelay(100);
  722. }
  723. } else {
  724. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  725. udelay(10);
  726. }
  727. /* Select FPM registers. */
  728. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  729. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  730. /* FPM Soft Reset. */
  731. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  732. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  733. /* Toggle Fpm Reset. */
  734. if (!IS_QLA2200(ha)) {
  735. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  736. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  737. }
  738. /* Select frame buffer registers. */
  739. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  740. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  741. /* Reset frame buffer FIFOs. */
  742. if (IS_QLA2200(ha)) {
  743. WRT_FB_CMD_REG(ha, reg, 0xa000);
  744. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  745. } else {
  746. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  747. /* Read back fb_cmd until zero or 3 seconds max */
  748. for (cnt = 0; cnt < 3000; cnt++) {
  749. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  750. break;
  751. udelay(100);
  752. }
  753. }
  754. /* Select RISC module registers. */
  755. WRT_REG_WORD(&reg->ctrl_status, 0);
  756. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  757. /* Reset RISC processor. */
  758. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  759. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  760. /* Release RISC processor. */
  761. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  762. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  763. }
  764. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  765. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  766. /* Reset ISP chip. */
  767. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  768. /* Wait for RISC to recover from reset. */
  769. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  770. /*
  771. * It is necessary to for a delay here since the card doesn't
  772. * respond to PCI reads during a reset. On some architectures
  773. * this will result in an MCA.
  774. */
  775. udelay(20);
  776. for (cnt = 30000; cnt; cnt--) {
  777. if ((RD_REG_WORD(&reg->ctrl_status) &
  778. CSR_ISP_SOFT_RESET) == 0)
  779. break;
  780. udelay(100);
  781. }
  782. } else
  783. udelay(10);
  784. /* Reset RISC processor. */
  785. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  786. WRT_REG_WORD(&reg->semaphore, 0);
  787. /* Release RISC processor. */
  788. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  789. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  790. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  791. for (cnt = 0; cnt < 30000; cnt++) {
  792. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  793. break;
  794. udelay(100);
  795. }
  796. } else
  797. udelay(100);
  798. /* Turn on master enable */
  799. cmd |= PCI_COMMAND_MASTER;
  800. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  801. /* Disable RISC pause on FPM parity error. */
  802. if (!IS_QLA2100(ha)) {
  803. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  804. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  805. }
  806. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  807. }
  808. /**
  809. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  810. *
  811. * Returns 0 on success.
  812. */
  813. int
  814. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  815. {
  816. uint16_t mb[4] = {0x1010, 0, 1, 0};
  817. if (!IS_QLA81XX(vha->hw))
  818. return QLA_SUCCESS;
  819. return qla81xx_write_mpi_register(vha, mb);
  820. }
  821. /**
  822. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  823. * @ha: HA context
  824. *
  825. * Returns 0 on success.
  826. */
  827. static inline void
  828. qla24xx_reset_risc(scsi_qla_host_t *vha)
  829. {
  830. unsigned long flags = 0;
  831. struct qla_hw_data *ha = vha->hw;
  832. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  833. uint32_t cnt, d2;
  834. uint16_t wd;
  835. static int abts_cnt; /* ISP abort retry counts */
  836. spin_lock_irqsave(&ha->hardware_lock, flags);
  837. /* Reset RISC. */
  838. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  839. for (cnt = 0; cnt < 30000; cnt++) {
  840. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  841. break;
  842. udelay(10);
  843. }
  844. WRT_REG_DWORD(&reg->ctrl_status,
  845. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  846. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  847. udelay(100);
  848. /* Wait for firmware to complete NVRAM accesses. */
  849. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  850. for (cnt = 10000 ; cnt && d2; cnt--) {
  851. udelay(5);
  852. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  853. barrier();
  854. }
  855. /* Wait for soft-reset to complete. */
  856. d2 = RD_REG_DWORD(&reg->ctrl_status);
  857. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  858. udelay(5);
  859. d2 = RD_REG_DWORD(&reg->ctrl_status);
  860. barrier();
  861. }
  862. /* If required, do an MPI FW reset now */
  863. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  864. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  865. if (++abts_cnt < 5) {
  866. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  867. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  868. } else {
  869. /*
  870. * We exhausted the ISP abort retries. We have to
  871. * set the board offline.
  872. */
  873. abts_cnt = 0;
  874. vha->flags.online = 0;
  875. }
  876. }
  877. }
  878. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  879. RD_REG_DWORD(&reg->hccr);
  880. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  881. RD_REG_DWORD(&reg->hccr);
  882. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  883. RD_REG_DWORD(&reg->hccr);
  884. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  885. for (cnt = 6000000 ; cnt && d2; cnt--) {
  886. udelay(5);
  887. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  888. barrier();
  889. }
  890. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  891. if (IS_NOPOLLING_TYPE(ha))
  892. ha->isp_ops->enable_intrs(ha);
  893. }
  894. /**
  895. * qla24xx_reset_chip() - Reset ISP24xx chip.
  896. * @ha: HA context
  897. *
  898. * Returns 0 on success.
  899. */
  900. void
  901. qla24xx_reset_chip(scsi_qla_host_t *vha)
  902. {
  903. struct qla_hw_data *ha = vha->hw;
  904. if (pci_channel_offline(ha->pdev) &&
  905. ha->flags.pci_channel_io_perm_failure) {
  906. return;
  907. }
  908. ha->isp_ops->disable_intrs(ha);
  909. /* Perform RISC reset. */
  910. qla24xx_reset_risc(vha);
  911. }
  912. /**
  913. * qla2x00_chip_diag() - Test chip for proper operation.
  914. * @ha: HA context
  915. *
  916. * Returns 0 on success.
  917. */
  918. int
  919. qla2x00_chip_diag(scsi_qla_host_t *vha)
  920. {
  921. int rval;
  922. struct qla_hw_data *ha = vha->hw;
  923. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  924. unsigned long flags = 0;
  925. uint16_t data;
  926. uint32_t cnt;
  927. uint16_t mb[5];
  928. struct req_que *req = ha->req_q_map[0];
  929. /* Assume a failed state */
  930. rval = QLA_FUNCTION_FAILED;
  931. ql_dbg(ql_dbg_init, vha, 0x007b,
  932. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  933. spin_lock_irqsave(&ha->hardware_lock, flags);
  934. /* Reset ISP chip. */
  935. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  936. /*
  937. * We need to have a delay here since the card will not respond while
  938. * in reset causing an MCA on some architectures.
  939. */
  940. udelay(20);
  941. data = qla2x00_debounce_register(&reg->ctrl_status);
  942. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  943. udelay(5);
  944. data = RD_REG_WORD(&reg->ctrl_status);
  945. barrier();
  946. }
  947. if (!cnt)
  948. goto chip_diag_failed;
  949. ql_dbg(ql_dbg_init, vha, 0x007c,
  950. "Reset register cleared by chip reset.\n");
  951. /* Reset RISC processor. */
  952. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  953. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  954. /* Workaround for QLA2312 PCI parity error */
  955. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  956. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  957. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  958. udelay(5);
  959. data = RD_MAILBOX_REG(ha, reg, 0);
  960. barrier();
  961. }
  962. } else
  963. udelay(10);
  964. if (!cnt)
  965. goto chip_diag_failed;
  966. /* Check product ID of chip */
  967. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  968. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  969. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  970. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  971. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  972. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  973. mb[3] != PROD_ID_3) {
  974. ql_log(ql_log_warn, vha, 0x0062,
  975. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  976. mb[1], mb[2], mb[3]);
  977. goto chip_diag_failed;
  978. }
  979. ha->product_id[0] = mb[1];
  980. ha->product_id[1] = mb[2];
  981. ha->product_id[2] = mb[3];
  982. ha->product_id[3] = mb[4];
  983. /* Adjust fw RISC transfer size */
  984. if (req->length > 1024)
  985. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  986. else
  987. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  988. req->length;
  989. if (IS_QLA2200(ha) &&
  990. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  991. /* Limit firmware transfer size with a 2200A */
  992. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  993. ha->device_type |= DT_ISP2200A;
  994. ha->fw_transfer_size = 128;
  995. }
  996. /* Wrap Incoming Mailboxes Test. */
  997. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  998. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  999. rval = qla2x00_mbx_reg_test(vha);
  1000. if (rval)
  1001. ql_log(ql_log_warn, vha, 0x0080,
  1002. "Failed mailbox send register test.\n");
  1003. else
  1004. /* Flag a successful rval */
  1005. rval = QLA_SUCCESS;
  1006. spin_lock_irqsave(&ha->hardware_lock, flags);
  1007. chip_diag_failed:
  1008. if (rval)
  1009. ql_log(ql_log_info, vha, 0x0081,
  1010. "Chip diagnostics **** FAILED ****.\n");
  1011. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1012. return (rval);
  1013. }
  1014. /**
  1015. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  1016. * @ha: HA context
  1017. *
  1018. * Returns 0 on success.
  1019. */
  1020. int
  1021. qla24xx_chip_diag(scsi_qla_host_t *vha)
  1022. {
  1023. int rval;
  1024. struct qla_hw_data *ha = vha->hw;
  1025. struct req_que *req = ha->req_q_map[0];
  1026. if (IS_QLA82XX(ha))
  1027. return QLA_SUCCESS;
  1028. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  1029. rval = qla2x00_mbx_reg_test(vha);
  1030. if (rval) {
  1031. ql_log(ql_log_warn, vha, 0x0082,
  1032. "Failed mailbox send register test.\n");
  1033. } else {
  1034. /* Flag a successful rval */
  1035. rval = QLA_SUCCESS;
  1036. }
  1037. return rval;
  1038. }
  1039. void
  1040. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  1041. {
  1042. int rval;
  1043. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  1044. eft_size, fce_size, mq_size;
  1045. dma_addr_t tc_dma;
  1046. void *tc;
  1047. struct qla_hw_data *ha = vha->hw;
  1048. struct req_que *req = ha->req_q_map[0];
  1049. struct rsp_que *rsp = ha->rsp_q_map[0];
  1050. if (ha->fw_dump) {
  1051. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1052. "Firmware dump already allocated.\n");
  1053. return;
  1054. }
  1055. ha->fw_dumped = 0;
  1056. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1057. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1058. fixed_size = sizeof(struct qla2100_fw_dump);
  1059. } else if (IS_QLA23XX(ha)) {
  1060. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1061. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1062. sizeof(uint16_t);
  1063. } else if (IS_FWI2_CAPABLE(ha)) {
  1064. if (IS_QLA83XX(ha))
  1065. fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
  1066. else if (IS_QLA81XX(ha))
  1067. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1068. else if (IS_QLA25XX(ha))
  1069. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1070. else
  1071. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1072. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1073. sizeof(uint32_t);
  1074. if (ha->mqenable) {
  1075. if (!IS_QLA83XX(ha))
  1076. mq_size = sizeof(struct qla2xxx_mq_chain);
  1077. /*
  1078. * Allocate maximum buffer size for all queues.
  1079. * Resizing must be done at end-of-dump processing.
  1080. */
  1081. mq_size += ha->max_req_queues *
  1082. (req->length * sizeof(request_t));
  1083. mq_size += ha->max_rsp_queues *
  1084. (rsp->length * sizeof(response_t));
  1085. }
  1086. /* Allocate memory for Fibre Channel Event Buffer. */
  1087. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  1088. goto try_eft;
  1089. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1090. GFP_KERNEL);
  1091. if (!tc) {
  1092. ql_log(ql_log_warn, vha, 0x00be,
  1093. "Unable to allocate (%d KB) for FCE.\n",
  1094. FCE_SIZE / 1024);
  1095. goto try_eft;
  1096. }
  1097. memset(tc, 0, FCE_SIZE);
  1098. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1099. ha->fce_mb, &ha->fce_bufs);
  1100. if (rval) {
  1101. ql_log(ql_log_warn, vha, 0x00bf,
  1102. "Unable to initialize FCE (%d).\n", rval);
  1103. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1104. tc_dma);
  1105. ha->flags.fce_enabled = 0;
  1106. goto try_eft;
  1107. }
  1108. ql_dbg(ql_dbg_init, vha, 0x00c0,
  1109. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1110. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1111. ha->flags.fce_enabled = 1;
  1112. ha->fce_dma = tc_dma;
  1113. ha->fce = tc;
  1114. try_eft:
  1115. /* Allocate memory for Extended Trace Buffer. */
  1116. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1117. GFP_KERNEL);
  1118. if (!tc) {
  1119. ql_log(ql_log_warn, vha, 0x00c1,
  1120. "Unable to allocate (%d KB) for EFT.\n",
  1121. EFT_SIZE / 1024);
  1122. goto cont_alloc;
  1123. }
  1124. memset(tc, 0, EFT_SIZE);
  1125. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1126. if (rval) {
  1127. ql_log(ql_log_warn, vha, 0x00c2,
  1128. "Unable to initialize EFT (%d).\n", rval);
  1129. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1130. tc_dma);
  1131. goto cont_alloc;
  1132. }
  1133. ql_dbg(ql_dbg_init, vha, 0x00c3,
  1134. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1135. eft_size = EFT_SIZE;
  1136. ha->eft_dma = tc_dma;
  1137. ha->eft = tc;
  1138. }
  1139. cont_alloc:
  1140. req_q_size = req->length * sizeof(request_t);
  1141. rsp_q_size = rsp->length * sizeof(response_t);
  1142. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1143. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1144. ha->chain_offset = dump_size;
  1145. dump_size += mq_size + fce_size;
  1146. ha->fw_dump = vmalloc(dump_size);
  1147. if (!ha->fw_dump) {
  1148. ql_log(ql_log_warn, vha, 0x00c4,
  1149. "Unable to allocate (%d KB) for firmware dump.\n",
  1150. dump_size / 1024);
  1151. if (ha->fce) {
  1152. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1153. ha->fce_dma);
  1154. ha->fce = NULL;
  1155. ha->fce_dma = 0;
  1156. }
  1157. if (ha->eft) {
  1158. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1159. ha->eft_dma);
  1160. ha->eft = NULL;
  1161. ha->eft_dma = 0;
  1162. }
  1163. return;
  1164. }
  1165. ql_dbg(ql_dbg_init, vha, 0x00c5,
  1166. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1167. ha->fw_dump_len = dump_size;
  1168. ha->fw_dump->signature[0] = 'Q';
  1169. ha->fw_dump->signature[1] = 'L';
  1170. ha->fw_dump->signature[2] = 'G';
  1171. ha->fw_dump->signature[3] = 'C';
  1172. ha->fw_dump->version = __constant_htonl(1);
  1173. ha->fw_dump->fixed_size = htonl(fixed_size);
  1174. ha->fw_dump->mem_size = htonl(mem_size);
  1175. ha->fw_dump->req_q_size = htonl(req_q_size);
  1176. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1177. ha->fw_dump->eft_size = htonl(eft_size);
  1178. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1179. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1180. ha->fw_dump->header_size =
  1181. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1182. }
  1183. static int
  1184. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1185. {
  1186. #define MPS_MASK 0xe0
  1187. int rval;
  1188. uint16_t dc;
  1189. uint32_t dw;
  1190. if (!IS_QLA81XX(vha->hw))
  1191. return QLA_SUCCESS;
  1192. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1193. if (rval != QLA_SUCCESS) {
  1194. ql_log(ql_log_warn, vha, 0x0105,
  1195. "Unable to acquire semaphore.\n");
  1196. goto done;
  1197. }
  1198. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1199. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1200. if (rval != QLA_SUCCESS) {
  1201. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1202. goto done_release;
  1203. }
  1204. dc &= MPS_MASK;
  1205. if (dc == (dw & MPS_MASK))
  1206. goto done_release;
  1207. dw &= ~MPS_MASK;
  1208. dw |= dc;
  1209. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1210. if (rval != QLA_SUCCESS) {
  1211. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1212. }
  1213. done_release:
  1214. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1215. if (rval != QLA_SUCCESS) {
  1216. ql_log(ql_log_warn, vha, 0x006d,
  1217. "Unable to release semaphore.\n");
  1218. }
  1219. done:
  1220. return rval;
  1221. }
  1222. /**
  1223. * qla2x00_setup_chip() - Load and start RISC firmware.
  1224. * @ha: HA context
  1225. *
  1226. * Returns 0 on success.
  1227. */
  1228. static int
  1229. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1230. {
  1231. int rval;
  1232. uint32_t srisc_address = 0;
  1233. struct qla_hw_data *ha = vha->hw;
  1234. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1235. unsigned long flags;
  1236. uint16_t fw_major_version;
  1237. if (IS_QLA82XX(ha)) {
  1238. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1239. if (rval == QLA_SUCCESS) {
  1240. qla2x00_stop_firmware(vha);
  1241. goto enable_82xx_npiv;
  1242. } else
  1243. goto failed;
  1244. }
  1245. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1246. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1247. spin_lock_irqsave(&ha->hardware_lock, flags);
  1248. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1249. RD_REG_WORD(&reg->hccr);
  1250. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1251. }
  1252. qla81xx_mpi_sync(vha);
  1253. /* Load firmware sequences */
  1254. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1255. if (rval == QLA_SUCCESS) {
  1256. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1257. "Verifying Checksum of loaded RISC code.\n");
  1258. rval = qla2x00_verify_checksum(vha, srisc_address);
  1259. if (rval == QLA_SUCCESS) {
  1260. /* Start firmware execution. */
  1261. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1262. "Starting firmware.\n");
  1263. rval = qla2x00_execute_fw(vha, srisc_address);
  1264. /* Retrieve firmware information. */
  1265. if (rval == QLA_SUCCESS) {
  1266. enable_82xx_npiv:
  1267. fw_major_version = ha->fw_major_version;
  1268. if (IS_QLA82XX(ha))
  1269. qla82xx_check_md_needed(vha);
  1270. else
  1271. rval = qla2x00_get_fw_version(vha);
  1272. if (rval != QLA_SUCCESS)
  1273. goto failed;
  1274. ha->flags.npiv_supported = 0;
  1275. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1276. (ha->fw_attributes & BIT_2)) {
  1277. ha->flags.npiv_supported = 1;
  1278. if ((!ha->max_npiv_vports) ||
  1279. ((ha->max_npiv_vports + 1) %
  1280. MIN_MULTI_ID_FABRIC))
  1281. ha->max_npiv_vports =
  1282. MIN_MULTI_ID_FABRIC - 1;
  1283. }
  1284. qla2x00_get_resource_cnts(vha, NULL,
  1285. &ha->fw_xcb_count, NULL, NULL,
  1286. &ha->max_npiv_vports, NULL);
  1287. if (!fw_major_version && ql2xallocfwdump
  1288. && !IS_QLA82XX(ha))
  1289. qla2x00_alloc_fw_dump(vha);
  1290. }
  1291. } else {
  1292. ql_log(ql_log_fatal, vha, 0x00cd,
  1293. "ISP Firmware failed checksum.\n");
  1294. goto failed;
  1295. }
  1296. }
  1297. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1298. /* Enable proper parity. */
  1299. spin_lock_irqsave(&ha->hardware_lock, flags);
  1300. if (IS_QLA2300(ha))
  1301. /* SRAM parity */
  1302. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1303. else
  1304. /* SRAM, Instruction RAM and GP RAM parity */
  1305. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1306. RD_REG_WORD(&reg->hccr);
  1307. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1308. }
  1309. if (IS_QLA83XX(ha))
  1310. goto skip_fac_check;
  1311. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1312. uint32_t size;
  1313. rval = qla81xx_fac_get_sector_size(vha, &size);
  1314. if (rval == QLA_SUCCESS) {
  1315. ha->flags.fac_supported = 1;
  1316. ha->fdt_block_size = size << 2;
  1317. } else {
  1318. ql_log(ql_log_warn, vha, 0x00ce,
  1319. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1320. ha->fw_major_version, ha->fw_minor_version,
  1321. ha->fw_subminor_version);
  1322. skip_fac_check:
  1323. if (IS_QLA83XX(ha)) {
  1324. ha->flags.fac_supported = 0;
  1325. rval = QLA_SUCCESS;
  1326. }
  1327. }
  1328. }
  1329. failed:
  1330. if (rval) {
  1331. ql_log(ql_log_fatal, vha, 0x00cf,
  1332. "Setup chip ****FAILED****.\n");
  1333. }
  1334. return (rval);
  1335. }
  1336. /**
  1337. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1338. * @ha: HA context
  1339. *
  1340. * Beginning of request ring has initialization control block already built
  1341. * by nvram config routine.
  1342. *
  1343. * Returns 0 on success.
  1344. */
  1345. void
  1346. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1347. {
  1348. uint16_t cnt;
  1349. response_t *pkt;
  1350. rsp->ring_ptr = rsp->ring;
  1351. rsp->ring_index = 0;
  1352. rsp->status_srb = NULL;
  1353. pkt = rsp->ring_ptr;
  1354. for (cnt = 0; cnt < rsp->length; cnt++) {
  1355. pkt->signature = RESPONSE_PROCESSED;
  1356. pkt++;
  1357. }
  1358. }
  1359. /**
  1360. * qla2x00_update_fw_options() - Read and process firmware options.
  1361. * @ha: HA context
  1362. *
  1363. * Returns 0 on success.
  1364. */
  1365. void
  1366. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1367. {
  1368. uint16_t swing, emphasis, tx_sens, rx_sens;
  1369. struct qla_hw_data *ha = vha->hw;
  1370. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1371. qla2x00_get_fw_options(vha, ha->fw_options);
  1372. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1373. return;
  1374. /* Serial Link options. */
  1375. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1376. "Serial link options.\n");
  1377. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1378. (uint8_t *)&ha->fw_seriallink_options,
  1379. sizeof(ha->fw_seriallink_options));
  1380. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1381. if (ha->fw_seriallink_options[3] & BIT_2) {
  1382. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1383. /* 1G settings */
  1384. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1385. emphasis = (ha->fw_seriallink_options[2] &
  1386. (BIT_4 | BIT_3)) >> 3;
  1387. tx_sens = ha->fw_seriallink_options[0] &
  1388. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1389. rx_sens = (ha->fw_seriallink_options[0] &
  1390. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1391. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1392. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1393. if (rx_sens == 0x0)
  1394. rx_sens = 0x3;
  1395. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1396. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1397. ha->fw_options[10] |= BIT_5 |
  1398. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1399. (tx_sens & (BIT_1 | BIT_0));
  1400. /* 2G settings */
  1401. swing = (ha->fw_seriallink_options[2] &
  1402. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1403. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1404. tx_sens = ha->fw_seriallink_options[1] &
  1405. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1406. rx_sens = (ha->fw_seriallink_options[1] &
  1407. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1408. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1409. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1410. if (rx_sens == 0x0)
  1411. rx_sens = 0x3;
  1412. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1413. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1414. ha->fw_options[11] |= BIT_5 |
  1415. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1416. (tx_sens & (BIT_1 | BIT_0));
  1417. }
  1418. /* FCP2 options. */
  1419. /* Return command IOCBs without waiting for an ABTS to complete. */
  1420. ha->fw_options[3] |= BIT_13;
  1421. /* LED scheme. */
  1422. if (ha->flags.enable_led_scheme)
  1423. ha->fw_options[2] |= BIT_12;
  1424. /* Detect ISP6312. */
  1425. if (IS_QLA6312(ha))
  1426. ha->fw_options[2] |= BIT_13;
  1427. /* Update firmware options. */
  1428. qla2x00_set_fw_options(vha, ha->fw_options);
  1429. }
  1430. void
  1431. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1432. {
  1433. int rval;
  1434. struct qla_hw_data *ha = vha->hw;
  1435. if (IS_QLA82XX(ha))
  1436. return;
  1437. /* Update Serial Link options. */
  1438. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1439. return;
  1440. rval = qla2x00_set_serdes_params(vha,
  1441. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1442. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1443. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1444. if (rval != QLA_SUCCESS) {
  1445. ql_log(ql_log_warn, vha, 0x0104,
  1446. "Unable to update Serial Link options (%x).\n", rval);
  1447. }
  1448. }
  1449. void
  1450. qla2x00_config_rings(struct scsi_qla_host *vha)
  1451. {
  1452. struct qla_hw_data *ha = vha->hw;
  1453. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1454. struct req_que *req = ha->req_q_map[0];
  1455. struct rsp_que *rsp = ha->rsp_q_map[0];
  1456. /* Setup ring parameters in initialization control block. */
  1457. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1458. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1459. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1460. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1461. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1462. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1463. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1464. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1465. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1466. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1467. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1468. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1469. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1470. }
  1471. void
  1472. qla24xx_config_rings(struct scsi_qla_host *vha)
  1473. {
  1474. struct qla_hw_data *ha = vha->hw;
  1475. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1476. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1477. struct qla_msix_entry *msix;
  1478. struct init_cb_24xx *icb;
  1479. uint16_t rid = 0;
  1480. struct req_que *req = ha->req_q_map[0];
  1481. struct rsp_que *rsp = ha->rsp_q_map[0];
  1482. /* Setup ring parameters in initialization control block. */
  1483. icb = (struct init_cb_24xx *)ha->init_cb;
  1484. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1485. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1486. icb->request_q_length = cpu_to_le16(req->length);
  1487. icb->response_q_length = cpu_to_le16(rsp->length);
  1488. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1489. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1490. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1491. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1492. if (ha->mqenable || IS_QLA83XX(ha)) {
  1493. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1494. icb->rid = __constant_cpu_to_le16(rid);
  1495. if (ha->flags.msix_enabled) {
  1496. msix = &ha->msix_entries[1];
  1497. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1498. "Registering vector 0x%x for base que.\n",
  1499. msix->entry);
  1500. icb->msix = cpu_to_le16(msix->entry);
  1501. }
  1502. /* Use alternate PCI bus number */
  1503. if (MSB(rid))
  1504. icb->firmware_options_2 |=
  1505. __constant_cpu_to_le32(BIT_19);
  1506. /* Use alternate PCI devfn */
  1507. if (LSB(rid))
  1508. icb->firmware_options_2 |=
  1509. __constant_cpu_to_le32(BIT_18);
  1510. /* Use Disable MSIX Handshake mode for capable adapters */
  1511. if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
  1512. (ha->flags.msix_enabled)) {
  1513. icb->firmware_options_2 &=
  1514. __constant_cpu_to_le32(~BIT_22);
  1515. ha->flags.disable_msix_handshake = 1;
  1516. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1517. "MSIX Handshake Disable Mode turned on.\n");
  1518. } else {
  1519. icb->firmware_options_2 |=
  1520. __constant_cpu_to_le32(BIT_22);
  1521. }
  1522. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1523. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1524. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1525. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1526. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1527. } else {
  1528. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1529. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1530. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1531. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1532. }
  1533. /* PCI posting */
  1534. RD_REG_DWORD(&ioreg->hccr);
  1535. }
  1536. /**
  1537. * qla2x00_init_rings() - Initializes firmware.
  1538. * @ha: HA context
  1539. *
  1540. * Beginning of request ring has initialization control block already built
  1541. * by nvram config routine.
  1542. *
  1543. * Returns 0 on success.
  1544. */
  1545. static int
  1546. qla2x00_init_rings(scsi_qla_host_t *vha)
  1547. {
  1548. int rval;
  1549. unsigned long flags = 0;
  1550. int cnt, que;
  1551. struct qla_hw_data *ha = vha->hw;
  1552. struct req_que *req;
  1553. struct rsp_que *rsp;
  1554. struct scsi_qla_host *vp;
  1555. struct mid_init_cb_24xx *mid_init_cb =
  1556. (struct mid_init_cb_24xx *) ha->init_cb;
  1557. spin_lock_irqsave(&ha->hardware_lock, flags);
  1558. /* Clear outstanding commands array. */
  1559. for (que = 0; que < ha->max_req_queues; que++) {
  1560. req = ha->req_q_map[que];
  1561. if (!req)
  1562. continue;
  1563. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1564. req->outstanding_cmds[cnt] = NULL;
  1565. req->current_outstanding_cmd = 1;
  1566. /* Initialize firmware. */
  1567. req->ring_ptr = req->ring;
  1568. req->ring_index = 0;
  1569. req->cnt = req->length;
  1570. }
  1571. for (que = 0; que < ha->max_rsp_queues; que++) {
  1572. rsp = ha->rsp_q_map[que];
  1573. if (!rsp)
  1574. continue;
  1575. /* Initialize response queue entries */
  1576. qla2x00_init_response_q_entries(rsp);
  1577. }
  1578. spin_lock(&ha->vport_slock);
  1579. /* Clear RSCN queue. */
  1580. list_for_each_entry(vp, &ha->vp_list, list) {
  1581. vp->rscn_in_ptr = 0;
  1582. vp->rscn_out_ptr = 0;
  1583. }
  1584. spin_unlock(&ha->vport_slock);
  1585. ha->isp_ops->config_rings(vha);
  1586. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1587. /* Update any ISP specific firmware options before initialization. */
  1588. ha->isp_ops->update_fw_options(vha);
  1589. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1590. if (ha->flags.npiv_supported) {
  1591. if (ha->operating_mode == LOOP)
  1592. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1593. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1594. }
  1595. if (IS_FWI2_CAPABLE(ha)) {
  1596. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1597. mid_init_cb->init_cb.execution_throttle =
  1598. cpu_to_le16(ha->fw_xcb_count);
  1599. }
  1600. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1601. if (rval) {
  1602. ql_log(ql_log_fatal, vha, 0x00d2,
  1603. "Init Firmware **** FAILED ****.\n");
  1604. } else {
  1605. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1606. "Init Firmware -- success.\n");
  1607. }
  1608. return (rval);
  1609. }
  1610. /**
  1611. * qla2x00_fw_ready() - Waits for firmware ready.
  1612. * @ha: HA context
  1613. *
  1614. * Returns 0 on success.
  1615. */
  1616. static int
  1617. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1618. {
  1619. int rval;
  1620. unsigned long wtime, mtime, cs84xx_time;
  1621. uint16_t min_wait; /* Minimum wait time if loop is down */
  1622. uint16_t wait_time; /* Wait time if loop is coming ready */
  1623. uint16_t state[5];
  1624. struct qla_hw_data *ha = vha->hw;
  1625. rval = QLA_SUCCESS;
  1626. /* 20 seconds for loop down. */
  1627. min_wait = 20;
  1628. /*
  1629. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1630. * our own processing.
  1631. */
  1632. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1633. wait_time = min_wait;
  1634. }
  1635. /* Min wait time if loop down */
  1636. mtime = jiffies + (min_wait * HZ);
  1637. /* wait time before firmware ready */
  1638. wtime = jiffies + (wait_time * HZ);
  1639. /* Wait for ISP to finish LIP */
  1640. if (!vha->flags.init_done)
  1641. ql_log(ql_log_info, vha, 0x801e,
  1642. "Waiting for LIP to complete.\n");
  1643. do {
  1644. rval = qla2x00_get_firmware_state(vha, state);
  1645. if (rval == QLA_SUCCESS) {
  1646. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1647. vha->device_flags &= ~DFLG_NO_CABLE;
  1648. }
  1649. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1650. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1651. "fw_state=%x 84xx=%x.\n", state[0],
  1652. state[2]);
  1653. if ((state[2] & FSTATE_LOGGED_IN) &&
  1654. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1655. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1656. "Sending verify iocb.\n");
  1657. cs84xx_time = jiffies;
  1658. rval = qla84xx_init_chip(vha);
  1659. if (rval != QLA_SUCCESS) {
  1660. ql_log(ql_log_warn,
  1661. vha, 0x8007,
  1662. "Init chip failed.\n");
  1663. break;
  1664. }
  1665. /* Add time taken to initialize. */
  1666. cs84xx_time = jiffies - cs84xx_time;
  1667. wtime += cs84xx_time;
  1668. mtime += cs84xx_time;
  1669. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  1670. "Increasing wait time by %ld. "
  1671. "New time %ld.\n", cs84xx_time,
  1672. wtime);
  1673. }
  1674. } else if (state[0] == FSTATE_READY) {
  1675. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1676. "F/W Ready - OK.\n");
  1677. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1678. &ha->login_timeout, &ha->r_a_tov);
  1679. rval = QLA_SUCCESS;
  1680. break;
  1681. }
  1682. rval = QLA_FUNCTION_FAILED;
  1683. if (atomic_read(&vha->loop_down_timer) &&
  1684. state[0] != FSTATE_READY) {
  1685. /* Loop down. Timeout on min_wait for states
  1686. * other than Wait for Login.
  1687. */
  1688. if (time_after_eq(jiffies, mtime)) {
  1689. ql_log(ql_log_info, vha, 0x8038,
  1690. "Cable is unplugged...\n");
  1691. vha->device_flags |= DFLG_NO_CABLE;
  1692. break;
  1693. }
  1694. }
  1695. } else {
  1696. /* Mailbox cmd failed. Timeout on min_wait. */
  1697. if (time_after_eq(jiffies, mtime) ||
  1698. ha->flags.isp82xx_fw_hung)
  1699. break;
  1700. }
  1701. if (time_after_eq(jiffies, wtime))
  1702. break;
  1703. /* Delay for a while */
  1704. msleep(500);
  1705. } while (1);
  1706. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1707. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1708. state[1], state[2], state[3], state[4], jiffies);
  1709. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  1710. ql_log(ql_log_warn, vha, 0x803b,
  1711. "Firmware ready **** FAILED ****.\n");
  1712. }
  1713. return (rval);
  1714. }
  1715. /*
  1716. * qla2x00_configure_hba
  1717. * Setup adapter context.
  1718. *
  1719. * Input:
  1720. * ha = adapter state pointer.
  1721. *
  1722. * Returns:
  1723. * 0 = success
  1724. *
  1725. * Context:
  1726. * Kernel context.
  1727. */
  1728. static int
  1729. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1730. {
  1731. int rval;
  1732. uint16_t loop_id;
  1733. uint16_t topo;
  1734. uint16_t sw_cap;
  1735. uint8_t al_pa;
  1736. uint8_t area;
  1737. uint8_t domain;
  1738. char connect_type[22];
  1739. struct qla_hw_data *ha = vha->hw;
  1740. /* Get host addresses. */
  1741. rval = qla2x00_get_adapter_id(vha,
  1742. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1743. if (rval != QLA_SUCCESS) {
  1744. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1745. IS_CNA_CAPABLE(ha) ||
  1746. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1747. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1748. "Loop is in a transition state.\n");
  1749. } else {
  1750. ql_log(ql_log_warn, vha, 0x2009,
  1751. "Unable to get host loop ID.\n");
  1752. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1753. }
  1754. return (rval);
  1755. }
  1756. if (topo == 4) {
  1757. ql_log(ql_log_info, vha, 0x200a,
  1758. "Cannot get topology - retrying.\n");
  1759. return (QLA_FUNCTION_FAILED);
  1760. }
  1761. vha->loop_id = loop_id;
  1762. /* initialize */
  1763. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1764. ha->operating_mode = LOOP;
  1765. ha->switch_cap = 0;
  1766. switch (topo) {
  1767. case 0:
  1768. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1769. ha->current_topology = ISP_CFG_NL;
  1770. strcpy(connect_type, "(Loop)");
  1771. break;
  1772. case 1:
  1773. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1774. ha->switch_cap = sw_cap;
  1775. ha->current_topology = ISP_CFG_FL;
  1776. strcpy(connect_type, "(FL_Port)");
  1777. break;
  1778. case 2:
  1779. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1780. ha->operating_mode = P2P;
  1781. ha->current_topology = ISP_CFG_N;
  1782. strcpy(connect_type, "(N_Port-to-N_Port)");
  1783. break;
  1784. case 3:
  1785. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1786. ha->switch_cap = sw_cap;
  1787. ha->operating_mode = P2P;
  1788. ha->current_topology = ISP_CFG_F;
  1789. strcpy(connect_type, "(F_Port)");
  1790. break;
  1791. default:
  1792. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1793. "HBA in unknown topology %x, using NL.\n", topo);
  1794. ha->current_topology = ISP_CFG_NL;
  1795. strcpy(connect_type, "(Loop)");
  1796. break;
  1797. }
  1798. /* Save Host port and loop ID. */
  1799. /* byte order - Big Endian */
  1800. vha->d_id.b.domain = domain;
  1801. vha->d_id.b.area = area;
  1802. vha->d_id.b.al_pa = al_pa;
  1803. if (!vha->flags.init_done)
  1804. ql_log(ql_log_info, vha, 0x2010,
  1805. "Topology - %s, Host Loop address 0x%x.\n",
  1806. connect_type, vha->loop_id);
  1807. if (rval) {
  1808. ql_log(ql_log_warn, vha, 0x2011,
  1809. "%s FAILED\n", __func__);
  1810. } else {
  1811. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1812. "%s success\n", __func__);
  1813. }
  1814. return(rval);
  1815. }
  1816. inline void
  1817. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1818. char *def)
  1819. {
  1820. char *st, *en;
  1821. uint16_t index;
  1822. struct qla_hw_data *ha = vha->hw;
  1823. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1824. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
  1825. if (memcmp(model, BINZERO, len) != 0) {
  1826. strncpy(ha->model_number, model, len);
  1827. st = en = ha->model_number;
  1828. en += len - 1;
  1829. while (en > st) {
  1830. if (*en != 0x20 && *en != 0x00)
  1831. break;
  1832. *en-- = '\0';
  1833. }
  1834. index = (ha->pdev->subsystem_device & 0xff);
  1835. if (use_tbl &&
  1836. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1837. index < QLA_MODEL_NAMES)
  1838. strncpy(ha->model_desc,
  1839. qla2x00_model_name[index * 2 + 1],
  1840. sizeof(ha->model_desc) - 1);
  1841. } else {
  1842. index = (ha->pdev->subsystem_device & 0xff);
  1843. if (use_tbl &&
  1844. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1845. index < QLA_MODEL_NAMES) {
  1846. strcpy(ha->model_number,
  1847. qla2x00_model_name[index * 2]);
  1848. strncpy(ha->model_desc,
  1849. qla2x00_model_name[index * 2 + 1],
  1850. sizeof(ha->model_desc) - 1);
  1851. } else {
  1852. strcpy(ha->model_number, def);
  1853. }
  1854. }
  1855. if (IS_FWI2_CAPABLE(ha))
  1856. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1857. sizeof(ha->model_desc));
  1858. }
  1859. /* On sparc systems, obtain port and node WWN from firmware
  1860. * properties.
  1861. */
  1862. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1863. {
  1864. #ifdef CONFIG_SPARC
  1865. struct qla_hw_data *ha = vha->hw;
  1866. struct pci_dev *pdev = ha->pdev;
  1867. struct device_node *dp = pci_device_to_OF_node(pdev);
  1868. const u8 *val;
  1869. int len;
  1870. val = of_get_property(dp, "port-wwn", &len);
  1871. if (val && len >= WWN_SIZE)
  1872. memcpy(nv->port_name, val, WWN_SIZE);
  1873. val = of_get_property(dp, "node-wwn", &len);
  1874. if (val && len >= WWN_SIZE)
  1875. memcpy(nv->node_name, val, WWN_SIZE);
  1876. #endif
  1877. }
  1878. /*
  1879. * NVRAM configuration for ISP 2xxx
  1880. *
  1881. * Input:
  1882. * ha = adapter block pointer.
  1883. *
  1884. * Output:
  1885. * initialization control block in response_ring
  1886. * host adapters parameters in host adapter block
  1887. *
  1888. * Returns:
  1889. * 0 = success.
  1890. */
  1891. int
  1892. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1893. {
  1894. int rval;
  1895. uint8_t chksum = 0;
  1896. uint16_t cnt;
  1897. uint8_t *dptr1, *dptr2;
  1898. struct qla_hw_data *ha = vha->hw;
  1899. init_cb_t *icb = ha->init_cb;
  1900. nvram_t *nv = ha->nvram;
  1901. uint8_t *ptr = ha->nvram;
  1902. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1903. rval = QLA_SUCCESS;
  1904. /* Determine NVRAM starting address. */
  1905. ha->nvram_size = sizeof(nvram_t);
  1906. ha->nvram_base = 0;
  1907. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1908. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1909. ha->nvram_base = 0x80;
  1910. /* Get NVRAM data and calculate checksum. */
  1911. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1912. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1913. chksum += *ptr++;
  1914. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1915. "Contents of NVRAM.\n");
  1916. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1917. (uint8_t *)nv, ha->nvram_size);
  1918. /* Bad NVRAM data, set defaults parameters. */
  1919. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1920. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1921. /* Reset NVRAM data. */
  1922. ql_log(ql_log_warn, vha, 0x0064,
  1923. "Inconisistent NVRAM "
  1924. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1925. chksum, nv->id[0], nv->nvram_version);
  1926. ql_log(ql_log_warn, vha, 0x0065,
  1927. "Falling back to "
  1928. "functioning (yet invalid -- WWPN) defaults.\n");
  1929. /*
  1930. * Set default initialization control block.
  1931. */
  1932. memset(nv, 0, ha->nvram_size);
  1933. nv->parameter_block_version = ICB_VERSION;
  1934. if (IS_QLA23XX(ha)) {
  1935. nv->firmware_options[0] = BIT_2 | BIT_1;
  1936. nv->firmware_options[1] = BIT_7 | BIT_5;
  1937. nv->add_firmware_options[0] = BIT_5;
  1938. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1939. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1940. nv->special_options[1] = BIT_7;
  1941. } else if (IS_QLA2200(ha)) {
  1942. nv->firmware_options[0] = BIT_2 | BIT_1;
  1943. nv->firmware_options[1] = BIT_7 | BIT_5;
  1944. nv->add_firmware_options[0] = BIT_5;
  1945. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1946. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1947. } else if (IS_QLA2100(ha)) {
  1948. nv->firmware_options[0] = BIT_3 | BIT_1;
  1949. nv->firmware_options[1] = BIT_5;
  1950. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1951. }
  1952. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1953. nv->execution_throttle = __constant_cpu_to_le16(16);
  1954. nv->retry_count = 8;
  1955. nv->retry_delay = 1;
  1956. nv->port_name[0] = 33;
  1957. nv->port_name[3] = 224;
  1958. nv->port_name[4] = 139;
  1959. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1960. nv->login_timeout = 4;
  1961. /*
  1962. * Set default host adapter parameters
  1963. */
  1964. nv->host_p[1] = BIT_2;
  1965. nv->reset_delay = 5;
  1966. nv->port_down_retry_count = 8;
  1967. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1968. nv->link_down_timeout = 60;
  1969. rval = 1;
  1970. }
  1971. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1972. /*
  1973. * The SN2 does not provide BIOS emulation which means you can't change
  1974. * potentially bogus BIOS settings. Force the use of default settings
  1975. * for link rate and frame size. Hope that the rest of the settings
  1976. * are valid.
  1977. */
  1978. if (ia64_platform_is("sn2")) {
  1979. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1980. if (IS_QLA23XX(ha))
  1981. nv->special_options[1] = BIT_7;
  1982. }
  1983. #endif
  1984. /* Reset Initialization control block */
  1985. memset(icb, 0, ha->init_cb_size);
  1986. /*
  1987. * Setup driver NVRAM options.
  1988. */
  1989. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1990. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1991. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1992. nv->firmware_options[1] &= ~BIT_4;
  1993. if (IS_QLA23XX(ha)) {
  1994. nv->firmware_options[0] |= BIT_2;
  1995. nv->firmware_options[0] &= ~BIT_3;
  1996. nv->firmware_options[0] &= ~BIT_6;
  1997. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1998. if (IS_QLA2300(ha)) {
  1999. if (ha->fb_rev == FPM_2310) {
  2000. strcpy(ha->model_number, "QLA2310");
  2001. } else {
  2002. strcpy(ha->model_number, "QLA2300");
  2003. }
  2004. } else {
  2005. qla2x00_set_model_info(vha, nv->model_number,
  2006. sizeof(nv->model_number), "QLA23xx");
  2007. }
  2008. } else if (IS_QLA2200(ha)) {
  2009. nv->firmware_options[0] |= BIT_2;
  2010. /*
  2011. * 'Point-to-point preferred, else loop' is not a safe
  2012. * connection mode setting.
  2013. */
  2014. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  2015. (BIT_5 | BIT_4)) {
  2016. /* Force 'loop preferred, else point-to-point'. */
  2017. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  2018. nv->add_firmware_options[0] |= BIT_5;
  2019. }
  2020. strcpy(ha->model_number, "QLA22xx");
  2021. } else /*if (IS_QLA2100(ha))*/ {
  2022. strcpy(ha->model_number, "QLA2100");
  2023. }
  2024. /*
  2025. * Copy over NVRAM RISC parameter block to initialization control block.
  2026. */
  2027. dptr1 = (uint8_t *)icb;
  2028. dptr2 = (uint8_t *)&nv->parameter_block_version;
  2029. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  2030. while (cnt--)
  2031. *dptr1++ = *dptr2++;
  2032. /* Copy 2nd half. */
  2033. dptr1 = (uint8_t *)icb->add_firmware_options;
  2034. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  2035. while (cnt--)
  2036. *dptr1++ = *dptr2++;
  2037. /* Use alternate WWN? */
  2038. if (nv->host_p[1] & BIT_7) {
  2039. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  2040. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  2041. }
  2042. /* Prepare nodename */
  2043. if ((icb->firmware_options[1] & BIT_6) == 0) {
  2044. /*
  2045. * Firmware will apply the following mask if the nodename was
  2046. * not provided.
  2047. */
  2048. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  2049. icb->node_name[0] &= 0xF0;
  2050. }
  2051. /*
  2052. * Set host adapter parameters.
  2053. */
  2054. /*
  2055. * BIT_7 in the host-parameters section allows for modification to
  2056. * internal driver logging.
  2057. */
  2058. if (nv->host_p[0] & BIT_7)
  2059. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  2060. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2061. /* Always load RISC code on non ISP2[12]00 chips. */
  2062. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2063. ha->flags.disable_risc_code_load = 0;
  2064. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2065. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2066. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2067. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2068. ha->flags.disable_serdes = 0;
  2069. ha->operating_mode =
  2070. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2071. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2072. sizeof(ha->fw_seriallink_options));
  2073. /* save HBA serial number */
  2074. ha->serial0 = icb->port_name[5];
  2075. ha->serial1 = icb->port_name[6];
  2076. ha->serial2 = icb->port_name[7];
  2077. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2078. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2079. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2080. ha->retry_count = nv->retry_count;
  2081. /* Set minimum login_timeout to 4 seconds. */
  2082. if (nv->login_timeout != ql2xlogintimeout)
  2083. nv->login_timeout = ql2xlogintimeout;
  2084. if (nv->login_timeout < 4)
  2085. nv->login_timeout = 4;
  2086. ha->login_timeout = nv->login_timeout;
  2087. icb->login_timeout = nv->login_timeout;
  2088. /* Set minimum RATOV to 100 tenths of a second. */
  2089. ha->r_a_tov = 100;
  2090. ha->loop_reset_delay = nv->reset_delay;
  2091. /* Link Down Timeout = 0:
  2092. *
  2093. * When Port Down timer expires we will start returning
  2094. * I/O's to OS with "DID_NO_CONNECT".
  2095. *
  2096. * Link Down Timeout != 0:
  2097. *
  2098. * The driver waits for the link to come up after link down
  2099. * before returning I/Os to OS with "DID_NO_CONNECT".
  2100. */
  2101. if (nv->link_down_timeout == 0) {
  2102. ha->loop_down_abort_time =
  2103. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2104. } else {
  2105. ha->link_down_timeout = nv->link_down_timeout;
  2106. ha->loop_down_abort_time =
  2107. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2108. }
  2109. /*
  2110. * Need enough time to try and get the port back.
  2111. */
  2112. ha->port_down_retry_count = nv->port_down_retry_count;
  2113. if (qlport_down_retry)
  2114. ha->port_down_retry_count = qlport_down_retry;
  2115. /* Set login_retry_count */
  2116. ha->login_retry_count = nv->retry_count;
  2117. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2118. ha->port_down_retry_count > 3)
  2119. ha->login_retry_count = ha->port_down_retry_count;
  2120. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2121. ha->login_retry_count = ha->port_down_retry_count;
  2122. if (ql2xloginretrycount)
  2123. ha->login_retry_count = ql2xloginretrycount;
  2124. icb->lun_enables = __constant_cpu_to_le16(0);
  2125. icb->command_resource_count = 0;
  2126. icb->immediate_notify_resource_count = 0;
  2127. icb->timeout = __constant_cpu_to_le16(0);
  2128. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2129. /* Enable RIO */
  2130. icb->firmware_options[0] &= ~BIT_3;
  2131. icb->add_firmware_options[0] &=
  2132. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2133. icb->add_firmware_options[0] |= BIT_2;
  2134. icb->response_accumulation_timer = 3;
  2135. icb->interrupt_delay_timer = 5;
  2136. vha->flags.process_response_queue = 1;
  2137. } else {
  2138. /* Enable ZIO. */
  2139. if (!vha->flags.init_done) {
  2140. ha->zio_mode = icb->add_firmware_options[0] &
  2141. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2142. ha->zio_timer = icb->interrupt_delay_timer ?
  2143. icb->interrupt_delay_timer: 2;
  2144. }
  2145. icb->add_firmware_options[0] &=
  2146. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2147. vha->flags.process_response_queue = 0;
  2148. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2149. ha->zio_mode = QLA_ZIO_MODE_6;
  2150. ql_log(ql_log_info, vha, 0x0068,
  2151. "ZIO mode %d enabled; timer delay (%d us).\n",
  2152. ha->zio_mode, ha->zio_timer * 100);
  2153. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2154. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2155. vha->flags.process_response_queue = 1;
  2156. }
  2157. }
  2158. if (rval) {
  2159. ql_log(ql_log_warn, vha, 0x0069,
  2160. "NVRAM configuration failed.\n");
  2161. }
  2162. return (rval);
  2163. }
  2164. static void
  2165. qla2x00_rport_del(void *data)
  2166. {
  2167. fc_port_t *fcport = data;
  2168. struct fc_rport *rport;
  2169. unsigned long flags;
  2170. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2171. rport = fcport->drport ? fcport->drport: fcport->rport;
  2172. fcport->drport = NULL;
  2173. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2174. if (rport)
  2175. fc_remote_port_delete(rport);
  2176. }
  2177. /**
  2178. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2179. * @ha: HA context
  2180. * @flags: allocation flags
  2181. *
  2182. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2183. */
  2184. fc_port_t *
  2185. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2186. {
  2187. fc_port_t *fcport;
  2188. fcport = kzalloc(sizeof(fc_port_t), flags);
  2189. if (!fcport)
  2190. return NULL;
  2191. /* Setup fcport template structure. */
  2192. fcport->vha = vha;
  2193. fcport->vp_idx = vha->vp_idx;
  2194. fcport->port_type = FCT_UNKNOWN;
  2195. fcport->loop_id = FC_NO_LOOP_ID;
  2196. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2197. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2198. return fcport;
  2199. }
  2200. /*
  2201. * qla2x00_configure_loop
  2202. * Updates Fibre Channel Device Database with what is actually on loop.
  2203. *
  2204. * Input:
  2205. * ha = adapter block pointer.
  2206. *
  2207. * Returns:
  2208. * 0 = success.
  2209. * 1 = error.
  2210. * 2 = database was full and device was not configured.
  2211. */
  2212. static int
  2213. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2214. {
  2215. int rval;
  2216. unsigned long flags, save_flags;
  2217. struct qla_hw_data *ha = vha->hw;
  2218. rval = QLA_SUCCESS;
  2219. /* Get Initiator ID */
  2220. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2221. rval = qla2x00_configure_hba(vha);
  2222. if (rval != QLA_SUCCESS) {
  2223. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2224. "Unable to configure HBA.\n");
  2225. return (rval);
  2226. }
  2227. }
  2228. save_flags = flags = vha->dpc_flags;
  2229. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2230. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2231. /*
  2232. * If we have both an RSCN and PORT UPDATE pending then handle them
  2233. * both at the same time.
  2234. */
  2235. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2236. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2237. qla2x00_get_data_rate(vha);
  2238. /* Determine what we need to do */
  2239. if (ha->current_topology == ISP_CFG_FL &&
  2240. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2241. vha->flags.rscn_queue_overflow = 1;
  2242. set_bit(RSCN_UPDATE, &flags);
  2243. } else if (ha->current_topology == ISP_CFG_F &&
  2244. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2245. vha->flags.rscn_queue_overflow = 1;
  2246. set_bit(RSCN_UPDATE, &flags);
  2247. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2248. } else if (ha->current_topology == ISP_CFG_N) {
  2249. clear_bit(RSCN_UPDATE, &flags);
  2250. } else if (!vha->flags.online ||
  2251. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2252. vha->flags.rscn_queue_overflow = 1;
  2253. set_bit(RSCN_UPDATE, &flags);
  2254. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2255. }
  2256. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2257. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2258. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2259. "Loop resync needed, failing.\n");
  2260. rval = QLA_FUNCTION_FAILED;
  2261. }
  2262. else
  2263. rval = qla2x00_configure_local_loop(vha);
  2264. }
  2265. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2266. if (LOOP_TRANSITION(vha)) {
  2267. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2268. "Needs RSCN update and loop transition.\n");
  2269. rval = QLA_FUNCTION_FAILED;
  2270. }
  2271. else
  2272. rval = qla2x00_configure_fabric(vha);
  2273. }
  2274. if (rval == QLA_SUCCESS) {
  2275. if (atomic_read(&vha->loop_down_timer) ||
  2276. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2277. rval = QLA_FUNCTION_FAILED;
  2278. } else {
  2279. atomic_set(&vha->loop_state, LOOP_READY);
  2280. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2281. "LOOP READY.\n");
  2282. }
  2283. }
  2284. if (rval) {
  2285. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2286. "%s *** FAILED ***.\n", __func__);
  2287. } else {
  2288. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2289. "%s: exiting normally.\n", __func__);
  2290. }
  2291. /* Restore state if a resync event occurred during processing */
  2292. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2293. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2294. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2295. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2296. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2297. if (!IS_ALOGIO_CAPABLE(ha))
  2298. vha->flags.rscn_queue_overflow = 1;
  2299. }
  2300. }
  2301. return (rval);
  2302. }
  2303. /*
  2304. * qla2x00_configure_local_loop
  2305. * Updates Fibre Channel Device Database with local loop devices.
  2306. *
  2307. * Input:
  2308. * ha = adapter block pointer.
  2309. *
  2310. * Returns:
  2311. * 0 = success.
  2312. */
  2313. static int
  2314. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2315. {
  2316. int rval, rval2;
  2317. int found_devs;
  2318. int found;
  2319. fc_port_t *fcport, *new_fcport;
  2320. uint16_t index;
  2321. uint16_t entries;
  2322. char *id_iter;
  2323. uint16_t loop_id;
  2324. uint8_t domain, area, al_pa;
  2325. struct qla_hw_data *ha = vha->hw;
  2326. found_devs = 0;
  2327. new_fcport = NULL;
  2328. entries = MAX_FIBRE_DEVICES;
  2329. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2330. "Getting FCAL position map.\n");
  2331. if (ql2xextended_error_logging & ql_dbg_disc)
  2332. qla2x00_get_fcal_position_map(vha, NULL);
  2333. /* Get list of logged in devices. */
  2334. memset(ha->gid_list, 0, GID_LIST_SIZE);
  2335. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2336. &entries);
  2337. if (rval != QLA_SUCCESS)
  2338. goto cleanup_allocation;
  2339. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2340. "Entries in ID list (%d).\n", entries);
  2341. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2342. (uint8_t *)ha->gid_list,
  2343. entries * sizeof(struct gid_list_info));
  2344. /* Allocate temporary fcport for any new fcports discovered. */
  2345. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2346. if (new_fcport == NULL) {
  2347. ql_log(ql_log_warn, vha, 0x2018,
  2348. "Memory allocation failed for fcport.\n");
  2349. rval = QLA_MEMORY_ALLOC_FAILED;
  2350. goto cleanup_allocation;
  2351. }
  2352. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2353. /*
  2354. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2355. */
  2356. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2357. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2358. fcport->port_type != FCT_BROADCAST &&
  2359. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2360. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2361. "Marking port lost loop_id=0x%04x.\n",
  2362. fcport->loop_id);
  2363. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2364. }
  2365. }
  2366. /* Add devices to port list. */
  2367. id_iter = (char *)ha->gid_list;
  2368. for (index = 0; index < entries; index++) {
  2369. domain = ((struct gid_list_info *)id_iter)->domain;
  2370. area = ((struct gid_list_info *)id_iter)->area;
  2371. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2372. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2373. loop_id = (uint16_t)
  2374. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2375. else
  2376. loop_id = le16_to_cpu(
  2377. ((struct gid_list_info *)id_iter)->loop_id);
  2378. id_iter += ha->gid_list_info_size;
  2379. /* Bypass reserved domain fields. */
  2380. if ((domain & 0xf0) == 0xf0)
  2381. continue;
  2382. /* Bypass if not same domain and area of adapter. */
  2383. if (area && domain &&
  2384. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2385. continue;
  2386. /* Bypass invalid local loop ID. */
  2387. if (loop_id > LAST_LOCAL_LOOP_ID)
  2388. continue;
  2389. /* Fill in member data. */
  2390. new_fcport->d_id.b.domain = domain;
  2391. new_fcport->d_id.b.area = area;
  2392. new_fcport->d_id.b.al_pa = al_pa;
  2393. new_fcport->loop_id = loop_id;
  2394. new_fcport->vp_idx = vha->vp_idx;
  2395. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2396. if (rval2 != QLA_SUCCESS) {
  2397. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2398. "Failed to retrieve fcport information "
  2399. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2400. rval2, new_fcport->loop_id);
  2401. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2402. "Scheduling resync.\n");
  2403. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2404. continue;
  2405. }
  2406. /* Check for matching device in port list. */
  2407. found = 0;
  2408. fcport = NULL;
  2409. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2410. if (memcmp(new_fcport->port_name, fcport->port_name,
  2411. WWN_SIZE))
  2412. continue;
  2413. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2414. fcport->loop_id = new_fcport->loop_id;
  2415. fcport->port_type = new_fcport->port_type;
  2416. fcport->d_id.b24 = new_fcport->d_id.b24;
  2417. memcpy(fcport->node_name, new_fcport->node_name,
  2418. WWN_SIZE);
  2419. found++;
  2420. break;
  2421. }
  2422. if (!found) {
  2423. /* New device, add to fcports list. */
  2424. if (vha->vp_idx) {
  2425. new_fcport->vha = vha;
  2426. new_fcport->vp_idx = vha->vp_idx;
  2427. }
  2428. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2429. /* Allocate a new replacement fcport. */
  2430. fcport = new_fcport;
  2431. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2432. if (new_fcport == NULL) {
  2433. ql_log(ql_log_warn, vha, 0x201c,
  2434. "Failed to allocate memory for fcport.\n");
  2435. rval = QLA_MEMORY_ALLOC_FAILED;
  2436. goto cleanup_allocation;
  2437. }
  2438. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2439. }
  2440. /* Base iIDMA settings on HBA port speed. */
  2441. fcport->fp_speed = ha->link_data_rate;
  2442. qla2x00_update_fcport(vha, fcport);
  2443. found_devs++;
  2444. }
  2445. cleanup_allocation:
  2446. kfree(new_fcport);
  2447. if (rval != QLA_SUCCESS) {
  2448. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2449. "Configure local loop error exit: rval=%x.\n", rval);
  2450. }
  2451. return (rval);
  2452. }
  2453. static void
  2454. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2455. {
  2456. #define LS_UNKNOWN 2
  2457. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2458. char *link_speed;
  2459. int rval;
  2460. uint16_t mb[4];
  2461. struct qla_hw_data *ha = vha->hw;
  2462. if (!IS_IIDMA_CAPABLE(ha))
  2463. return;
  2464. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2465. return;
  2466. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2467. fcport->fp_speed > ha->link_data_rate)
  2468. return;
  2469. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2470. mb);
  2471. if (rval != QLA_SUCCESS) {
  2472. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2473. "Unable to adjust iIDMA "
  2474. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2475. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2476. fcport->port_name[2], fcport->port_name[3],
  2477. fcport->port_name[4], fcport->port_name[5],
  2478. fcport->port_name[6], fcport->port_name[7], rval,
  2479. fcport->fp_speed, mb[0], mb[1]);
  2480. } else {
  2481. link_speed = link_speeds[LS_UNKNOWN];
  2482. if (fcport->fp_speed < 5)
  2483. link_speed = link_speeds[fcport->fp_speed];
  2484. else if (fcport->fp_speed == 0x13)
  2485. link_speed = link_speeds[5];
  2486. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2487. "iIDMA adjusted to %s GB/s "
  2488. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2489. fcport->port_name[0], fcport->port_name[1],
  2490. fcport->port_name[2], fcport->port_name[3],
  2491. fcport->port_name[4], fcport->port_name[5],
  2492. fcport->port_name[6], fcport->port_name[7]);
  2493. }
  2494. }
  2495. static void
  2496. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2497. {
  2498. struct fc_rport_identifiers rport_ids;
  2499. struct fc_rport *rport;
  2500. unsigned long flags;
  2501. qla2x00_rport_del(fcport);
  2502. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2503. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2504. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2505. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2506. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2507. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2508. if (!rport) {
  2509. ql_log(ql_log_warn, vha, 0x2006,
  2510. "Unable to allocate fc remote port.\n");
  2511. return;
  2512. }
  2513. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2514. *((fc_port_t **)rport->dd_data) = fcport;
  2515. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2516. rport->supported_classes = fcport->supported_classes;
  2517. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2518. if (fcport->port_type == FCT_INITIATOR)
  2519. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2520. if (fcport->port_type == FCT_TARGET)
  2521. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2522. fc_remote_port_rolechg(rport, rport_ids.roles);
  2523. }
  2524. /*
  2525. * qla2x00_update_fcport
  2526. * Updates device on list.
  2527. *
  2528. * Input:
  2529. * ha = adapter block pointer.
  2530. * fcport = port structure pointer.
  2531. *
  2532. * Return:
  2533. * 0 - Success
  2534. * BIT_0 - error
  2535. *
  2536. * Context:
  2537. * Kernel context.
  2538. */
  2539. void
  2540. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2541. {
  2542. fcport->vha = vha;
  2543. fcport->login_retry = 0;
  2544. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2545. qla2x00_iidma_fcport(vha, fcport);
  2546. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2547. qla2x00_reg_remote_port(vha, fcport);
  2548. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2549. }
  2550. /*
  2551. * qla2x00_configure_fabric
  2552. * Setup SNS devices with loop ID's.
  2553. *
  2554. * Input:
  2555. * ha = adapter block pointer.
  2556. *
  2557. * Returns:
  2558. * 0 = success.
  2559. * BIT_0 = error
  2560. */
  2561. static int
  2562. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2563. {
  2564. int rval, rval2;
  2565. fc_port_t *fcport, *fcptemp;
  2566. uint16_t next_loopid;
  2567. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2568. uint16_t loop_id;
  2569. LIST_HEAD(new_fcports);
  2570. struct qla_hw_data *ha = vha->hw;
  2571. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2572. /* If FL port exists, then SNS is present */
  2573. if (IS_FWI2_CAPABLE(ha))
  2574. loop_id = NPH_F_PORT;
  2575. else
  2576. loop_id = SNS_FL_PORT;
  2577. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2578. if (rval != QLA_SUCCESS) {
  2579. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2580. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2581. vha->device_flags &= ~SWITCH_FOUND;
  2582. return (QLA_SUCCESS);
  2583. }
  2584. vha->device_flags |= SWITCH_FOUND;
  2585. /* Mark devices that need re-synchronization. */
  2586. rval2 = qla2x00_device_resync(vha);
  2587. if (rval2 == QLA_RSCNS_HANDLED) {
  2588. /* No point doing the scan, just continue. */
  2589. return (QLA_SUCCESS);
  2590. }
  2591. do {
  2592. /* FDMI support. */
  2593. if (ql2xfdmienable &&
  2594. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2595. qla2x00_fdmi_register(vha);
  2596. /* Ensure we are logged into the SNS. */
  2597. if (IS_FWI2_CAPABLE(ha))
  2598. loop_id = NPH_SNS;
  2599. else
  2600. loop_id = SIMPLE_NAME_SERVER;
  2601. ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2602. 0xfc, mb, BIT_1 | BIT_0);
  2603. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2604. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2605. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2606. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2607. mb[2], mb[6], mb[7]);
  2608. return (QLA_SUCCESS);
  2609. }
  2610. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2611. if (qla2x00_rft_id(vha)) {
  2612. /* EMPTY */
  2613. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2614. "Register FC-4 TYPE failed.\n");
  2615. }
  2616. if (qla2x00_rff_id(vha)) {
  2617. /* EMPTY */
  2618. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2619. "Register FC-4 Features failed.\n");
  2620. }
  2621. if (qla2x00_rnn_id(vha)) {
  2622. /* EMPTY */
  2623. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2624. "Register Node Name failed.\n");
  2625. } else if (qla2x00_rsnn_nn(vha)) {
  2626. /* EMPTY */
  2627. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2628. "Register Symobilic Node Name failed.\n");
  2629. }
  2630. }
  2631. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2632. if (rval != QLA_SUCCESS)
  2633. break;
  2634. /*
  2635. * Logout all previous fabric devices marked lost, except
  2636. * FCP2 devices.
  2637. */
  2638. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2639. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2640. break;
  2641. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2642. continue;
  2643. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  2644. qla2x00_mark_device_lost(vha, fcport,
  2645. ql2xplogiabsentdevice, 0);
  2646. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2647. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2648. fcport->port_type != FCT_INITIATOR &&
  2649. fcport->port_type != FCT_BROADCAST) {
  2650. ha->isp_ops->fabric_logout(vha,
  2651. fcport->loop_id,
  2652. fcport->d_id.b.domain,
  2653. fcport->d_id.b.area,
  2654. fcport->d_id.b.al_pa);
  2655. fcport->loop_id = FC_NO_LOOP_ID;
  2656. }
  2657. }
  2658. }
  2659. /* Starting free loop ID. */
  2660. next_loopid = ha->min_external_loopid;
  2661. /*
  2662. * Scan through our port list and login entries that need to be
  2663. * logged in.
  2664. */
  2665. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2666. if (atomic_read(&vha->loop_down_timer) ||
  2667. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2668. break;
  2669. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2670. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2671. continue;
  2672. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2673. fcport->loop_id = next_loopid;
  2674. rval = qla2x00_find_new_loop_id(
  2675. base_vha, fcport);
  2676. if (rval != QLA_SUCCESS) {
  2677. /* Ran out of IDs to use */
  2678. break;
  2679. }
  2680. }
  2681. /* Login and update database */
  2682. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2683. }
  2684. /* Exit if out of loop IDs. */
  2685. if (rval != QLA_SUCCESS) {
  2686. break;
  2687. }
  2688. /*
  2689. * Login and add the new devices to our port list.
  2690. */
  2691. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2692. if (atomic_read(&vha->loop_down_timer) ||
  2693. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2694. break;
  2695. /* Find a new loop ID to use. */
  2696. fcport->loop_id = next_loopid;
  2697. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2698. if (rval != QLA_SUCCESS) {
  2699. /* Ran out of IDs to use */
  2700. break;
  2701. }
  2702. /* Login and update database */
  2703. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2704. if (vha->vp_idx) {
  2705. fcport->vha = vha;
  2706. fcport->vp_idx = vha->vp_idx;
  2707. }
  2708. list_move_tail(&fcport->list, &vha->vp_fcports);
  2709. }
  2710. } while (0);
  2711. /* Free all new device structures not processed. */
  2712. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2713. list_del(&fcport->list);
  2714. kfree(fcport);
  2715. }
  2716. if (rval) {
  2717. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2718. "Configure fabric error exit rval=%d.\n", rval);
  2719. }
  2720. return (rval);
  2721. }
  2722. /*
  2723. * qla2x00_find_all_fabric_devs
  2724. *
  2725. * Input:
  2726. * ha = adapter block pointer.
  2727. * dev = database device entry pointer.
  2728. *
  2729. * Returns:
  2730. * 0 = success.
  2731. *
  2732. * Context:
  2733. * Kernel context.
  2734. */
  2735. static int
  2736. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2737. struct list_head *new_fcports)
  2738. {
  2739. int rval;
  2740. uint16_t loop_id;
  2741. fc_port_t *fcport, *new_fcport, *fcptemp;
  2742. int found;
  2743. sw_info_t *swl;
  2744. int swl_idx;
  2745. int first_dev, last_dev;
  2746. port_id_t wrap = {}, nxt_d_id;
  2747. struct qla_hw_data *ha = vha->hw;
  2748. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2749. struct scsi_qla_host *tvp;
  2750. rval = QLA_SUCCESS;
  2751. /* Try GID_PT to get device list, else GAN. */
  2752. swl = kcalloc(MAX_FIBRE_DEVICES, sizeof(sw_info_t), GFP_KERNEL);
  2753. if (!swl) {
  2754. /*EMPTY*/
  2755. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2756. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2757. } else {
  2758. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2759. kfree(swl);
  2760. swl = NULL;
  2761. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2762. kfree(swl);
  2763. swl = NULL;
  2764. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2765. kfree(swl);
  2766. swl = NULL;
  2767. } else if (ql2xiidmaenable &&
  2768. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2769. qla2x00_gpsc(vha, swl);
  2770. }
  2771. /* If other queries succeeded probe for FC-4 type */
  2772. if (swl)
  2773. qla2x00_gff_id(vha, swl);
  2774. }
  2775. swl_idx = 0;
  2776. /* Allocate temporary fcport for any new fcports discovered. */
  2777. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2778. if (new_fcport == NULL) {
  2779. ql_log(ql_log_warn, vha, 0x205e,
  2780. "Failed to allocate memory for fcport.\n");
  2781. kfree(swl);
  2782. return (QLA_MEMORY_ALLOC_FAILED);
  2783. }
  2784. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2785. /* Set start port ID scan at adapter ID. */
  2786. first_dev = 1;
  2787. last_dev = 0;
  2788. /* Starting free loop ID. */
  2789. loop_id = ha->min_external_loopid;
  2790. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2791. if (qla2x00_is_reserved_id(vha, loop_id))
  2792. continue;
  2793. if (ha->current_topology == ISP_CFG_FL &&
  2794. (atomic_read(&vha->loop_down_timer) ||
  2795. LOOP_TRANSITION(vha))) {
  2796. atomic_set(&vha->loop_down_timer, 0);
  2797. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2798. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2799. break;
  2800. }
  2801. if (swl != NULL) {
  2802. if (last_dev) {
  2803. wrap.b24 = new_fcport->d_id.b24;
  2804. } else {
  2805. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2806. memcpy(new_fcport->node_name,
  2807. swl[swl_idx].node_name, WWN_SIZE);
  2808. memcpy(new_fcport->port_name,
  2809. swl[swl_idx].port_name, WWN_SIZE);
  2810. memcpy(new_fcport->fabric_port_name,
  2811. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2812. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2813. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2814. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2815. last_dev = 1;
  2816. }
  2817. swl_idx++;
  2818. }
  2819. } else {
  2820. /* Send GA_NXT to the switch */
  2821. rval = qla2x00_ga_nxt(vha, new_fcport);
  2822. if (rval != QLA_SUCCESS) {
  2823. ql_log(ql_log_warn, vha, 0x2064,
  2824. "SNS scan failed -- assuming "
  2825. "zero-entry result.\n");
  2826. list_for_each_entry_safe(fcport, fcptemp,
  2827. new_fcports, list) {
  2828. list_del(&fcport->list);
  2829. kfree(fcport);
  2830. }
  2831. rval = QLA_SUCCESS;
  2832. break;
  2833. }
  2834. }
  2835. /* If wrap on switch device list, exit. */
  2836. if (first_dev) {
  2837. wrap.b24 = new_fcport->d_id.b24;
  2838. first_dev = 0;
  2839. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2840. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2841. "Device wrap (%02x%02x%02x).\n",
  2842. new_fcport->d_id.b.domain,
  2843. new_fcport->d_id.b.area,
  2844. new_fcport->d_id.b.al_pa);
  2845. break;
  2846. }
  2847. /* Bypass if same physical adapter. */
  2848. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2849. continue;
  2850. /* Bypass virtual ports of the same host. */
  2851. found = 0;
  2852. if (ha->num_vhosts) {
  2853. unsigned long flags;
  2854. spin_lock_irqsave(&ha->vport_slock, flags);
  2855. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2856. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2857. found = 1;
  2858. break;
  2859. }
  2860. }
  2861. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2862. if (found)
  2863. continue;
  2864. }
  2865. /* Bypass if same domain and area of adapter. */
  2866. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2867. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2868. ISP_CFG_FL)
  2869. continue;
  2870. /* Bypass reserved domain fields. */
  2871. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2872. continue;
  2873. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2874. if (ql2xgffidenable &&
  2875. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2876. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2877. continue;
  2878. /* Locate matching device in database. */
  2879. found = 0;
  2880. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2881. if (memcmp(new_fcport->port_name, fcport->port_name,
  2882. WWN_SIZE))
  2883. continue;
  2884. found++;
  2885. /* Update port state. */
  2886. memcpy(fcport->fabric_port_name,
  2887. new_fcport->fabric_port_name, WWN_SIZE);
  2888. fcport->fp_speed = new_fcport->fp_speed;
  2889. /*
  2890. * If address the same and state FCS_ONLINE, nothing
  2891. * changed.
  2892. */
  2893. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2894. atomic_read(&fcport->state) == FCS_ONLINE) {
  2895. break;
  2896. }
  2897. /*
  2898. * If device was not a fabric device before.
  2899. */
  2900. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2901. fcport->d_id.b24 = new_fcport->d_id.b24;
  2902. fcport->loop_id = FC_NO_LOOP_ID;
  2903. fcport->flags |= (FCF_FABRIC_DEVICE |
  2904. FCF_LOGIN_NEEDED);
  2905. break;
  2906. }
  2907. /*
  2908. * Port ID changed or device was marked to be updated;
  2909. * Log it out if still logged in and mark it for
  2910. * relogin later.
  2911. */
  2912. fcport->d_id.b24 = new_fcport->d_id.b24;
  2913. fcport->flags |= FCF_LOGIN_NEEDED;
  2914. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2915. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2916. fcport->port_type != FCT_INITIATOR &&
  2917. fcport->port_type != FCT_BROADCAST) {
  2918. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2919. fcport->d_id.b.domain, fcport->d_id.b.area,
  2920. fcport->d_id.b.al_pa);
  2921. fcport->loop_id = FC_NO_LOOP_ID;
  2922. }
  2923. break;
  2924. }
  2925. if (found)
  2926. continue;
  2927. /* If device was not in our fcports list, then add it. */
  2928. list_add_tail(&new_fcport->list, new_fcports);
  2929. /* Allocate a new replacement fcport. */
  2930. nxt_d_id.b24 = new_fcport->d_id.b24;
  2931. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2932. if (new_fcport == NULL) {
  2933. ql_log(ql_log_warn, vha, 0x2066,
  2934. "Memory allocation failed for fcport.\n");
  2935. kfree(swl);
  2936. return (QLA_MEMORY_ALLOC_FAILED);
  2937. }
  2938. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2939. new_fcport->d_id.b24 = nxt_d_id.b24;
  2940. }
  2941. kfree(swl);
  2942. kfree(new_fcport);
  2943. return (rval);
  2944. }
  2945. /*
  2946. * qla2x00_find_new_loop_id
  2947. * Scan through our port list and find a new usable loop ID.
  2948. *
  2949. * Input:
  2950. * ha: adapter state pointer.
  2951. * dev: port structure pointer.
  2952. *
  2953. * Returns:
  2954. * qla2x00 local function return status code.
  2955. *
  2956. * Context:
  2957. * Kernel context.
  2958. */
  2959. int
  2960. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2961. {
  2962. int rval;
  2963. int found;
  2964. fc_port_t *fcport;
  2965. uint16_t first_loop_id;
  2966. struct qla_hw_data *ha = vha->hw;
  2967. struct scsi_qla_host *vp;
  2968. struct scsi_qla_host *tvp;
  2969. unsigned long flags = 0;
  2970. rval = QLA_SUCCESS;
  2971. /* Save starting loop ID. */
  2972. first_loop_id = dev->loop_id;
  2973. for (;;) {
  2974. /* Skip loop ID if already used by adapter. */
  2975. if (dev->loop_id == vha->loop_id)
  2976. dev->loop_id++;
  2977. /* Skip reserved loop IDs. */
  2978. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2979. dev->loop_id++;
  2980. /* Reset loop ID if passed the end. */
  2981. if (dev->loop_id > ha->max_loop_id) {
  2982. /* first loop ID. */
  2983. dev->loop_id = ha->min_external_loopid;
  2984. }
  2985. /* Check for loop ID being already in use. */
  2986. found = 0;
  2987. fcport = NULL;
  2988. spin_lock_irqsave(&ha->vport_slock, flags);
  2989. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2990. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2991. if (fcport->loop_id == dev->loop_id &&
  2992. fcport != dev) {
  2993. /* ID possibly in use */
  2994. found++;
  2995. break;
  2996. }
  2997. }
  2998. if (found)
  2999. break;
  3000. }
  3001. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3002. /* If not in use then it is free to use. */
  3003. if (!found) {
  3004. break;
  3005. }
  3006. /* ID in use. Try next value. */
  3007. dev->loop_id++;
  3008. /* If wrap around. No free ID to use. */
  3009. if (dev->loop_id == first_loop_id) {
  3010. dev->loop_id = FC_NO_LOOP_ID;
  3011. rval = QLA_FUNCTION_FAILED;
  3012. break;
  3013. }
  3014. }
  3015. return (rval);
  3016. }
  3017. /*
  3018. * qla2x00_device_resync
  3019. * Marks devices in the database that needs resynchronization.
  3020. *
  3021. * Input:
  3022. * ha = adapter block pointer.
  3023. *
  3024. * Context:
  3025. * Kernel context.
  3026. */
  3027. static int
  3028. qla2x00_device_resync(scsi_qla_host_t *vha)
  3029. {
  3030. int rval;
  3031. uint32_t mask;
  3032. fc_port_t *fcport;
  3033. uint32_t rscn_entry;
  3034. uint8_t rscn_out_iter;
  3035. uint8_t format;
  3036. port_id_t d_id = {};
  3037. rval = QLA_RSCNS_HANDLED;
  3038. while (vha->rscn_out_ptr != vha->rscn_in_ptr ||
  3039. vha->flags.rscn_queue_overflow) {
  3040. rscn_entry = vha->rscn_queue[vha->rscn_out_ptr];
  3041. format = MSB(MSW(rscn_entry));
  3042. d_id.b.domain = LSB(MSW(rscn_entry));
  3043. d_id.b.area = MSB(LSW(rscn_entry));
  3044. d_id.b.al_pa = LSB(LSW(rscn_entry));
  3045. ql_dbg(ql_dbg_disc, vha, 0x2020,
  3046. "RSCN queue entry[%d] = [%02x/%02x%02x%02x].\n",
  3047. vha->rscn_out_ptr, format, d_id.b.domain, d_id.b.area,
  3048. d_id.b.al_pa);
  3049. vha->rscn_out_ptr++;
  3050. if (vha->rscn_out_ptr == MAX_RSCN_COUNT)
  3051. vha->rscn_out_ptr = 0;
  3052. /* Skip duplicate entries. */
  3053. for (rscn_out_iter = vha->rscn_out_ptr;
  3054. !vha->flags.rscn_queue_overflow &&
  3055. rscn_out_iter != vha->rscn_in_ptr;
  3056. rscn_out_iter = (rscn_out_iter ==
  3057. (MAX_RSCN_COUNT - 1)) ? 0: rscn_out_iter + 1) {
  3058. if (rscn_entry != vha->rscn_queue[rscn_out_iter])
  3059. break;
  3060. ql_dbg(ql_dbg_disc, vha, 0x2021,
  3061. "Skipping duplicate RSCN queue entry found at "
  3062. "[%d].\n", rscn_out_iter);
  3063. vha->rscn_out_ptr = rscn_out_iter;
  3064. }
  3065. /* Queue overflow, set switch default case. */
  3066. if (vha->flags.rscn_queue_overflow) {
  3067. ql_dbg(ql_dbg_disc, vha, 0x2022,
  3068. "device_resync: rscn overflow.\n");
  3069. format = 3;
  3070. vha->flags.rscn_queue_overflow = 0;
  3071. }
  3072. switch (format) {
  3073. case 0:
  3074. mask = 0xffffff;
  3075. break;
  3076. case 1:
  3077. mask = 0xffff00;
  3078. break;
  3079. case 2:
  3080. mask = 0xff0000;
  3081. break;
  3082. default:
  3083. mask = 0x0;
  3084. d_id.b24 = 0;
  3085. vha->rscn_out_ptr = vha->rscn_in_ptr;
  3086. break;
  3087. }
  3088. rval = QLA_SUCCESS;
  3089. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3090. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  3091. (fcport->d_id.b24 & mask) != d_id.b24 ||
  3092. fcport->port_type == FCT_BROADCAST)
  3093. continue;
  3094. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  3095. if (format != 3 ||
  3096. fcport->port_type != FCT_INITIATOR) {
  3097. qla2x00_mark_device_lost(vha, fcport,
  3098. 0, 0);
  3099. }
  3100. }
  3101. }
  3102. }
  3103. return (rval);
  3104. }
  3105. /*
  3106. * qla2x00_fabric_dev_login
  3107. * Login fabric target device and update FC port database.
  3108. *
  3109. * Input:
  3110. * ha: adapter state pointer.
  3111. * fcport: port structure list pointer.
  3112. * next_loopid: contains value of a new loop ID that can be used
  3113. * by the next login attempt.
  3114. *
  3115. * Returns:
  3116. * qla2x00 local function return status code.
  3117. *
  3118. * Context:
  3119. * Kernel context.
  3120. */
  3121. static int
  3122. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3123. uint16_t *next_loopid)
  3124. {
  3125. int rval;
  3126. int retry;
  3127. uint8_t opts;
  3128. struct qla_hw_data *ha = vha->hw;
  3129. rval = QLA_SUCCESS;
  3130. retry = 0;
  3131. if (IS_ALOGIO_CAPABLE(ha)) {
  3132. if (fcport->flags & FCF_ASYNC_SENT)
  3133. return rval;
  3134. fcport->flags |= FCF_ASYNC_SENT;
  3135. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  3136. if (!rval)
  3137. return rval;
  3138. }
  3139. fcport->flags &= ~FCF_ASYNC_SENT;
  3140. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  3141. if (rval == QLA_SUCCESS) {
  3142. /* Send an ADISC to FCP2 devices.*/
  3143. opts = 0;
  3144. if (fcport->flags & FCF_FCP2_DEVICE)
  3145. opts |= BIT_1;
  3146. rval = qla2x00_get_port_database(vha, fcport, opts);
  3147. if (rval != QLA_SUCCESS) {
  3148. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3149. fcport->d_id.b.domain, fcport->d_id.b.area,
  3150. fcport->d_id.b.al_pa);
  3151. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3152. } else {
  3153. qla2x00_update_fcport(vha, fcport);
  3154. }
  3155. }
  3156. return (rval);
  3157. }
  3158. /*
  3159. * qla2x00_fabric_login
  3160. * Issue fabric login command.
  3161. *
  3162. * Input:
  3163. * ha = adapter block pointer.
  3164. * device = pointer to FC device type structure.
  3165. *
  3166. * Returns:
  3167. * 0 - Login successfully
  3168. * 1 - Login failed
  3169. * 2 - Initiator device
  3170. * 3 - Fatal error
  3171. */
  3172. int
  3173. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3174. uint16_t *next_loopid)
  3175. {
  3176. int rval;
  3177. int retry;
  3178. uint16_t tmp_loopid;
  3179. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3180. struct qla_hw_data *ha = vha->hw;
  3181. retry = 0;
  3182. tmp_loopid = 0;
  3183. for (;;) {
  3184. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3185. "Trying Fabric Login w/loop id 0x%04x for port "
  3186. "%02x%02x%02x.\n",
  3187. fcport->loop_id, fcport->d_id.b.domain,
  3188. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3189. /* Login fcport on switch. */
  3190. ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3191. fcport->d_id.b.domain, fcport->d_id.b.area,
  3192. fcport->d_id.b.al_pa, mb, BIT_0);
  3193. if (mb[0] == MBS_PORT_ID_USED) {
  3194. /*
  3195. * Device has another loop ID. The firmware team
  3196. * recommends the driver perform an implicit login with
  3197. * the specified ID again. The ID we just used is save
  3198. * here so we return with an ID that can be tried by
  3199. * the next login.
  3200. */
  3201. retry++;
  3202. tmp_loopid = fcport->loop_id;
  3203. fcport->loop_id = mb[1];
  3204. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3205. "Fabric Login: port in use - next loop "
  3206. "id=0x%04x, port id= %02x%02x%02x.\n",
  3207. fcport->loop_id, fcport->d_id.b.domain,
  3208. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3209. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3210. /*
  3211. * Login succeeded.
  3212. */
  3213. if (retry) {
  3214. /* A retry occurred before. */
  3215. *next_loopid = tmp_loopid;
  3216. } else {
  3217. /*
  3218. * No retry occurred before. Just increment the
  3219. * ID value for next login.
  3220. */
  3221. *next_loopid = (fcport->loop_id + 1);
  3222. }
  3223. if (mb[1] & BIT_0) {
  3224. fcport->port_type = FCT_INITIATOR;
  3225. } else {
  3226. fcport->port_type = FCT_TARGET;
  3227. if (mb[1] & BIT_1) {
  3228. fcport->flags |= FCF_FCP2_DEVICE;
  3229. }
  3230. }
  3231. if (mb[10] & BIT_0)
  3232. fcport->supported_classes |= FC_COS_CLASS2;
  3233. if (mb[10] & BIT_1)
  3234. fcport->supported_classes |= FC_COS_CLASS3;
  3235. rval = QLA_SUCCESS;
  3236. break;
  3237. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3238. /*
  3239. * Loop ID already used, try next loop ID.
  3240. */
  3241. fcport->loop_id++;
  3242. rval = qla2x00_find_new_loop_id(vha, fcport);
  3243. if (rval != QLA_SUCCESS) {
  3244. /* Ran out of loop IDs to use */
  3245. break;
  3246. }
  3247. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3248. /*
  3249. * Firmware possibly timed out during login. If NO
  3250. * retries are left to do then the device is declared
  3251. * dead.
  3252. */
  3253. *next_loopid = fcport->loop_id;
  3254. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3255. fcport->d_id.b.domain, fcport->d_id.b.area,
  3256. fcport->d_id.b.al_pa);
  3257. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3258. rval = 1;
  3259. break;
  3260. } else {
  3261. /*
  3262. * unrecoverable / not handled error
  3263. */
  3264. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3265. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3266. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3267. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3268. fcport->loop_id, jiffies);
  3269. *next_loopid = fcport->loop_id;
  3270. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3271. fcport->d_id.b.domain, fcport->d_id.b.area,
  3272. fcport->d_id.b.al_pa);
  3273. fcport->loop_id = FC_NO_LOOP_ID;
  3274. fcport->login_retry = 0;
  3275. rval = 3;
  3276. break;
  3277. }
  3278. }
  3279. return (rval);
  3280. }
  3281. /*
  3282. * qla2x00_local_device_login
  3283. * Issue local device login command.
  3284. *
  3285. * Input:
  3286. * ha = adapter block pointer.
  3287. * loop_id = loop id of device to login to.
  3288. *
  3289. * Returns (Where's the #define!!!!):
  3290. * 0 - Login successfully
  3291. * 1 - Login failed
  3292. * 3 - Fatal error
  3293. */
  3294. int
  3295. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3296. {
  3297. int rval;
  3298. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3299. memset(mb, 0, sizeof(mb));
  3300. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3301. if (rval == QLA_SUCCESS) {
  3302. /* Interrogate mailbox registers for any errors */
  3303. if (mb[0] == MBS_COMMAND_ERROR)
  3304. rval = 1;
  3305. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3306. /* device not in PCB table */
  3307. rval = 3;
  3308. }
  3309. return (rval);
  3310. }
  3311. /*
  3312. * qla2x00_loop_resync
  3313. * Resync with fibre channel devices.
  3314. *
  3315. * Input:
  3316. * ha = adapter block pointer.
  3317. *
  3318. * Returns:
  3319. * 0 = success
  3320. */
  3321. int
  3322. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3323. {
  3324. int rval = QLA_SUCCESS;
  3325. uint32_t wait_time;
  3326. struct req_que *req;
  3327. struct rsp_que *rsp;
  3328. if (vha->hw->flags.cpu_affinity_enabled)
  3329. req = vha->hw->req_q_map[0];
  3330. else
  3331. req = vha->req;
  3332. rsp = req->rsp;
  3333. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3334. if (vha->flags.online) {
  3335. if (!(rval = qla2x00_fw_ready(vha))) {
  3336. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3337. wait_time = 256;
  3338. do {
  3339. /* Issue a marker after FW becomes ready. */
  3340. qla2x00_marker(vha, req, rsp, 0, 0,
  3341. MK_SYNC_ALL);
  3342. vha->marker_needed = 0;
  3343. /* Remap devices on Loop. */
  3344. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3345. qla2x00_configure_loop(vha);
  3346. wait_time--;
  3347. } while (!atomic_read(&vha->loop_down_timer) &&
  3348. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3349. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3350. &vha->dpc_flags)));
  3351. }
  3352. }
  3353. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3354. return (QLA_FUNCTION_FAILED);
  3355. if (rval)
  3356. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3357. "%s *** FAILED ***.\n", __func__);
  3358. return (rval);
  3359. }
  3360. /*
  3361. * qla2x00_perform_loop_resync
  3362. * Description: This function will set the appropriate flags and call
  3363. * qla2x00_loop_resync. If successful loop will be resynced
  3364. * Arguments : scsi_qla_host_t pointer
  3365. * returm : Success or Failure
  3366. */
  3367. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3368. {
  3369. int32_t rval = 0;
  3370. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3371. /*Configure the flags so that resync happens properly*/
  3372. atomic_set(&ha->loop_down_timer, 0);
  3373. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3374. atomic_set(&ha->loop_state, LOOP_UP);
  3375. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3376. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3377. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3378. rval = qla2x00_loop_resync(ha);
  3379. } else
  3380. atomic_set(&ha->loop_state, LOOP_DEAD);
  3381. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3382. }
  3383. return rval;
  3384. }
  3385. void
  3386. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3387. {
  3388. fc_port_t *fcport;
  3389. struct scsi_qla_host *vha;
  3390. struct qla_hw_data *ha = base_vha->hw;
  3391. unsigned long flags;
  3392. spin_lock_irqsave(&ha->vport_slock, flags);
  3393. /* Go with deferred removal of rport references. */
  3394. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3395. atomic_inc(&vha->vref_count);
  3396. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3397. if (fcport->drport &&
  3398. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3399. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3400. qla2x00_rport_del(fcport);
  3401. spin_lock_irqsave(&ha->vport_slock, flags);
  3402. }
  3403. }
  3404. atomic_dec(&vha->vref_count);
  3405. }
  3406. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3407. }
  3408. /*
  3409. * qla82xx_quiescent_state_cleanup
  3410. * Description: This function will block the new I/Os
  3411. * Its not aborting any I/Os as context
  3412. * is not destroyed during quiescence
  3413. * Arguments: scsi_qla_host_t
  3414. * return : void
  3415. */
  3416. void
  3417. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3418. {
  3419. struct qla_hw_data *ha = vha->hw;
  3420. struct scsi_qla_host *vp;
  3421. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3422. "Performing ISP error recovery - ha=%p.\n", ha);
  3423. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3424. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3425. atomic_set(&vha->loop_state, LOOP_DOWN);
  3426. qla2x00_mark_all_devices_lost(vha, 0);
  3427. list_for_each_entry(vp, &ha->vp_list, list)
  3428. qla2x00_mark_all_devices_lost(vha, 0);
  3429. } else {
  3430. if (!atomic_read(&vha->loop_down_timer))
  3431. atomic_set(&vha->loop_down_timer,
  3432. LOOP_DOWN_TIME);
  3433. }
  3434. /* Wait for pending cmds to complete */
  3435. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3436. }
  3437. void
  3438. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3439. {
  3440. struct qla_hw_data *ha = vha->hw;
  3441. struct scsi_qla_host *vp;
  3442. unsigned long flags;
  3443. fc_port_t *fcport;
  3444. /* For ISP82XX, driver waits for completion of the commands.
  3445. * online flag should be set.
  3446. */
  3447. if (!IS_QLA82XX(ha))
  3448. vha->flags.online = 0;
  3449. ha->flags.chip_reset_done = 0;
  3450. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3451. ha->qla_stats.total_isp_aborts++;
  3452. ql_log(ql_log_info, vha, 0x00af,
  3453. "Performing ISP error recovery - ha=%p.\n", ha);
  3454. /* For ISP82XX, reset_chip is just disabling interrupts.
  3455. * Driver waits for the completion of the commands.
  3456. * the interrupts need to be enabled.
  3457. */
  3458. if (!IS_QLA82XX(ha))
  3459. ha->isp_ops->reset_chip(vha);
  3460. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3461. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3462. atomic_set(&vha->loop_state, LOOP_DOWN);
  3463. qla2x00_mark_all_devices_lost(vha, 0);
  3464. spin_lock_irqsave(&ha->vport_slock, flags);
  3465. list_for_each_entry(vp, &ha->vp_list, list) {
  3466. atomic_inc(&vp->vref_count);
  3467. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3468. qla2x00_mark_all_devices_lost(vp, 0);
  3469. spin_lock_irqsave(&ha->vport_slock, flags);
  3470. atomic_dec(&vp->vref_count);
  3471. }
  3472. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3473. } else {
  3474. if (!atomic_read(&vha->loop_down_timer))
  3475. atomic_set(&vha->loop_down_timer,
  3476. LOOP_DOWN_TIME);
  3477. }
  3478. /* Clear all async request states across all VPs. */
  3479. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3480. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3481. spin_lock_irqsave(&ha->vport_slock, flags);
  3482. list_for_each_entry(vp, &ha->vp_list, list) {
  3483. atomic_inc(&vp->vref_count);
  3484. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3485. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3486. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3487. spin_lock_irqsave(&ha->vport_slock, flags);
  3488. atomic_dec(&vp->vref_count);
  3489. }
  3490. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3491. if (!ha->flags.eeh_busy) {
  3492. /* Make sure for ISP 82XX IO DMA is complete */
  3493. if (IS_QLA82XX(ha)) {
  3494. qla82xx_chip_reset_cleanup(vha);
  3495. ql_log(ql_log_info, vha, 0x00b4,
  3496. "Done chip reset cleanup.\n");
  3497. /* Done waiting for pending commands.
  3498. * Reset the online flag.
  3499. */
  3500. vha->flags.online = 0;
  3501. }
  3502. /* Requeue all commands in outstanding command list. */
  3503. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3504. }
  3505. }
  3506. /*
  3507. * qla2x00_abort_isp
  3508. * Resets ISP and aborts all outstanding commands.
  3509. *
  3510. * Input:
  3511. * ha = adapter block pointer.
  3512. *
  3513. * Returns:
  3514. * 0 = success
  3515. */
  3516. int
  3517. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3518. {
  3519. int rval;
  3520. uint8_t status = 0;
  3521. struct qla_hw_data *ha = vha->hw;
  3522. struct scsi_qla_host *vp;
  3523. struct req_que *req = ha->req_q_map[0];
  3524. unsigned long flags;
  3525. if (vha->flags.online) {
  3526. qla2x00_abort_isp_cleanup(vha);
  3527. if (unlikely(pci_channel_offline(ha->pdev) &&
  3528. ha->flags.pci_channel_io_perm_failure)) {
  3529. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3530. status = 0;
  3531. return status;
  3532. }
  3533. ha->isp_ops->get_flash_version(vha, req->ring);
  3534. ha->isp_ops->nvram_config(vha);
  3535. if (!qla2x00_restart_isp(vha)) {
  3536. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3537. if (!atomic_read(&vha->loop_down_timer)) {
  3538. /*
  3539. * Issue marker command only when we are going
  3540. * to start the I/O .
  3541. */
  3542. vha->marker_needed = 1;
  3543. }
  3544. vha->flags.online = 1;
  3545. ha->isp_ops->enable_intrs(ha);
  3546. ha->isp_abort_cnt = 0;
  3547. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3548. if (IS_QLA81XX(ha) || IS_QLA8031(ha))
  3549. qla2x00_get_fw_version(vha);
  3550. if (ha->fce) {
  3551. ha->flags.fce_enabled = 1;
  3552. memset(ha->fce, 0,
  3553. fce_calc_size(ha->fce_bufs));
  3554. rval = qla2x00_enable_fce_trace(vha,
  3555. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3556. &ha->fce_bufs);
  3557. if (rval) {
  3558. ql_log(ql_log_warn, vha, 0x8033,
  3559. "Unable to reinitialize FCE "
  3560. "(%d).\n", rval);
  3561. ha->flags.fce_enabled = 0;
  3562. }
  3563. }
  3564. if (ha->eft) {
  3565. memset(ha->eft, 0, EFT_SIZE);
  3566. rval = qla2x00_enable_eft_trace(vha,
  3567. ha->eft_dma, EFT_NUM_BUFFERS);
  3568. if (rval) {
  3569. ql_log(ql_log_warn, vha, 0x8034,
  3570. "Unable to reinitialize EFT "
  3571. "(%d).\n", rval);
  3572. }
  3573. }
  3574. } else { /* failed the ISP abort */
  3575. vha->flags.online = 1;
  3576. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3577. if (ha->isp_abort_cnt == 0) {
  3578. ql_log(ql_log_fatal, vha, 0x8035,
  3579. "ISP error recover failed - "
  3580. "board disabled.\n");
  3581. /*
  3582. * The next call disables the board
  3583. * completely.
  3584. */
  3585. ha->isp_ops->reset_adapter(vha);
  3586. vha->flags.online = 0;
  3587. clear_bit(ISP_ABORT_RETRY,
  3588. &vha->dpc_flags);
  3589. status = 0;
  3590. } else { /* schedule another ISP abort */
  3591. ha->isp_abort_cnt--;
  3592. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3593. "ISP abort - retry remaining %d.\n",
  3594. ha->isp_abort_cnt);
  3595. status = 1;
  3596. }
  3597. } else {
  3598. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3599. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3600. "ISP error recovery - retrying (%d) "
  3601. "more times.\n", ha->isp_abort_cnt);
  3602. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3603. status = 1;
  3604. }
  3605. }
  3606. }
  3607. if (!status) {
  3608. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3609. spin_lock_irqsave(&ha->vport_slock, flags);
  3610. list_for_each_entry(vp, &ha->vp_list, list) {
  3611. if (vp->vp_idx) {
  3612. atomic_inc(&vp->vref_count);
  3613. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3614. qla2x00_vp_abort_isp(vp);
  3615. spin_lock_irqsave(&ha->vport_slock, flags);
  3616. atomic_dec(&vp->vref_count);
  3617. }
  3618. }
  3619. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3620. } else {
  3621. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  3622. __func__);
  3623. }
  3624. return(status);
  3625. }
  3626. /*
  3627. * qla2x00_restart_isp
  3628. * restarts the ISP after a reset
  3629. *
  3630. * Input:
  3631. * ha = adapter block pointer.
  3632. *
  3633. * Returns:
  3634. * 0 = success
  3635. */
  3636. static int
  3637. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3638. {
  3639. int status = 0;
  3640. uint32_t wait_time;
  3641. struct qla_hw_data *ha = vha->hw;
  3642. struct req_que *req = ha->req_q_map[0];
  3643. struct rsp_que *rsp = ha->rsp_q_map[0];
  3644. /* If firmware needs to be loaded */
  3645. if (qla2x00_isp_firmware(vha)) {
  3646. vha->flags.online = 0;
  3647. status = ha->isp_ops->chip_diag(vha);
  3648. if (!status)
  3649. status = qla2x00_setup_chip(vha);
  3650. }
  3651. if (!status && !(status = qla2x00_init_rings(vha))) {
  3652. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3653. ha->flags.chip_reset_done = 1;
  3654. /* Initialize the queues in use */
  3655. qla25xx_init_queues(ha);
  3656. status = qla2x00_fw_ready(vha);
  3657. if (!status) {
  3658. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3659. "Start configure loop status = %d.\n", status);
  3660. /* Issue a marker after FW becomes ready. */
  3661. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3662. vha->flags.online = 1;
  3663. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3664. wait_time = 256;
  3665. do {
  3666. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3667. qla2x00_configure_loop(vha);
  3668. wait_time--;
  3669. } while (!atomic_read(&vha->loop_down_timer) &&
  3670. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3671. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3672. &vha->dpc_flags)));
  3673. }
  3674. /* if no cable then assume it's good */
  3675. if ((vha->device_flags & DFLG_NO_CABLE))
  3676. status = 0;
  3677. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3678. "Configure loop done, status = 0x%x.\n", status);
  3679. }
  3680. return (status);
  3681. }
  3682. static int
  3683. qla25xx_init_queues(struct qla_hw_data *ha)
  3684. {
  3685. struct rsp_que *rsp = NULL;
  3686. struct req_que *req = NULL;
  3687. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3688. int ret = -1;
  3689. int i;
  3690. for (i = 1; i < ha->max_rsp_queues; i++) {
  3691. rsp = ha->rsp_q_map[i];
  3692. if (rsp) {
  3693. rsp->options &= ~BIT_0;
  3694. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3695. if (ret != QLA_SUCCESS)
  3696. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3697. "%s Rsp que: %d init failed.\n",
  3698. __func__, rsp->id);
  3699. else
  3700. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3701. "%s Rsp que: %d inited.\n",
  3702. __func__, rsp->id);
  3703. }
  3704. }
  3705. for (i = 1; i < ha->max_req_queues; i++) {
  3706. req = ha->req_q_map[i];
  3707. if (req) {
  3708. /* Clear outstanding commands array. */
  3709. req->options &= ~BIT_0;
  3710. ret = qla25xx_init_req_que(base_vha, req);
  3711. if (ret != QLA_SUCCESS)
  3712. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3713. "%s Req que: %d init failed.\n",
  3714. __func__, req->id);
  3715. else
  3716. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3717. "%s Req que: %d inited.\n",
  3718. __func__, req->id);
  3719. }
  3720. }
  3721. return ret;
  3722. }
  3723. /*
  3724. * qla2x00_reset_adapter
  3725. * Reset adapter.
  3726. *
  3727. * Input:
  3728. * ha = adapter block pointer.
  3729. */
  3730. void
  3731. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3732. {
  3733. unsigned long flags = 0;
  3734. struct qla_hw_data *ha = vha->hw;
  3735. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3736. vha->flags.online = 0;
  3737. ha->isp_ops->disable_intrs(ha);
  3738. spin_lock_irqsave(&ha->hardware_lock, flags);
  3739. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3740. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3741. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3742. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3743. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3744. }
  3745. void
  3746. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3747. {
  3748. unsigned long flags = 0;
  3749. struct qla_hw_data *ha = vha->hw;
  3750. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3751. if (IS_QLA82XX(ha))
  3752. return;
  3753. vha->flags.online = 0;
  3754. ha->isp_ops->disable_intrs(ha);
  3755. spin_lock_irqsave(&ha->hardware_lock, flags);
  3756. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3757. RD_REG_DWORD(&reg->hccr);
  3758. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3759. RD_REG_DWORD(&reg->hccr);
  3760. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3761. if (IS_NOPOLLING_TYPE(ha))
  3762. ha->isp_ops->enable_intrs(ha);
  3763. }
  3764. /* On sparc systems, obtain port and node WWN from firmware
  3765. * properties.
  3766. */
  3767. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3768. struct nvram_24xx *nv)
  3769. {
  3770. #ifdef CONFIG_SPARC
  3771. struct qla_hw_data *ha = vha->hw;
  3772. struct pci_dev *pdev = ha->pdev;
  3773. struct device_node *dp = pci_device_to_OF_node(pdev);
  3774. const u8 *val;
  3775. int len;
  3776. val = of_get_property(dp, "port-wwn", &len);
  3777. if (val && len >= WWN_SIZE)
  3778. memcpy(nv->port_name, val, WWN_SIZE);
  3779. val = of_get_property(dp, "node-wwn", &len);
  3780. if (val && len >= WWN_SIZE)
  3781. memcpy(nv->node_name, val, WWN_SIZE);
  3782. #endif
  3783. }
  3784. int
  3785. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3786. {
  3787. int rval;
  3788. struct init_cb_24xx *icb;
  3789. struct nvram_24xx *nv;
  3790. uint32_t *dptr;
  3791. uint8_t *dptr1, *dptr2;
  3792. uint32_t chksum;
  3793. uint16_t cnt;
  3794. struct qla_hw_data *ha = vha->hw;
  3795. rval = QLA_SUCCESS;
  3796. icb = (struct init_cb_24xx *)ha->init_cb;
  3797. nv = ha->nvram;
  3798. /* Determine NVRAM starting address. */
  3799. if (ha->flags.port0) {
  3800. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3801. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3802. } else {
  3803. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3804. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3805. }
  3806. ha->nvram_size = sizeof(struct nvram_24xx);
  3807. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3808. if (IS_QLA82XX(ha))
  3809. ha->vpd_size = FA_VPD_SIZE_82XX;
  3810. /* Get VPD data into cache */
  3811. ha->vpd = ha->nvram + VPD_OFFSET;
  3812. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3813. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3814. /* Get NVRAM data into cache and calculate checksum. */
  3815. dptr = (uint32_t *)nv;
  3816. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3817. ha->nvram_size);
  3818. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3819. chksum += le32_to_cpu(*dptr++);
  3820. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3821. "Contents of NVRAM\n");
  3822. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3823. (uint8_t *)nv, ha->nvram_size);
  3824. /* Bad NVRAM data, set defaults parameters. */
  3825. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3826. || nv->id[3] != ' ' ||
  3827. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3828. /* Reset NVRAM data. */
  3829. ql_log(ql_log_warn, vha, 0x006b,
  3830. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  3831. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3832. ql_log(ql_log_warn, vha, 0x006c,
  3833. "Falling back to functioning (yet invalid -- WWPN) "
  3834. "defaults.\n");
  3835. /*
  3836. * Set default initialization control block.
  3837. */
  3838. memset(nv, 0, ha->nvram_size);
  3839. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3840. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3841. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3842. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3843. nv->exchange_count = __constant_cpu_to_le16(0);
  3844. nv->hard_address = __constant_cpu_to_le16(124);
  3845. nv->port_name[0] = 0x21;
  3846. nv->port_name[1] = 0x00 + ha->port_no;
  3847. nv->port_name[2] = 0x00;
  3848. nv->port_name[3] = 0xe0;
  3849. nv->port_name[4] = 0x8b;
  3850. nv->port_name[5] = 0x1c;
  3851. nv->port_name[6] = 0x55;
  3852. nv->port_name[7] = 0x86;
  3853. nv->node_name[0] = 0x20;
  3854. nv->node_name[1] = 0x00;
  3855. nv->node_name[2] = 0x00;
  3856. nv->node_name[3] = 0xe0;
  3857. nv->node_name[4] = 0x8b;
  3858. nv->node_name[5] = 0x1c;
  3859. nv->node_name[6] = 0x55;
  3860. nv->node_name[7] = 0x86;
  3861. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3862. nv->login_retry_count = __constant_cpu_to_le16(8);
  3863. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3864. nv->login_timeout = __constant_cpu_to_le16(0);
  3865. nv->firmware_options_1 =
  3866. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3867. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3868. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3869. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3870. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3871. nv->efi_parameters = __constant_cpu_to_le32(0);
  3872. nv->reset_delay = 5;
  3873. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3874. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3875. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3876. rval = 1;
  3877. }
  3878. /* Reset Initialization control block */
  3879. memset(icb, 0, ha->init_cb_size);
  3880. /* Copy 1st segment. */
  3881. dptr1 = (uint8_t *)icb;
  3882. dptr2 = (uint8_t *)&nv->version;
  3883. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3884. while (cnt--)
  3885. *dptr1++ = *dptr2++;
  3886. icb->login_retry_count = nv->login_retry_count;
  3887. icb->link_down_on_nos = nv->link_down_on_nos;
  3888. /* Copy 2nd segment. */
  3889. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3890. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3891. cnt = (uint8_t *)&icb->reserved_3 -
  3892. (uint8_t *)&icb->interrupt_delay_timer;
  3893. while (cnt--)
  3894. *dptr1++ = *dptr2++;
  3895. /*
  3896. * Setup driver NVRAM options.
  3897. */
  3898. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3899. "QLA2462");
  3900. /* Use alternate WWN? */
  3901. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3902. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3903. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3904. }
  3905. /* Prepare nodename */
  3906. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3907. /*
  3908. * Firmware will apply the following mask if the nodename was
  3909. * not provided.
  3910. */
  3911. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3912. icb->node_name[0] &= 0xF0;
  3913. }
  3914. /* Set host adapter parameters. */
  3915. ha->flags.disable_risc_code_load = 0;
  3916. ha->flags.enable_lip_reset = 0;
  3917. ha->flags.enable_lip_full_login =
  3918. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3919. ha->flags.enable_target_reset =
  3920. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3921. ha->flags.enable_led_scheme = 0;
  3922. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3923. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3924. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3925. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3926. sizeof(ha->fw_seriallink_options24));
  3927. /* save HBA serial number */
  3928. ha->serial0 = icb->port_name[5];
  3929. ha->serial1 = icb->port_name[6];
  3930. ha->serial2 = icb->port_name[7];
  3931. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3932. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3933. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3934. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3935. /* Set minimum login_timeout to 4 seconds. */
  3936. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3937. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3938. if (le16_to_cpu(nv->login_timeout) < 4)
  3939. nv->login_timeout = __constant_cpu_to_le16(4);
  3940. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3941. icb->login_timeout = nv->login_timeout;
  3942. /* Set minimum RATOV to 100 tenths of a second. */
  3943. ha->r_a_tov = 100;
  3944. ha->loop_reset_delay = nv->reset_delay;
  3945. /* Link Down Timeout = 0:
  3946. *
  3947. * When Port Down timer expires we will start returning
  3948. * I/O's to OS with "DID_NO_CONNECT".
  3949. *
  3950. * Link Down Timeout != 0:
  3951. *
  3952. * The driver waits for the link to come up after link down
  3953. * before returning I/Os to OS with "DID_NO_CONNECT".
  3954. */
  3955. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3956. ha->loop_down_abort_time =
  3957. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3958. } else {
  3959. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3960. ha->loop_down_abort_time =
  3961. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3962. }
  3963. /* Need enough time to try and get the port back. */
  3964. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3965. if (qlport_down_retry)
  3966. ha->port_down_retry_count = qlport_down_retry;
  3967. /* Set login_retry_count */
  3968. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3969. if (ha->port_down_retry_count ==
  3970. le16_to_cpu(nv->port_down_retry_count) &&
  3971. ha->port_down_retry_count > 3)
  3972. ha->login_retry_count = ha->port_down_retry_count;
  3973. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3974. ha->login_retry_count = ha->port_down_retry_count;
  3975. if (ql2xloginretrycount)
  3976. ha->login_retry_count = ql2xloginretrycount;
  3977. /* Enable ZIO. */
  3978. if (!vha->flags.init_done) {
  3979. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3980. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3981. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3982. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3983. }
  3984. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3985. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3986. vha->flags.process_response_queue = 0;
  3987. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3988. ha->zio_mode = QLA_ZIO_MODE_6;
  3989. ql_log(ql_log_info, vha, 0x006f,
  3990. "ZIO mode %d enabled; timer delay (%d us).\n",
  3991. ha->zio_mode, ha->zio_timer * 100);
  3992. icb->firmware_options_2 |= cpu_to_le32(
  3993. (uint32_t)ha->zio_mode);
  3994. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3995. vha->flags.process_response_queue = 1;
  3996. }
  3997. if (rval) {
  3998. ql_log(ql_log_warn, vha, 0x0070,
  3999. "NVRAM configuration failed.\n");
  4000. }
  4001. return (rval);
  4002. }
  4003. static int
  4004. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  4005. uint32_t faddr)
  4006. {
  4007. int rval = QLA_SUCCESS;
  4008. int segments, fragment;
  4009. uint32_t *dcode, dlen;
  4010. uint32_t risc_addr;
  4011. uint32_t risc_size;
  4012. uint32_t i;
  4013. struct qla_hw_data *ha = vha->hw;
  4014. struct req_que *req = ha->req_q_map[0];
  4015. ql_dbg(ql_dbg_init, vha, 0x008b,
  4016. "FW: Loading firmware from flash (%x).\n", faddr);
  4017. rval = QLA_SUCCESS;
  4018. segments = FA_RISC_CODE_SEGMENTS;
  4019. dcode = (uint32_t *)req->ring;
  4020. *srisc_addr = 0;
  4021. /* Validate firmware image by checking version. */
  4022. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  4023. for (i = 0; i < 4; i++)
  4024. dcode[i] = be32_to_cpu(dcode[i]);
  4025. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4026. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4027. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4028. dcode[3] == 0)) {
  4029. ql_log(ql_log_fatal, vha, 0x008c,
  4030. "Unable to verify the integrity of flash firmware "
  4031. "image.\n");
  4032. ql_log(ql_log_fatal, vha, 0x008d,
  4033. "Firmware data: %08x %08x %08x %08x.\n",
  4034. dcode[0], dcode[1], dcode[2], dcode[3]);
  4035. return QLA_FUNCTION_FAILED;
  4036. }
  4037. while (segments && rval == QLA_SUCCESS) {
  4038. /* Read segment's load information. */
  4039. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  4040. risc_addr = be32_to_cpu(dcode[2]);
  4041. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4042. risc_size = be32_to_cpu(dcode[3]);
  4043. fragment = 0;
  4044. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4045. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4046. if (dlen > risc_size)
  4047. dlen = risc_size;
  4048. ql_dbg(ql_dbg_init, vha, 0x008e,
  4049. "Loading risc segment@ risc addr %x "
  4050. "number of dwords 0x%x offset 0x%x.\n",
  4051. risc_addr, dlen, faddr);
  4052. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  4053. for (i = 0; i < dlen; i++)
  4054. dcode[i] = swab32(dcode[i]);
  4055. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4056. dlen);
  4057. if (rval) {
  4058. ql_log(ql_log_fatal, vha, 0x008f,
  4059. "Failed to load segment %d of firmware.\n",
  4060. fragment);
  4061. break;
  4062. }
  4063. faddr += dlen;
  4064. risc_addr += dlen;
  4065. risc_size -= dlen;
  4066. fragment++;
  4067. }
  4068. /* Next segment. */
  4069. segments--;
  4070. }
  4071. return rval;
  4072. }
  4073. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  4074. int
  4075. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4076. {
  4077. int rval;
  4078. int i, fragment;
  4079. uint16_t *wcode, *fwcode;
  4080. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  4081. struct fw_blob *blob;
  4082. struct qla_hw_data *ha = vha->hw;
  4083. struct req_que *req = ha->req_q_map[0];
  4084. /* Load firmware blob. */
  4085. blob = qla2x00_request_firmware(vha);
  4086. if (!blob) {
  4087. ql_log(ql_log_info, vha, 0x0083,
  4088. "Fimware image unavailable.\n");
  4089. ql_log(ql_log_info, vha, 0x0084,
  4090. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  4091. return QLA_FUNCTION_FAILED;
  4092. }
  4093. rval = QLA_SUCCESS;
  4094. wcode = (uint16_t *)req->ring;
  4095. *srisc_addr = 0;
  4096. fwcode = (uint16_t *)blob->fw->data;
  4097. fwclen = 0;
  4098. /* Validate firmware image by checking version. */
  4099. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  4100. ql_log(ql_log_fatal, vha, 0x0085,
  4101. "Unable to verify integrity of firmware image (%Zd).\n",
  4102. blob->fw->size);
  4103. goto fail_fw_integrity;
  4104. }
  4105. for (i = 0; i < 4; i++)
  4106. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  4107. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  4108. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  4109. wcode[2] == 0 && wcode[3] == 0)) {
  4110. ql_log(ql_log_fatal, vha, 0x0086,
  4111. "Unable to verify integrity of firmware image.\n");
  4112. ql_log(ql_log_fatal, vha, 0x0087,
  4113. "Firmware data: %04x %04x %04x %04x.\n",
  4114. wcode[0], wcode[1], wcode[2], wcode[3]);
  4115. goto fail_fw_integrity;
  4116. }
  4117. seg = blob->segs;
  4118. while (*seg && rval == QLA_SUCCESS) {
  4119. risc_addr = *seg;
  4120. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  4121. risc_size = be16_to_cpu(fwcode[3]);
  4122. /* Validate firmware image size. */
  4123. fwclen += risc_size * sizeof(uint16_t);
  4124. if (blob->fw->size < fwclen) {
  4125. ql_log(ql_log_fatal, vha, 0x0088,
  4126. "Unable to verify integrity of firmware image "
  4127. "(%Zd).\n", blob->fw->size);
  4128. goto fail_fw_integrity;
  4129. }
  4130. fragment = 0;
  4131. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4132. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  4133. if (wlen > risc_size)
  4134. wlen = risc_size;
  4135. ql_dbg(ql_dbg_init, vha, 0x0089,
  4136. "Loading risc segment@ risc addr %x number of "
  4137. "words 0x%x.\n", risc_addr, wlen);
  4138. for (i = 0; i < wlen; i++)
  4139. wcode[i] = swab16(fwcode[i]);
  4140. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4141. wlen);
  4142. if (rval) {
  4143. ql_log(ql_log_fatal, vha, 0x008a,
  4144. "Failed to load segment %d of firmware.\n",
  4145. fragment);
  4146. break;
  4147. }
  4148. fwcode += wlen;
  4149. risc_addr += wlen;
  4150. risc_size -= wlen;
  4151. fragment++;
  4152. }
  4153. /* Next segment. */
  4154. seg++;
  4155. }
  4156. return rval;
  4157. fail_fw_integrity:
  4158. return QLA_FUNCTION_FAILED;
  4159. }
  4160. static int
  4161. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4162. {
  4163. int rval;
  4164. int segments, fragment;
  4165. uint32_t *dcode, dlen;
  4166. uint32_t risc_addr;
  4167. uint32_t risc_size;
  4168. uint32_t i;
  4169. struct fw_blob *blob;
  4170. uint32_t *fwcode, fwclen;
  4171. struct qla_hw_data *ha = vha->hw;
  4172. struct req_que *req = ha->req_q_map[0];
  4173. /* Load firmware blob. */
  4174. blob = qla2x00_request_firmware(vha);
  4175. if (!blob) {
  4176. ql_log(ql_log_warn, vha, 0x0090,
  4177. "Fimware image unavailable.\n");
  4178. ql_log(ql_log_warn, vha, 0x0091,
  4179. "Firmware images can be retrieved from: "
  4180. QLA_FW_URL ".\n");
  4181. return QLA_FUNCTION_FAILED;
  4182. }
  4183. ql_dbg(ql_dbg_init, vha, 0x0092,
  4184. "FW: Loading via request-firmware.\n");
  4185. rval = QLA_SUCCESS;
  4186. segments = FA_RISC_CODE_SEGMENTS;
  4187. dcode = (uint32_t *)req->ring;
  4188. *srisc_addr = 0;
  4189. fwcode = (uint32_t *)blob->fw->data;
  4190. fwclen = 0;
  4191. /* Validate firmware image by checking version. */
  4192. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4193. ql_log(ql_log_fatal, vha, 0x0093,
  4194. "Unable to verify integrity of firmware image (%Zd).\n",
  4195. blob->fw->size);
  4196. goto fail_fw_integrity;
  4197. }
  4198. for (i = 0; i < 4; i++)
  4199. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4200. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4201. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4202. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4203. dcode[3] == 0)) {
  4204. ql_log(ql_log_fatal, vha, 0x0094,
  4205. "Unable to verify integrity of firmware image (%Zd).\n",
  4206. blob->fw->size);
  4207. ql_log(ql_log_fatal, vha, 0x0095,
  4208. "Firmware data: %08x %08x %08x %08x.\n",
  4209. dcode[0], dcode[1], dcode[2], dcode[3]);
  4210. goto fail_fw_integrity;
  4211. }
  4212. while (segments && rval == QLA_SUCCESS) {
  4213. risc_addr = be32_to_cpu(fwcode[2]);
  4214. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4215. risc_size = be32_to_cpu(fwcode[3]);
  4216. /* Validate firmware image size. */
  4217. fwclen += risc_size * sizeof(uint32_t);
  4218. if (blob->fw->size < fwclen) {
  4219. ql_log(ql_log_fatal, vha, 0x0096,
  4220. "Unable to verify integrity of firmware image "
  4221. "(%Zd).\n", blob->fw->size);
  4222. goto fail_fw_integrity;
  4223. }
  4224. fragment = 0;
  4225. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4226. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4227. if (dlen > risc_size)
  4228. dlen = risc_size;
  4229. ql_dbg(ql_dbg_init, vha, 0x0097,
  4230. "Loading risc segment@ risc addr %x "
  4231. "number of dwords 0x%x.\n", risc_addr, dlen);
  4232. for (i = 0; i < dlen; i++)
  4233. dcode[i] = swab32(fwcode[i]);
  4234. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4235. dlen);
  4236. if (rval) {
  4237. ql_log(ql_log_fatal, vha, 0x0098,
  4238. "Failed to load segment %d of firmware.\n",
  4239. fragment);
  4240. break;
  4241. }
  4242. fwcode += dlen;
  4243. risc_addr += dlen;
  4244. risc_size -= dlen;
  4245. fragment++;
  4246. }
  4247. /* Next segment. */
  4248. segments--;
  4249. }
  4250. return rval;
  4251. fail_fw_integrity:
  4252. return QLA_FUNCTION_FAILED;
  4253. }
  4254. int
  4255. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4256. {
  4257. int rval;
  4258. if (ql2xfwloadbin == 1)
  4259. return qla81xx_load_risc(vha, srisc_addr);
  4260. /*
  4261. * FW Load priority:
  4262. * 1) Firmware via request-firmware interface (.bin file).
  4263. * 2) Firmware residing in flash.
  4264. */
  4265. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4266. if (rval == QLA_SUCCESS)
  4267. return rval;
  4268. return qla24xx_load_risc_flash(vha, srisc_addr,
  4269. vha->hw->flt_region_fw);
  4270. }
  4271. int
  4272. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4273. {
  4274. int rval;
  4275. struct qla_hw_data *ha = vha->hw;
  4276. if (ql2xfwloadbin == 2)
  4277. goto try_blob_fw;
  4278. /*
  4279. * FW Load priority:
  4280. * 1) Firmware residing in flash.
  4281. * 2) Firmware via request-firmware interface (.bin file).
  4282. * 3) Golden-Firmware residing in flash -- limited operation.
  4283. */
  4284. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4285. if (rval == QLA_SUCCESS)
  4286. return rval;
  4287. try_blob_fw:
  4288. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4289. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4290. return rval;
  4291. ql_log(ql_log_info, vha, 0x0099,
  4292. "Attempting to fallback to golden firmware.\n");
  4293. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4294. if (rval != QLA_SUCCESS)
  4295. return rval;
  4296. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4297. ha->flags.running_gold_fw = 1;
  4298. return rval;
  4299. }
  4300. void
  4301. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4302. {
  4303. int ret, retries;
  4304. struct qla_hw_data *ha = vha->hw;
  4305. if (ha->flags.pci_channel_io_perm_failure)
  4306. return;
  4307. if (!IS_FWI2_CAPABLE(ha))
  4308. return;
  4309. if (!ha->fw_major_version)
  4310. return;
  4311. ret = qla2x00_stop_firmware(vha);
  4312. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4313. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4314. ha->isp_ops->reset_chip(vha);
  4315. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4316. continue;
  4317. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4318. continue;
  4319. ql_log(ql_log_info, vha, 0x8015,
  4320. "Attempting retry of stop-firmware command.\n");
  4321. ret = qla2x00_stop_firmware(vha);
  4322. }
  4323. }
  4324. int
  4325. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4326. {
  4327. int rval = QLA_SUCCESS;
  4328. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4329. struct qla_hw_data *ha = vha->hw;
  4330. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4331. struct req_que *req;
  4332. struct rsp_que *rsp;
  4333. if (!vha->vp_idx)
  4334. return -EINVAL;
  4335. rval = qla2x00_fw_ready(base_vha);
  4336. if (ha->flags.cpu_affinity_enabled)
  4337. req = ha->req_q_map[0];
  4338. else
  4339. req = vha->req;
  4340. rsp = req->rsp;
  4341. if (rval == QLA_SUCCESS) {
  4342. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4343. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4344. }
  4345. vha->flags.management_server_logged_in = 0;
  4346. /* Login to SNS first */
  4347. ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, BIT_1);
  4348. if (mb[0] != MBS_COMMAND_COMPLETE) {
  4349. ql_dbg(ql_dbg_init, vha, 0x0103,
  4350. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  4351. "mb[6]=%x mb[7]=%x.\n",
  4352. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4353. return (QLA_FUNCTION_FAILED);
  4354. }
  4355. atomic_set(&vha->loop_down_timer, 0);
  4356. atomic_set(&vha->loop_state, LOOP_UP);
  4357. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4358. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4359. rval = qla2x00_loop_resync(base_vha);
  4360. return rval;
  4361. }
  4362. /* 84XX Support **************************************************************/
  4363. static LIST_HEAD(qla_cs84xx_list);
  4364. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4365. static struct qla_chip_state_84xx *
  4366. qla84xx_get_chip(struct scsi_qla_host *vha)
  4367. {
  4368. struct qla_chip_state_84xx *cs84xx;
  4369. struct qla_hw_data *ha = vha->hw;
  4370. mutex_lock(&qla_cs84xx_mutex);
  4371. /* Find any shared 84xx chip. */
  4372. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4373. if (cs84xx->bus == ha->pdev->bus) {
  4374. kref_get(&cs84xx->kref);
  4375. goto done;
  4376. }
  4377. }
  4378. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4379. if (!cs84xx)
  4380. goto done;
  4381. kref_init(&cs84xx->kref);
  4382. spin_lock_init(&cs84xx->access_lock);
  4383. mutex_init(&cs84xx->fw_update_mutex);
  4384. cs84xx->bus = ha->pdev->bus;
  4385. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4386. done:
  4387. mutex_unlock(&qla_cs84xx_mutex);
  4388. return cs84xx;
  4389. }
  4390. static void
  4391. __qla84xx_chip_release(struct kref *kref)
  4392. {
  4393. struct qla_chip_state_84xx *cs84xx =
  4394. container_of(kref, struct qla_chip_state_84xx, kref);
  4395. mutex_lock(&qla_cs84xx_mutex);
  4396. list_del(&cs84xx->list);
  4397. mutex_unlock(&qla_cs84xx_mutex);
  4398. kfree(cs84xx);
  4399. }
  4400. void
  4401. qla84xx_put_chip(struct scsi_qla_host *vha)
  4402. {
  4403. struct qla_hw_data *ha = vha->hw;
  4404. if (ha->cs84xx)
  4405. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4406. }
  4407. static int
  4408. qla84xx_init_chip(scsi_qla_host_t *vha)
  4409. {
  4410. int rval;
  4411. uint16_t status[2];
  4412. struct qla_hw_data *ha = vha->hw;
  4413. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4414. rval = qla84xx_verify_chip(vha, status);
  4415. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4416. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4417. QLA_SUCCESS;
  4418. }
  4419. /* 81XX Support **************************************************************/
  4420. int
  4421. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4422. {
  4423. int rval;
  4424. struct init_cb_81xx *icb;
  4425. struct nvram_81xx *nv;
  4426. uint32_t *dptr;
  4427. uint8_t *dptr1, *dptr2;
  4428. uint32_t chksum;
  4429. uint16_t cnt;
  4430. struct qla_hw_data *ha = vha->hw;
  4431. rval = QLA_SUCCESS;
  4432. icb = (struct init_cb_81xx *)ha->init_cb;
  4433. nv = ha->nvram;
  4434. /* Determine NVRAM starting address. */
  4435. ha->nvram_size = sizeof(struct nvram_81xx);
  4436. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4437. /* Get VPD data into cache */
  4438. ha->vpd = ha->nvram + VPD_OFFSET;
  4439. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4440. ha->vpd_size);
  4441. /* Get NVRAM data into cache and calculate checksum. */
  4442. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4443. ha->nvram_size);
  4444. dptr = (uint32_t *)nv;
  4445. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4446. chksum += le32_to_cpu(*dptr++);
  4447. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4448. "Contents of NVRAM:\n");
  4449. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4450. (uint8_t *)nv, ha->nvram_size);
  4451. /* Bad NVRAM data, set defaults parameters. */
  4452. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4453. || nv->id[3] != ' ' ||
  4454. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4455. /* Reset NVRAM data. */
  4456. ql_log(ql_log_info, vha, 0x0073,
  4457. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  4458. "version=0x%x.\n", chksum, nv->id[0],
  4459. le16_to_cpu(nv->nvram_version));
  4460. ql_log(ql_log_info, vha, 0x0074,
  4461. "Falling back to functioning (yet invalid -- WWPN) "
  4462. "defaults.\n");
  4463. /*
  4464. * Set default initialization control block.
  4465. */
  4466. memset(nv, 0, ha->nvram_size);
  4467. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4468. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4469. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4470. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4471. nv->exchange_count = __constant_cpu_to_le16(0);
  4472. nv->port_name[0] = 0x21;
  4473. nv->port_name[1] = 0x00 + ha->port_no;
  4474. nv->port_name[2] = 0x00;
  4475. nv->port_name[3] = 0xe0;
  4476. nv->port_name[4] = 0x8b;
  4477. nv->port_name[5] = 0x1c;
  4478. nv->port_name[6] = 0x55;
  4479. nv->port_name[7] = 0x86;
  4480. nv->node_name[0] = 0x20;
  4481. nv->node_name[1] = 0x00;
  4482. nv->node_name[2] = 0x00;
  4483. nv->node_name[3] = 0xe0;
  4484. nv->node_name[4] = 0x8b;
  4485. nv->node_name[5] = 0x1c;
  4486. nv->node_name[6] = 0x55;
  4487. nv->node_name[7] = 0x86;
  4488. nv->login_retry_count = __constant_cpu_to_le16(8);
  4489. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4490. nv->login_timeout = __constant_cpu_to_le16(0);
  4491. nv->firmware_options_1 =
  4492. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4493. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4494. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4495. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4496. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4497. nv->efi_parameters = __constant_cpu_to_le32(0);
  4498. nv->reset_delay = 5;
  4499. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4500. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4501. nv->link_down_timeout = __constant_cpu_to_le16(180);
  4502. nv->enode_mac[0] = 0x00;
  4503. nv->enode_mac[1] = 0xC0;
  4504. nv->enode_mac[2] = 0xDD;
  4505. nv->enode_mac[3] = 0x04;
  4506. nv->enode_mac[4] = 0x05;
  4507. nv->enode_mac[5] = 0x06 + ha->port_no;
  4508. rval = 1;
  4509. }
  4510. /* Reset Initialization control block */
  4511. memset(icb, 0, ha->init_cb_size);
  4512. /* Copy 1st segment. */
  4513. dptr1 = (uint8_t *)icb;
  4514. dptr2 = (uint8_t *)&nv->version;
  4515. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4516. while (cnt--)
  4517. *dptr1++ = *dptr2++;
  4518. icb->login_retry_count = nv->login_retry_count;
  4519. /* Copy 2nd segment. */
  4520. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4521. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4522. cnt = (uint8_t *)&icb->reserved_5 -
  4523. (uint8_t *)&icb->interrupt_delay_timer;
  4524. while (cnt--)
  4525. *dptr1++ = *dptr2++;
  4526. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4527. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4528. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4529. icb->enode_mac[0] = 0x00;
  4530. icb->enode_mac[1] = 0xC0;
  4531. icb->enode_mac[2] = 0xDD;
  4532. icb->enode_mac[3] = 0x04;
  4533. icb->enode_mac[4] = 0x05;
  4534. icb->enode_mac[5] = 0x06 + ha->port_no;
  4535. }
  4536. /* Use extended-initialization control block. */
  4537. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4538. /*
  4539. * Setup driver NVRAM options.
  4540. */
  4541. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4542. "QLE8XXX");
  4543. /* Use alternate WWN? */
  4544. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4545. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4546. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4547. }
  4548. /* Prepare nodename */
  4549. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4550. /*
  4551. * Firmware will apply the following mask if the nodename was
  4552. * not provided.
  4553. */
  4554. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4555. icb->node_name[0] &= 0xF0;
  4556. }
  4557. /* Set host adapter parameters. */
  4558. ha->flags.disable_risc_code_load = 0;
  4559. ha->flags.enable_lip_reset = 0;
  4560. ha->flags.enable_lip_full_login =
  4561. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4562. ha->flags.enable_target_reset =
  4563. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4564. ha->flags.enable_led_scheme = 0;
  4565. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4566. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4567. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4568. /* save HBA serial number */
  4569. ha->serial0 = icb->port_name[5];
  4570. ha->serial1 = icb->port_name[6];
  4571. ha->serial2 = icb->port_name[7];
  4572. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4573. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4574. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4575. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4576. /* Set minimum login_timeout to 4 seconds. */
  4577. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4578. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4579. if (le16_to_cpu(nv->login_timeout) < 4)
  4580. nv->login_timeout = __constant_cpu_to_le16(4);
  4581. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4582. icb->login_timeout = nv->login_timeout;
  4583. /* Set minimum RATOV to 100 tenths of a second. */
  4584. ha->r_a_tov = 100;
  4585. ha->loop_reset_delay = nv->reset_delay;
  4586. /* Link Down Timeout = 0:
  4587. *
  4588. * When Port Down timer expires we will start returning
  4589. * I/O's to OS with "DID_NO_CONNECT".
  4590. *
  4591. * Link Down Timeout != 0:
  4592. *
  4593. * The driver waits for the link to come up after link down
  4594. * before returning I/Os to OS with "DID_NO_CONNECT".
  4595. */
  4596. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4597. ha->loop_down_abort_time =
  4598. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4599. } else {
  4600. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4601. ha->loop_down_abort_time =
  4602. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4603. }
  4604. /* Need enough time to try and get the port back. */
  4605. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4606. if (qlport_down_retry)
  4607. ha->port_down_retry_count = qlport_down_retry;
  4608. /* Set login_retry_count */
  4609. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4610. if (ha->port_down_retry_count ==
  4611. le16_to_cpu(nv->port_down_retry_count) &&
  4612. ha->port_down_retry_count > 3)
  4613. ha->login_retry_count = ha->port_down_retry_count;
  4614. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4615. ha->login_retry_count = ha->port_down_retry_count;
  4616. if (ql2xloginretrycount)
  4617. ha->login_retry_count = ql2xloginretrycount;
  4618. /* if not running MSI-X we need handshaking on interrupts */
  4619. if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
  4620. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
  4621. /* Enable ZIO. */
  4622. if (!vha->flags.init_done) {
  4623. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4624. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4625. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4626. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4627. }
  4628. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4629. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4630. vha->flags.process_response_queue = 0;
  4631. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4632. ha->zio_mode = QLA_ZIO_MODE_6;
  4633. ql_log(ql_log_info, vha, 0x0075,
  4634. "ZIO mode %d enabled; timer delay (%d us).\n",
  4635. ha->zio_mode,
  4636. ha->zio_timer * 100);
  4637. icb->firmware_options_2 |= cpu_to_le32(
  4638. (uint32_t)ha->zio_mode);
  4639. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4640. vha->flags.process_response_queue = 1;
  4641. }
  4642. if (rval) {
  4643. ql_log(ql_log_warn, vha, 0x0076,
  4644. "NVRAM configuration failed.\n");
  4645. }
  4646. return (rval);
  4647. }
  4648. int
  4649. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4650. {
  4651. int status, rval;
  4652. uint32_t wait_time;
  4653. struct qla_hw_data *ha = vha->hw;
  4654. struct req_que *req = ha->req_q_map[0];
  4655. struct rsp_que *rsp = ha->rsp_q_map[0];
  4656. struct scsi_qla_host *vp;
  4657. unsigned long flags;
  4658. status = qla2x00_init_rings(vha);
  4659. if (!status) {
  4660. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4661. ha->flags.chip_reset_done = 1;
  4662. status = qla2x00_fw_ready(vha);
  4663. if (!status) {
  4664. ql_log(ql_log_info, vha, 0x803c,
  4665. "Start configure loop, status =%d.\n", status);
  4666. /* Issue a marker after FW becomes ready. */
  4667. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4668. vha->flags.online = 1;
  4669. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4670. wait_time = 256;
  4671. do {
  4672. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4673. qla2x00_configure_loop(vha);
  4674. wait_time--;
  4675. } while (!atomic_read(&vha->loop_down_timer) &&
  4676. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4677. wait_time &&
  4678. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4679. }
  4680. /* if no cable then assume it's good */
  4681. if ((vha->device_flags & DFLG_NO_CABLE))
  4682. status = 0;
  4683. ql_log(ql_log_info, vha, 0x8000,
  4684. "Configure loop done, status = 0x%x.\n", status);
  4685. }
  4686. if (!status) {
  4687. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4688. if (!atomic_read(&vha->loop_down_timer)) {
  4689. /*
  4690. * Issue marker command only when we are going
  4691. * to start the I/O .
  4692. */
  4693. vha->marker_needed = 1;
  4694. }
  4695. vha->flags.online = 1;
  4696. ha->isp_ops->enable_intrs(ha);
  4697. ha->isp_abort_cnt = 0;
  4698. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4699. /* Update the firmware version */
  4700. status = qla82xx_check_md_needed(vha);
  4701. if (ha->fce) {
  4702. ha->flags.fce_enabled = 1;
  4703. memset(ha->fce, 0,
  4704. fce_calc_size(ha->fce_bufs));
  4705. rval = qla2x00_enable_fce_trace(vha,
  4706. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4707. &ha->fce_bufs);
  4708. if (rval) {
  4709. ql_log(ql_log_warn, vha, 0x8001,
  4710. "Unable to reinitialize FCE (%d).\n",
  4711. rval);
  4712. ha->flags.fce_enabled = 0;
  4713. }
  4714. }
  4715. if (ha->eft) {
  4716. memset(ha->eft, 0, EFT_SIZE);
  4717. rval = qla2x00_enable_eft_trace(vha,
  4718. ha->eft_dma, EFT_NUM_BUFFERS);
  4719. if (rval) {
  4720. ql_log(ql_log_warn, vha, 0x8010,
  4721. "Unable to reinitialize EFT (%d).\n",
  4722. rval);
  4723. }
  4724. }
  4725. }
  4726. if (!status) {
  4727. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  4728. "qla82xx_restart_isp succeeded.\n");
  4729. spin_lock_irqsave(&ha->vport_slock, flags);
  4730. list_for_each_entry(vp, &ha->vp_list, list) {
  4731. if (vp->vp_idx) {
  4732. atomic_inc(&vp->vref_count);
  4733. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4734. qla2x00_vp_abort_isp(vp);
  4735. spin_lock_irqsave(&ha->vport_slock, flags);
  4736. atomic_dec(&vp->vref_count);
  4737. }
  4738. }
  4739. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4740. } else {
  4741. ql_log(ql_log_warn, vha, 0x8016,
  4742. "qla82xx_restart_isp **** FAILED ****.\n");
  4743. }
  4744. return status;
  4745. }
  4746. void
  4747. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4748. {
  4749. struct qla_hw_data *ha = vha->hw;
  4750. if (!ql2xetsenable)
  4751. return;
  4752. /* Enable ETS Burst. */
  4753. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4754. ha->fw_options[2] |= BIT_9;
  4755. qla2x00_set_fw_options(vha, ha->fw_options);
  4756. }
  4757. /*
  4758. * qla24xx_get_fcp_prio
  4759. * Gets the fcp cmd priority value for the logged in port.
  4760. * Looks for a match of the port descriptors within
  4761. * each of the fcp prio config entries. If a match is found,
  4762. * the tag (priority) value is returned.
  4763. *
  4764. * Input:
  4765. * vha = scsi host structure pointer.
  4766. * fcport = port structure pointer.
  4767. *
  4768. * Return:
  4769. * non-zero (if found)
  4770. * -1 (if not found)
  4771. *
  4772. * Context:
  4773. * Kernel context
  4774. */
  4775. static int
  4776. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4777. {
  4778. int i, entries;
  4779. uint8_t pid_match, wwn_match;
  4780. int priority;
  4781. uint32_t pid1, pid2;
  4782. uint64_t wwn1, wwn2;
  4783. struct qla_fcp_prio_entry *pri_entry;
  4784. struct qla_hw_data *ha = vha->hw;
  4785. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4786. return -1;
  4787. priority = -1;
  4788. entries = ha->fcp_prio_cfg->num_entries;
  4789. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4790. for (i = 0; i < entries; i++) {
  4791. pid_match = wwn_match = 0;
  4792. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4793. pri_entry++;
  4794. continue;
  4795. }
  4796. /* check source pid for a match */
  4797. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4798. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4799. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4800. if (pid1 == INVALID_PORT_ID)
  4801. pid_match++;
  4802. else if (pid1 == pid2)
  4803. pid_match++;
  4804. }
  4805. /* check destination pid for a match */
  4806. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4807. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4808. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4809. if (pid1 == INVALID_PORT_ID)
  4810. pid_match++;
  4811. else if (pid1 == pid2)
  4812. pid_match++;
  4813. }
  4814. /* check source WWN for a match */
  4815. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4816. wwn1 = wwn_to_u64(vha->port_name);
  4817. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4818. if (wwn2 == (uint64_t)-1)
  4819. wwn_match++;
  4820. else if (wwn1 == wwn2)
  4821. wwn_match++;
  4822. }
  4823. /* check destination WWN for a match */
  4824. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4825. wwn1 = wwn_to_u64(fcport->port_name);
  4826. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4827. if (wwn2 == (uint64_t)-1)
  4828. wwn_match++;
  4829. else if (wwn1 == wwn2)
  4830. wwn_match++;
  4831. }
  4832. if (pid_match == 2 || wwn_match == 2) {
  4833. /* Found a matching entry */
  4834. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4835. priority = pri_entry->tag;
  4836. break;
  4837. }
  4838. pri_entry++;
  4839. }
  4840. return priority;
  4841. }
  4842. /*
  4843. * qla24xx_update_fcport_fcp_prio
  4844. * Activates fcp priority for the logged in fc port
  4845. *
  4846. * Input:
  4847. * vha = scsi host structure pointer.
  4848. * fcp = port structure pointer.
  4849. *
  4850. * Return:
  4851. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4852. *
  4853. * Context:
  4854. * Kernel context.
  4855. */
  4856. int
  4857. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4858. {
  4859. int ret;
  4860. int priority;
  4861. uint16_t mb[5];
  4862. if (fcport->port_type != FCT_TARGET ||
  4863. fcport->loop_id == FC_NO_LOOP_ID)
  4864. return QLA_FUNCTION_FAILED;
  4865. priority = qla24xx_get_fcp_prio(vha, fcport);
  4866. if (priority < 0)
  4867. return QLA_FUNCTION_FAILED;
  4868. if (IS_QLA82XX(vha->hw)) {
  4869. fcport->fcp_prio = priority & 0xf;
  4870. return QLA_SUCCESS;
  4871. }
  4872. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4873. if (ret == QLA_SUCCESS) {
  4874. if (fcport->fcp_prio != priority)
  4875. ql_dbg(ql_dbg_user, vha, 0x709e,
  4876. "Updated FCP_CMND priority - value=%d loop_id=%d "
  4877. "port_id=%02x%02x%02x.\n", priority,
  4878. fcport->loop_id, fcport->d_id.b.domain,
  4879. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  4880. fcport->fcp_prio = priority & 0xf;
  4881. } else
  4882. ql_dbg(ql_dbg_user, vha, 0x704f,
  4883. "Unable to update FCP_CMND priority - ret=0x%x for "
  4884. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  4885. fcport->d_id.b.domain, fcport->d_id.b.area,
  4886. fcport->d_id.b.al_pa);
  4887. return ret;
  4888. }
  4889. /*
  4890. * qla24xx_update_all_fcp_prio
  4891. * Activates fcp priority for all the logged in ports
  4892. *
  4893. * Input:
  4894. * ha = adapter block pointer.
  4895. *
  4896. * Return:
  4897. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4898. *
  4899. * Context:
  4900. * Kernel context.
  4901. */
  4902. int
  4903. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4904. {
  4905. int ret;
  4906. fc_port_t *fcport;
  4907. ret = QLA_FUNCTION_FAILED;
  4908. /* We need to set priority for all logged in ports */
  4909. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4910. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4911. return ret;
  4912. }