sba_iommu.c 63 KB

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  1. /*
  2. ** System Bus Adapter (SBA) I/O MMU manager
  3. **
  4. ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
  5. ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
  6. ** (c) Copyright 2000-2004 Hewlett-Packard Company
  7. **
  8. ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
  9. **
  10. ** This program is free software; you can redistribute it and/or modify
  11. ** it under the terms of the GNU General Public License as published by
  12. ** the Free Software Foundation; either version 2 of the License, or
  13. ** (at your option) any later version.
  14. **
  15. **
  16. ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
  17. ** J5000/J7000/N-class/L-class machines and their successors.
  18. **
  19. ** FIXME: add DMA hint support programming in both sba and lba modules.
  20. */
  21. #include <linux/config.h>
  22. #include <linux/types.h>
  23. #include <linux/kernel.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/slab.h>
  26. #include <linux/init.h>
  27. #include <linux/mm.h>
  28. #include <linux/string.h>
  29. #include <linux/pci.h>
  30. #include <asm/byteorder.h>
  31. #include <asm/io.h>
  32. #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
  33. #include <asm/hardware.h> /* for register_parisc_driver() stuff */
  34. #include <linux/proc_fs.h>
  35. #include <linux/seq_file.h>
  36. #include <asm/runway.h> /* for proc_runway_root */
  37. #include <asm/pdc.h> /* for PDC_MODEL_* */
  38. #include <asm/pdcpat.h> /* for is_pdc_pat() */
  39. #include <asm/parisc-device.h>
  40. /* declared in arch/parisc/kernel/setup.c */
  41. extern struct proc_dir_entry * proc_mckinley_root;
  42. #define MODULE_NAME "SBA"
  43. #ifdef CONFIG_PROC_FS
  44. /* depends on proc fs support. But costs CPU performance */
  45. #undef SBA_COLLECT_STATS
  46. #endif
  47. /*
  48. ** The number of debug flags is a clue - this code is fragile.
  49. ** Don't even think about messing with it unless you have
  50. ** plenty of 710's to sacrifice to the computer gods. :^)
  51. */
  52. #undef DEBUG_SBA_INIT
  53. #undef DEBUG_SBA_RUN
  54. #undef DEBUG_SBA_RUN_SG
  55. #undef DEBUG_SBA_RESOURCE
  56. #undef ASSERT_PDIR_SANITY
  57. #undef DEBUG_LARGE_SG_ENTRIES
  58. #undef DEBUG_DMB_TRAP
  59. #ifdef DEBUG_SBA_INIT
  60. #define DBG_INIT(x...) printk(x)
  61. #else
  62. #define DBG_INIT(x...)
  63. #endif
  64. #ifdef DEBUG_SBA_RUN
  65. #define DBG_RUN(x...) printk(x)
  66. #else
  67. #define DBG_RUN(x...)
  68. #endif
  69. #ifdef DEBUG_SBA_RUN_SG
  70. #define DBG_RUN_SG(x...) printk(x)
  71. #else
  72. #define DBG_RUN_SG(x...)
  73. #endif
  74. #ifdef DEBUG_SBA_RESOURCE
  75. #define DBG_RES(x...) printk(x)
  76. #else
  77. #define DBG_RES(x...)
  78. #endif
  79. #if defined(CONFIG_64BIT)
  80. /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
  81. #define ZX1_SUPPORT
  82. #endif
  83. #define SBA_INLINE __inline__
  84. /*
  85. ** The number of pdir entries to "free" before issueing
  86. ** a read to PCOM register to flush out PCOM writes.
  87. ** Interacts with allocation granularity (ie 4 or 8 entries
  88. ** allocated and free'd/purged at a time might make this
  89. ** less interesting).
  90. */
  91. #define DELAYED_RESOURCE_CNT 16
  92. #define DEFAULT_DMA_HINT_REG 0
  93. #define ASTRO_RUNWAY_PORT 0x582
  94. #define IKE_MERCED_PORT 0x803
  95. #define REO_MERCED_PORT 0x804
  96. #define REOG_MERCED_PORT 0x805
  97. #define PLUTO_MCKINLEY_PORT 0x880
  98. #define SBA_FUNC_ID 0x0000 /* function id */
  99. #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
  100. #define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
  101. #define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
  102. #define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
  103. #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
  104. #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
  105. #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
  106. /* Ike's IOC's occupy functions 2 and 3 */
  107. #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
  108. #define IOC_CTRL 0x8 /* IOC_CTRL offset */
  109. #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
  110. #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
  111. #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
  112. #define IOC_CTRL_RM (1 << 8) /* Real Mode */
  113. #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
  114. #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
  115. #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
  116. #define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
  117. #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
  118. /*
  119. ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
  120. ** Firmware programs this stuff. Don't touch it.
  121. */
  122. #define LMMIO_DIRECT0_BASE 0x300
  123. #define LMMIO_DIRECT0_MASK 0x308
  124. #define LMMIO_DIRECT0_ROUTE 0x310
  125. #define LMMIO_DIST_BASE 0x360
  126. #define LMMIO_DIST_MASK 0x368
  127. #define LMMIO_DIST_ROUTE 0x370
  128. #define IOS_DIST_BASE 0x390
  129. #define IOS_DIST_MASK 0x398
  130. #define IOS_DIST_ROUTE 0x3A0
  131. #define IOS_DIRECT_BASE 0x3C0
  132. #define IOS_DIRECT_MASK 0x3C8
  133. #define IOS_DIRECT_ROUTE 0x3D0
  134. /*
  135. ** Offsets into I/O TLB (Function 2 and 3 on Ike)
  136. */
  137. #define ROPE0_CTL 0x200 /* "regbus pci0" */
  138. #define ROPE1_CTL 0x208
  139. #define ROPE2_CTL 0x210
  140. #define ROPE3_CTL 0x218
  141. #define ROPE4_CTL 0x220
  142. #define ROPE5_CTL 0x228
  143. #define ROPE6_CTL 0x230
  144. #define ROPE7_CTL 0x238
  145. #define IOC_ROPE0_CFG 0x500 /* pluto only */
  146. #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
  147. #define HF_ENABLE 0x40
  148. #define IOC_IBASE 0x300 /* IO TLB */
  149. #define IOC_IMASK 0x308
  150. #define IOC_PCOM 0x310
  151. #define IOC_TCNFG 0x318
  152. #define IOC_PDIR_BASE 0x320
  153. /* AGP GART driver looks for this */
  154. #define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
  155. /*
  156. ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
  157. ** It's safer (avoid memory corruption) to keep DMA page mappings
  158. ** equivalently sized to VM PAGE_SIZE.
  159. **
  160. ** We really can't avoid generating a new mapping for each
  161. ** page since the Virtual Coherence Index has to be generated
  162. ** and updated for each page.
  163. **
  164. ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
  165. */
  166. #define IOVP_SIZE PAGE_SIZE
  167. #define IOVP_SHIFT PAGE_SHIFT
  168. #define IOVP_MASK PAGE_MASK
  169. #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
  170. #define SBA_PERF_MASK1 0x718
  171. #define SBA_PERF_MASK2 0x730
  172. /*
  173. ** Offsets into PCI Performance Counters (functions 12 and 13)
  174. ** Controlled by PERF registers in function 2 & 3 respectively.
  175. */
  176. #define SBA_PERF_CNT1 0x200
  177. #define SBA_PERF_CNT2 0x208
  178. #define SBA_PERF_CNT3 0x210
  179. struct ioc {
  180. void __iomem *ioc_hpa; /* I/O MMU base address */
  181. char *res_map; /* resource map, bit == pdir entry */
  182. u64 *pdir_base; /* physical base address */
  183. unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
  184. unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
  185. #ifdef ZX1_SUPPORT
  186. unsigned long iovp_mask; /* help convert IOVA to IOVP */
  187. #endif
  188. unsigned long *res_hint; /* next avail IOVP - circular search */
  189. spinlock_t res_lock;
  190. unsigned int res_bitshift; /* from the LEFT! */
  191. unsigned int res_size; /* size of resource map in bytes */
  192. #ifdef SBA_HINT_SUPPORT
  193. /* FIXME : DMA HINTs not used */
  194. unsigned long hint_mask_pdir; /* bits used for DMA hints */
  195. unsigned int hint_shift_pdir;
  196. #endif
  197. #if DELAYED_RESOURCE_CNT > 0
  198. int saved_cnt;
  199. struct sba_dma_pair {
  200. dma_addr_t iova;
  201. size_t size;
  202. } saved[DELAYED_RESOURCE_CNT];
  203. #endif
  204. #ifdef SBA_COLLECT_STATS
  205. #define SBA_SEARCH_SAMPLE 0x100
  206. unsigned long avg_search[SBA_SEARCH_SAMPLE];
  207. unsigned long avg_idx; /* current index into avg_search */
  208. unsigned long used_pages;
  209. unsigned long msingle_calls;
  210. unsigned long msingle_pages;
  211. unsigned long msg_calls;
  212. unsigned long msg_pages;
  213. unsigned long usingle_calls;
  214. unsigned long usingle_pages;
  215. unsigned long usg_calls;
  216. unsigned long usg_pages;
  217. #endif
  218. /* STUFF We don't need in performance path */
  219. unsigned int pdir_size; /* in bytes, determined by IOV Space size */
  220. };
  221. struct sba_device {
  222. struct sba_device *next; /* list of SBA's in system */
  223. struct parisc_device *dev; /* dev found in bus walk */
  224. struct parisc_device_id *iodc; /* data about dev from firmware */
  225. const char *name;
  226. void __iomem *sba_hpa; /* base address */
  227. spinlock_t sba_lock;
  228. unsigned int flags; /* state/functionality enabled */
  229. unsigned int hw_rev; /* HW revision of chip */
  230. struct resource chip_resv; /* MMIO reserved for chip */
  231. struct resource iommu_resv; /* MMIO reserved for iommu */
  232. unsigned int num_ioc; /* number of on-board IOC's */
  233. struct ioc ioc[MAX_IOC];
  234. };
  235. static struct sba_device *sba_list;
  236. static unsigned long ioc_needs_fdc = 0;
  237. /* global count of IOMMUs in the system */
  238. static unsigned int global_ioc_cnt = 0;
  239. /* PA8700 (Piranha 2.2) bug workaround */
  240. static unsigned long piranha_bad_128k = 0;
  241. /* Looks nice and keeps the compiler happy */
  242. #define SBA_DEV(d) ((struct sba_device *) (d))
  243. #ifdef SBA_AGP_SUPPORT
  244. static int reserve_sba_gart = 1;
  245. #endif
  246. #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
  247. /************************************
  248. ** SBA register read and write support
  249. **
  250. ** BE WARNED: register writes are posted.
  251. ** (ie follow writes which must reach HW with a read)
  252. **
  253. ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
  254. */
  255. #define READ_REG32(addr) readl(addr)
  256. #define READ_REG64(addr) readq(addr)
  257. #define WRITE_REG32(val, addr) writel((val), (addr))
  258. #define WRITE_REG64(val, addr) writeq((val), (addr))
  259. #ifdef CONFIG_64BIT
  260. #define READ_REG(addr) READ_REG64(addr)
  261. #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
  262. #else
  263. #define READ_REG(addr) READ_REG32(addr)
  264. #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
  265. #endif
  266. #ifdef DEBUG_SBA_INIT
  267. /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
  268. /**
  269. * sba_dump_ranges - debugging only - print ranges assigned to this IOA
  270. * @hpa: base address of the sba
  271. *
  272. * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
  273. * IO Adapter (aka Bus Converter).
  274. */
  275. static void
  276. sba_dump_ranges(void __iomem *hpa)
  277. {
  278. DBG_INIT("SBA at 0x%p\n", hpa);
  279. DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
  280. DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
  281. DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
  282. DBG_INIT("\n");
  283. DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
  284. DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
  285. DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
  286. }
  287. /**
  288. * sba_dump_tlb - debugging only - print IOMMU operating parameters
  289. * @hpa: base address of the IOMMU
  290. *
  291. * Print the size/location of the IO MMU PDIR.
  292. */
  293. static void sba_dump_tlb(void __iomem *hpa)
  294. {
  295. DBG_INIT("IO TLB at 0x%p\n", hpa);
  296. DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
  297. DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
  298. DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
  299. DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
  300. DBG_INIT("\n");
  301. }
  302. #else
  303. #define sba_dump_ranges(x)
  304. #define sba_dump_tlb(x)
  305. #endif /* DEBUG_SBA_INIT */
  306. #ifdef ASSERT_PDIR_SANITY
  307. /**
  308. * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
  309. * @ioc: IO MMU structure which owns the pdir we are interested in.
  310. * @msg: text to print ont the output line.
  311. * @pide: pdir index.
  312. *
  313. * Print one entry of the IO MMU PDIR in human readable form.
  314. */
  315. static void
  316. sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
  317. {
  318. /* start printing from lowest pde in rval */
  319. u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
  320. unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
  321. uint rcnt;
  322. printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
  323. msg,
  324. rptr, pide & (BITS_PER_LONG - 1), *rptr);
  325. rcnt = 0;
  326. while (rcnt < BITS_PER_LONG) {
  327. printk(KERN_DEBUG "%s %2d %p %016Lx\n",
  328. (rcnt == (pide & (BITS_PER_LONG - 1)))
  329. ? " -->" : " ",
  330. rcnt, ptr, *ptr );
  331. rcnt++;
  332. ptr++;
  333. }
  334. printk(KERN_DEBUG "%s", msg);
  335. }
  336. /**
  337. * sba_check_pdir - debugging only - consistency checker
  338. * @ioc: IO MMU structure which owns the pdir we are interested in.
  339. * @msg: text to print ont the output line.
  340. *
  341. * Verify the resource map and pdir state is consistent
  342. */
  343. static int
  344. sba_check_pdir(struct ioc *ioc, char *msg)
  345. {
  346. u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
  347. u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
  348. u64 *pptr = ioc->pdir_base; /* pdir ptr */
  349. uint pide = 0;
  350. while (rptr < rptr_end) {
  351. u32 rval = *rptr;
  352. int rcnt = 32; /* number of bits we might check */
  353. while (rcnt) {
  354. /* Get last byte and highest bit from that */
  355. u32 pde = ((u32) (((char *)pptr)[7])) << 24;
  356. if ((rval ^ pde) & 0x80000000)
  357. {
  358. /*
  359. ** BUMMER! -- res_map != pdir --
  360. ** Dump rval and matching pdir entries
  361. */
  362. sba_dump_pdir_entry(ioc, msg, pide);
  363. return(1);
  364. }
  365. rcnt--;
  366. rval <<= 1; /* try the next bit */
  367. pptr++;
  368. pide++;
  369. }
  370. rptr++; /* look at next word of res_map */
  371. }
  372. /* It'd be nice if we always got here :^) */
  373. return 0;
  374. }
  375. /**
  376. * sba_dump_sg - debugging only - print Scatter-Gather list
  377. * @ioc: IO MMU structure which owns the pdir we are interested in.
  378. * @startsg: head of the SG list
  379. * @nents: number of entries in SG list
  380. *
  381. * print the SG list so we can verify it's correct by hand.
  382. */
  383. static void
  384. sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
  385. {
  386. while (nents-- > 0) {
  387. printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
  388. nents,
  389. (unsigned long) sg_dma_address(startsg),
  390. sg_dma_len(startsg),
  391. sg_virt_addr(startsg), startsg->length);
  392. startsg++;
  393. }
  394. }
  395. #endif /* ASSERT_PDIR_SANITY */
  396. /**************************************************************
  397. *
  398. * I/O Pdir Resource Management
  399. *
  400. * Bits set in the resource map are in use.
  401. * Each bit can represent a number of pages.
  402. * LSbs represent lower addresses (IOVA's).
  403. *
  404. ***************************************************************/
  405. #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
  406. /* Convert from IOVP to IOVA and vice versa. */
  407. #ifdef ZX1_SUPPORT
  408. /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
  409. #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
  410. #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
  411. #else
  412. /* only support Astro and ancestors. Saves a few cycles in key places */
  413. #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
  414. #define SBA_IOVP(ioc,iova) (iova)
  415. #endif
  416. #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
  417. #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
  418. #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
  419. /**
  420. * sba_search_bitmap - find free space in IO PDIR resource bitmap
  421. * @ioc: IO MMU structure which owns the pdir we are interested in.
  422. * @bits_wanted: number of entries we need.
  423. *
  424. * Find consecutive free bits in resource bitmap.
  425. * Each bit represents one entry in the IO Pdir.
  426. * Cool perf optimization: search for log2(size) bits at a time.
  427. */
  428. static SBA_INLINE unsigned long
  429. sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
  430. {
  431. unsigned long *res_ptr = ioc->res_hint;
  432. unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
  433. unsigned long pide = ~0UL;
  434. if (bits_wanted > (BITS_PER_LONG/2)) {
  435. /* Search word at a time - no mask needed */
  436. for(; res_ptr < res_end; ++res_ptr) {
  437. if (*res_ptr == 0) {
  438. *res_ptr = RESMAP_MASK(bits_wanted);
  439. pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
  440. pide <<= 3; /* convert to bit address */
  441. break;
  442. }
  443. }
  444. /* point to the next word on next pass */
  445. res_ptr++;
  446. ioc->res_bitshift = 0;
  447. } else {
  448. /*
  449. ** Search the resource bit map on well-aligned values.
  450. ** "o" is the alignment.
  451. ** We need the alignment to invalidate I/O TLB using
  452. ** SBA HW features in the unmap path.
  453. */
  454. unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
  455. uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
  456. unsigned long mask;
  457. if (bitshiftcnt >= BITS_PER_LONG) {
  458. bitshiftcnt = 0;
  459. res_ptr++;
  460. }
  461. mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
  462. DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
  463. while(res_ptr < res_end)
  464. {
  465. DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
  466. WARN_ON(mask == 0);
  467. if(((*res_ptr) & mask) == 0) {
  468. *res_ptr |= mask; /* mark resources busy! */
  469. pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
  470. pide <<= 3; /* convert to bit address */
  471. pide += bitshiftcnt;
  472. break;
  473. }
  474. mask >>= o;
  475. bitshiftcnt += o;
  476. if (mask == 0) {
  477. mask = RESMAP_MASK(bits_wanted);
  478. bitshiftcnt=0;
  479. res_ptr++;
  480. }
  481. }
  482. /* look in the same word on the next pass */
  483. ioc->res_bitshift = bitshiftcnt + bits_wanted;
  484. }
  485. /* wrapped ? */
  486. if (res_end <= res_ptr) {
  487. ioc->res_hint = (unsigned long *) ioc->res_map;
  488. ioc->res_bitshift = 0;
  489. } else {
  490. ioc->res_hint = res_ptr;
  491. }
  492. return (pide);
  493. }
  494. /**
  495. * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
  496. * @ioc: IO MMU structure which owns the pdir we are interested in.
  497. * @size: number of bytes to create a mapping for
  498. *
  499. * Given a size, find consecutive unmarked and then mark those bits in the
  500. * resource bit map.
  501. */
  502. static int
  503. sba_alloc_range(struct ioc *ioc, size_t size)
  504. {
  505. unsigned int pages_needed = size >> IOVP_SHIFT;
  506. #ifdef SBA_COLLECT_STATS
  507. unsigned long cr_start = mfctl(16);
  508. #endif
  509. unsigned long pide;
  510. pide = sba_search_bitmap(ioc, pages_needed);
  511. if (pide >= (ioc->res_size << 3)) {
  512. pide = sba_search_bitmap(ioc, pages_needed);
  513. if (pide >= (ioc->res_size << 3))
  514. panic("%s: I/O MMU @ %p is out of mapping resources\n",
  515. __FILE__, ioc->ioc_hpa);
  516. }
  517. #ifdef ASSERT_PDIR_SANITY
  518. /* verify the first enable bit is clear */
  519. if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
  520. sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
  521. }
  522. #endif
  523. DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
  524. __FUNCTION__, size, pages_needed, pide,
  525. (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
  526. ioc->res_bitshift );
  527. #ifdef SBA_COLLECT_STATS
  528. {
  529. unsigned long cr_end = mfctl(16);
  530. unsigned long tmp = cr_end - cr_start;
  531. /* check for roll over */
  532. cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
  533. }
  534. ioc->avg_search[ioc->avg_idx++] = cr_start;
  535. ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
  536. ioc->used_pages += pages_needed;
  537. #endif
  538. return (pide);
  539. }
  540. /**
  541. * sba_free_range - unmark bits in IO PDIR resource bitmap
  542. * @ioc: IO MMU structure which owns the pdir we are interested in.
  543. * @iova: IO virtual address which was previously allocated.
  544. * @size: number of bytes to create a mapping for
  545. *
  546. * clear bits in the ioc's resource map
  547. */
  548. static SBA_INLINE void
  549. sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
  550. {
  551. unsigned long iovp = SBA_IOVP(ioc, iova);
  552. unsigned int pide = PDIR_INDEX(iovp);
  553. unsigned int ridx = pide >> 3; /* convert bit to byte address */
  554. unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
  555. int bits_not_wanted = size >> IOVP_SHIFT;
  556. /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
  557. unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
  558. DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
  559. __FUNCTION__, (uint) iova, size,
  560. bits_not_wanted, m, pide, res_ptr, *res_ptr);
  561. #ifdef SBA_COLLECT_STATS
  562. ioc->used_pages -= bits_not_wanted;
  563. #endif
  564. *res_ptr &= ~m;
  565. }
  566. /**************************************************************
  567. *
  568. * "Dynamic DMA Mapping" support (aka "Coherent I/O")
  569. *
  570. ***************************************************************/
  571. #ifdef SBA_HINT_SUPPORT
  572. #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
  573. #endif
  574. typedef unsigned long space_t;
  575. #define KERNEL_SPACE 0
  576. /**
  577. * sba_io_pdir_entry - fill in one IO PDIR entry
  578. * @pdir_ptr: pointer to IO PDIR entry
  579. * @sid: process Space ID - currently only support KERNEL_SPACE
  580. * @vba: Virtual CPU address of buffer to map
  581. * @hint: DMA hint set to use for this mapping
  582. *
  583. * SBA Mapping Routine
  584. *
  585. * Given a virtual address (vba, arg2) and space id, (sid, arg1)
  586. * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
  587. * pdir_ptr (arg0).
  588. * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
  589. * for Astro/Ike looks like:
  590. *
  591. *
  592. * 0 19 51 55 63
  593. * +-+---------------------+----------------------------------+----+--------+
  594. * |V| U | PPN[43:12] | U | VI |
  595. * +-+---------------------+----------------------------------+----+--------+
  596. *
  597. * Pluto is basically identical, supports fewer physical address bits:
  598. *
  599. * 0 23 51 55 63
  600. * +-+------------------------+-------------------------------+----+--------+
  601. * |V| U | PPN[39:12] | U | VI |
  602. * +-+------------------------+-------------------------------+----+--------+
  603. *
  604. * V == Valid Bit (Most Significant Bit is bit 0)
  605. * U == Unused
  606. * PPN == Physical Page Number
  607. * VI == Virtual Index (aka Coherent Index)
  608. *
  609. * LPA instruction output is put into PPN field.
  610. * LCI (Load Coherence Index) instruction provides the "VI" bits.
  611. *
  612. * We pre-swap the bytes since PCX-W is Big Endian and the
  613. * IOMMU uses little endian for the pdir.
  614. */
  615. void SBA_INLINE
  616. sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
  617. unsigned long hint)
  618. {
  619. u64 pa; /* physical address */
  620. register unsigned ci; /* coherent index */
  621. pa = virt_to_phys(vba);
  622. pa &= IOVP_MASK;
  623. mtsp(sid,1);
  624. asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
  625. pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
  626. pa |= 0x8000000000000000ULL; /* set "valid" bit */
  627. *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
  628. /*
  629. * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
  630. * (bit #61, big endian), we have to flush and sync every time
  631. * IO-PDIR is changed in Ike/Astro.
  632. */
  633. if (ioc_needs_fdc)
  634. asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
  635. }
  636. /**
  637. * sba_mark_invalid - invalidate one or more IO PDIR entries
  638. * @ioc: IO MMU structure which owns the pdir we are interested in.
  639. * @iova: IO Virtual Address mapped earlier
  640. * @byte_cnt: number of bytes this mapping covers.
  641. *
  642. * Marking the IO PDIR entry(ies) as Invalid and invalidate
  643. * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
  644. * is to purge stale entries in the IO TLB when unmapping entries.
  645. *
  646. * The PCOM register supports purging of multiple pages, with a minium
  647. * of 1 page and a maximum of 2GB. Hardware requires the address be
  648. * aligned to the size of the range being purged. The size of the range
  649. * must be a power of 2. The "Cool perf optimization" in the
  650. * allocation routine helps keep that true.
  651. */
  652. static SBA_INLINE void
  653. sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
  654. {
  655. u32 iovp = (u32) SBA_IOVP(ioc,iova);
  656. u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
  657. #ifdef ASSERT_PDIR_SANITY
  658. /* Assert first pdir entry is set.
  659. **
  660. ** Even though this is a big-endian machine, the entries
  661. ** in the iopdir are little endian. That's why we look at
  662. ** the byte at +7 instead of at +0.
  663. */
  664. if (0x80 != (((u8 *) pdir_ptr)[7])) {
  665. sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
  666. }
  667. #endif
  668. if (byte_cnt > IOVP_SIZE)
  669. {
  670. #if 0
  671. unsigned long entries_per_cacheline = ioc_needs_fdc ?
  672. L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
  673. - (unsigned long) pdir_ptr;
  674. : 262144;
  675. #endif
  676. /* set "size" field for PCOM */
  677. iovp |= get_order(byte_cnt) + PAGE_SHIFT;
  678. do {
  679. /* clear I/O Pdir entry "valid" bit first */
  680. ((u8 *) pdir_ptr)[7] = 0;
  681. if (ioc_needs_fdc) {
  682. asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
  683. #if 0
  684. entries_per_cacheline = L1_CACHE_SHIFT - 3;
  685. #endif
  686. }
  687. pdir_ptr++;
  688. byte_cnt -= IOVP_SIZE;
  689. } while (byte_cnt > IOVP_SIZE);
  690. } else
  691. iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
  692. /*
  693. ** clear I/O PDIR entry "valid" bit.
  694. ** We have to R/M/W the cacheline regardless how much of the
  695. ** pdir entry that we clobber.
  696. ** The rest of the entry would be useful for debugging if we
  697. ** could dump core on HPMC.
  698. */
  699. ((u8 *) pdir_ptr)[7] = 0;
  700. if (ioc_needs_fdc)
  701. asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
  702. WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
  703. }
  704. /**
  705. * sba_dma_supported - PCI driver can query DMA support
  706. * @dev: instance of PCI owned by the driver that's asking
  707. * @mask: number of address bits this PCI device can handle
  708. *
  709. * See Documentation/DMA-mapping.txt
  710. */
  711. static int sba_dma_supported( struct device *dev, u64 mask)
  712. {
  713. struct ioc *ioc;
  714. if (dev == NULL) {
  715. printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
  716. BUG();
  717. return(0);
  718. }
  719. /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
  720. * then fall back to 32-bit if that fails.
  721. * We are just "encouraging" 32-bit DMA masks here since we can
  722. * never allow IOMMU bypass unless we add special support for ZX1.
  723. */
  724. if (mask > ~0U)
  725. return 0;
  726. ioc = GET_IOC(dev);
  727. /*
  728. * check if mask is >= than the current max IO Virt Address
  729. * The max IO Virt address will *always* < 30 bits.
  730. */
  731. return((int)(mask >= (ioc->ibase - 1 +
  732. (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
  733. }
  734. /**
  735. * sba_map_single - map one buffer and return IOVA for DMA
  736. * @dev: instance of PCI owned by the driver that's asking.
  737. * @addr: driver buffer to map.
  738. * @size: number of bytes to map in driver buffer.
  739. * @direction: R/W or both.
  740. *
  741. * See Documentation/DMA-mapping.txt
  742. */
  743. static dma_addr_t
  744. sba_map_single(struct device *dev, void *addr, size_t size,
  745. enum dma_data_direction direction)
  746. {
  747. struct ioc *ioc;
  748. unsigned long flags;
  749. dma_addr_t iovp;
  750. dma_addr_t offset;
  751. u64 *pdir_start;
  752. int pide;
  753. ioc = GET_IOC(dev);
  754. /* save offset bits */
  755. offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
  756. /* round up to nearest IOVP_SIZE */
  757. size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
  758. spin_lock_irqsave(&ioc->res_lock, flags);
  759. #ifdef ASSERT_PDIR_SANITY
  760. sba_check_pdir(ioc,"Check before sba_map_single()");
  761. #endif
  762. #ifdef SBA_COLLECT_STATS
  763. ioc->msingle_calls++;
  764. ioc->msingle_pages += size >> IOVP_SHIFT;
  765. #endif
  766. pide = sba_alloc_range(ioc, size);
  767. iovp = (dma_addr_t) pide << IOVP_SHIFT;
  768. DBG_RUN("%s() 0x%p -> 0x%lx\n",
  769. __FUNCTION__, addr, (long) iovp | offset);
  770. pdir_start = &(ioc->pdir_base[pide]);
  771. while (size > 0) {
  772. sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
  773. DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
  774. pdir_start,
  775. (u8) (((u8 *) pdir_start)[7]),
  776. (u8) (((u8 *) pdir_start)[6]),
  777. (u8) (((u8 *) pdir_start)[5]),
  778. (u8) (((u8 *) pdir_start)[4]),
  779. (u8) (((u8 *) pdir_start)[3]),
  780. (u8) (((u8 *) pdir_start)[2]),
  781. (u8) (((u8 *) pdir_start)[1]),
  782. (u8) (((u8 *) pdir_start)[0])
  783. );
  784. addr += IOVP_SIZE;
  785. size -= IOVP_SIZE;
  786. pdir_start++;
  787. }
  788. /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
  789. if (ioc_needs_fdc)
  790. asm volatile("sync" : : );
  791. #ifdef ASSERT_PDIR_SANITY
  792. sba_check_pdir(ioc,"Check after sba_map_single()");
  793. #endif
  794. spin_unlock_irqrestore(&ioc->res_lock, flags);
  795. /* form complete address */
  796. return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
  797. }
  798. /**
  799. * sba_unmap_single - unmap one IOVA and free resources
  800. * @dev: instance of PCI owned by the driver that's asking.
  801. * @iova: IOVA of driver buffer previously mapped.
  802. * @size: number of bytes mapped in driver buffer.
  803. * @direction: R/W or both.
  804. *
  805. * See Documentation/DMA-mapping.txt
  806. */
  807. static void
  808. sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
  809. enum dma_data_direction direction)
  810. {
  811. struct ioc *ioc;
  812. #if DELAYED_RESOURCE_CNT > 0
  813. struct sba_dma_pair *d;
  814. #endif
  815. unsigned long flags;
  816. dma_addr_t offset;
  817. DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
  818. ioc = GET_IOC(dev);
  819. offset = iova & ~IOVP_MASK;
  820. iova ^= offset; /* clear offset bits */
  821. size += offset;
  822. size = ROUNDUP(size, IOVP_SIZE);
  823. spin_lock_irqsave(&ioc->res_lock, flags);
  824. #ifdef SBA_COLLECT_STATS
  825. ioc->usingle_calls++;
  826. ioc->usingle_pages += size >> IOVP_SHIFT;
  827. #endif
  828. sba_mark_invalid(ioc, iova, size);
  829. #if DELAYED_RESOURCE_CNT > 0
  830. /* Delaying when we re-use a IO Pdir entry reduces the number
  831. * of MMIO reads needed to flush writes to the PCOM register.
  832. */
  833. d = &(ioc->saved[ioc->saved_cnt]);
  834. d->iova = iova;
  835. d->size = size;
  836. if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
  837. int cnt = ioc->saved_cnt;
  838. while (cnt--) {
  839. sba_free_range(ioc, d->iova, d->size);
  840. d--;
  841. }
  842. ioc->saved_cnt = 0;
  843. READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
  844. }
  845. #else /* DELAYED_RESOURCE_CNT == 0 */
  846. sba_free_range(ioc, iova, size);
  847. /* If fdc's were issued, force fdc's to be visible now */
  848. if (ioc_needs_fdc)
  849. asm volatile("sync" : : );
  850. READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
  851. #endif /* DELAYED_RESOURCE_CNT == 0 */
  852. spin_unlock_irqrestore(&ioc->res_lock, flags);
  853. /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
  854. ** For Astro based systems this isn't a big deal WRT performance.
  855. ** As long as 2.4 kernels copyin/copyout data from/to userspace,
  856. ** we don't need the syncdma. The issue here is I/O MMU cachelines
  857. ** are *not* coherent in all cases. May be hwrev dependent.
  858. ** Need to investigate more.
  859. asm volatile("syncdma");
  860. */
  861. }
  862. /**
  863. * sba_alloc_consistent - allocate/map shared mem for DMA
  864. * @hwdev: instance of PCI owned by the driver that's asking.
  865. * @size: number of bytes mapped in driver buffer.
  866. * @dma_handle: IOVA of new buffer.
  867. *
  868. * See Documentation/DMA-mapping.txt
  869. */
  870. static void *sba_alloc_consistent(struct device *hwdev, size_t size,
  871. dma_addr_t *dma_handle, gfp_t gfp)
  872. {
  873. void *ret;
  874. if (!hwdev) {
  875. /* only support PCI */
  876. *dma_handle = 0;
  877. return 0;
  878. }
  879. ret = (void *) __get_free_pages(gfp, get_order(size));
  880. if (ret) {
  881. memset(ret, 0, size);
  882. *dma_handle = sba_map_single(hwdev, ret, size, 0);
  883. }
  884. return ret;
  885. }
  886. /**
  887. * sba_free_consistent - free/unmap shared mem for DMA
  888. * @hwdev: instance of PCI owned by the driver that's asking.
  889. * @size: number of bytes mapped in driver buffer.
  890. * @vaddr: virtual address IOVA of "consistent" buffer.
  891. * @dma_handler: IO virtual address of "consistent" buffer.
  892. *
  893. * See Documentation/DMA-mapping.txt
  894. */
  895. static void
  896. sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
  897. dma_addr_t dma_handle)
  898. {
  899. sba_unmap_single(hwdev, dma_handle, size, 0);
  900. free_pages((unsigned long) vaddr, get_order(size));
  901. }
  902. /*
  903. ** Since 0 is a valid pdir_base index value, can't use that
  904. ** to determine if a value is valid or not. Use a flag to indicate
  905. ** the SG list entry contains a valid pdir index.
  906. */
  907. #define PIDE_FLAG 0x80000000UL
  908. #ifdef SBA_COLLECT_STATS
  909. #define IOMMU_MAP_STATS
  910. #endif
  911. #include "iommu-helpers.h"
  912. #ifdef DEBUG_LARGE_SG_ENTRIES
  913. int dump_run_sg = 0;
  914. #endif
  915. /**
  916. * sba_map_sg - map Scatter/Gather list
  917. * @dev: instance of PCI owned by the driver that's asking.
  918. * @sglist: array of buffer/length pairs
  919. * @nents: number of entries in list
  920. * @direction: R/W or both.
  921. *
  922. * See Documentation/DMA-mapping.txt
  923. */
  924. static int
  925. sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
  926. enum dma_data_direction direction)
  927. {
  928. struct ioc *ioc;
  929. int coalesced, filled = 0;
  930. unsigned long flags;
  931. DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
  932. ioc = GET_IOC(dev);
  933. /* Fast path single entry scatterlists. */
  934. if (nents == 1) {
  935. sg_dma_address(sglist) = sba_map_single(dev,
  936. (void *)sg_virt_addr(sglist),
  937. sglist->length, direction);
  938. sg_dma_len(sglist) = sglist->length;
  939. return 1;
  940. }
  941. spin_lock_irqsave(&ioc->res_lock, flags);
  942. #ifdef ASSERT_PDIR_SANITY
  943. if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
  944. {
  945. sba_dump_sg(ioc, sglist, nents);
  946. panic("Check before sba_map_sg()");
  947. }
  948. #endif
  949. #ifdef SBA_COLLECT_STATS
  950. ioc->msg_calls++;
  951. #endif
  952. /*
  953. ** First coalesce the chunks and allocate I/O pdir space
  954. **
  955. ** If this is one DMA stream, we can properly map using the
  956. ** correct virtual address associated with each DMA page.
  957. ** w/o this association, we wouldn't have coherent DMA!
  958. ** Access to the virtual address is what forces a two pass algorithm.
  959. */
  960. coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
  961. /*
  962. ** Program the I/O Pdir
  963. **
  964. ** map the virtual addresses to the I/O Pdir
  965. ** o dma_address will contain the pdir index
  966. ** o dma_len will contain the number of bytes to map
  967. ** o address contains the virtual address.
  968. */
  969. filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
  970. /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
  971. if (ioc_needs_fdc)
  972. asm volatile("sync" : : );
  973. #ifdef ASSERT_PDIR_SANITY
  974. if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
  975. {
  976. sba_dump_sg(ioc, sglist, nents);
  977. panic("Check after sba_map_sg()\n");
  978. }
  979. #endif
  980. spin_unlock_irqrestore(&ioc->res_lock, flags);
  981. DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
  982. return filled;
  983. }
  984. /**
  985. * sba_unmap_sg - unmap Scatter/Gather list
  986. * @dev: instance of PCI owned by the driver that's asking.
  987. * @sglist: array of buffer/length pairs
  988. * @nents: number of entries in list
  989. * @direction: R/W or both.
  990. *
  991. * See Documentation/DMA-mapping.txt
  992. */
  993. static void
  994. sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
  995. enum dma_data_direction direction)
  996. {
  997. struct ioc *ioc;
  998. #ifdef ASSERT_PDIR_SANITY
  999. unsigned long flags;
  1000. #endif
  1001. DBG_RUN_SG("%s() START %d entries, %p,%x\n",
  1002. __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
  1003. ioc = GET_IOC(dev);
  1004. #ifdef SBA_COLLECT_STATS
  1005. ioc->usg_calls++;
  1006. #endif
  1007. #ifdef ASSERT_PDIR_SANITY
  1008. spin_lock_irqsave(&ioc->res_lock, flags);
  1009. sba_check_pdir(ioc,"Check before sba_unmap_sg()");
  1010. spin_unlock_irqrestore(&ioc->res_lock, flags);
  1011. #endif
  1012. while (sg_dma_len(sglist) && nents--) {
  1013. sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
  1014. #ifdef SBA_COLLECT_STATS
  1015. ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
  1016. ioc->usingle_calls--; /* kluge since call is unmap_sg() */
  1017. #endif
  1018. ++sglist;
  1019. }
  1020. DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
  1021. #ifdef ASSERT_PDIR_SANITY
  1022. spin_lock_irqsave(&ioc->res_lock, flags);
  1023. sba_check_pdir(ioc,"Check after sba_unmap_sg()");
  1024. spin_unlock_irqrestore(&ioc->res_lock, flags);
  1025. #endif
  1026. }
  1027. static struct hppa_dma_ops sba_ops = {
  1028. .dma_supported = sba_dma_supported,
  1029. .alloc_consistent = sba_alloc_consistent,
  1030. .alloc_noncoherent = sba_alloc_consistent,
  1031. .free_consistent = sba_free_consistent,
  1032. .map_single = sba_map_single,
  1033. .unmap_single = sba_unmap_single,
  1034. .map_sg = sba_map_sg,
  1035. .unmap_sg = sba_unmap_sg,
  1036. .dma_sync_single_for_cpu = NULL,
  1037. .dma_sync_single_for_device = NULL,
  1038. .dma_sync_sg_for_cpu = NULL,
  1039. .dma_sync_sg_for_device = NULL,
  1040. };
  1041. /**************************************************************************
  1042. **
  1043. ** SBA PAT PDC support
  1044. **
  1045. ** o call pdc_pat_cell_module()
  1046. ** o store ranges in PCI "resource" structures
  1047. **
  1048. **************************************************************************/
  1049. static void
  1050. sba_get_pat_resources(struct sba_device *sba_dev)
  1051. {
  1052. #if 0
  1053. /*
  1054. ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
  1055. ** PAT PDC to program the SBA/LBA directed range registers...this
  1056. ** burden may fall on the LBA code since it directly supports the
  1057. ** PCI subsystem. It's not clear yet. - ggg
  1058. */
  1059. PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
  1060. FIXME : ???
  1061. PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
  1062. Tells where the dvi bits are located in the address.
  1063. PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
  1064. FIXME : ???
  1065. #endif
  1066. }
  1067. /**************************************************************
  1068. *
  1069. * Initialization and claim
  1070. *
  1071. ***************************************************************/
  1072. #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
  1073. #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
  1074. static void *
  1075. sba_alloc_pdir(unsigned int pdir_size)
  1076. {
  1077. unsigned long pdir_base;
  1078. unsigned long pdir_order = get_order(pdir_size);
  1079. pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
  1080. if (NULL == (void *) pdir_base) {
  1081. panic("%s() could not allocate I/O Page Table\n",
  1082. __FUNCTION__);
  1083. }
  1084. /* If this is not PA8700 (PCX-W2)
  1085. ** OR newer than ver 2.2
  1086. ** OR in a system that doesn't need VINDEX bits from SBA,
  1087. **
  1088. ** then we aren't exposed to the HW bug.
  1089. */
  1090. if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
  1091. || (boot_cpu_data.pdc.versions > 0x202)
  1092. || (boot_cpu_data.pdc.capabilities & 0x08L) )
  1093. return (void *) pdir_base;
  1094. /*
  1095. * PA8700 (PCX-W2, aka piranha) silent data corruption fix
  1096. *
  1097. * An interaction between PA8700 CPU (Ver 2.2 or older) and
  1098. * Ike/Astro can cause silent data corruption. This is only
  1099. * a problem if the I/O PDIR is located in memory such that
  1100. * (little-endian) bits 17 and 18 are on and bit 20 is off.
  1101. *
  1102. * Since the max IO Pdir size is 2MB, by cleverly allocating the
  1103. * right physical address, we can either avoid (IOPDIR <= 1MB)
  1104. * or minimize (2MB IO Pdir) the problem if we restrict the
  1105. * IO Pdir to a maximum size of 2MB-128K (1902K).
  1106. *
  1107. * Because we always allocate 2^N sized IO pdirs, either of the
  1108. * "bad" regions will be the last 128K if at all. That's easy
  1109. * to test for.
  1110. *
  1111. */
  1112. if (pdir_order <= (19-12)) {
  1113. if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
  1114. /* allocate a new one on 512k alignment */
  1115. unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
  1116. /* release original */
  1117. free_pages(pdir_base, pdir_order);
  1118. pdir_base = new_pdir;
  1119. /* release excess */
  1120. while (pdir_order < (19-12)) {
  1121. new_pdir += pdir_size;
  1122. free_pages(new_pdir, pdir_order);
  1123. pdir_order +=1;
  1124. pdir_size <<=1;
  1125. }
  1126. }
  1127. } else {
  1128. /*
  1129. ** 1MB or 2MB Pdir
  1130. ** Needs to be aligned on an "odd" 1MB boundary.
  1131. */
  1132. unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
  1133. /* release original */
  1134. free_pages( pdir_base, pdir_order);
  1135. /* release first 1MB */
  1136. free_pages(new_pdir, 20-12);
  1137. pdir_base = new_pdir + 1024*1024;
  1138. if (pdir_order > (20-12)) {
  1139. /*
  1140. ** 2MB Pdir.
  1141. **
  1142. ** Flag tells init_bitmap() to mark bad 128k as used
  1143. ** and to reduce the size by 128k.
  1144. */
  1145. piranha_bad_128k = 1;
  1146. new_pdir += 3*1024*1024;
  1147. /* release last 1MB */
  1148. free_pages(new_pdir, 20-12);
  1149. /* release unusable 128KB */
  1150. free_pages(new_pdir - 128*1024 , 17-12);
  1151. pdir_size -= 128*1024;
  1152. }
  1153. }
  1154. memset((void *) pdir_base, 0, pdir_size);
  1155. return (void *) pdir_base;
  1156. }
  1157. static struct device *next_device(struct klist_iter *i)
  1158. {
  1159. struct klist_node * n = klist_next(i);
  1160. return n ? container_of(n, struct device, knode_parent) : NULL;
  1161. }
  1162. /* setup Mercury or Elroy IBASE/IMASK registers. */
  1163. static void
  1164. setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1165. {
  1166. /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
  1167. extern void lba_set_iregs(struct parisc_device *, u32, u32);
  1168. struct device *dev;
  1169. struct klist_iter i;
  1170. klist_iter_init(&sba->dev.klist_children, &i);
  1171. while ((dev = next_device(&i))) {
  1172. struct parisc_device *lba = to_parisc_device(dev);
  1173. int rope_num = (lba->hpa.start >> 13) & 0xf;
  1174. if (rope_num >> 3 == ioc_num)
  1175. lba_set_iregs(lba, ioc->ibase, ioc->imask);
  1176. }
  1177. klist_iter_exit(&i);
  1178. }
  1179. static void
  1180. sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1181. {
  1182. u32 iova_space_mask;
  1183. u32 iova_space_size;
  1184. int iov_order, tcnfg;
  1185. #ifdef SBA_AGP_SUPPORT
  1186. int agp_found = 0;
  1187. #endif
  1188. /*
  1189. ** Firmware programs the base and size of a "safe IOVA space"
  1190. ** (one that doesn't overlap memory or LMMIO space) in the
  1191. ** IBASE and IMASK registers.
  1192. */
  1193. ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
  1194. iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
  1195. if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
  1196. printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
  1197. iova_space_size /= 2;
  1198. }
  1199. /*
  1200. ** iov_order is always based on a 1GB IOVA space since we want to
  1201. ** turn on the other half for AGP GART.
  1202. */
  1203. iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
  1204. ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
  1205. DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
  1206. __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
  1207. iov_order + PAGE_SHIFT);
  1208. ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
  1209. get_order(ioc->pdir_size));
  1210. if (!ioc->pdir_base)
  1211. panic("Couldn't allocate I/O Page Table\n");
  1212. memset(ioc->pdir_base, 0, ioc->pdir_size);
  1213. DBG_INIT("%s() pdir %p size %x\n",
  1214. __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
  1215. #ifdef SBA_HINT_SUPPORT
  1216. ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
  1217. ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
  1218. DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
  1219. ioc->hint_shift_pdir, ioc->hint_mask_pdir);
  1220. #endif
  1221. WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
  1222. WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1223. /* build IMASK for IOC and Elroy */
  1224. iova_space_mask = 0xffffffff;
  1225. iova_space_mask <<= (iov_order + PAGE_SHIFT);
  1226. ioc->imask = iova_space_mask;
  1227. #ifdef ZX1_SUPPORT
  1228. ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
  1229. #endif
  1230. sba_dump_tlb(ioc->ioc_hpa);
  1231. setup_ibase_imask(sba, ioc, ioc_num);
  1232. WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
  1233. #ifdef CONFIG_64BIT
  1234. /*
  1235. ** Setting the upper bits makes checking for bypass addresses
  1236. ** a little faster later on.
  1237. */
  1238. ioc->imask |= 0xFFFFFFFF00000000UL;
  1239. #endif
  1240. /* Set I/O PDIR Page size to system page size */
  1241. switch (PAGE_SHIFT) {
  1242. case 12: tcnfg = 0; break; /* 4K */
  1243. case 13: tcnfg = 1; break; /* 8K */
  1244. case 14: tcnfg = 2; break; /* 16K */
  1245. case 16: tcnfg = 3; break; /* 64K */
  1246. default:
  1247. panic(__FILE__ "Unsupported system page size %d",
  1248. 1 << PAGE_SHIFT);
  1249. break;
  1250. }
  1251. WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
  1252. /*
  1253. ** Program the IOC's ibase and enable IOVA translation
  1254. ** Bit zero == enable bit.
  1255. */
  1256. WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
  1257. /*
  1258. ** Clear I/O TLB of any possible entries.
  1259. ** (Yes. This is a bit paranoid...but so what)
  1260. */
  1261. WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
  1262. #ifdef SBA_AGP_SUPPORT
  1263. /*
  1264. ** If an AGP device is present, only use half of the IOV space
  1265. ** for PCI DMA. Unfortunately we can't know ahead of time
  1266. ** whether GART support will actually be used, for now we
  1267. ** can just key on any AGP device found in the system.
  1268. ** We program the next pdir index after we stop w/ a key for
  1269. ** the GART code to handshake on.
  1270. */
  1271. device=NULL;
  1272. for (lba = sba->child; lba; lba = lba->sibling) {
  1273. if (IS_QUICKSILVER(lba))
  1274. break;
  1275. }
  1276. if (lba) {
  1277. DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
  1278. ioc->pdir_size /= 2;
  1279. ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
  1280. } else {
  1281. DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
  1282. }
  1283. #endif /* 0 */
  1284. }
  1285. static void
  1286. sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
  1287. {
  1288. u32 iova_space_size, iova_space_mask;
  1289. unsigned int pdir_size, iov_order;
  1290. /*
  1291. ** Determine IOVA Space size from memory size.
  1292. **
  1293. ** Ideally, PCI drivers would register the maximum number
  1294. ** of DMA they can have outstanding for each device they
  1295. ** own. Next best thing would be to guess how much DMA
  1296. ** can be outstanding based on PCI Class/sub-class. Both
  1297. ** methods still require some "extra" to support PCI
  1298. ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
  1299. **
  1300. ** While we have 32-bits "IOVA" space, top two 2 bits are used
  1301. ** for DMA hints - ergo only 30 bits max.
  1302. */
  1303. iova_space_size = (u32) (num_physpages/global_ioc_cnt);
  1304. /* limit IOVA space size to 1MB-1GB */
  1305. if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
  1306. iova_space_size = 1 << (20 - PAGE_SHIFT);
  1307. }
  1308. else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
  1309. iova_space_size = 1 << (30 - PAGE_SHIFT);
  1310. }
  1311. /*
  1312. ** iova space must be log2() in size.
  1313. ** thus, pdir/res_map will also be log2().
  1314. ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
  1315. */
  1316. iov_order = get_order(iova_space_size << PAGE_SHIFT);
  1317. /* iova_space_size is now bytes, not pages */
  1318. iova_space_size = 1 << (iov_order + PAGE_SHIFT);
  1319. ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
  1320. DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
  1321. __FUNCTION__,
  1322. ioc->ioc_hpa,
  1323. (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
  1324. iova_space_size>>20,
  1325. iov_order + PAGE_SHIFT);
  1326. ioc->pdir_base = sba_alloc_pdir(pdir_size);
  1327. DBG_INIT("%s() pdir %p size %x\n",
  1328. __FUNCTION__, ioc->pdir_base, pdir_size);
  1329. #ifdef SBA_HINT_SUPPORT
  1330. /* FIXME : DMA HINTs not used */
  1331. ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
  1332. ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
  1333. DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
  1334. ioc->hint_shift_pdir, ioc->hint_mask_pdir);
  1335. #endif
  1336. WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1337. /* build IMASK for IOC and Elroy */
  1338. iova_space_mask = 0xffffffff;
  1339. iova_space_mask <<= (iov_order + PAGE_SHIFT);
  1340. /*
  1341. ** On C3000 w/512MB mem, HP-UX 10.20 reports:
  1342. ** ibase=0, imask=0xFE000000, size=0x2000000.
  1343. */
  1344. ioc->ibase = 0;
  1345. ioc->imask = iova_space_mask; /* save it */
  1346. #ifdef ZX1_SUPPORT
  1347. ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
  1348. #endif
  1349. DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
  1350. __FUNCTION__, ioc->ibase, ioc->imask);
  1351. /*
  1352. ** FIXME: Hint registers are programmed with default hint
  1353. ** values during boot, so hints should be sane even if we
  1354. ** can't reprogram them the way drivers want.
  1355. */
  1356. setup_ibase_imask(sba, ioc, ioc_num);
  1357. /*
  1358. ** Program the IOC's ibase and enable IOVA translation
  1359. */
  1360. WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
  1361. WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
  1362. /* Set I/O PDIR Page size to 4K */
  1363. WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
  1364. /*
  1365. ** Clear I/O TLB of any possible entries.
  1366. ** (Yes. This is a bit paranoid...but so what)
  1367. */
  1368. WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
  1369. ioc->ibase = 0; /* used by SBA_IOVA and related macros */
  1370. DBG_INIT("%s() DONE\n", __FUNCTION__);
  1371. }
  1372. /**************************************************************************
  1373. **
  1374. ** SBA initialization code (HW and SW)
  1375. **
  1376. ** o identify SBA chip itself
  1377. ** o initialize SBA chip modes (HardFail)
  1378. ** o initialize SBA chip modes (HardFail)
  1379. ** o FIXME: initialize DMA hints for reasonable defaults
  1380. **
  1381. **************************************************************************/
  1382. static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
  1383. {
  1384. return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
  1385. }
  1386. static void sba_hw_init(struct sba_device *sba_dev)
  1387. {
  1388. int i;
  1389. int num_ioc;
  1390. u64 ioc_ctl;
  1391. if (!is_pdc_pat()) {
  1392. /* Shutdown the USB controller on Astro-based workstations.
  1393. ** Once we reprogram the IOMMU, the next DMA performed by
  1394. ** USB will HPMC the box. USB is only enabled if a
  1395. ** keyboard is present and found.
  1396. **
  1397. ** With serial console, j6k v5.0 firmware says:
  1398. ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
  1399. **
  1400. ** FIXME: Using GFX+USB console at power up but direct
  1401. ** linux to serial console is still broken.
  1402. ** USB could generate DMA so we must reset USB.
  1403. ** The proper sequence would be:
  1404. ** o block console output
  1405. ** o reset USB device
  1406. ** o reprogram serial port
  1407. ** o unblock console output
  1408. */
  1409. if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
  1410. pdc_io_reset_devices();
  1411. }
  1412. }
  1413. #if 0
  1414. printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
  1415. PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
  1416. /*
  1417. ** Need to deal with DMA from LAN.
  1418. ** Maybe use page zero boot device as a handle to talk
  1419. ** to PDC about which device to shutdown.
  1420. **
  1421. ** Netbooting, j6k v5.0 firmware says:
  1422. ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
  1423. ** ARGH! invalid class.
  1424. */
  1425. if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
  1426. && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
  1427. pdc_io_reset();
  1428. }
  1429. #endif
  1430. if (!IS_PLUTO(sba_dev->iodc)) {
  1431. ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
  1432. DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
  1433. __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
  1434. ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
  1435. ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
  1436. /* j6700 v1.6 firmware sets 0x294f */
  1437. /* A500 firmware sets 0x4d */
  1438. WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
  1439. #ifdef DEBUG_SBA_INIT
  1440. ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
  1441. DBG_INIT(" 0x%Lx\n", ioc_ctl);
  1442. #endif
  1443. } /* if !PLUTO */
  1444. if (IS_ASTRO(sba_dev->iodc)) {
  1445. int err;
  1446. /* PAT_PDC (L-class) also reports the same goofy base */
  1447. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
  1448. num_ioc = 1;
  1449. sba_dev->chip_resv.name = "Astro Intr Ack";
  1450. sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
  1451. sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
  1452. err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
  1453. BUG_ON(err < 0);
  1454. } else if (IS_PLUTO(sba_dev->iodc)) {
  1455. int err;
  1456. /* We use a negative value for IOC HPA so it gets
  1457. * corrected when we add it with IKE's IOC offset.
  1458. * Doesnt look clean, but fewer code.
  1459. */
  1460. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
  1461. num_ioc = 1;
  1462. sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
  1463. sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
  1464. sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
  1465. err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
  1466. WARN_ON(err < 0);
  1467. sba_dev->iommu_resv.name = "IOVA Space";
  1468. sba_dev->iommu_resv.start = 0x40000000UL;
  1469. sba_dev->iommu_resv.end = 0x50000000UL - 1;
  1470. err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
  1471. WARN_ON(err < 0);
  1472. } else {
  1473. /* IS_IKE (ie N-class, L3000, L1500) */
  1474. sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
  1475. sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
  1476. num_ioc = 2;
  1477. /* TODO - LOOKUP Ike/Stretch chipset mem map */
  1478. }
  1479. /* XXX: What about Reo? */
  1480. sba_dev->num_ioc = num_ioc;
  1481. for (i = 0; i < num_ioc; i++) {
  1482. void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
  1483. unsigned int j;
  1484. for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
  1485. /*
  1486. * Clear ROPE(N)_CONFIG AO bit.
  1487. * Disables "NT Ordering" (~= !"Relaxed Ordering")
  1488. * Overrides bit 1 in DMA Hint Sets.
  1489. * Improves netperf UDP_STREAM by ~10% for bcm5701.
  1490. */
  1491. if (IS_PLUTO(sba_dev->iodc)) {
  1492. void __iomem *rope_cfg;
  1493. unsigned long cfg_val;
  1494. rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
  1495. cfg_val = READ_REG(rope_cfg);
  1496. cfg_val &= ~IOC_ROPE_AO;
  1497. WRITE_REG(cfg_val, rope_cfg);
  1498. }
  1499. /*
  1500. ** Make sure the box crashes on rope errors.
  1501. */
  1502. WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
  1503. }
  1504. /* flush out the last writes */
  1505. READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
  1506. DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
  1507. i,
  1508. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
  1509. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
  1510. );
  1511. DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
  1512. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
  1513. READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
  1514. );
  1515. if (IS_PLUTO(sba_dev->iodc)) {
  1516. sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
  1517. } else {
  1518. sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
  1519. }
  1520. }
  1521. }
  1522. static void
  1523. sba_common_init(struct sba_device *sba_dev)
  1524. {
  1525. int i;
  1526. /* add this one to the head of the list (order doesn't matter)
  1527. ** This will be useful for debugging - especially if we get coredumps
  1528. */
  1529. sba_dev->next = sba_list;
  1530. sba_list = sba_dev;
  1531. for(i=0; i< sba_dev->num_ioc; i++) {
  1532. int res_size;
  1533. #ifdef DEBUG_DMB_TRAP
  1534. extern void iterate_pages(unsigned long , unsigned long ,
  1535. void (*)(pte_t * , unsigned long),
  1536. unsigned long );
  1537. void set_data_memory_break(pte_t * , unsigned long);
  1538. #endif
  1539. /* resource map size dictated by pdir_size */
  1540. res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
  1541. /* Second part of PIRANHA BUG */
  1542. if (piranha_bad_128k) {
  1543. res_size -= (128*1024)/sizeof(u64);
  1544. }
  1545. res_size >>= 3; /* convert bit count to byte count */
  1546. DBG_INIT("%s() res_size 0x%x\n",
  1547. __FUNCTION__, res_size);
  1548. sba_dev->ioc[i].res_size = res_size;
  1549. sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
  1550. #ifdef DEBUG_DMB_TRAP
  1551. iterate_pages( sba_dev->ioc[i].res_map, res_size,
  1552. set_data_memory_break, 0);
  1553. #endif
  1554. if (NULL == sba_dev->ioc[i].res_map)
  1555. {
  1556. panic("%s:%s() could not allocate resource map\n",
  1557. __FILE__, __FUNCTION__ );
  1558. }
  1559. memset(sba_dev->ioc[i].res_map, 0, res_size);
  1560. /* next available IOVP - circular search */
  1561. sba_dev->ioc[i].res_hint = (unsigned long *)
  1562. &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
  1563. #ifdef ASSERT_PDIR_SANITY
  1564. /* Mark first bit busy - ie no IOVA 0 */
  1565. sba_dev->ioc[i].res_map[0] = 0x80;
  1566. sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
  1567. #endif
  1568. /* Third (and last) part of PIRANHA BUG */
  1569. if (piranha_bad_128k) {
  1570. /* region from +1408K to +1536 is un-usable. */
  1571. int idx_start = (1408*1024/sizeof(u64)) >> 3;
  1572. int idx_end = (1536*1024/sizeof(u64)) >> 3;
  1573. long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
  1574. long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
  1575. /* mark that part of the io pdir busy */
  1576. while (p_start < p_end)
  1577. *p_start++ = -1;
  1578. }
  1579. #ifdef DEBUG_DMB_TRAP
  1580. iterate_pages( sba_dev->ioc[i].res_map, res_size,
  1581. set_data_memory_break, 0);
  1582. iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
  1583. set_data_memory_break, 0);
  1584. #endif
  1585. DBG_INIT("%s() %d res_map %x %p\n",
  1586. __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
  1587. }
  1588. spin_lock_init(&sba_dev->sba_lock);
  1589. ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
  1590. #ifdef DEBUG_SBA_INIT
  1591. /*
  1592. * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
  1593. * (bit #61, big endian), we have to flush and sync every time
  1594. * IO-PDIR is changed in Ike/Astro.
  1595. */
  1596. if (ioc_needs_fdc) {
  1597. printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
  1598. } else {
  1599. printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
  1600. }
  1601. #endif
  1602. }
  1603. #ifdef CONFIG_PROC_FS
  1604. static int sba_proc_info(struct seq_file *m, void *p)
  1605. {
  1606. struct sba_device *sba_dev = sba_list;
  1607. struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
  1608. int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
  1609. #ifdef SBA_COLLECT_STATS
  1610. unsigned long avg = 0, min, max;
  1611. #endif
  1612. int i, len = 0;
  1613. len += seq_printf(m, "%s rev %d.%d\n",
  1614. sba_dev->name,
  1615. (sba_dev->hw_rev & 0x7) + 1,
  1616. (sba_dev->hw_rev & 0x18) >> 3
  1617. );
  1618. len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
  1619. (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
  1620. total_pages);
  1621. len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
  1622. ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
  1623. len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
  1624. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
  1625. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
  1626. READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
  1627. );
  1628. for (i=0; i<4; i++)
  1629. len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
  1630. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
  1631. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
  1632. READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
  1633. );
  1634. #ifdef SBA_COLLECT_STATS
  1635. len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
  1636. total_pages - ioc->used_pages, ioc->used_pages,
  1637. (int) (ioc->used_pages * 100 / total_pages));
  1638. min = max = ioc->avg_search[0];
  1639. for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
  1640. avg += ioc->avg_search[i];
  1641. if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
  1642. if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
  1643. }
  1644. avg /= SBA_SEARCH_SAMPLE;
  1645. len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
  1646. min, avg, max);
  1647. len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
  1648. ioc->msingle_calls, ioc->msingle_pages,
  1649. (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
  1650. /* KLUGE - unmap_sg calls unmap_single for each mapped page */
  1651. min = ioc->usingle_calls;
  1652. max = ioc->usingle_pages - ioc->usg_pages;
  1653. len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
  1654. min, max, (int) ((max * 1000)/min));
  1655. len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
  1656. ioc->msg_calls, ioc->msg_pages,
  1657. (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
  1658. len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
  1659. ioc->usg_calls, ioc->usg_pages,
  1660. (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
  1661. #endif
  1662. return 0;
  1663. }
  1664. static int
  1665. sba_proc_open(struct inode *i, struct file *f)
  1666. {
  1667. return single_open(f, &sba_proc_info, NULL);
  1668. }
  1669. static struct file_operations sba_proc_fops = {
  1670. .owner = THIS_MODULE,
  1671. .open = sba_proc_open,
  1672. .read = seq_read,
  1673. .llseek = seq_lseek,
  1674. .release = single_release,
  1675. };
  1676. static int
  1677. sba_proc_bitmap_info(struct seq_file *m, void *p)
  1678. {
  1679. struct sba_device *sba_dev = sba_list;
  1680. struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
  1681. unsigned int *res_ptr = (unsigned int *)ioc->res_map;
  1682. int i, len = 0;
  1683. for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
  1684. if ((i & 7) == 0)
  1685. len += seq_printf(m, "\n ");
  1686. len += seq_printf(m, " %08x", *res_ptr);
  1687. }
  1688. len += seq_printf(m, "\n");
  1689. return 0;
  1690. }
  1691. static int
  1692. sba_proc_bitmap_open(struct inode *i, struct file *f)
  1693. {
  1694. return single_open(f, &sba_proc_bitmap_info, NULL);
  1695. }
  1696. static struct file_operations sba_proc_bitmap_fops = {
  1697. .owner = THIS_MODULE,
  1698. .open = sba_proc_bitmap_open,
  1699. .read = seq_read,
  1700. .llseek = seq_lseek,
  1701. .release = single_release,
  1702. };
  1703. #endif /* CONFIG_PROC_FS */
  1704. static struct parisc_device_id sba_tbl[] = {
  1705. { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
  1706. { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
  1707. { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
  1708. { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
  1709. { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
  1710. { 0, }
  1711. };
  1712. int sba_driver_callback(struct parisc_device *);
  1713. static struct parisc_driver sba_driver = {
  1714. .name = MODULE_NAME,
  1715. .id_table = sba_tbl,
  1716. .probe = sba_driver_callback,
  1717. };
  1718. /*
  1719. ** Determine if sba should claim this chip (return 0) or not (return 1).
  1720. ** If so, initialize the chip and tell other partners in crime they
  1721. ** have work to do.
  1722. */
  1723. int
  1724. sba_driver_callback(struct parisc_device *dev)
  1725. {
  1726. struct sba_device *sba_dev;
  1727. u32 func_class;
  1728. int i;
  1729. char *version;
  1730. void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
  1731. struct proc_dir_entry *info_entry, *bitmap_entry, *root;
  1732. sba_dump_ranges(sba_addr);
  1733. /* Read HW Rev First */
  1734. func_class = READ_REG(sba_addr + SBA_FCLASS);
  1735. if (IS_ASTRO(&dev->id)) {
  1736. unsigned long fclass;
  1737. static char astro_rev[]="Astro ?.?";
  1738. /* Astro is broken...Read HW Rev First */
  1739. fclass = READ_REG(sba_addr);
  1740. astro_rev[6] = '1' + (char) (fclass & 0x7);
  1741. astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
  1742. version = astro_rev;
  1743. } else if (IS_IKE(&dev->id)) {
  1744. static char ike_rev[] = "Ike rev ?";
  1745. ike_rev[8] = '0' + (char) (func_class & 0xff);
  1746. version = ike_rev;
  1747. } else if (IS_PLUTO(&dev->id)) {
  1748. static char pluto_rev[]="Pluto ?.?";
  1749. pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
  1750. pluto_rev[8] = '0' + (char) (func_class & 0x0f);
  1751. version = pluto_rev;
  1752. } else {
  1753. static char reo_rev[] = "REO rev ?";
  1754. reo_rev[8] = '0' + (char) (func_class & 0xff);
  1755. version = reo_rev;
  1756. }
  1757. if (!global_ioc_cnt) {
  1758. global_ioc_cnt = count_parisc_driver(&sba_driver);
  1759. /* Astro and Pluto have one IOC per SBA */
  1760. if ((!IS_ASTRO(&dev->id)) || (!IS_PLUTO(&dev->id)))
  1761. global_ioc_cnt *= 2;
  1762. }
  1763. printk(KERN_INFO "%s found %s at 0x%lx\n",
  1764. MODULE_NAME, version, dev->hpa.start);
  1765. sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
  1766. if (!sba_dev) {
  1767. printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
  1768. return -ENOMEM;
  1769. }
  1770. parisc_set_drvdata(dev, sba_dev);
  1771. for(i=0; i<MAX_IOC; i++)
  1772. spin_lock_init(&(sba_dev->ioc[i].res_lock));
  1773. sba_dev->dev = dev;
  1774. sba_dev->hw_rev = func_class;
  1775. sba_dev->iodc = &dev->id;
  1776. sba_dev->name = dev->name;
  1777. sba_dev->sba_hpa = sba_addr;
  1778. sba_get_pat_resources(sba_dev);
  1779. sba_hw_init(sba_dev);
  1780. sba_common_init(sba_dev);
  1781. hppa_dma_ops = &sba_ops;
  1782. #ifdef CONFIG_PROC_FS
  1783. switch (dev->id.hversion) {
  1784. case PLUTO_MCKINLEY_PORT:
  1785. root = proc_mckinley_root;
  1786. break;
  1787. case ASTRO_RUNWAY_PORT:
  1788. case IKE_MERCED_PORT:
  1789. default:
  1790. root = proc_runway_root;
  1791. break;
  1792. }
  1793. info_entry = create_proc_entry("sba_iommu", 0, root);
  1794. bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root);
  1795. if (info_entry)
  1796. info_entry->proc_fops = &sba_proc_fops;
  1797. if (bitmap_entry)
  1798. bitmap_entry->proc_fops = &sba_proc_bitmap_fops;
  1799. #endif
  1800. parisc_vmerge_boundary = IOVP_SIZE;
  1801. parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
  1802. parisc_has_iommu();
  1803. return 0;
  1804. }
  1805. /*
  1806. ** One time initialization to let the world know the SBA was found.
  1807. ** This is the only routine which is NOT static.
  1808. ** Must be called exactly once before pci_init().
  1809. */
  1810. void __init sba_init(void)
  1811. {
  1812. register_parisc_driver(&sba_driver);
  1813. }
  1814. /**
  1815. * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
  1816. * @dev: The parisc device.
  1817. *
  1818. * Returns the appropriate IOMMU data for the given parisc PCI controller.
  1819. * This is cached and used later for PCI DMA Mapping.
  1820. */
  1821. void * sba_get_iommu(struct parisc_device *pci_hba)
  1822. {
  1823. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1824. struct sba_device *sba = sba_dev->dev.driver_data;
  1825. char t = sba_dev->id.hw_type;
  1826. int iocnum = (pci_hba->hw_path >> 3); /* rope # */
  1827. WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
  1828. return &(sba->ioc[iocnum]);
  1829. }
  1830. /**
  1831. * sba_directed_lmmio - return first directed LMMIO range routed to rope
  1832. * @pa_dev: The parisc device.
  1833. * @r: resource PCI host controller wants start/end fields assigned.
  1834. *
  1835. * For the given parisc PCI controller, determine if any direct ranges
  1836. * are routed down the corresponding rope.
  1837. */
  1838. void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
  1839. {
  1840. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1841. struct sba_device *sba = sba_dev->dev.driver_data;
  1842. char t = sba_dev->id.hw_type;
  1843. int i;
  1844. int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
  1845. BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
  1846. r->start = r->end = 0;
  1847. /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
  1848. for (i=0; i<4; i++) {
  1849. int base, size;
  1850. void __iomem *reg = sba->sba_hpa + i*0x18;
  1851. base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
  1852. if ((base & 1) == 0)
  1853. continue; /* not enabled */
  1854. size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
  1855. if ((size & (ROPES_PER_IOC-1)) != rope)
  1856. continue; /* directed down different rope */
  1857. r->start = (base & ~1UL) | PCI_F_EXTEND;
  1858. size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
  1859. r->end = r->start + size;
  1860. }
  1861. }
  1862. /**
  1863. * sba_distributed_lmmio - return portion of distributed LMMIO range
  1864. * @pa_dev: The parisc device.
  1865. * @r: resource PCI host controller wants start/end fields assigned.
  1866. *
  1867. * For the given parisc PCI controller, return portion of distributed LMMIO
  1868. * range. The distributed LMMIO is always present and it's just a question
  1869. * of the base address and size of the range.
  1870. */
  1871. void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
  1872. {
  1873. struct parisc_device *sba_dev = parisc_parent(pci_hba);
  1874. struct sba_device *sba = sba_dev->dev.driver_data;
  1875. char t = sba_dev->id.hw_type;
  1876. int base, size;
  1877. int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
  1878. BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
  1879. r->start = r->end = 0;
  1880. base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
  1881. if ((base & 1) == 0) {
  1882. BUG(); /* Gah! Distr Range wasn't enabled! */
  1883. return;
  1884. }
  1885. r->start = (base & ~1UL) | PCI_F_EXTEND;
  1886. size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
  1887. r->start += rope * (size + 1); /* adjust base for this rope */
  1888. r->end = r->start + size;
  1889. }