irq.c 20 KB

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  1. /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
  2. * irq.c: UltraSparc IRQ handling/init/registry.
  3. *
  4. * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
  5. * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
  6. * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
  7. */
  8. #include <linux/config.h>
  9. #include <linux/module.h>
  10. #include <linux/sched.h>
  11. #include <linux/ptrace.h>
  12. #include <linux/errno.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/signal.h>
  15. #include <linux/mm.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/slab.h>
  18. #include <linux/random.h>
  19. #include <linux/init.h>
  20. #include <linux/delay.h>
  21. #include <linux/proc_fs.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/bootmem.h>
  24. #include <linux/irq.h>
  25. #include <asm/ptrace.h>
  26. #include <asm/processor.h>
  27. #include <asm/atomic.h>
  28. #include <asm/system.h>
  29. #include <asm/irq.h>
  30. #include <asm/io.h>
  31. #include <asm/sbus.h>
  32. #include <asm/iommu.h>
  33. #include <asm/upa.h>
  34. #include <asm/oplib.h>
  35. #include <asm/prom.h>
  36. #include <asm/timer.h>
  37. #include <asm/smp.h>
  38. #include <asm/starfire.h>
  39. #include <asm/uaccess.h>
  40. #include <asm/cache.h>
  41. #include <asm/cpudata.h>
  42. #include <asm/auxio.h>
  43. #include <asm/head.h>
  44. /* UPA nodes send interrupt packet to UltraSparc with first data reg
  45. * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  46. * delivered. We must translate this into a non-vector IRQ so we can
  47. * set the softint on this cpu.
  48. *
  49. * To make processing these packets efficient and race free we use
  50. * an array of irq buckets below. The interrupt vector handler in
  51. * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  52. * The IVEC handler does not need to act atomically, the PIL dispatch
  53. * code uses CAS to get an atomic snapshot of the list and clear it
  54. * at the same time.
  55. *
  56. * If you make changes to ino_bucket, please update hand coded assembler
  57. * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
  58. */
  59. struct ino_bucket {
  60. /* Next handler in per-CPU IRQ worklist. We know that
  61. * bucket pointers have the high 32-bits clear, so to
  62. * save space we only store the bits we need.
  63. */
  64. /*0x00*/unsigned int irq_chain;
  65. /* Virtual interrupt number assigned to this INO. */
  66. /*0x04*/unsigned int virt_irq;
  67. };
  68. #define NUM_IVECS (IMAP_INR + 1)
  69. struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  70. #define __irq_ino(irq) \
  71. (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
  72. #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
  73. #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
  74. /* This has to be in the main kernel image, it cannot be
  75. * turned into per-cpu data. The reason is that the main
  76. * kernel image is locked into the TLB and this structure
  77. * is accessed from the vectored interrupt trap handler. If
  78. * access to this structure takes a TLB miss it could cause
  79. * the 5-level sparc v9 trap stack to overflow.
  80. */
  81. #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
  82. static unsigned int virt_to_real_irq_table[NR_IRQS];
  83. static unsigned char virt_irq_cur = 1;
  84. static unsigned char virt_irq_alloc(unsigned int real_irq)
  85. {
  86. unsigned char ent;
  87. BUILD_BUG_ON(NR_IRQS >= 256);
  88. ent = virt_irq_cur;
  89. if (ent >= NR_IRQS) {
  90. printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
  91. return 0;
  92. }
  93. virt_irq_cur = ent + 1;
  94. virt_to_real_irq_table[ent] = real_irq;
  95. return ent;
  96. }
  97. #if 0 /* Currently unused. */
  98. static unsigned char real_to_virt_irq(unsigned int real_irq)
  99. {
  100. struct ino_bucket *bucket = __bucket(real_irq);
  101. return bucket->virt_irq;
  102. }
  103. #endif
  104. static unsigned int virt_to_real_irq(unsigned char virt_irq)
  105. {
  106. return virt_to_real_irq_table[virt_irq];
  107. }
  108. /*
  109. * /proc/interrupts printing:
  110. */
  111. int show_interrupts(struct seq_file *p, void *v)
  112. {
  113. int i = *(loff_t *) v, j;
  114. struct irqaction * action;
  115. unsigned long flags;
  116. if (i == 0) {
  117. seq_printf(p, " ");
  118. for_each_online_cpu(j)
  119. seq_printf(p, "CPU%d ",j);
  120. seq_putc(p, '\n');
  121. }
  122. if (i < NR_IRQS) {
  123. spin_lock_irqsave(&irq_desc[i].lock, flags);
  124. action = irq_desc[i].action;
  125. if (!action)
  126. goto skip;
  127. seq_printf(p, "%3d: ",i);
  128. #ifndef CONFIG_SMP
  129. seq_printf(p, "%10u ", kstat_irqs(i));
  130. #else
  131. for_each_online_cpu(j)
  132. seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
  133. #endif
  134. seq_printf(p, " %9s", irq_desc[i].handler->typename);
  135. seq_printf(p, " %s", action->name);
  136. for (action=action->next; action; action = action->next)
  137. seq_printf(p, ", %s", action->name);
  138. seq_putc(p, '\n');
  139. skip:
  140. spin_unlock_irqrestore(&irq_desc[i].lock, flags);
  141. }
  142. return 0;
  143. }
  144. extern unsigned long real_hard_smp_processor_id(void);
  145. static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
  146. {
  147. unsigned int tid;
  148. if (this_is_starfire) {
  149. tid = starfire_translate(imap, cpuid);
  150. tid <<= IMAP_TID_SHIFT;
  151. tid &= IMAP_TID_UPA;
  152. } else {
  153. if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  154. unsigned long ver;
  155. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  156. if ((ver >> 32UL) == __JALAPENO_ID ||
  157. (ver >> 32UL) == __SERRANO_ID) {
  158. tid = cpuid << IMAP_TID_SHIFT;
  159. tid &= IMAP_TID_JBUS;
  160. } else {
  161. unsigned int a = cpuid & 0x1f;
  162. unsigned int n = (cpuid >> 5) & 0x1f;
  163. tid = ((a << IMAP_AID_SHIFT) |
  164. (n << IMAP_NID_SHIFT));
  165. tid &= (IMAP_AID_SAFARI |
  166. IMAP_NID_SAFARI);;
  167. }
  168. } else {
  169. tid = cpuid << IMAP_TID_SHIFT;
  170. tid &= IMAP_TID_UPA;
  171. }
  172. }
  173. return tid;
  174. }
  175. struct irq_handler_data {
  176. unsigned long iclr;
  177. unsigned long imap;
  178. void (*pre_handler)(unsigned int, void *, void *);
  179. void *pre_handler_arg1;
  180. void *pre_handler_arg2;
  181. };
  182. static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
  183. {
  184. unsigned int real_irq = virt_to_real_irq(virt_irq);
  185. struct ino_bucket *bucket = NULL;
  186. if (likely(real_irq))
  187. bucket = __bucket(real_irq);
  188. return bucket;
  189. }
  190. #ifdef CONFIG_SMP
  191. static int irq_choose_cpu(unsigned int virt_irq)
  192. {
  193. cpumask_t mask = irq_affinity[virt_irq];
  194. int cpuid;
  195. if (cpus_equal(mask, CPU_MASK_ALL)) {
  196. static int irq_rover;
  197. static DEFINE_SPINLOCK(irq_rover_lock);
  198. unsigned long flags;
  199. /* Round-robin distribution... */
  200. do_round_robin:
  201. spin_lock_irqsave(&irq_rover_lock, flags);
  202. while (!cpu_online(irq_rover)) {
  203. if (++irq_rover >= NR_CPUS)
  204. irq_rover = 0;
  205. }
  206. cpuid = irq_rover;
  207. do {
  208. if (++irq_rover >= NR_CPUS)
  209. irq_rover = 0;
  210. } while (!cpu_online(irq_rover));
  211. spin_unlock_irqrestore(&irq_rover_lock, flags);
  212. } else {
  213. cpumask_t tmp;
  214. cpus_and(tmp, cpu_online_map, mask);
  215. if (cpus_empty(tmp))
  216. goto do_round_robin;
  217. cpuid = first_cpu(tmp);
  218. }
  219. return cpuid;
  220. }
  221. #else
  222. static int irq_choose_cpu(unsigned int virt_irq)
  223. {
  224. return real_hard_smp_processor_id();
  225. }
  226. #endif
  227. static void sun4u_irq_enable(unsigned int virt_irq)
  228. {
  229. irq_desc_t *desc = irq_desc + virt_irq;
  230. struct irq_handler_data *data = desc->handler_data;
  231. if (likely(data)) {
  232. unsigned long cpuid, imap;
  233. unsigned int tid;
  234. cpuid = irq_choose_cpu(virt_irq);
  235. imap = data->imap;
  236. tid = sun4u_compute_tid(imap, cpuid);
  237. upa_writel(tid | IMAP_VALID, imap);
  238. }
  239. }
  240. static void sun4u_irq_disable(unsigned int virt_irq)
  241. {
  242. irq_desc_t *desc = irq_desc + virt_irq;
  243. struct irq_handler_data *data = desc->handler_data;
  244. if (likely(data)) {
  245. unsigned long imap = data->imap;
  246. u32 tmp = upa_readl(imap);
  247. tmp &= ~IMAP_VALID;
  248. upa_writel(tmp, imap);
  249. }
  250. }
  251. static void sun4u_irq_end(unsigned int virt_irq)
  252. {
  253. irq_desc_t *desc = irq_desc + virt_irq;
  254. struct irq_handler_data *data = desc->handler_data;
  255. if (likely(data))
  256. upa_writel(ICLR_IDLE, data->iclr);
  257. }
  258. static void sun4v_irq_enable(unsigned int virt_irq)
  259. {
  260. struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
  261. unsigned int ino = bucket - &ivector_table[0];
  262. if (likely(bucket)) {
  263. unsigned long cpuid;
  264. int err;
  265. cpuid = irq_choose_cpu(virt_irq);
  266. err = sun4v_intr_settarget(ino, cpuid);
  267. if (err != HV_EOK)
  268. printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
  269. ino, cpuid, err);
  270. err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
  271. if (err != HV_EOK)
  272. printk("sun4v_intr_setenabled(%x): err(%d)\n",
  273. ino, err);
  274. }
  275. }
  276. static void sun4v_irq_disable(unsigned int virt_irq)
  277. {
  278. struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
  279. unsigned int ino = bucket - &ivector_table[0];
  280. if (likely(bucket)) {
  281. int err;
  282. err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
  283. if (err != HV_EOK)
  284. printk("sun4v_intr_setenabled(%x): "
  285. "err(%d)\n", ino, err);
  286. }
  287. }
  288. static void sun4v_irq_end(unsigned int virt_irq)
  289. {
  290. struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
  291. unsigned int ino = bucket - &ivector_table[0];
  292. if (likely(bucket)) {
  293. int err;
  294. err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
  295. if (err != HV_EOK)
  296. printk("sun4v_intr_setstate(%x): "
  297. "err(%d)\n", ino, err);
  298. }
  299. }
  300. static void run_pre_handler(unsigned int virt_irq)
  301. {
  302. struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
  303. irq_desc_t *desc = irq_desc + virt_irq;
  304. struct irq_handler_data *data = desc->handler_data;
  305. if (likely(data->pre_handler)) {
  306. data->pre_handler(__irq_ino(__irq(bucket)),
  307. data->pre_handler_arg1,
  308. data->pre_handler_arg2);
  309. }
  310. }
  311. static struct hw_interrupt_type sun4u_irq = {
  312. .typename = "sun4u",
  313. .enable = sun4u_irq_enable,
  314. .disable = sun4u_irq_disable,
  315. .end = sun4u_irq_end,
  316. };
  317. static struct hw_interrupt_type sun4u_irq_ack = {
  318. .typename = "sun4u+ack",
  319. .enable = sun4u_irq_enable,
  320. .disable = sun4u_irq_disable,
  321. .ack = run_pre_handler,
  322. .end = sun4u_irq_end,
  323. };
  324. static struct hw_interrupt_type sun4v_irq = {
  325. .typename = "sun4v",
  326. .enable = sun4v_irq_enable,
  327. .disable = sun4v_irq_disable,
  328. .end = sun4v_irq_end,
  329. };
  330. static struct hw_interrupt_type sun4v_irq_ack = {
  331. .typename = "sun4v+ack",
  332. .enable = sun4v_irq_enable,
  333. .disable = sun4v_irq_disable,
  334. .ack = run_pre_handler,
  335. .end = sun4v_irq_end,
  336. };
  337. void irq_install_pre_handler(int virt_irq,
  338. void (*func)(unsigned int, void *, void *),
  339. void *arg1, void *arg2)
  340. {
  341. irq_desc_t *desc = irq_desc + virt_irq;
  342. struct irq_handler_data *data = desc->handler_data;
  343. data->pre_handler = func;
  344. data->pre_handler_arg1 = arg1;
  345. data->pre_handler_arg2 = arg2;
  346. desc->handler = (desc->handler == &sun4u_irq ?
  347. &sun4u_irq_ack : &sun4v_irq_ack);
  348. }
  349. unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
  350. {
  351. struct ino_bucket *bucket;
  352. struct irq_handler_data *data;
  353. irq_desc_t *desc;
  354. int ino;
  355. BUG_ON(tlb_type == hypervisor);
  356. ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
  357. bucket = &ivector_table[ino];
  358. if (!bucket->virt_irq) {
  359. bucket->virt_irq = virt_irq_alloc(__irq(bucket));
  360. irq_desc[bucket->virt_irq].handler = &sun4u_irq;
  361. }
  362. desc = irq_desc + bucket->virt_irq;
  363. if (unlikely(desc->handler_data))
  364. goto out;
  365. data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
  366. if (unlikely(!data)) {
  367. prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
  368. prom_halt();
  369. }
  370. desc->handler_data = data;
  371. data->imap = imap;
  372. data->iclr = iclr;
  373. out:
  374. return bucket->virt_irq;
  375. }
  376. unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
  377. {
  378. struct ino_bucket *bucket;
  379. struct irq_handler_data *data;
  380. unsigned long sysino;
  381. irq_desc_t *desc;
  382. BUG_ON(tlb_type != hypervisor);
  383. sysino = sun4v_devino_to_sysino(devhandle, devino);
  384. bucket = &ivector_table[sysino];
  385. if (!bucket->virt_irq) {
  386. bucket->virt_irq = virt_irq_alloc(__irq(bucket));
  387. irq_desc[bucket->virt_irq].handler = &sun4v_irq;
  388. }
  389. desc = irq_desc + bucket->virt_irq;
  390. if (unlikely(desc->handler_data))
  391. goto out;
  392. data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
  393. if (unlikely(!data)) {
  394. prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
  395. prom_halt();
  396. }
  397. desc->handler_data = data;
  398. /* Catch accidental accesses to these things. IMAP/ICLR handling
  399. * is done by hypervisor calls on sun4v platforms, not by direct
  400. * register accesses.
  401. */
  402. data->imap = ~0UL;
  403. data->iclr = ~0UL;
  404. out:
  405. return bucket->virt_irq;
  406. }
  407. void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq)
  408. {
  409. struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
  410. unsigned long pstate;
  411. unsigned int *ent;
  412. __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
  413. __asm__ __volatile__("wrpr %0, %1, %%pstate"
  414. : : "r" (pstate), "i" (PSTATE_IE));
  415. ent = irq_work(smp_processor_id());
  416. bucket->irq_chain = *ent;
  417. *ent = __irq(bucket);
  418. set_softint(1 << PIL_DEVICE_IRQ);
  419. __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
  420. }
  421. void ack_bad_irq(unsigned int virt_irq)
  422. {
  423. struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
  424. unsigned int ino = 0xdeadbeef;
  425. if (bucket)
  426. ino = bucket - &ivector_table[0];
  427. printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
  428. ino, virt_irq);
  429. }
  430. #ifndef CONFIG_SMP
  431. extern irqreturn_t timer_interrupt(int, void *, struct pt_regs *);
  432. void timer_irq(int irq, struct pt_regs *regs)
  433. {
  434. unsigned long clr_mask = 1 << irq;
  435. unsigned long tick_mask = tick_ops->softint_mask;
  436. if (get_softint() & tick_mask) {
  437. irq = 0;
  438. clr_mask = tick_mask;
  439. }
  440. clear_softint(clr_mask);
  441. irq_enter();
  442. kstat_this_cpu.irqs[0]++;
  443. timer_interrupt(irq, NULL, regs);
  444. irq_exit();
  445. }
  446. #endif
  447. void handler_irq(int irq, struct pt_regs *regs)
  448. {
  449. struct ino_bucket *bucket;
  450. clear_softint(1 << irq);
  451. irq_enter();
  452. /* Sliiiick... */
  453. bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
  454. while (bucket) {
  455. struct ino_bucket *next = __bucket(bucket->irq_chain);
  456. bucket->irq_chain = 0;
  457. __do_IRQ(bucket->virt_irq, regs);
  458. bucket = next;
  459. }
  460. irq_exit();
  461. }
  462. #ifdef CONFIG_BLK_DEV_FD
  463. extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);
  464. /* XXX No easy way to include asm/floppy.h XXX */
  465. extern unsigned char *pdma_vaddr;
  466. extern unsigned long pdma_size;
  467. extern volatile int doing_pdma;
  468. extern unsigned long fdc_status;
  469. irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
  470. {
  471. if (likely(doing_pdma)) {
  472. void __iomem *stat = (void __iomem *) fdc_status;
  473. unsigned char *vaddr = pdma_vaddr;
  474. unsigned long size = pdma_size;
  475. u8 val;
  476. while (size) {
  477. val = readb(stat);
  478. if (unlikely(!(val & 0x80))) {
  479. pdma_vaddr = vaddr;
  480. pdma_size = size;
  481. return IRQ_HANDLED;
  482. }
  483. if (unlikely(!(val & 0x20))) {
  484. pdma_vaddr = vaddr;
  485. pdma_size = size;
  486. doing_pdma = 0;
  487. goto main_interrupt;
  488. }
  489. if (val & 0x40) {
  490. /* read */
  491. *vaddr++ = readb(stat + 1);
  492. } else {
  493. unsigned char data = *vaddr++;
  494. /* write */
  495. writeb(data, stat + 1);
  496. }
  497. size--;
  498. }
  499. pdma_vaddr = vaddr;
  500. pdma_size = size;
  501. /* Send Terminal Count pulse to floppy controller. */
  502. val = readb(auxio_register);
  503. val |= AUXIO_AUX1_FTCNT;
  504. writeb(val, auxio_register);
  505. val &= ~AUXIO_AUX1_FTCNT;
  506. writeb(val, auxio_register);
  507. doing_pdma = 0;
  508. }
  509. main_interrupt:
  510. return floppy_interrupt(irq, dev_cookie, regs);
  511. }
  512. EXPORT_SYMBOL(sparc_floppy_irq);
  513. #endif
  514. struct sun5_timer {
  515. u64 count0;
  516. u64 limit0;
  517. u64 count1;
  518. u64 limit1;
  519. };
  520. static struct sun5_timer *prom_timers;
  521. static u64 prom_limit0, prom_limit1;
  522. static void map_prom_timers(void)
  523. {
  524. struct device_node *dp;
  525. unsigned int *addr;
  526. /* PROM timer node hangs out in the top level of device siblings... */
  527. dp = of_find_node_by_path("/");
  528. dp = dp->child;
  529. while (dp) {
  530. if (!strcmp(dp->name, "counter-timer"))
  531. break;
  532. dp = dp->sibling;
  533. }
  534. /* Assume if node is not present, PROM uses different tick mechanism
  535. * which we should not care about.
  536. */
  537. if (!dp) {
  538. prom_timers = (struct sun5_timer *) 0;
  539. return;
  540. }
  541. /* If PROM is really using this, it must be mapped by him. */
  542. addr = of_get_property(dp, "address", NULL);
  543. if (!addr) {
  544. prom_printf("PROM does not have timer mapped, trying to continue.\n");
  545. prom_timers = (struct sun5_timer *) 0;
  546. return;
  547. }
  548. prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
  549. }
  550. static void kill_prom_timer(void)
  551. {
  552. if (!prom_timers)
  553. return;
  554. /* Save them away for later. */
  555. prom_limit0 = prom_timers->limit0;
  556. prom_limit1 = prom_timers->limit1;
  557. /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
  558. * We turn both off here just to be paranoid.
  559. */
  560. prom_timers->limit0 = 0;
  561. prom_timers->limit1 = 0;
  562. /* Wheee, eat the interrupt packet too... */
  563. __asm__ __volatile__(
  564. " mov 0x40, %%g2\n"
  565. " ldxa [%%g0] %0, %%g1\n"
  566. " ldxa [%%g2] %1, %%g1\n"
  567. " stxa %%g0, [%%g0] %0\n"
  568. " membar #Sync\n"
  569. : /* no outputs */
  570. : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
  571. : "g1", "g2");
  572. }
  573. void init_irqwork_curcpu(void)
  574. {
  575. int cpu = hard_smp_processor_id();
  576. trap_block[cpu].irq_worklist = 0;
  577. }
  578. static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
  579. {
  580. unsigned long num_entries = 128;
  581. unsigned long status;
  582. status = sun4v_cpu_qconf(type, paddr, num_entries);
  583. if (status != HV_EOK) {
  584. prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
  585. "err %lu\n", type, paddr, num_entries, status);
  586. prom_halt();
  587. }
  588. }
  589. static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
  590. {
  591. struct trap_per_cpu *tb = &trap_block[this_cpu];
  592. register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
  593. register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
  594. register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
  595. register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
  596. }
  597. static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
  598. {
  599. void *page;
  600. if (use_bootmem)
  601. page = alloc_bootmem_low_pages(PAGE_SIZE);
  602. else
  603. page = (void *) get_zeroed_page(GFP_ATOMIC);
  604. if (!page) {
  605. prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
  606. prom_halt();
  607. }
  608. *pa_ptr = __pa(page);
  609. }
  610. static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
  611. {
  612. void *page;
  613. if (use_bootmem)
  614. page = alloc_bootmem_low_pages(PAGE_SIZE);
  615. else
  616. page = (void *) get_zeroed_page(GFP_ATOMIC);
  617. if (!page) {
  618. prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
  619. prom_halt();
  620. }
  621. *pa_ptr = __pa(page);
  622. }
  623. static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
  624. {
  625. #ifdef CONFIG_SMP
  626. void *page;
  627. BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
  628. if (use_bootmem)
  629. page = alloc_bootmem_low_pages(PAGE_SIZE);
  630. else
  631. page = (void *) get_zeroed_page(GFP_ATOMIC);
  632. if (!page) {
  633. prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
  634. prom_halt();
  635. }
  636. tb->cpu_mondo_block_pa = __pa(page);
  637. tb->cpu_list_pa = __pa(page + 64);
  638. #endif
  639. }
  640. /* Allocate and register the mondo and error queues for this cpu. */
  641. void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
  642. {
  643. struct trap_per_cpu *tb = &trap_block[cpu];
  644. if (alloc) {
  645. alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
  646. alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
  647. alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
  648. alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
  649. alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
  650. alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
  651. init_cpu_send_mondo_info(tb, use_bootmem);
  652. }
  653. if (load) {
  654. if (cpu != hard_smp_processor_id()) {
  655. prom_printf("SUN4V: init mondo on cpu %d not %d\n",
  656. cpu, hard_smp_processor_id());
  657. prom_halt();
  658. }
  659. sun4v_register_mondo_queues(cpu);
  660. }
  661. }
  662. static struct irqaction timer_irq_action = {
  663. .name = "timer",
  664. };
  665. /* Only invoked on boot processor. */
  666. void __init init_IRQ(void)
  667. {
  668. map_prom_timers();
  669. kill_prom_timer();
  670. memset(&ivector_table[0], 0, sizeof(ivector_table));
  671. if (tlb_type == hypervisor)
  672. sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
  673. /* We need to clear any IRQ's pending in the soft interrupt
  674. * registers, a spurious one could be left around from the
  675. * PROM timer which we just disabled.
  676. */
  677. clear_softint(get_softint());
  678. /* Now that ivector table is initialized, it is safe
  679. * to receive IRQ vector traps. We will normally take
  680. * one or two right now, in case some device PROM used
  681. * to boot us wants to speak to us. We just ignore them.
  682. */
  683. __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
  684. "or %%g1, %0, %%g1\n\t"
  685. "wrpr %%g1, 0x0, %%pstate"
  686. : /* No outputs */
  687. : "i" (PSTATE_IE)
  688. : "g1");
  689. irq_desc[0].action = &timer_irq_action;
  690. }