radeon_fence.c 18 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  43. {
  44. if (rdev->wb.enabled) {
  45. *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
  46. } else {
  47. WREG32(rdev->fence_drv[ring].scratch_reg, seq);
  48. }
  49. }
  50. static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  51. {
  52. u32 seq = 0;
  53. if (rdev->wb.enabled) {
  54. seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
  55. } else {
  56. seq = RREG32(rdev->fence_drv[ring].scratch_reg);
  57. }
  58. return seq;
  59. }
  60. int radeon_fence_emit(struct radeon_device *rdev,
  61. struct radeon_fence **fence,
  62. int ring)
  63. {
  64. /* we are protected by the ring emission mutex */
  65. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  66. if ((*fence) == NULL) {
  67. return -ENOMEM;
  68. }
  69. kref_init(&((*fence)->kref));
  70. (*fence)->rdev = rdev;
  71. (*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
  72. (*fence)->ring = ring;
  73. radeon_fence_ring_emit(rdev, ring, *fence);
  74. trace_radeon_fence_emit(rdev->ddev, (*fence)->seq);
  75. return 0;
  76. }
  77. void radeon_fence_process(struct radeon_device *rdev, int ring)
  78. {
  79. uint64_t seq, last_seq;
  80. unsigned count_loop = 0;
  81. bool wake = false;
  82. /* Note there is a scenario here for an infinite loop but it's
  83. * very unlikely to happen. For it to happen, the current polling
  84. * process need to be interrupted by another process and another
  85. * process needs to update the last_seq btw the atomic read and
  86. * xchg of the current process.
  87. *
  88. * More over for this to go in infinite loop there need to be
  89. * continuously new fence signaled ie radeon_fence_read needs
  90. * to return a different value each time for both the currently
  91. * polling process and the other process that xchg the last_seq
  92. * btw atomic read and xchg of the current process. And the
  93. * value the other process set as last seq must be higher than
  94. * the seq value we just read. Which means that current process
  95. * need to be interrupted after radeon_fence_read and before
  96. * atomic xchg.
  97. *
  98. * To be even more safe we count the number of time we loop and
  99. * we bail after 10 loop just accepting the fact that we might
  100. * have temporarly set the last_seq not to the true real last
  101. * seq but to an older one.
  102. */
  103. last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
  104. do {
  105. seq = radeon_fence_read(rdev, ring);
  106. seq |= last_seq & 0xffffffff00000000LL;
  107. if (seq < last_seq) {
  108. seq += 0x100000000LL;
  109. }
  110. if (seq == last_seq) {
  111. break;
  112. }
  113. /* If we loop over we don't want to return without
  114. * checking if a fence is signaled as it means that the
  115. * seq we just read is different from the previous on.
  116. */
  117. wake = true;
  118. last_seq = seq;
  119. if ((count_loop++) > 10) {
  120. /* We looped over too many time leave with the
  121. * fact that we might have set an older fence
  122. * seq then the current real last seq as signaled
  123. * by the hw.
  124. */
  125. break;
  126. }
  127. } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
  128. if (wake) {
  129. rdev->fence_drv[ring].last_activity = jiffies;
  130. wake_up_all(&rdev->fence_queue);
  131. }
  132. }
  133. static void radeon_fence_destroy(struct kref *kref)
  134. {
  135. struct radeon_fence *fence;
  136. fence = container_of(kref, struct radeon_fence, kref);
  137. kfree(fence);
  138. }
  139. static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
  140. u64 seq, unsigned ring)
  141. {
  142. if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
  143. return true;
  144. }
  145. /* poll new last sequence at least once */
  146. radeon_fence_process(rdev, ring);
  147. if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
  148. return true;
  149. }
  150. return false;
  151. }
  152. bool radeon_fence_signaled(struct radeon_fence *fence)
  153. {
  154. if (!fence) {
  155. return true;
  156. }
  157. if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
  158. return true;
  159. }
  160. if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
  161. fence->seq = RADEON_FENCE_SIGNALED_SEQ;
  162. return true;
  163. }
  164. return false;
  165. }
  166. static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
  167. unsigned ring, bool intr, bool lock_ring)
  168. {
  169. unsigned long timeout, last_activity;
  170. uint64_t seq;
  171. unsigned i;
  172. bool signaled;
  173. int r;
  174. while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
  175. if (!rdev->ring[ring].ready) {
  176. return -EBUSY;
  177. }
  178. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  179. if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
  180. /* the normal case, timeout is somewhere before last_activity */
  181. timeout = rdev->fence_drv[ring].last_activity - timeout;
  182. } else {
  183. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  184. * anyway we will just wait for the minimum amount and then check for a lockup
  185. */
  186. timeout = 1;
  187. }
  188. seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
  189. /* Save current last activity valuee, used to check for GPU lockups */
  190. last_activity = rdev->fence_drv[ring].last_activity;
  191. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  192. radeon_irq_kms_sw_irq_get(rdev, ring);
  193. if (intr) {
  194. r = wait_event_interruptible_timeout(rdev->fence_queue,
  195. (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
  196. timeout);
  197. } else {
  198. r = wait_event_timeout(rdev->fence_queue,
  199. (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
  200. timeout);
  201. }
  202. radeon_irq_kms_sw_irq_put(rdev, ring);
  203. if (unlikely(r < 0)) {
  204. return r;
  205. }
  206. trace_radeon_fence_wait_end(rdev->ddev, seq);
  207. if (unlikely(!signaled)) {
  208. /* we were interrupted for some reason and fence
  209. * isn't signaled yet, resume waiting */
  210. if (r) {
  211. continue;
  212. }
  213. /* check if sequence value has changed since last_activity */
  214. if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
  215. continue;
  216. }
  217. if (lock_ring) {
  218. mutex_lock(&rdev->ring_lock);
  219. }
  220. /* test if somebody else has already decided that this is a lockup */
  221. if (last_activity != rdev->fence_drv[ring].last_activity) {
  222. if (lock_ring) {
  223. mutex_unlock(&rdev->ring_lock);
  224. }
  225. continue;
  226. }
  227. if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
  228. /* good news we believe it's a lockup */
  229. dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx last fence id 0x%016llx)\n",
  230. target_seq, seq);
  231. /* change last activity so nobody else think there is a lockup */
  232. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  233. rdev->fence_drv[i].last_activity = jiffies;
  234. }
  235. /* mark the ring as not ready any more */
  236. rdev->ring[ring].ready = false;
  237. if (lock_ring) {
  238. mutex_unlock(&rdev->ring_lock);
  239. }
  240. return -EDEADLK;
  241. }
  242. if (lock_ring) {
  243. mutex_unlock(&rdev->ring_lock);
  244. }
  245. }
  246. }
  247. return 0;
  248. }
  249. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  250. {
  251. int r;
  252. if (fence == NULL) {
  253. WARN(1, "Querying an invalid fence : %p !\n", fence);
  254. return -EINVAL;
  255. }
  256. r = radeon_fence_wait_seq(fence->rdev, fence->seq,
  257. fence->ring, intr, true);
  258. if (r) {
  259. return r;
  260. }
  261. fence->seq = RADEON_FENCE_SIGNALED_SEQ;
  262. return 0;
  263. }
  264. bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
  265. {
  266. unsigned i;
  267. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  268. if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
  269. return true;
  270. }
  271. }
  272. return false;
  273. }
  274. static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
  275. u64 *target_seq, bool intr)
  276. {
  277. unsigned long timeout, last_activity, tmp;
  278. unsigned i, ring = RADEON_NUM_RINGS;
  279. bool signaled;
  280. int r;
  281. for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
  282. if (!target_seq[i]) {
  283. continue;
  284. }
  285. /* use the most recent one as indicator */
  286. if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
  287. last_activity = rdev->fence_drv[i].last_activity;
  288. }
  289. /* For lockup detection just pick the lowest ring we are
  290. * actively waiting for
  291. */
  292. if (i < ring) {
  293. ring = i;
  294. }
  295. }
  296. /* nothing to wait for ? */
  297. if (ring == RADEON_NUM_RINGS) {
  298. return 0;
  299. }
  300. while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
  301. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  302. if (time_after(last_activity, timeout)) {
  303. /* the normal case, timeout is somewhere before last_activity */
  304. timeout = last_activity - timeout;
  305. } else {
  306. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  307. * anyway we will just wait for the minimum amount and then check for a lockup
  308. */
  309. timeout = 1;
  310. }
  311. trace_radeon_fence_wait_begin(rdev->ddev, target_seq[ring]);
  312. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  313. if (target_seq[i]) {
  314. radeon_irq_kms_sw_irq_get(rdev, i);
  315. }
  316. }
  317. if (intr) {
  318. r = wait_event_interruptible_timeout(rdev->fence_queue,
  319. (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
  320. timeout);
  321. } else {
  322. r = wait_event_timeout(rdev->fence_queue,
  323. (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
  324. timeout);
  325. }
  326. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  327. if (target_seq[i]) {
  328. radeon_irq_kms_sw_irq_put(rdev, i);
  329. }
  330. }
  331. if (unlikely(r < 0)) {
  332. return r;
  333. }
  334. trace_radeon_fence_wait_end(rdev->ddev, target_seq[ring]);
  335. if (unlikely(!signaled)) {
  336. /* we were interrupted for some reason and fence
  337. * isn't signaled yet, resume waiting */
  338. if (r) {
  339. continue;
  340. }
  341. mutex_lock(&rdev->ring_lock);
  342. for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
  343. if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
  344. tmp = rdev->fence_drv[i].last_activity;
  345. }
  346. }
  347. /* test if somebody else has already decided that this is a lockup */
  348. if (last_activity != tmp) {
  349. last_activity = tmp;
  350. mutex_unlock(&rdev->ring_lock);
  351. continue;
  352. }
  353. if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
  354. /* good news we believe it's a lockup */
  355. dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx)\n",
  356. target_seq[ring]);
  357. /* change last activity so nobody else think there is a lockup */
  358. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  359. rdev->fence_drv[i].last_activity = jiffies;
  360. }
  361. /* mark the ring as not ready any more */
  362. rdev->ring[ring].ready = false;
  363. mutex_unlock(&rdev->ring_lock);
  364. return -EDEADLK;
  365. }
  366. mutex_unlock(&rdev->ring_lock);
  367. }
  368. }
  369. return 0;
  370. }
  371. int radeon_fence_wait_any(struct radeon_device *rdev,
  372. struct radeon_fence **fences,
  373. bool intr)
  374. {
  375. uint64_t seq[RADEON_NUM_RINGS];
  376. unsigned i;
  377. int r;
  378. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  379. seq[i] = 0;
  380. if (!fences[i]) {
  381. continue;
  382. }
  383. if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
  384. /* something was allready signaled */
  385. return 0;
  386. }
  387. seq[i] = fences[i]->seq;
  388. }
  389. r = radeon_fence_wait_any_seq(rdev, seq, intr);
  390. if (r) {
  391. return r;
  392. }
  393. return 0;
  394. }
  395. int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
  396. {
  397. uint64_t seq;
  398. /* We are not protected by ring lock when reading current seq but
  399. * it's ok as worst case is we return to early while we could have
  400. * wait.
  401. */
  402. seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
  403. if (seq >= rdev->fence_drv[ring].sync_seq[ring]) {
  404. /* nothing to wait for, last_seq is
  405. already the last emited fence */
  406. return -ENOENT;
  407. }
  408. return radeon_fence_wait_seq(rdev, seq, ring, false, false);
  409. }
  410. int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
  411. {
  412. /* We are not protected by ring lock when reading current seq
  413. * but it's ok as wait empty is call from place where no more
  414. * activity can be scheduled so there won't be concurrent access
  415. * to seq value.
  416. */
  417. return radeon_fence_wait_seq(rdev, rdev->fence_drv[ring].sync_seq[ring],
  418. ring, false, false);
  419. }
  420. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  421. {
  422. kref_get(&fence->kref);
  423. return fence;
  424. }
  425. void radeon_fence_unref(struct radeon_fence **fence)
  426. {
  427. struct radeon_fence *tmp = *fence;
  428. *fence = NULL;
  429. if (tmp) {
  430. kref_put(&tmp->kref, radeon_fence_destroy);
  431. }
  432. }
  433. unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
  434. {
  435. uint64_t emitted;
  436. /* We are not protected by ring lock when reading the last sequence
  437. * but it's ok to report slightly wrong fence count here.
  438. */
  439. radeon_fence_process(rdev, ring);
  440. emitted = rdev->fence_drv[ring].sync_seq[ring]
  441. - atomic64_read(&rdev->fence_drv[ring].last_seq);
  442. /* to avoid 32bits warp around */
  443. if (emitted > 0x10000000) {
  444. emitted = 0x10000000;
  445. }
  446. return (unsigned)emitted;
  447. }
  448. bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
  449. {
  450. struct radeon_fence_driver *fdrv;
  451. if (!fence) {
  452. return false;
  453. }
  454. if (fence->ring == dst_ring) {
  455. return false;
  456. }
  457. /* we are protected by the ring mutex */
  458. fdrv = &fence->rdev->fence_drv[dst_ring];
  459. if (fence->seq <= fdrv->sync_seq[fence->ring]) {
  460. return false;
  461. }
  462. return true;
  463. }
  464. void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
  465. {
  466. struct radeon_fence_driver *dst, *src;
  467. unsigned i;
  468. if (!fence) {
  469. return;
  470. }
  471. if (fence->ring == dst_ring) {
  472. return;
  473. }
  474. /* we are protected by the ring mutex */
  475. src = &fence->rdev->fence_drv[fence->ring];
  476. dst = &fence->rdev->fence_drv[dst_ring];
  477. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  478. if (i == dst_ring) {
  479. continue;
  480. }
  481. dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
  482. }
  483. }
  484. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  485. {
  486. uint64_t index;
  487. int r;
  488. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  489. if (rdev->wb.use_event) {
  490. rdev->fence_drv[ring].scratch_reg = 0;
  491. index = R600_WB_EVENT_OFFSET + ring * 4;
  492. } else {
  493. r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
  494. if (r) {
  495. dev_err(rdev->dev, "fence failed to get scratch register\n");
  496. return r;
  497. }
  498. index = RADEON_WB_SCRATCH_OFFSET +
  499. rdev->fence_drv[ring].scratch_reg -
  500. rdev->scratch.reg_base;
  501. }
  502. rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
  503. rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
  504. radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
  505. rdev->fence_drv[ring].initialized = true;
  506. dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
  507. ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
  508. return 0;
  509. }
  510. static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
  511. {
  512. int i;
  513. rdev->fence_drv[ring].scratch_reg = -1;
  514. rdev->fence_drv[ring].cpu_addr = NULL;
  515. rdev->fence_drv[ring].gpu_addr = 0;
  516. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  517. rdev->fence_drv[ring].sync_seq[i] = 0;
  518. atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
  519. rdev->fence_drv[ring].last_activity = jiffies;
  520. rdev->fence_drv[ring].initialized = false;
  521. }
  522. int radeon_fence_driver_init(struct radeon_device *rdev)
  523. {
  524. int ring;
  525. init_waitqueue_head(&rdev->fence_queue);
  526. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  527. radeon_fence_driver_init_ring(rdev, ring);
  528. }
  529. if (radeon_debugfs_fence_init(rdev)) {
  530. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  531. }
  532. return 0;
  533. }
  534. void radeon_fence_driver_fini(struct radeon_device *rdev)
  535. {
  536. int ring;
  537. mutex_lock(&rdev->ring_lock);
  538. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  539. if (!rdev->fence_drv[ring].initialized)
  540. continue;
  541. radeon_fence_wait_empty_locked(rdev, ring);
  542. wake_up_all(&rdev->fence_queue);
  543. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  544. rdev->fence_drv[ring].initialized = false;
  545. }
  546. mutex_unlock(&rdev->ring_lock);
  547. }
  548. /*
  549. * Fence debugfs
  550. */
  551. #if defined(CONFIG_DEBUG_FS)
  552. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  553. {
  554. struct drm_info_node *node = (struct drm_info_node *)m->private;
  555. struct drm_device *dev = node->minor->dev;
  556. struct radeon_device *rdev = dev->dev_private;
  557. int i, j;
  558. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  559. if (!rdev->fence_drv[i].initialized)
  560. continue;
  561. seq_printf(m, "--- ring %d ---\n", i);
  562. seq_printf(m, "Last signaled fence 0x%016llx\n",
  563. (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
  564. seq_printf(m, "Last emitted 0x%016llx\n",
  565. rdev->fence_drv[i].sync_seq[i]);
  566. for (j = 0; j < RADEON_NUM_RINGS; ++j) {
  567. if (i != j && rdev->fence_drv[j].initialized)
  568. seq_printf(m, "Last sync to ring %d 0x%016llx\n",
  569. j, rdev->fence_drv[i].sync_seq[j]);
  570. }
  571. }
  572. return 0;
  573. }
  574. static struct drm_info_list radeon_debugfs_fence_list[] = {
  575. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  576. };
  577. #endif
  578. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  579. {
  580. #if defined(CONFIG_DEBUG_FS)
  581. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  582. #else
  583. return 0;
  584. #endif
  585. }