rtc-bfin.c 12 KB

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  1. /*
  2. * Blackfin On-Chip Real Time Clock Driver
  3. * Supports BF53[123]/BF53[467]/BF54[2489]
  4. *
  5. * Copyright 2004-2007 Analog Devices Inc.
  6. *
  7. * Enter bugs at http://blackfin.uclinux.org/
  8. *
  9. * Licensed under the GPL-2 or later.
  10. */
  11. /* The biggest issue we deal with in this driver is that register writes are
  12. * synced to the RTC frequency of 1Hz. So if you write to a register and
  13. * attempt to write again before the first write has completed, the new write
  14. * is simply discarded. This can easily be troublesome if userspace disables
  15. * one event (say periodic) and then right after enables an event (say alarm).
  16. * Since all events are maintained in the same interrupt mask register, if
  17. * we wrote to it to disable the first event and then wrote to it again to
  18. * enable the second event, that second event would not be enabled as the
  19. * write would be discarded and things quickly fall apart.
  20. *
  21. * To keep this delay from significantly degrading performance (we, in theory,
  22. * would have to sleep for up to 1 second everytime we wanted to write a
  23. * register), we only check the write pending status before we start to issue
  24. * a new write. We bank on the idea that it doesnt matter when the sync
  25. * happens so long as we don't attempt another write before it does. The only
  26. * time userspace would take this penalty is when they try and do multiple
  27. * operations right after another ... but in this case, they need to take the
  28. * sync penalty, so we should be OK.
  29. *
  30. * Also note that the RTC_ISTAT register does not suffer this penalty; its
  31. * writes to clear status registers complete immediately.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/bcd.h>
  36. #include <linux/rtc.h>
  37. #include <linux/init.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/spinlock.h>
  42. #include <linux/delay.h>
  43. #include <asm/blackfin.h>
  44. #define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
  45. struct bfin_rtc {
  46. struct rtc_device *rtc_dev;
  47. struct rtc_time rtc_alarm;
  48. spinlock_t lock;
  49. };
  50. /* Bit values for the ISTAT / ICTL registers */
  51. #define RTC_ISTAT_WRITE_COMPLETE 0x8000
  52. #define RTC_ISTAT_WRITE_PENDING 0x4000
  53. #define RTC_ISTAT_ALARM_DAY 0x0040
  54. #define RTC_ISTAT_24HR 0x0020
  55. #define RTC_ISTAT_HOUR 0x0010
  56. #define RTC_ISTAT_MIN 0x0008
  57. #define RTC_ISTAT_SEC 0x0004
  58. #define RTC_ISTAT_ALARM 0x0002
  59. #define RTC_ISTAT_STOPWATCH 0x0001
  60. /* Shift values for RTC_STAT register */
  61. #define DAY_BITS_OFF 17
  62. #define HOUR_BITS_OFF 12
  63. #define MIN_BITS_OFF 6
  64. #define SEC_BITS_OFF 0
  65. /* Some helper functions to convert between the common RTC notion of time
  66. * and the internal Blackfin notion that is encoded in 32bits.
  67. */
  68. static inline u32 rtc_time_to_bfin(unsigned long now)
  69. {
  70. u32 sec = (now % 60);
  71. u32 min = (now % (60 * 60)) / 60;
  72. u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
  73. u32 days = (now / (60 * 60 * 24));
  74. return (sec << SEC_BITS_OFF) +
  75. (min << MIN_BITS_OFF) +
  76. (hour << HOUR_BITS_OFF) +
  77. (days << DAY_BITS_OFF);
  78. }
  79. static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
  80. {
  81. return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
  82. (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
  83. (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
  84. (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
  85. }
  86. static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
  87. {
  88. rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
  89. }
  90. /* Wait for the previous write to a RTC register to complete.
  91. * Unfortunately, we can't sleep here as that introduces a race condition when
  92. * turning on interrupt events. Consider this:
  93. * - process sets alarm
  94. * - process enables alarm
  95. * - process sleeps while waiting for rtc write to sync
  96. * - interrupt fires while process is sleeping
  97. * - interrupt acks the event by writing to ISTAT
  98. * - interrupt sets the WRITE PENDING bit
  99. * - interrupt handler finishes
  100. * - process wakes up, sees WRITE PENDING bit set, goes to sleep
  101. * - interrupt fires while process is sleeping
  102. * If anyone can point out the obvious solution here, i'm listening :). This
  103. * shouldn't be an issue on an SMP or preempt system as this function should
  104. * only be called with the rtc lock held.
  105. *
  106. * Other options:
  107. * - disable PREN so the sync happens at 32.768kHZ ... but this changes the
  108. * inc rate for all RTC registers from 1HZ to 32.768kHZ ...
  109. * - use the write complete IRQ
  110. */
  111. static void rtc_bfin_sync_pending(void)
  112. {
  113. while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE)) {
  114. if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
  115. break;
  116. }
  117. bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
  118. }
  119. static void rtc_bfin_reset(struct device *dev)
  120. {
  121. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  122. /* Initialize the RTC. Enable pre-scaler to scale RTC clock
  123. * to 1Hz and clear interrupt/status registers. */
  124. spin_lock_irq(&rtc->lock);
  125. rtc_bfin_sync_pending();
  126. bfin_write_RTC_PREN(0x1);
  127. bfin_write_RTC_ICTL(0);
  128. bfin_write_RTC_SWCNT(0);
  129. bfin_write_RTC_ALARM(0);
  130. bfin_write_RTC_ISTAT(0xFFFF);
  131. spin_unlock_irq(&rtc->lock);
  132. }
  133. static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
  134. {
  135. struct device *dev = dev_id;
  136. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  137. unsigned long events = 0;
  138. u16 rtc_istat;
  139. dev_dbg_stamp(dev);
  140. spin_lock_irq(&rtc->lock);
  141. rtc_istat = bfin_read_RTC_ISTAT();
  142. if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
  143. bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
  144. events |= RTC_AF | RTC_IRQF;
  145. }
  146. if (rtc_istat & RTC_ISTAT_STOPWATCH) {
  147. bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
  148. events |= RTC_PF | RTC_IRQF;
  149. bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
  150. }
  151. if (rtc_istat & RTC_ISTAT_SEC) {
  152. bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
  153. events |= RTC_UF | RTC_IRQF;
  154. }
  155. rtc_update_irq(rtc->rtc_dev, 1, events);
  156. spin_unlock_irq(&rtc->lock);
  157. return IRQ_HANDLED;
  158. }
  159. static int bfin_rtc_open(struct device *dev)
  160. {
  161. int ret;
  162. dev_dbg_stamp(dev);
  163. ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_DISABLED, "rtc-bfin", dev);
  164. if (unlikely(ret)) {
  165. dev_err(dev, "request RTC IRQ failed with %d\n", ret);
  166. return ret;
  167. }
  168. rtc_bfin_reset(dev);
  169. return ret;
  170. }
  171. static void bfin_rtc_release(struct device *dev)
  172. {
  173. dev_dbg_stamp(dev);
  174. rtc_bfin_reset(dev);
  175. free_irq(IRQ_RTC, dev);
  176. }
  177. static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
  178. {
  179. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  180. dev_dbg_stamp(dev);
  181. switch (cmd) {
  182. case RTC_PIE_ON:
  183. dev_dbg_stamp(dev);
  184. spin_lock_irq(&rtc->lock);
  185. rtc_bfin_sync_pending();
  186. bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
  187. bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
  188. bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | RTC_ISTAT_STOPWATCH);
  189. spin_unlock_irq(&rtc->lock);
  190. return 0;
  191. case RTC_PIE_OFF:
  192. dev_dbg_stamp(dev);
  193. spin_lock_irq(&rtc->lock);
  194. rtc_bfin_sync_pending();
  195. bfin_write_RTC_SWCNT(0);
  196. bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & ~RTC_ISTAT_STOPWATCH);
  197. spin_unlock_irq(&rtc->lock);
  198. return 0;
  199. case RTC_UIE_ON:
  200. dev_dbg_stamp(dev);
  201. spin_lock_irq(&rtc->lock);
  202. rtc_bfin_sync_pending();
  203. bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
  204. bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | RTC_ISTAT_SEC);
  205. spin_unlock_irq(&rtc->lock);
  206. return 0;
  207. case RTC_UIE_OFF:
  208. dev_dbg_stamp(dev);
  209. spin_lock_irq(&rtc->lock);
  210. rtc_bfin_sync_pending();
  211. bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & ~RTC_ISTAT_SEC);
  212. spin_unlock_irq(&rtc->lock);
  213. return 0;
  214. case RTC_AIE_ON: {
  215. unsigned long rtc_alarm;
  216. u16 which_alarm;
  217. int ret = 0;
  218. dev_dbg_stamp(dev);
  219. spin_lock_irq(&rtc->lock);
  220. rtc_bfin_sync_pending();
  221. if (rtc->rtc_alarm.tm_yday == -1) {
  222. struct rtc_time now;
  223. rtc_bfin_to_tm(bfin_read_RTC_STAT(), &now);
  224. now.tm_sec = rtc->rtc_alarm.tm_sec;
  225. now.tm_min = rtc->rtc_alarm.tm_min;
  226. now.tm_hour = rtc->rtc_alarm.tm_hour;
  227. ret = rtc_tm_to_time(&now, &rtc_alarm);
  228. which_alarm = RTC_ISTAT_ALARM;
  229. } else {
  230. ret = rtc_tm_to_time(&rtc->rtc_alarm, &rtc_alarm);
  231. which_alarm = RTC_ISTAT_ALARM_DAY;
  232. }
  233. if (ret == 0) {
  234. bfin_write_RTC_ISTAT(which_alarm);
  235. bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
  236. bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | which_alarm);
  237. }
  238. spin_unlock_irq(&rtc->lock);
  239. return ret;
  240. }
  241. case RTC_AIE_OFF:
  242. dev_dbg_stamp(dev);
  243. spin_lock_irq(&rtc->lock);
  244. rtc_bfin_sync_pending();
  245. bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & ~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
  246. spin_unlock_irq(&rtc->lock);
  247. return 0;
  248. }
  249. return -ENOIOCTLCMD;
  250. }
  251. static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
  252. {
  253. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  254. dev_dbg_stamp(dev);
  255. spin_lock_irq(&rtc->lock);
  256. rtc_bfin_sync_pending();
  257. rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
  258. spin_unlock_irq(&rtc->lock);
  259. return 0;
  260. }
  261. static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
  262. {
  263. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  264. int ret;
  265. unsigned long now;
  266. dev_dbg_stamp(dev);
  267. spin_lock_irq(&rtc->lock);
  268. ret = rtc_tm_to_time(tm, &now);
  269. if (ret == 0) {
  270. rtc_bfin_sync_pending();
  271. bfin_write_RTC_STAT(rtc_time_to_bfin(now));
  272. }
  273. spin_unlock_irq(&rtc->lock);
  274. return ret;
  275. }
  276. static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  277. {
  278. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  279. dev_dbg_stamp(dev);
  280. memcpy(&alrm->time, &rtc->rtc_alarm, sizeof(struct rtc_time));
  281. alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
  282. return 0;
  283. }
  284. static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  285. {
  286. struct bfin_rtc *rtc = dev_get_drvdata(dev);
  287. dev_dbg_stamp(dev);
  288. rtc->rtc_alarm = alrm->time;
  289. return 0;
  290. }
  291. static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
  292. {
  293. #define yesno(x) ((x) ? "yes" : "no")
  294. u16 ictl = bfin_read_RTC_ICTL();
  295. dev_dbg_stamp(dev);
  296. seq_printf(seq,
  297. "alarm_IRQ\t: %s\n"
  298. "wkalarm_IRQ\t: %s\n"
  299. "seconds_IRQ\t: %s\n"
  300. "periodic_IRQ\t: %s\n",
  301. yesno(ictl & RTC_ISTAT_ALARM),
  302. yesno(ictl & RTC_ISTAT_ALARM_DAY),
  303. yesno(ictl & RTC_ISTAT_SEC),
  304. yesno(ictl & RTC_ISTAT_STOPWATCH));
  305. return 0;
  306. #undef yesno
  307. }
  308. /**
  309. * bfin_irq_set_freq - make sure hardware supports requested freq
  310. * @dev: pointer to RTC device structure
  311. * @freq: requested frequency rate
  312. *
  313. * The Blackfin RTC can only generate periodic events at 1 per
  314. * second (1 Hz), so reject any attempt at changing it.
  315. */
  316. static int bfin_irq_set_freq(struct device *dev, int freq)
  317. {
  318. dev_dbg_stamp(dev);
  319. return -ENOTTY;
  320. }
  321. static struct rtc_class_ops bfin_rtc_ops = {
  322. .open = bfin_rtc_open,
  323. .release = bfin_rtc_release,
  324. .ioctl = bfin_rtc_ioctl,
  325. .read_time = bfin_rtc_read_time,
  326. .set_time = bfin_rtc_set_time,
  327. .read_alarm = bfin_rtc_read_alarm,
  328. .set_alarm = bfin_rtc_set_alarm,
  329. .proc = bfin_rtc_proc,
  330. .irq_set_freq = bfin_irq_set_freq,
  331. };
  332. static int __devinit bfin_rtc_probe(struct platform_device *pdev)
  333. {
  334. struct bfin_rtc *rtc;
  335. int ret = 0;
  336. dev_dbg_stamp(&pdev->dev);
  337. rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
  338. if (unlikely(!rtc))
  339. return -ENOMEM;
  340. spin_lock_init(&rtc->lock);
  341. rtc->rtc_dev = rtc_device_register(pdev->name, &pdev->dev, &bfin_rtc_ops, THIS_MODULE);
  342. if (unlikely(IS_ERR(rtc))) {
  343. ret = PTR_ERR(rtc->rtc_dev);
  344. goto err;
  345. }
  346. rtc->rtc_dev->irq_freq = 1;
  347. platform_set_drvdata(pdev, rtc);
  348. return 0;
  349. err:
  350. kfree(rtc);
  351. return ret;
  352. }
  353. static int __devexit bfin_rtc_remove(struct platform_device *pdev)
  354. {
  355. struct bfin_rtc *rtc = platform_get_drvdata(pdev);
  356. rtc_device_unregister(rtc->rtc_dev);
  357. platform_set_drvdata(pdev, NULL);
  358. kfree(rtc);
  359. return 0;
  360. }
  361. static struct platform_driver bfin_rtc_driver = {
  362. .driver = {
  363. .name = "rtc-bfin",
  364. .owner = THIS_MODULE,
  365. },
  366. .probe = bfin_rtc_probe,
  367. .remove = __devexit_p(bfin_rtc_remove),
  368. };
  369. static int __init bfin_rtc_init(void)
  370. {
  371. return platform_driver_register(&bfin_rtc_driver);
  372. }
  373. static void __exit bfin_rtc_exit(void)
  374. {
  375. platform_driver_unregister(&bfin_rtc_driver);
  376. }
  377. module_init(bfin_rtc_init);
  378. module_exit(bfin_rtc_exit);
  379. MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
  380. MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
  381. MODULE_LICENSE("GPL");