initio.c 94 KB

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  1. /**************************************************************************
  2. * Initio 9100 device driver for Linux.
  3. *
  4. * Copyright (c) 1994-1998 Initio Corporation
  5. * Copyright (c) 1998 Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; see the file COPYING. If not, write to
  20. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * --------------------------------------------------------------------------
  23. *
  24. * Redistribution and use in source and binary forms, with or without
  25. * modification, are permitted provided that the following conditions
  26. * are met:
  27. * 1. Redistributions of source code must retain the above copyright
  28. * notice, this list of conditions, and the following disclaimer,
  29. * without modification, immediately at the beginning of the file.
  30. * 2. Redistributions in binary form must reproduce the above copyright
  31. * notice, this list of conditions and the following disclaimer in the
  32. * documentation and/or other materials provided with the distribution.
  33. * 3. The name of the author may not be used to endorse or promote products
  34. * derived from this software without specific prior written permission.
  35. *
  36. * Where this Software is combined with software released under the terms of
  37. * the GNU General Public License ("GPL") and the terms of the GPL would require the
  38. * combined work to also be released under the terms of the GPL, the terms
  39. * and conditions of this License will apply in addition to those of the
  40. * GPL with the exception of any terms or conditions of this License that
  41. * conflict with, or are expressly prohibited by, the GPL.
  42. *
  43. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  44. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  45. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  46. * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  47. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  48. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  49. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  51. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  52. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  53. * SUCH DAMAGE.
  54. *
  55. *************************************************************************
  56. *
  57. * DESCRIPTION:
  58. *
  59. * This is the Linux low-level SCSI driver for Initio INI-9X00U/UW SCSI host
  60. * adapters
  61. *
  62. * 08/06/97 hc - v1.01h
  63. * - Support inic-940 and inic-935
  64. * 09/26/97 hc - v1.01i
  65. * - Make correction from J.W. Schultz suggestion
  66. * 10/13/97 hc - Support reset function
  67. * 10/21/97 hc - v1.01j
  68. * - Support 32 LUN (SCSI 3)
  69. * 01/14/98 hc - v1.01k
  70. * - Fix memory allocation problem
  71. * 03/04/98 hc - v1.01l
  72. * - Fix tape rewind which will hang the system problem
  73. * - Set can_queue to tul_num_scb
  74. * 06/25/98 hc - v1.01m
  75. * - Get it work for kernel version >= 2.1.75
  76. * - Dynamic assign SCSI bus reset holding time in init_tulip()
  77. * 07/02/98 hc - v1.01n
  78. * - Support 0002134A
  79. * 08/07/98 hc - v1.01o
  80. * - Change the tul_abort_srb routine to use scsi_done. <01>
  81. * 09/07/98 hl - v1.02
  82. * - Change the INI9100U define and proc_dir_entry to
  83. * reflect the newer Kernel 2.1.118, but the v1.o1o
  84. * should work with Kernel 2.1.118.
  85. * 09/20/98 wh - v1.02a
  86. * - Support Abort command.
  87. * - Handle reset routine.
  88. * 09/21/98 hl - v1.03
  89. * - remove comments.
  90. * 12/09/98 bv - v1.03a
  91. * - Removed unused code
  92. * 12/13/98 bv - v1.03b
  93. * - Remove cli() locking for kernels >= 2.1.95. This uses
  94. * spinlocks to serialize access to the pSRB_head and
  95. * pSRB_tail members of the HCS structure.
  96. * 09/01/99 bv - v1.03d
  97. * - Fixed a deadlock problem in SMP.
  98. * 21/01/99 bv - v1.03e
  99. * - Add support for the Domex 3192U PCI SCSI
  100. * This is a slightly modified patch by
  101. * Brian Macy <bmacy@sunshinecomputing.com>
  102. * 22/02/99 bv - v1.03f
  103. * - Didn't detect the INIC-950 in 2.0.x correctly.
  104. * Now fixed.
  105. * 05/07/99 bv - v1.03g
  106. * - Changed the assumption that HZ = 100
  107. * 10/17/03 mc - v1.04
  108. * - added new DMA API support
  109. * 06/01/04 jmd - v1.04a
  110. * - Re-add reset_bus support
  111. **************************************************************************/
  112. #include <linux/module.h>
  113. #include <linux/errno.h>
  114. #include <linux/delay.h>
  115. #include <linux/pci.h>
  116. #include <linux/init.h>
  117. #include <linux/blkdev.h>
  118. #include <linux/spinlock.h>
  119. #include <linux/stat.h>
  120. #include <linux/config.h>
  121. #include <linux/kernel.h>
  122. #include <linux/proc_fs.h>
  123. #include <linux/string.h>
  124. #include <linux/interrupt.h>
  125. #include <linux/ioport.h>
  126. #include <linux/sched.h>
  127. #include <linux/slab.h>
  128. #include <linux/jiffies.h>
  129. #include <asm/io.h>
  130. #include <scsi/scsi.h>
  131. #include <scsi/scsi_cmnd.h>
  132. #include <scsi/scsi_device.h>
  133. #include <scsi/scsi_host.h>
  134. #include <scsi/scsi_tcq.h>
  135. #include "initio.h"
  136. #define SENSE_SIZE 14
  137. #define i91u_MAXQUEUE 2
  138. #define i91u_REVID "Initio INI-9X00U/UW SCSI device driver; Revision: 1.04a"
  139. #define INI_VENDOR_ID 0x1101 /* Initio's PCI vendor ID */
  140. #define DMX_VENDOR_ID 0x134a /* Domex's PCI vendor ID */
  141. #define I950_DEVICE_ID 0x9500 /* Initio's inic-950 product ID */
  142. #define I940_DEVICE_ID 0x9400 /* Initio's inic-940 product ID */
  143. #define I935_DEVICE_ID 0x9401 /* Initio's inic-935 product ID */
  144. #define I920_DEVICE_ID 0x0002 /* Initio's other product ID */
  145. #ifdef DEBUG_i91u
  146. static unsigned int i91u_debug = DEBUG_DEFAULT;
  147. #endif
  148. #define TULSZ(sz) (sizeof(sz) / sizeof(sz[0]))
  149. #define TUL_RDWORD(x,y) (short)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
  150. typedef struct PCI_ID_Struc {
  151. unsigned short vendor_id;
  152. unsigned short device_id;
  153. } PCI_ID;
  154. static int tul_num_ch = 4; /* Maximum 4 adapters */
  155. static int tul_num_scb;
  156. static int tul_tag_enable = 1;
  157. static SCB *tul_scb;
  158. #ifdef DEBUG_i91u
  159. static int setup_debug = 0;
  160. #endif
  161. static void i91uSCBPost(BYTE * pHcb, BYTE * pScb);
  162. static const PCI_ID i91u_pci_devices[] = {
  163. { INI_VENDOR_ID, I950_DEVICE_ID },
  164. { INI_VENDOR_ID, I940_DEVICE_ID },
  165. { INI_VENDOR_ID, I935_DEVICE_ID },
  166. { INI_VENDOR_ID, I920_DEVICE_ID },
  167. { DMX_VENDOR_ID, I920_DEVICE_ID },
  168. };
  169. #define DEBUG_INTERRUPT 0
  170. #define DEBUG_QUEUE 0
  171. #define DEBUG_STATE 0
  172. #define INT_DISC 0
  173. /*--- external functions --*/
  174. static void tul_se2_wait(void);
  175. /*--- forward refrence ---*/
  176. static SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun);
  177. static SCB *tul_find_done_scb(HCS * pCurHcb);
  178. static int tulip_main(HCS * pCurHcb);
  179. static int tul_next_state(HCS * pCurHcb);
  180. static int tul_state_1(HCS * pCurHcb);
  181. static int tul_state_2(HCS * pCurHcb);
  182. static int tul_state_3(HCS * pCurHcb);
  183. static int tul_state_4(HCS * pCurHcb);
  184. static int tul_state_5(HCS * pCurHcb);
  185. static int tul_state_6(HCS * pCurHcb);
  186. static int tul_state_7(HCS * pCurHcb);
  187. static int tul_xfer_data_in(HCS * pCurHcb);
  188. static int tul_xfer_data_out(HCS * pCurHcb);
  189. static int tul_xpad_in(HCS * pCurHcb);
  190. static int tul_xpad_out(HCS * pCurHcb);
  191. static int tul_status_msg(HCS * pCurHcb);
  192. static int tul_msgin(HCS * pCurHcb);
  193. static int tul_msgin_sync(HCS * pCurHcb);
  194. static int tul_msgin_accept(HCS * pCurHcb);
  195. static int tul_msgout_reject(HCS * pCurHcb);
  196. static int tul_msgin_extend(HCS * pCurHcb);
  197. static int tul_msgout_ide(HCS * pCurHcb);
  198. static int tul_msgout_abort_targ(HCS * pCurHcb);
  199. static int tul_msgout_abort_tag(HCS * pCurHcb);
  200. static int tul_bus_device_reset(HCS * pCurHcb);
  201. static void tul_select_atn(HCS * pCurHcb, SCB * pCurScb);
  202. static void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb);
  203. static void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb);
  204. static int int_tul_busfree(HCS * pCurHcb);
  205. int int_tul_scsi_rst(HCS * pCurHcb);
  206. static int int_tul_bad_seq(HCS * pCurHcb);
  207. static int int_tul_resel(HCS * pCurHcb);
  208. static int tul_sync_done(HCS * pCurHcb);
  209. static int wdtr_done(HCS * pCurHcb);
  210. static int wait_tulip(HCS * pCurHcb);
  211. static int tul_wait_done_disc(HCS * pCurHcb);
  212. static int tul_wait_disc(HCS * pCurHcb);
  213. static void tulip_scsi(HCS * pCurHcb);
  214. static int tul_post_scsi_rst(HCS * pCurHcb);
  215. static void tul_se2_ew_en(WORD CurBase);
  216. static void tul_se2_ew_ds(WORD CurBase);
  217. static int tul_se2_rd_all(WORD CurBase);
  218. static void tul_se2_update_all(WORD CurBase); /* setup default pattern */
  219. static void tul_read_eeprom(WORD CurBase);
  220. /* ---- EXTERNAL VARIABLES ---- */
  221. HCS tul_hcs[MAX_SUPPORTED_ADAPTERS];
  222. /* ---- INTERNAL VARIABLES ---- */
  223. static INI_ADPT_STRUCT i91u_adpt[MAX_SUPPORTED_ADAPTERS];
  224. /*NVRAM nvram, *nvramp = &nvram; */
  225. static NVRAM i91unvram;
  226. static NVRAM *i91unvramp;
  227. static UCHAR i91udftNvRam[64] =
  228. {
  229. /*----------- header -----------*/
  230. 0x25, 0xc9, /* Signature */
  231. 0x40, /* Size */
  232. 0x01, /* Revision */
  233. /* -- Host Adapter Structure -- */
  234. 0x95, /* ModelByte0 */
  235. 0x00, /* ModelByte1 */
  236. 0x00, /* ModelInfo */
  237. 0x01, /* NumOfCh */
  238. NBC1_DEFAULT, /* BIOSConfig1 */
  239. 0, /* BIOSConfig2 */
  240. 0, /* HAConfig1 */
  241. 0, /* HAConfig2 */
  242. /* SCSI channel 0 and target Structure */
  243. 7, /* SCSIid */
  244. NCC1_DEFAULT, /* SCSIconfig1 */
  245. 0, /* SCSIconfig2 */
  246. 0x10, /* NumSCSItarget */
  247. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  248. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  249. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  250. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  251. /* SCSI channel 1 and target Structure */
  252. 7, /* SCSIid */
  253. NCC1_DEFAULT, /* SCSIconfig1 */
  254. 0, /* SCSIconfig2 */
  255. 0x10, /* NumSCSItarget */
  256. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  257. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  258. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  259. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  260. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  261. 0, 0}; /* - CheckSum - */
  262. static UCHAR tul_rate_tbl[8] = /* fast 20 */
  263. {
  264. /* nanosecond devide by 4 */
  265. 12, /* 50ns, 20M */
  266. 18, /* 75ns, 13.3M */
  267. 25, /* 100ns, 10M */
  268. 31, /* 125ns, 8M */
  269. 37, /* 150ns, 6.6M */
  270. 43, /* 175ns, 5.7M */
  271. 50, /* 200ns, 5M */
  272. 62 /* 250ns, 4M */
  273. };
  274. static void tul_do_pause(unsigned amount)
  275. { /* Pause for amount jiffies */
  276. unsigned long the_time = jiffies + amount;
  277. while (time_before_eq(jiffies, the_time));
  278. }
  279. /*-- forward reference --*/
  280. /*******************************************************************
  281. Use memeory refresh time ~ 15us * 2
  282. ********************************************************************/
  283. void tul_se2_wait(void)
  284. {
  285. #if 1
  286. udelay(30);
  287. #else
  288. UCHAR readByte;
  289. readByte = TUL_RD(0, 0x61);
  290. if ((readByte & 0x10) == 0x10) {
  291. for (;;) {
  292. readByte = TUL_RD(0, 0x61);
  293. if ((readByte & 0x10) == 0x10)
  294. break;
  295. }
  296. for (;;) {
  297. readByte = TUL_RD(0, 0x61);
  298. if ((readByte & 0x10) != 0x10)
  299. break;
  300. }
  301. } else {
  302. for (;;) {
  303. readByte = TUL_RD(0, 0x61);
  304. if ((readByte & 0x10) == 0x10)
  305. break;
  306. }
  307. for (;;) {
  308. readByte = TUL_RD(0, 0x61);
  309. if ((readByte & 0x10) != 0x10)
  310. break;
  311. }
  312. }
  313. #endif
  314. }
  315. /******************************************************************
  316. Input: instruction for Serial E2PROM
  317. EX: se2_rd(0 call se2_instr() to send address and read command
  318. StartBit OP_Code Address Data
  319. --------- -------- ------------------ -------
  320. 1 1 , 0 A5,A4,A3,A2,A1,A0 D15-D0
  321. +-----------------------------------------------------
  322. |
  323. CS -----+
  324. +--+ +--+ +--+ +--+ +--+
  325. ^ | ^ | ^ | ^ | ^ |
  326. | | | | | | | | | |
  327. CLK -------+ +--+ +--+ +--+ +--+ +--
  328. (leading edge trigger)
  329. +--1-----1--+
  330. | SB OP | OP A5 A4
  331. DI ----+ +--0------------------
  332. (address and cmd sent to nvram)
  333. -------------------------------------------+
  334. |
  335. DO +---
  336. (data sent from nvram)
  337. ******************************************************************/
  338. void tul_se2_instr(WORD CurBase, UCHAR instr)
  339. {
  340. int i;
  341. UCHAR b;
  342. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* cs+start bit */
  343. tul_se2_wait();
  344. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK | SE2DO); /* +CLK */
  345. tul_se2_wait();
  346. for (i = 0; i < 8; i++) {
  347. if (instr & 0x80)
  348. b = SE2CS | SE2DO; /* -CLK+dataBit */
  349. else
  350. b = SE2CS; /* -CLK */
  351. TUL_WR(CurBase + TUL_NVRAM, b);
  352. tul_se2_wait();
  353. TUL_WR(CurBase + TUL_NVRAM, b | SE2CLK); /* +CLK */
  354. tul_se2_wait();
  355. instr <<= 1;
  356. }
  357. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  358. tul_se2_wait();
  359. return;
  360. }
  361. /******************************************************************
  362. Function name : tul_se2_ew_en
  363. Description : Enable erase/write state of serial EEPROM
  364. ******************************************************************/
  365. void tul_se2_ew_en(WORD CurBase)
  366. {
  367. tul_se2_instr(CurBase, 0x30); /* EWEN */
  368. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  369. tul_se2_wait();
  370. return;
  371. }
  372. /************************************************************************
  373. Disable erase/write state of serial EEPROM
  374. *************************************************************************/
  375. void tul_se2_ew_ds(WORD CurBase)
  376. {
  377. tul_se2_instr(CurBase, 0); /* EWDS */
  378. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  379. tul_se2_wait();
  380. return;
  381. }
  382. /******************************************************************
  383. Input :address of Serial E2PROM
  384. Output :value stored in Serial E2PROM
  385. *******************************************************************/
  386. USHORT tul_se2_rd(WORD CurBase, ULONG adr)
  387. {
  388. UCHAR instr, readByte;
  389. USHORT readWord;
  390. int i;
  391. instr = (UCHAR) (adr | 0x80);
  392. tul_se2_instr(CurBase, instr); /* READ INSTR */
  393. readWord = 0;
  394. for (i = 15; i >= 0; i--) {
  395. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  396. tul_se2_wait();
  397. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  398. /* sample data after the following edge of clock */
  399. readByte = TUL_RD(CurBase, TUL_NVRAM);
  400. readByte &= SE2DI;
  401. readWord += (readByte << i);
  402. tul_se2_wait(); /* 6/20/95 */
  403. }
  404. TUL_WR(CurBase + TUL_NVRAM, 0); /* no chip select */
  405. tul_se2_wait();
  406. return readWord;
  407. }
  408. /******************************************************************
  409. Input: new value in Serial E2PROM, address of Serial E2PROM
  410. *******************************************************************/
  411. void tul_se2_wr(WORD CurBase, UCHAR adr, USHORT writeWord)
  412. {
  413. UCHAR readByte;
  414. UCHAR instr;
  415. int i;
  416. instr = (UCHAR) (adr | 0x40);
  417. tul_se2_instr(CurBase, instr); /* WRITE INSTR */
  418. for (i = 15; i >= 0; i--) {
  419. if (writeWord & 0x8000)
  420. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* -CLK+dataBit 1 */
  421. else
  422. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK+dataBit 0 */
  423. tul_se2_wait();
  424. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  425. tul_se2_wait();
  426. writeWord <<= 1;
  427. }
  428. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  429. tul_se2_wait();
  430. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  431. tul_se2_wait();
  432. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* +CS */
  433. tul_se2_wait();
  434. for (;;) {
  435. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  436. tul_se2_wait();
  437. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  438. tul_se2_wait();
  439. if ((readByte = TUL_RD(CurBase, TUL_NVRAM)) & SE2DI)
  440. break; /* write complete */
  441. }
  442. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  443. return;
  444. }
  445. /***********************************************************************
  446. Read SCSI H/A configuration parameters from serial EEPROM
  447. ************************************************************************/
  448. int tul_se2_rd_all(WORD CurBase)
  449. {
  450. int i;
  451. ULONG chksum = 0;
  452. USHORT *np;
  453. i91unvramp = &i91unvram;
  454. np = (USHORT *) i91unvramp;
  455. for (i = 0; i < 32; i++) {
  456. *np++ = tul_se2_rd(CurBase, i);
  457. }
  458. /*--------------------Is signature "ini" ok ? ----------------*/
  459. if (i91unvramp->NVM_Signature != INI_SIGNATURE)
  460. return -1;
  461. /*---------------------- Is ckecksum ok ? ----------------------*/
  462. np = (USHORT *) i91unvramp;
  463. for (i = 0; i < 31; i++)
  464. chksum += *np++;
  465. if (i91unvramp->NVM_CheckSum != (USHORT) chksum)
  466. return -1;
  467. return 1;
  468. }
  469. /***********************************************************************
  470. Update SCSI H/A configuration parameters from serial EEPROM
  471. ************************************************************************/
  472. void tul_se2_update_all(WORD CurBase)
  473. { /* setup default pattern */
  474. int i;
  475. ULONG chksum = 0;
  476. USHORT *np, *np1;
  477. i91unvramp = &i91unvram;
  478. /* Calculate checksum first */
  479. np = (USHORT *) i91udftNvRam;
  480. for (i = 0; i < 31; i++)
  481. chksum += *np++;
  482. *np = (USHORT) chksum;
  483. tul_se2_ew_en(CurBase); /* Enable write */
  484. np = (USHORT *) i91udftNvRam;
  485. np1 = (USHORT *) i91unvramp;
  486. for (i = 0; i < 32; i++, np++, np1++) {
  487. if (*np != *np1) {
  488. tul_se2_wr(CurBase, i, *np);
  489. }
  490. }
  491. tul_se2_ew_ds(CurBase); /* Disable write */
  492. return;
  493. }
  494. /*************************************************************************
  495. Function name : read_eeprom
  496. **************************************************************************/
  497. void tul_read_eeprom(WORD CurBase)
  498. {
  499. UCHAR gctrl;
  500. i91unvramp = &i91unvram;
  501. /*------Enable EEProm programming ---*/
  502. gctrl = TUL_RD(CurBase, TUL_GCTRL);
  503. TUL_WR(CurBase + TUL_GCTRL, gctrl | TUL_GCTRL_EEPROM_BIT);
  504. if (tul_se2_rd_all(CurBase) != 1) {
  505. tul_se2_update_all(CurBase); /* setup default pattern */
  506. tul_se2_rd_all(CurBase); /* load again */
  507. }
  508. /*------ Disable EEProm programming ---*/
  509. gctrl = TUL_RD(CurBase, TUL_GCTRL);
  510. TUL_WR(CurBase + TUL_GCTRL, gctrl & ~TUL_GCTRL_EEPROM_BIT);
  511. } /* read_eeprom */
  512. int Addi91u_into_Adapter_table(WORD wBIOS, WORD wBASE, BYTE bInterrupt,
  513. BYTE bBus, BYTE bDevice)
  514. {
  515. int i, j;
  516. for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) {
  517. if (i91u_adpt[i].ADPT_BIOS < wBIOS)
  518. continue;
  519. if (i91u_adpt[i].ADPT_BIOS == wBIOS) {
  520. if (i91u_adpt[i].ADPT_BASE == wBASE) {
  521. if (i91u_adpt[i].ADPT_Bus != 0xFF)
  522. return 1;
  523. } else if (i91u_adpt[i].ADPT_BASE < wBASE)
  524. continue;
  525. }
  526. for (j = MAX_SUPPORTED_ADAPTERS - 1; j > i; j--) {
  527. i91u_adpt[j].ADPT_BASE = i91u_adpt[j - 1].ADPT_BASE;
  528. i91u_adpt[j].ADPT_INTR = i91u_adpt[j - 1].ADPT_INTR;
  529. i91u_adpt[j].ADPT_BIOS = i91u_adpt[j - 1].ADPT_BIOS;
  530. i91u_adpt[j].ADPT_Bus = i91u_adpt[j - 1].ADPT_Bus;
  531. i91u_adpt[j].ADPT_Device = i91u_adpt[j - 1].ADPT_Device;
  532. }
  533. i91u_adpt[i].ADPT_BASE = wBASE;
  534. i91u_adpt[i].ADPT_INTR = bInterrupt;
  535. i91u_adpt[i].ADPT_BIOS = wBIOS;
  536. i91u_adpt[i].ADPT_Bus = bBus;
  537. i91u_adpt[i].ADPT_Device = bDevice;
  538. return 0;
  539. }
  540. return 1;
  541. }
  542. void init_i91uAdapter_table(void)
  543. {
  544. int i;
  545. for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) { /* Initialize adapter structure */
  546. i91u_adpt[i].ADPT_BIOS = 0xffff;
  547. i91u_adpt[i].ADPT_BASE = 0xffff;
  548. i91u_adpt[i].ADPT_INTR = 0xff;
  549. i91u_adpt[i].ADPT_Bus = 0xff;
  550. i91u_adpt[i].ADPT_Device = 0xff;
  551. }
  552. return;
  553. }
  554. void tul_stop_bm(HCS * pCurHcb)
  555. {
  556. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
  557. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
  558. /* wait Abort DMA xfer done */
  559. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0);
  560. }
  561. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  562. }
  563. /***************************************************************************/
  564. void get_tulipPCIConfig(HCS * pCurHcb, int ch_idx)
  565. {
  566. pCurHcb->HCS_Base = i91u_adpt[ch_idx].ADPT_BASE; /* Supply base address */
  567. pCurHcb->HCS_BIOS = i91u_adpt[ch_idx].ADPT_BIOS; /* Supply BIOS address */
  568. pCurHcb->HCS_Intr = i91u_adpt[ch_idx].ADPT_INTR; /* Supply interrupt line */
  569. return;
  570. }
  571. /***************************************************************************/
  572. int tul_reset_scsi(HCS * pCurHcb, int seconds)
  573. {
  574. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_BUS);
  575. while (!((pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt)) & TSS_SCSIRST_INT));
  576. /* reset tulip chip */
  577. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, 0);
  578. /* Stall for a while, wait for target's firmware ready,make it 2 sec ! */
  579. /* SONY 5200 tape drive won't work if only stall for 1 sec */
  580. tul_do_pause(seconds * HZ);
  581. TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  582. return (SCSI_RESET_SUCCESS);
  583. }
  584. /***************************************************************************/
  585. int init_tulip(HCS * pCurHcb, SCB * scbp, int tul_num_scb, BYTE * pbBiosAdr, int seconds)
  586. {
  587. int i;
  588. BYTE *pwFlags;
  589. BYTE *pbHeads;
  590. SCB *pTmpScb, *pPrevScb = NULL;
  591. pCurHcb->HCS_NumScbs = tul_num_scb;
  592. pCurHcb->HCS_Semaph = 1;
  593. spin_lock_init(&pCurHcb->HCS_SemaphLock);
  594. pCurHcb->HCS_JSStatus0 = 0;
  595. pCurHcb->HCS_Scb = scbp;
  596. pCurHcb->HCS_NxtPend = scbp;
  597. pCurHcb->HCS_NxtAvail = scbp;
  598. for (i = 0, pTmpScb = scbp; i < tul_num_scb; i++, pTmpScb++) {
  599. pTmpScb->SCB_TagId = i;
  600. if (i != 0)
  601. pPrevScb->SCB_NxtScb = pTmpScb;
  602. pPrevScb = pTmpScb;
  603. }
  604. pPrevScb->SCB_NxtScb = NULL;
  605. pCurHcb->HCS_ScbEnd = pTmpScb;
  606. pCurHcb->HCS_FirstAvail = scbp;
  607. pCurHcb->HCS_LastAvail = pPrevScb;
  608. spin_lock_init(&pCurHcb->HCS_AvailLock);
  609. pCurHcb->HCS_FirstPend = NULL;
  610. pCurHcb->HCS_LastPend = NULL;
  611. pCurHcb->HCS_FirstBusy = NULL;
  612. pCurHcb->HCS_LastBusy = NULL;
  613. pCurHcb->HCS_FirstDone = NULL;
  614. pCurHcb->HCS_LastDone = NULL;
  615. pCurHcb->HCS_ActScb = NULL;
  616. pCurHcb->HCS_ActTcs = NULL;
  617. tul_read_eeprom(pCurHcb->HCS_Base);
  618. /*---------- get H/A configuration -------------*/
  619. if (i91unvramp->NVM_SCSIInfo[0].NVM_NumOfTarg == 8)
  620. pCurHcb->HCS_MaxTar = 8;
  621. else
  622. pCurHcb->HCS_MaxTar = 16;
  623. pCurHcb->HCS_Config = i91unvramp->NVM_SCSIInfo[0].NVM_ChConfig1;
  624. pCurHcb->HCS_SCSI_ID = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID;
  625. pCurHcb->HCS_IdMask = ~(1 << pCurHcb->HCS_SCSI_ID);
  626. #if CHK_PARITY
  627. /* Enable parity error response */
  628. TUL_WR(pCurHcb->HCS_Base + TUL_PCMD, TUL_RD(pCurHcb->HCS_Base, TUL_PCMD) | 0x40);
  629. #endif
  630. /* Mask all the interrupt */
  631. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  632. tul_stop_bm(pCurHcb);
  633. /* --- Initialize the tulip --- */
  634. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_CHIP);
  635. /* program HBA's SCSI ID */
  636. TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId, pCurHcb->HCS_SCSI_ID << 4);
  637. /* Enable Initiator Mode ,phase latch,alternate sync period mode,
  638. disable SCSI reset */
  639. if (pCurHcb->HCS_Config & HCC_EN_PAR)
  640. pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
  641. else
  642. pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT);
  643. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_SConf1);
  644. /* Enable HW reselect */
  645. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT);
  646. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, 0);
  647. /* selection time out = 250 ms */
  648. TUL_WR(pCurHcb->HCS_Base + TUL_STimeOut, 153);
  649. /*--------- Enable SCSI terminator -----*/
  650. TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, (pCurHcb->HCS_Config & (HCC_ACT_TERM1 | HCC_ACT_TERM2)));
  651. TUL_WR(pCurHcb->HCS_Base + TUL_GCTRL1,
  652. ((pCurHcb->HCS_Config & HCC_AUTO_TERM) >> 4) | (TUL_RD(pCurHcb->HCS_Base, TUL_GCTRL1) & 0xFE));
  653. for (i = 0,
  654. pwFlags = & (i91unvramp->NVM_SCSIInfo[0].NVM_Targ0Config),
  655. pbHeads = pbBiosAdr + 0x180;
  656. i < pCurHcb->HCS_MaxTar;
  657. i++, pwFlags++) {
  658. pCurHcb->HCS_Tcs[i].TCS_Flags = *pwFlags & ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  659. if (pCurHcb->HCS_Tcs[i].TCS_Flags & TCF_EN_255)
  660. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63;
  661. else
  662. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0;
  663. pCurHcb->HCS_Tcs[i].TCS_JS_Period = 0;
  664. pCurHcb->HCS_Tcs[i].TCS_SConfig0 = pCurHcb->HCS_SConf1;
  665. pCurHcb->HCS_Tcs[i].TCS_DrvHead = *pbHeads++;
  666. if (pCurHcb->HCS_Tcs[i].TCS_DrvHead == 255)
  667. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63;
  668. else
  669. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0;
  670. pCurHcb->HCS_Tcs[i].TCS_DrvSector = *pbHeads++;
  671. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY;
  672. pCurHcb->HCS_ActTags[i] = 0;
  673. pCurHcb->HCS_MaxTags[i] = 0xFF;
  674. } /* for */
  675. printk("i91u: PCI Base=0x%04X, IRQ=%d, BIOS=0x%04X0, SCSI ID=%d\n",
  676. pCurHcb->HCS_Base, pCurHcb->HCS_Intr,
  677. pCurHcb->HCS_BIOS, pCurHcb->HCS_SCSI_ID);
  678. /*------------------- reset SCSI Bus ---------------------------*/
  679. if (pCurHcb->HCS_Config & HCC_SCSI_RESET) {
  680. printk("i91u: Reset SCSI Bus ... \n");
  681. tul_reset_scsi(pCurHcb, seconds);
  682. }
  683. TUL_WR(pCurHcb->HCS_Base + TUL_SCFG1, 0x17);
  684. TUL_WR(pCurHcb->HCS_Base + TUL_SIntEnable, 0xE9);
  685. return (0);
  686. }
  687. /***************************************************************************/
  688. SCB *tul_alloc_scb(HCS * hcsp)
  689. {
  690. SCB *pTmpScb;
  691. ULONG flags;
  692. spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags);
  693. if ((pTmpScb = hcsp->HCS_FirstAvail) != NULL) {
  694. #if DEBUG_QUEUE
  695. printk("find scb at %08lx\n", (ULONG) pTmpScb);
  696. #endif
  697. if ((hcsp->HCS_FirstAvail = pTmpScb->SCB_NxtScb) == NULL)
  698. hcsp->HCS_LastAvail = NULL;
  699. pTmpScb->SCB_NxtScb = NULL;
  700. pTmpScb->SCB_Status = SCB_RENT;
  701. }
  702. spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags);
  703. return (pTmpScb);
  704. }
  705. /***************************************************************************/
  706. void tul_release_scb(HCS * hcsp, SCB * scbp)
  707. {
  708. ULONG flags;
  709. #if DEBUG_QUEUE
  710. printk("Release SCB %lx; ", (ULONG) scbp);
  711. #endif
  712. spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags);
  713. scbp->SCB_Srb = NULL;
  714. scbp->SCB_Status = 0;
  715. scbp->SCB_NxtScb = NULL;
  716. if (hcsp->HCS_LastAvail != NULL) {
  717. hcsp->HCS_LastAvail->SCB_NxtScb = scbp;
  718. hcsp->HCS_LastAvail = scbp;
  719. } else {
  720. hcsp->HCS_FirstAvail = scbp;
  721. hcsp->HCS_LastAvail = scbp;
  722. }
  723. spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags);
  724. }
  725. /***************************************************************************/
  726. void tul_append_pend_scb(HCS * pCurHcb, SCB * scbp)
  727. {
  728. #if DEBUG_QUEUE
  729. printk("Append pend SCB %lx; ", (ULONG) scbp);
  730. #endif
  731. scbp->SCB_Status = SCB_PEND;
  732. scbp->SCB_NxtScb = NULL;
  733. if (pCurHcb->HCS_LastPend != NULL) {
  734. pCurHcb->HCS_LastPend->SCB_NxtScb = scbp;
  735. pCurHcb->HCS_LastPend = scbp;
  736. } else {
  737. pCurHcb->HCS_FirstPend = scbp;
  738. pCurHcb->HCS_LastPend = scbp;
  739. }
  740. }
  741. /***************************************************************************/
  742. void tul_push_pend_scb(HCS * pCurHcb, SCB * scbp)
  743. {
  744. #if DEBUG_QUEUE
  745. printk("Push pend SCB %lx; ", (ULONG) scbp);
  746. #endif
  747. scbp->SCB_Status = SCB_PEND;
  748. if ((scbp->SCB_NxtScb = pCurHcb->HCS_FirstPend) != NULL) {
  749. pCurHcb->HCS_FirstPend = scbp;
  750. } else {
  751. pCurHcb->HCS_FirstPend = scbp;
  752. pCurHcb->HCS_LastPend = scbp;
  753. }
  754. }
  755. /***************************************************************************/
  756. SCB *tul_find_first_pend_scb(HCS * pCurHcb)
  757. {
  758. SCB *pFirstPend;
  759. pFirstPend = pCurHcb->HCS_FirstPend;
  760. while (pFirstPend != NULL) {
  761. if (pFirstPend->SCB_Opcode != ExecSCSI) {
  762. return (pFirstPend);
  763. }
  764. if (pFirstPend->SCB_TagMsg == 0) {
  765. if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] == 0) &&
  766. !(pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) {
  767. return (pFirstPend);
  768. }
  769. } else {
  770. if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] >=
  771. pCurHcb->HCS_MaxTags[pFirstPend->SCB_Target]) |
  772. (pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) {
  773. pFirstPend = pFirstPend->SCB_NxtScb;
  774. continue;
  775. }
  776. return (pFirstPend);
  777. }
  778. pFirstPend = pFirstPend->SCB_NxtScb;
  779. }
  780. return (pFirstPend);
  781. }
  782. /***************************************************************************/
  783. SCB *tul_pop_pend_scb(HCS * pCurHcb)
  784. {
  785. SCB *pTmpScb;
  786. if ((pTmpScb = pCurHcb->HCS_FirstPend) != NULL) {
  787. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  788. pCurHcb->HCS_LastPend = NULL;
  789. pTmpScb->SCB_NxtScb = NULL;
  790. }
  791. #if DEBUG_QUEUE
  792. printk("Pop pend SCB %lx; ", (ULONG) pTmpScb);
  793. #endif
  794. return (pTmpScb);
  795. }
  796. /***************************************************************************/
  797. void tul_unlink_pend_scb(HCS * pCurHcb, SCB * pCurScb)
  798. {
  799. SCB *pTmpScb, *pPrevScb;
  800. #if DEBUG_QUEUE
  801. printk("unlink pend SCB %lx; ", (ULONG) pCurScb);
  802. #endif
  803. pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend;
  804. while (pTmpScb != NULL) {
  805. if (pCurScb == pTmpScb) { /* Unlink this SCB */
  806. if (pTmpScb == pCurHcb->HCS_FirstPend) {
  807. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  808. pCurHcb->HCS_LastPend = NULL;
  809. } else {
  810. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  811. if (pTmpScb == pCurHcb->HCS_LastPend)
  812. pCurHcb->HCS_LastPend = pPrevScb;
  813. }
  814. pTmpScb->SCB_NxtScb = NULL;
  815. break;
  816. }
  817. pPrevScb = pTmpScb;
  818. pTmpScb = pTmpScb->SCB_NxtScb;
  819. }
  820. return;
  821. }
  822. /***************************************************************************/
  823. void tul_append_busy_scb(HCS * pCurHcb, SCB * scbp)
  824. {
  825. #if DEBUG_QUEUE
  826. printk("append busy SCB %lx; ", (ULONG) scbp);
  827. #endif
  828. if (scbp->SCB_TagMsg)
  829. pCurHcb->HCS_ActTags[scbp->SCB_Target]++;
  830. else
  831. pCurHcb->HCS_Tcs[scbp->SCB_Target].TCS_Flags |= TCF_BUSY;
  832. scbp->SCB_Status = SCB_BUSY;
  833. scbp->SCB_NxtScb = NULL;
  834. if (pCurHcb->HCS_LastBusy != NULL) {
  835. pCurHcb->HCS_LastBusy->SCB_NxtScb = scbp;
  836. pCurHcb->HCS_LastBusy = scbp;
  837. } else {
  838. pCurHcb->HCS_FirstBusy = scbp;
  839. pCurHcb->HCS_LastBusy = scbp;
  840. }
  841. }
  842. /***************************************************************************/
  843. SCB *tul_pop_busy_scb(HCS * pCurHcb)
  844. {
  845. SCB *pTmpScb;
  846. if ((pTmpScb = pCurHcb->HCS_FirstBusy) != NULL) {
  847. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  848. pCurHcb->HCS_LastBusy = NULL;
  849. pTmpScb->SCB_NxtScb = NULL;
  850. if (pTmpScb->SCB_TagMsg)
  851. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  852. else
  853. pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY;
  854. }
  855. #if DEBUG_QUEUE
  856. printk("Pop busy SCB %lx; ", (ULONG) pTmpScb);
  857. #endif
  858. return (pTmpScb);
  859. }
  860. /***************************************************************************/
  861. void tul_unlink_busy_scb(HCS * pCurHcb, SCB * pCurScb)
  862. {
  863. SCB *pTmpScb, *pPrevScb;
  864. #if DEBUG_QUEUE
  865. printk("unlink busy SCB %lx; ", (ULONG) pCurScb);
  866. #endif
  867. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy;
  868. while (pTmpScb != NULL) {
  869. if (pCurScb == pTmpScb) { /* Unlink this SCB */
  870. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  871. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  872. pCurHcb->HCS_LastBusy = NULL;
  873. } else {
  874. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  875. if (pTmpScb == pCurHcb->HCS_LastBusy)
  876. pCurHcb->HCS_LastBusy = pPrevScb;
  877. }
  878. pTmpScb->SCB_NxtScb = NULL;
  879. if (pTmpScb->SCB_TagMsg)
  880. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  881. else
  882. pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY;
  883. break;
  884. }
  885. pPrevScb = pTmpScb;
  886. pTmpScb = pTmpScb->SCB_NxtScb;
  887. }
  888. return;
  889. }
  890. /***************************************************************************/
  891. SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun)
  892. {
  893. SCB *pTmpScb, *pPrevScb;
  894. WORD scbp_tarlun;
  895. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy;
  896. while (pTmpScb != NULL) {
  897. scbp_tarlun = (pTmpScb->SCB_Lun << 8) | (pTmpScb->SCB_Target);
  898. if (scbp_tarlun == tarlun) { /* Unlink this SCB */
  899. break;
  900. }
  901. pPrevScb = pTmpScb;
  902. pTmpScb = pTmpScb->SCB_NxtScb;
  903. }
  904. #if DEBUG_QUEUE
  905. printk("find busy SCB %lx; ", (ULONG) pTmpScb);
  906. #endif
  907. return (pTmpScb);
  908. }
  909. /***************************************************************************/
  910. void tul_append_done_scb(HCS * pCurHcb, SCB * scbp)
  911. {
  912. #if DEBUG_QUEUE
  913. printk("append done SCB %lx; ", (ULONG) scbp);
  914. #endif
  915. scbp->SCB_Status = SCB_DONE;
  916. scbp->SCB_NxtScb = NULL;
  917. if (pCurHcb->HCS_LastDone != NULL) {
  918. pCurHcb->HCS_LastDone->SCB_NxtScb = scbp;
  919. pCurHcb->HCS_LastDone = scbp;
  920. } else {
  921. pCurHcb->HCS_FirstDone = scbp;
  922. pCurHcb->HCS_LastDone = scbp;
  923. }
  924. }
  925. /***************************************************************************/
  926. SCB *tul_find_done_scb(HCS * pCurHcb)
  927. {
  928. SCB *pTmpScb;
  929. if ((pTmpScb = pCurHcb->HCS_FirstDone) != NULL) {
  930. if ((pCurHcb->HCS_FirstDone = pTmpScb->SCB_NxtScb) == NULL)
  931. pCurHcb->HCS_LastDone = NULL;
  932. pTmpScb->SCB_NxtScb = NULL;
  933. }
  934. #if DEBUG_QUEUE
  935. printk("find done SCB %lx; ", (ULONG) pTmpScb);
  936. #endif
  937. return (pTmpScb);
  938. }
  939. /***************************************************************************/
  940. int tul_abort_srb(HCS * pCurHcb, struct scsi_cmnd *srbp)
  941. {
  942. ULONG flags;
  943. SCB *pTmpScb, *pPrevScb;
  944. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  945. if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
  946. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  947. /* disable Jasmin SCSI Int */
  948. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  949. tulip_main(pCurHcb);
  950. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  951. pCurHcb->HCS_Semaph = 1;
  952. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  953. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  954. return SCSI_ABORT_SNOOZE;
  955. }
  956. pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend; /* Check Pend queue */
  957. while (pTmpScb != NULL) {
  958. /* 07/27/98 */
  959. if (pTmpScb->SCB_Srb == srbp) {
  960. if (pTmpScb == pCurHcb->HCS_ActScb) {
  961. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  962. return SCSI_ABORT_BUSY;
  963. } else if (pTmpScb == pCurHcb->HCS_FirstPend) {
  964. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  965. pCurHcb->HCS_LastPend = NULL;
  966. } else {
  967. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  968. if (pTmpScb == pCurHcb->HCS_LastPend)
  969. pCurHcb->HCS_LastPend = pPrevScb;
  970. }
  971. pTmpScb->SCB_HaStat = HOST_ABORTED;
  972. pTmpScb->SCB_Flags |= SCF_DONE;
  973. if (pTmpScb->SCB_Flags & SCF_POST)
  974. (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb);
  975. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  976. return SCSI_ABORT_SUCCESS;
  977. }
  978. pPrevScb = pTmpScb;
  979. pTmpScb = pTmpScb->SCB_NxtScb;
  980. }
  981. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  982. while (pTmpScb != NULL) {
  983. if (pTmpScb->SCB_Srb == srbp) {
  984. if (pTmpScb == pCurHcb->HCS_ActScb) {
  985. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  986. return SCSI_ABORT_BUSY;
  987. } else if (pTmpScb->SCB_TagMsg == 0) {
  988. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  989. return SCSI_ABORT_BUSY;
  990. } else {
  991. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  992. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  993. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  994. pCurHcb->HCS_LastBusy = NULL;
  995. } else {
  996. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  997. if (pTmpScb == pCurHcb->HCS_LastBusy)
  998. pCurHcb->HCS_LastBusy = pPrevScb;
  999. }
  1000. pTmpScb->SCB_NxtScb = NULL;
  1001. pTmpScb->SCB_HaStat = HOST_ABORTED;
  1002. pTmpScb->SCB_Flags |= SCF_DONE;
  1003. if (pTmpScb->SCB_Flags & SCF_POST)
  1004. (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb);
  1005. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1006. return SCSI_ABORT_SUCCESS;
  1007. }
  1008. }
  1009. pPrevScb = pTmpScb;
  1010. pTmpScb = pTmpScb->SCB_NxtScb;
  1011. }
  1012. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1013. return (SCSI_ABORT_NOT_RUNNING);
  1014. }
  1015. /***************************************************************************/
  1016. int tul_bad_seq(HCS * pCurHcb)
  1017. {
  1018. SCB *pCurScb;
  1019. printk("tul_bad_seg c=%d\n", pCurHcb->HCS_Index);
  1020. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
  1021. tul_unlink_busy_scb(pCurHcb, pCurScb);
  1022. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1023. pCurScb->SCB_TaStat = 0;
  1024. tul_append_done_scb(pCurHcb, pCurScb);
  1025. }
  1026. tul_stop_bm(pCurHcb);
  1027. tul_reset_scsi(pCurHcb, 8); /* 7/29/98 */
  1028. return (tul_post_scsi_rst(pCurHcb));
  1029. }
  1030. /************************************************************************/
  1031. int tul_device_reset(HCS * pCurHcb, struct scsi_cmnd *pSrb,
  1032. unsigned int target, unsigned int ResetFlags)
  1033. {
  1034. ULONG flags;
  1035. SCB *pScb;
  1036. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1037. if (ResetFlags & SCSI_RESET_ASYNCHRONOUS) {
  1038. if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
  1039. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1040. /* disable Jasmin SCSI Int */
  1041. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1042. tulip_main(pCurHcb);
  1043. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1044. pCurHcb->HCS_Semaph = 1;
  1045. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1046. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1047. return SCSI_RESET_SNOOZE;
  1048. }
  1049. pScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  1050. while (pScb != NULL) {
  1051. if (pScb->SCB_Srb == pSrb)
  1052. break;
  1053. pScb = pScb->SCB_NxtScb;
  1054. }
  1055. if (pScb == NULL) {
  1056. printk("Unable to Reset - No SCB Found\n");
  1057. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1058. return SCSI_RESET_NOT_RUNNING;
  1059. }
  1060. }
  1061. if ((pScb = tul_alloc_scb(pCurHcb)) == NULL) {
  1062. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1063. return SCSI_RESET_NOT_RUNNING;
  1064. }
  1065. pScb->SCB_Opcode = BusDevRst;
  1066. pScb->SCB_Flags = SCF_POST;
  1067. pScb->SCB_Target = target;
  1068. pScb->SCB_Mode = 0;
  1069. pScb->SCB_Srb = NULL;
  1070. if (ResetFlags & SCSI_RESET_SYNCHRONOUS) {
  1071. pScb->SCB_Srb = pSrb;
  1072. }
  1073. tul_push_pend_scb(pCurHcb, pScb); /* push this SCB to Pending queue */
  1074. if (pCurHcb->HCS_Semaph == 1) {
  1075. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1076. /* disable Jasmin SCSI Int */
  1077. pCurHcb->HCS_Semaph = 0;
  1078. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1079. tulip_main(pCurHcb);
  1080. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1081. pCurHcb->HCS_Semaph = 1;
  1082. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1083. }
  1084. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1085. return SCSI_RESET_PENDING;
  1086. }
  1087. int tul_reset_scsi_bus(HCS * pCurHcb)
  1088. {
  1089. ULONG flags;
  1090. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1091. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1092. pCurHcb->HCS_Semaph = 0;
  1093. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1094. tul_stop_bm(pCurHcb);
  1095. tul_reset_scsi(pCurHcb, 2); /* 7/29/98 */
  1096. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1097. tul_post_scsi_rst(pCurHcb);
  1098. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1099. tulip_main(pCurHcb);
  1100. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1101. pCurHcb->HCS_Semaph = 1;
  1102. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1103. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1104. return (SCSI_RESET_SUCCESS | SCSI_RESET_HOST_RESET);
  1105. }
  1106. /************************************************************************/
  1107. void tul_exec_scb(HCS * pCurHcb, SCB * pCurScb)
  1108. {
  1109. ULONG flags;
  1110. pCurScb->SCB_Mode = 0;
  1111. pCurScb->SCB_SGIdx = 0;
  1112. pCurScb->SCB_SGMax = pCurScb->SCB_SGLen;
  1113. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1114. tul_append_pend_scb(pCurHcb, pCurScb); /* Append this SCB to Pending queue */
  1115. /* VVVVV 07/21/98 */
  1116. if (pCurHcb->HCS_Semaph == 1) {
  1117. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1118. /* disable Jasmin SCSI Int */
  1119. pCurHcb->HCS_Semaph = 0;
  1120. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1121. tulip_main(pCurHcb);
  1122. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1123. pCurHcb->HCS_Semaph = 1;
  1124. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1125. }
  1126. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1127. return;
  1128. }
  1129. /***************************************************************************/
  1130. int tul_isr(HCS * pCurHcb)
  1131. {
  1132. /* Enter critical section */
  1133. if (TUL_RD(pCurHcb->HCS_Base, TUL_Int) & TSS_INT_PENDING) {
  1134. if (pCurHcb->HCS_Semaph == 1) {
  1135. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1136. /* Disable Tulip SCSI Int */
  1137. pCurHcb->HCS_Semaph = 0;
  1138. tulip_main(pCurHcb);
  1139. pCurHcb->HCS_Semaph = 1;
  1140. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1141. return (1);
  1142. }
  1143. }
  1144. return (0);
  1145. }
  1146. /***************************************************************************/
  1147. int tulip_main(HCS * pCurHcb)
  1148. {
  1149. SCB *pCurScb;
  1150. for (;;) {
  1151. tulip_scsi(pCurHcb); /* Call tulip_scsi */
  1152. while ((pCurScb = tul_find_done_scb(pCurHcb)) != NULL) { /* find done entry */
  1153. if (pCurScb->SCB_TaStat == INI_QUEUE_FULL) {
  1154. pCurHcb->HCS_MaxTags[pCurScb->SCB_Target] =
  1155. pCurHcb->HCS_ActTags[pCurScb->SCB_Target] - 1;
  1156. pCurScb->SCB_TaStat = 0;
  1157. tul_append_pend_scb(pCurHcb, pCurScb);
  1158. continue;
  1159. }
  1160. if (!(pCurScb->SCB_Mode & SCM_RSENS)) { /* not in auto req. sense mode */
  1161. if (pCurScb->SCB_TaStat == 2) {
  1162. /* clr sync. nego flag */
  1163. if (pCurScb->SCB_Flags & SCF_SENSE) {
  1164. BYTE len;
  1165. len = pCurScb->SCB_SenseLen;
  1166. if (len == 0)
  1167. len = 1;
  1168. pCurScb->SCB_BufLen = pCurScb->SCB_SenseLen;
  1169. pCurScb->SCB_BufPtr = pCurScb->SCB_SensePtr;
  1170. pCurScb->SCB_Flags &= ~(SCF_SG | SCF_DIR); /* for xfer_data_in */
  1171. /* pCurScb->SCB_Flags |= SCF_NO_DCHK; */
  1172. /* so, we won't report worng direction in xfer_data_in,
  1173. and won't report HOST_DO_DU in state_6 */
  1174. pCurScb->SCB_Mode = SCM_RSENS;
  1175. pCurScb->SCB_Ident &= 0xBF; /* Disable Disconnect */
  1176. pCurScb->SCB_TagMsg = 0;
  1177. pCurScb->SCB_TaStat = 0;
  1178. pCurScb->SCB_CDBLen = 6;
  1179. pCurScb->SCB_CDB[0] = SCSICMD_RequestSense;
  1180. pCurScb->SCB_CDB[1] = 0;
  1181. pCurScb->SCB_CDB[2] = 0;
  1182. pCurScb->SCB_CDB[3] = 0;
  1183. pCurScb->SCB_CDB[4] = len;
  1184. pCurScb->SCB_CDB[5] = 0;
  1185. tul_push_pend_scb(pCurHcb, pCurScb);
  1186. break;
  1187. }
  1188. }
  1189. } else { /* in request sense mode */
  1190. if (pCurScb->SCB_TaStat == 2) { /* check contition status again after sending
  1191. requset sense cmd 0x3 */
  1192. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1193. }
  1194. pCurScb->SCB_TaStat = 2;
  1195. }
  1196. pCurScb->SCB_Flags |= SCF_DONE;
  1197. if (pCurScb->SCB_Flags & SCF_POST) {
  1198. (*pCurScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pCurScb);
  1199. }
  1200. } /* while */
  1201. /* find_active: */
  1202. if (TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0) & TSS_INT_PENDING)
  1203. continue;
  1204. if (pCurHcb->HCS_ActScb) { /* return to OS and wait for xfer_done_ISR/Selected_ISR */
  1205. return 1; /* return to OS, enable interrupt */
  1206. }
  1207. /* Check pending SCB */
  1208. if (tul_find_first_pend_scb(pCurHcb) == NULL) {
  1209. return 1; /* return to OS, enable interrupt */
  1210. }
  1211. } /* End of for loop */
  1212. /* statement won't reach here */
  1213. }
  1214. /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
  1215. /***************************************************************************/
  1216. /***************************************************************************/
  1217. /***************************************************************************/
  1218. /***************************************************************************/
  1219. /***************************************************************************/
  1220. void tulip_scsi(HCS * pCurHcb)
  1221. {
  1222. SCB *pCurScb;
  1223. TCS *pCurTcb;
  1224. /* make sure to service interrupt asap */
  1225. if ((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0)) & TSS_INT_PENDING) {
  1226. pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK;
  1227. pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1);
  1228. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  1229. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* SCSI bus reset detected */
  1230. int_tul_scsi_rst(pCurHcb);
  1231. return;
  1232. }
  1233. if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if selected/reselected interrupt */
  1234. if (int_tul_resel(pCurHcb) == 0)
  1235. tul_next_state(pCurHcb);
  1236. return;
  1237. }
  1238. if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) {
  1239. int_tul_busfree(pCurHcb);
  1240. return;
  1241. }
  1242. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  1243. int_tul_busfree(pCurHcb); /* unexpected bus free or sel timeout */
  1244. return;
  1245. }
  1246. if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) { /* func complete or Bus service */
  1247. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL)
  1248. tul_next_state(pCurHcb);
  1249. return;
  1250. }
  1251. }
  1252. if (pCurHcb->HCS_ActScb != NULL)
  1253. return;
  1254. if ((pCurScb = tul_find_first_pend_scb(pCurHcb)) == NULL)
  1255. return;
  1256. /* program HBA's SCSI ID & target SCSI ID */
  1257. TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId,
  1258. (pCurHcb->HCS_SCSI_ID << 4) | (pCurScb->SCB_Target & 0x0F));
  1259. if (pCurScb->SCB_Opcode == ExecSCSI) {
  1260. pCurTcb = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  1261. if (pCurScb->SCB_TagMsg)
  1262. pCurTcb->TCS_DrvFlags |= TCF_DRV_EN_TAG;
  1263. else
  1264. pCurTcb->TCS_DrvFlags &= ~TCF_DRV_EN_TAG;
  1265. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period);
  1266. if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) { /* do wdtr negotiation */
  1267. tul_select_atn_stop(pCurHcb, pCurScb);
  1268. } else {
  1269. if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync negotiation */
  1270. tul_select_atn_stop(pCurHcb, pCurScb);
  1271. } else {
  1272. if (pCurScb->SCB_TagMsg)
  1273. tul_select_atn3(pCurHcb, pCurScb);
  1274. else
  1275. tul_select_atn(pCurHcb, pCurScb);
  1276. }
  1277. }
  1278. if (pCurScb->SCB_Flags & SCF_POLL) {
  1279. while (wait_tulip(pCurHcb) != -1) {
  1280. if (tul_next_state(pCurHcb) == -1)
  1281. break;
  1282. }
  1283. }
  1284. } else if (pCurScb->SCB_Opcode == BusDevRst) {
  1285. tul_select_atn_stop(pCurHcb, pCurScb);
  1286. pCurScb->SCB_NxtStat = 8;
  1287. if (pCurScb->SCB_Flags & SCF_POLL) {
  1288. while (wait_tulip(pCurHcb) != -1) {
  1289. if (tul_next_state(pCurHcb) == -1)
  1290. break;
  1291. }
  1292. }
  1293. } else if (pCurScb->SCB_Opcode == AbortCmd) {
  1294. if (tul_abort_srb(pCurHcb, pCurScb->SCB_Srb) != 0) {
  1295. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1296. tul_release_scb(pCurHcb, pCurScb);
  1297. } else {
  1298. pCurScb->SCB_Opcode = BusDevRst;
  1299. tul_select_atn_stop(pCurHcb, pCurScb);
  1300. pCurScb->SCB_NxtStat = 8;
  1301. }
  1302. /* 08/03/98 */
  1303. } else {
  1304. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1305. pCurScb->SCB_HaStat = 0x16; /* bad command */
  1306. tul_append_done_scb(pCurHcb, pCurScb);
  1307. }
  1308. return;
  1309. }
  1310. /***************************************************************************/
  1311. int tul_next_state(HCS * pCurHcb)
  1312. {
  1313. int next;
  1314. next = pCurHcb->HCS_ActScb->SCB_NxtStat;
  1315. for (;;) {
  1316. switch (next) {
  1317. case 1:
  1318. next = tul_state_1(pCurHcb);
  1319. break;
  1320. case 2:
  1321. next = tul_state_2(pCurHcb);
  1322. break;
  1323. case 3:
  1324. next = tul_state_3(pCurHcb);
  1325. break;
  1326. case 4:
  1327. next = tul_state_4(pCurHcb);
  1328. break;
  1329. case 5:
  1330. next = tul_state_5(pCurHcb);
  1331. break;
  1332. case 6:
  1333. next = tul_state_6(pCurHcb);
  1334. break;
  1335. case 7:
  1336. next = tul_state_7(pCurHcb);
  1337. break;
  1338. case 8:
  1339. return (tul_bus_device_reset(pCurHcb));
  1340. default:
  1341. return (tul_bad_seq(pCurHcb));
  1342. }
  1343. if (next <= 0)
  1344. return next;
  1345. }
  1346. }
  1347. /***************************************************************************/
  1348. /* sTate after selection with attention & stop */
  1349. int tul_state_1(HCS * pCurHcb)
  1350. {
  1351. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1352. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1353. #if DEBUG_STATE
  1354. printk("-s1-");
  1355. #endif
  1356. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1357. tul_append_busy_scb(pCurHcb, pCurScb);
  1358. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1359. /* ATN on */
  1360. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1361. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, (TSC_EN_BUS_IN | TSC_HW_RESELECT));
  1362. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  1363. if (pCurScb->SCB_TagMsg) {
  1364. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg);
  1365. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId);
  1366. }
  1367. if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) {
  1368. pCurTcb->TCS_Flags |= TCF_WDTR_DONE;
  1369. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1370. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2); /* Extended msg length */
  1371. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* Sync request */
  1372. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* Start from 16 bits */
  1373. } else if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) {
  1374. pCurTcb->TCS_Flags |= TCF_SYNC_DONE;
  1375. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1376. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* extended msg length */
  1377. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */
  1378. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]);
  1379. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */
  1380. }
  1381. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1382. if (wait_tulip(pCurHcb) == -1)
  1383. return (-1);
  1384. }
  1385. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1386. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1387. return (3);
  1388. }
  1389. /***************************************************************************/
  1390. /* state after selection with attention */
  1391. /* state after selection with attention3 */
  1392. int tul_state_2(HCS * pCurHcb)
  1393. {
  1394. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1395. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1396. #if DEBUG_STATE
  1397. printk("-s2-");
  1398. #endif
  1399. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1400. tul_append_busy_scb(pCurHcb, pCurScb);
  1401. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1402. if (pCurHcb->HCS_JSStatus1 & TSS_CMD_PH_CMP) {
  1403. return (4);
  1404. }
  1405. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1406. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1407. return (3);
  1408. }
  1409. /***************************************************************************/
  1410. /* state before CDB xfer is done */
  1411. int tul_state_3(HCS * pCurHcb)
  1412. {
  1413. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1414. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1415. int i;
  1416. #if DEBUG_STATE
  1417. printk("-s3-");
  1418. #endif
  1419. for (;;) {
  1420. switch (pCurHcb->HCS_Phase) {
  1421. case CMD_OUT: /* Command out phase */
  1422. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  1423. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  1424. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1425. if (wait_tulip(pCurHcb) == -1)
  1426. return (-1);
  1427. if (pCurHcb->HCS_Phase == CMD_OUT) {
  1428. return (tul_bad_seq(pCurHcb));
  1429. }
  1430. return (4);
  1431. case MSG_IN: /* Message in phase */
  1432. pCurScb->SCB_NxtStat = 3;
  1433. if (tul_msgin(pCurHcb) == -1)
  1434. return (-1);
  1435. break;
  1436. case STATUS_IN: /* Status phase */
  1437. if (tul_status_msg(pCurHcb) == -1)
  1438. return (-1);
  1439. break;
  1440. case MSG_OUT: /* Message out phase */
  1441. if (pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) {
  1442. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1443. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1444. if (wait_tulip(pCurHcb) == -1)
  1445. return (-1);
  1446. } else {
  1447. pCurTcb->TCS_Flags |= TCF_SYNC_DONE;
  1448. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1449. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* ext. msg len */
  1450. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */
  1451. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]);
  1452. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */
  1453. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1454. if (wait_tulip(pCurHcb) == -1)
  1455. return (-1);
  1456. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1457. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7));
  1458. }
  1459. break;
  1460. default:
  1461. return (tul_bad_seq(pCurHcb));
  1462. }
  1463. }
  1464. }
  1465. /***************************************************************************/
  1466. int tul_state_4(HCS * pCurHcb)
  1467. {
  1468. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1469. #if DEBUG_STATE
  1470. printk("-s4-");
  1471. #endif
  1472. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_NO_XF) {
  1473. return (6); /* Go to state 6 */
  1474. }
  1475. for (;;) {
  1476. if (pCurScb->SCB_BufLen == 0)
  1477. return (6); /* Go to state 6 */
  1478. switch (pCurHcb->HCS_Phase) {
  1479. case STATUS_IN: /* Status phase */
  1480. if ((pCurScb->SCB_Flags & SCF_DIR) != 0) { /* if direction bit set then report data underrun */
  1481. pCurScb->SCB_HaStat = HOST_DO_DU;
  1482. }
  1483. if ((tul_status_msg(pCurHcb)) == -1)
  1484. return (-1);
  1485. break;
  1486. case MSG_IN: /* Message in phase */
  1487. pCurScb->SCB_NxtStat = 0x4;
  1488. if (tul_msgin(pCurHcb) == -1)
  1489. return (-1);
  1490. break;
  1491. case MSG_OUT: /* Message out phase */
  1492. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1493. pCurScb->SCB_BufLen = 0;
  1494. pCurScb->SCB_HaStat = HOST_DO_DU;
  1495. if (tul_msgout_ide(pCurHcb) == -1)
  1496. return (-1);
  1497. return (6); /* Go to state 6 */
  1498. } else {
  1499. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1500. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1501. if (wait_tulip(pCurHcb) == -1)
  1502. return (-1);
  1503. }
  1504. break;
  1505. case DATA_IN: /* Data in phase */
  1506. return (tul_xfer_data_in(pCurHcb));
  1507. case DATA_OUT: /* Data out phase */
  1508. return (tul_xfer_data_out(pCurHcb));
  1509. default:
  1510. return (tul_bad_seq(pCurHcb));
  1511. }
  1512. }
  1513. }
  1514. /***************************************************************************/
  1515. /* state after dma xfer done or phase change before xfer done */
  1516. int tul_state_5(HCS * pCurHcb)
  1517. {
  1518. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1519. long cnt, xcnt; /* cannot use unsigned !! code: if (xcnt < 0) */
  1520. #if DEBUG_STATE
  1521. printk("-s5-");
  1522. #endif
  1523. /*------ get remaining count -------*/
  1524. cnt = TUL_RDLONG(pCurHcb->HCS_Base, TUL_SCnt0) & 0x0FFFFFF;
  1525. if (TUL_RD(pCurHcb->HCS_Base, TUL_XCmd) & 0x20) {
  1526. /* ----------------------- DATA_IN ----------------------------- */
  1527. /* check scsi parity error */
  1528. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1529. pCurScb->SCB_HaStat = HOST_DO_DU;
  1530. }
  1531. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* DMA xfer pending, Send STOP */
  1532. /* tell Hardware scsi xfer has been terminated */
  1533. TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, TUL_RD(pCurHcb->HCS_Base, TUL_XCtrl) | 0x80);
  1534. /* wait until DMA xfer not pending */
  1535. while (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND);
  1536. }
  1537. } else {
  1538. /*-------- DATA OUT -----------*/
  1539. if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0) {
  1540. if (pCurHcb->HCS_ActTcs->TCS_JS_Period & TSC_WIDE_SCSI)
  1541. cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F) << 1;
  1542. else
  1543. cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F);
  1544. }
  1545. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
  1546. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT);
  1547. /* wait Abort DMA xfer done */
  1548. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0);
  1549. }
  1550. if ((cnt == 1) && (pCurHcb->HCS_Phase == DATA_OUT)) {
  1551. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1552. if (wait_tulip(pCurHcb) == -1) {
  1553. return (-1);
  1554. }
  1555. cnt = 0;
  1556. } else {
  1557. if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0)
  1558. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1559. }
  1560. }
  1561. if (cnt == 0) {
  1562. pCurScb->SCB_BufLen = 0;
  1563. return (6); /* Go to state 6 */
  1564. }
  1565. /* Update active data pointer */
  1566. xcnt = (long) pCurScb->SCB_BufLen - cnt; /* xcnt== bytes already xferred */
  1567. pCurScb->SCB_BufLen = (U32) cnt; /* cnt == bytes left to be xferred */
  1568. if (pCurScb->SCB_Flags & SCF_SG) {
  1569. register SG *sgp;
  1570. ULONG i;
  1571. sgp = &pCurScb->SCB_SGList[pCurScb->SCB_SGIdx];
  1572. for (i = pCurScb->SCB_SGIdx; i < pCurScb->SCB_SGMax; sgp++, i++) {
  1573. xcnt -= (long) sgp->SG_Len;
  1574. if (xcnt < 0) { /* this sgp xfer half done */
  1575. xcnt += (long) sgp->SG_Len; /* xcnt == bytes xferred in this sgp */
  1576. sgp->SG_Ptr += (U32) xcnt; /* new ptr to be xfer */
  1577. sgp->SG_Len -= (U32) xcnt; /* new len to be xfer */
  1578. pCurScb->SCB_BufPtr += ((U32) (i - pCurScb->SCB_SGIdx) << 3);
  1579. /* new SG table ptr */
  1580. pCurScb->SCB_SGLen = (BYTE) (pCurScb->SCB_SGMax - i);
  1581. /* new SG table len */
  1582. pCurScb->SCB_SGIdx = (WORD) i;
  1583. /* for next disc and come in this loop */
  1584. return (4); /* Go to state 4 */
  1585. }
  1586. /* else (xcnt >= 0 , i.e. this sgp already xferred */
  1587. } /* for */
  1588. return (6); /* Go to state 6 */
  1589. } else {
  1590. pCurScb->SCB_BufPtr += (U32) xcnt;
  1591. }
  1592. return (4); /* Go to state 4 */
  1593. }
  1594. /***************************************************************************/
  1595. /* state after Data phase */
  1596. int tul_state_6(HCS * pCurHcb)
  1597. {
  1598. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1599. #if DEBUG_STATE
  1600. printk("-s6-");
  1601. #endif
  1602. for (;;) {
  1603. switch (pCurHcb->HCS_Phase) {
  1604. case STATUS_IN: /* Status phase */
  1605. if ((tul_status_msg(pCurHcb)) == -1)
  1606. return (-1);
  1607. break;
  1608. case MSG_IN: /* Message in phase */
  1609. pCurScb->SCB_NxtStat = 6;
  1610. if ((tul_msgin(pCurHcb)) == -1)
  1611. return (-1);
  1612. break;
  1613. case MSG_OUT: /* Message out phase */
  1614. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1615. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1616. if (wait_tulip(pCurHcb) == -1)
  1617. return (-1);
  1618. break;
  1619. case DATA_IN: /* Data in phase */
  1620. return (tul_xpad_in(pCurHcb));
  1621. case DATA_OUT: /* Data out phase */
  1622. return (tul_xpad_out(pCurHcb));
  1623. default:
  1624. return (tul_bad_seq(pCurHcb));
  1625. }
  1626. }
  1627. }
  1628. /***************************************************************************/
  1629. int tul_state_7(HCS * pCurHcb)
  1630. {
  1631. int cnt, i;
  1632. #if DEBUG_STATE
  1633. printk("-s7-");
  1634. #endif
  1635. /* flush SCSI FIFO */
  1636. cnt = TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F;
  1637. if (cnt) {
  1638. for (i = 0; i < cnt; i++)
  1639. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1640. }
  1641. switch (pCurHcb->HCS_Phase) {
  1642. case DATA_IN: /* Data in phase */
  1643. case DATA_OUT: /* Data out phase */
  1644. return (tul_bad_seq(pCurHcb));
  1645. default:
  1646. return (6); /* Go to state 6 */
  1647. }
  1648. }
  1649. /***************************************************************************/
  1650. int tul_xfer_data_in(HCS * pCurHcb)
  1651. {
  1652. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1653. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DOUT) {
  1654. return (6); /* wrong direction */
  1655. }
  1656. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
  1657. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_IN); /* 7/25/95 */
  1658. if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */
  1659. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3);
  1660. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1661. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_IN);
  1662. } else {
  1663. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen);
  1664. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1665. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_IN);
  1666. }
  1667. pCurScb->SCB_NxtStat = 0x5;
  1668. return (0); /* return to OS, wait xfer done , let jas_isr come in */
  1669. }
  1670. /***************************************************************************/
  1671. int tul_xfer_data_out(HCS * pCurHcb)
  1672. {
  1673. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1674. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DIN) {
  1675. return (6); /* wrong direction */
  1676. }
  1677. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
  1678. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_OUT);
  1679. if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */
  1680. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3);
  1681. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1682. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_OUT);
  1683. } else {
  1684. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen);
  1685. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1686. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_OUT);
  1687. }
  1688. pCurScb->SCB_NxtStat = 0x5;
  1689. return (0); /* return to OS, wait xfer done , let jas_isr come in */
  1690. }
  1691. /***************************************************************************/
  1692. int tul_xpad_in(HCS * pCurHcb)
  1693. {
  1694. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1695. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1696. if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) {
  1697. pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */
  1698. }
  1699. for (;;) {
  1700. if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI)
  1701. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2);
  1702. else
  1703. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1704. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1705. if ((wait_tulip(pCurHcb)) == -1) {
  1706. return (-1);
  1707. }
  1708. if (pCurHcb->HCS_Phase != DATA_IN) {
  1709. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1710. return (6);
  1711. }
  1712. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1713. }
  1714. }
  1715. int tul_xpad_out(HCS * pCurHcb)
  1716. {
  1717. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1718. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1719. if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) {
  1720. pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */
  1721. }
  1722. for (;;) {
  1723. if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI)
  1724. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2);
  1725. else
  1726. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1727. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0);
  1728. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1729. if ((wait_tulip(pCurHcb)) == -1) {
  1730. return (-1);
  1731. }
  1732. if (pCurHcb->HCS_Phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */
  1733. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT);
  1734. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1735. return (6);
  1736. }
  1737. }
  1738. }
  1739. /***************************************************************************/
  1740. int tul_status_msg(HCS * pCurHcb)
  1741. { /* status & MSG_IN */
  1742. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1743. BYTE msg;
  1744. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_CMD_COMP);
  1745. if ((wait_tulip(pCurHcb)) == -1) {
  1746. return (-1);
  1747. }
  1748. /* get status */
  1749. pCurScb->SCB_TaStat = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1750. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1751. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1752. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY);
  1753. } else {
  1754. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP);
  1755. }
  1756. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1757. return (wait_tulip(pCurHcb));
  1758. }
  1759. if (pCurHcb->HCS_Phase == MSG_IN) {
  1760. msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1761. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { /* Parity error */
  1762. if ((tul_msgin_accept(pCurHcb)) == -1)
  1763. return (-1);
  1764. if (pCurHcb->HCS_Phase != MSG_OUT)
  1765. return (tul_bad_seq(pCurHcb));
  1766. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY);
  1767. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1768. return (wait_tulip(pCurHcb));
  1769. }
  1770. if (msg == 0) { /* Command complete */
  1771. if ((pCurScb->SCB_TaStat & 0x18) == 0x10) { /* No link support */
  1772. return (tul_bad_seq(pCurHcb));
  1773. }
  1774. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1775. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1776. return tul_wait_done_disc(pCurHcb);
  1777. }
  1778. if ((msg == MSG_LINK_COMP) || (msg == MSG_LINK_FLAG)) {
  1779. if ((pCurScb->SCB_TaStat & 0x18) == 0x10)
  1780. return (tul_msgin_accept(pCurHcb));
  1781. }
  1782. }
  1783. return (tul_bad_seq(pCurHcb));
  1784. }
  1785. /***************************************************************************/
  1786. /* scsi bus free */
  1787. int int_tul_busfree(HCS * pCurHcb)
  1788. {
  1789. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1790. if (pCurScb != NULL) {
  1791. if (pCurScb->SCB_Status & SCB_SELECT) { /* selection timeout */
  1792. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1793. pCurScb->SCB_HaStat = HOST_SEL_TOUT;
  1794. tul_append_done_scb(pCurHcb, pCurScb);
  1795. } else { /* Unexpected bus free */
  1796. tul_unlink_busy_scb(pCurHcb, pCurScb);
  1797. pCurScb->SCB_HaStat = HOST_BUS_FREE;
  1798. tul_append_done_scb(pCurHcb, pCurScb);
  1799. }
  1800. pCurHcb->HCS_ActScb = NULL;
  1801. pCurHcb->HCS_ActTcs = NULL;
  1802. }
  1803. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  1804. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  1805. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  1806. return (-1);
  1807. }
  1808. /***************************************************************************/
  1809. /* scsi bus reset */
  1810. int int_tul_scsi_rst(HCS * pCurHcb)
  1811. {
  1812. SCB *pCurScb;
  1813. int i;
  1814. /* if DMA xfer is pending, abort DMA xfer */
  1815. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & 0x01) {
  1816. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
  1817. /* wait Abort DMA xfer done */
  1818. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & 0x04) == 0);
  1819. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1820. }
  1821. /* Abort all active & disconnected scb */
  1822. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  1823. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1824. tul_append_done_scb(pCurHcb, pCurScb);
  1825. }
  1826. pCurHcb->HCS_ActScb = NULL;
  1827. pCurHcb->HCS_ActTcs = NULL;
  1828. /* clr sync nego. done flag */
  1829. for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
  1830. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  1831. }
  1832. return (-1);
  1833. }
  1834. /***************************************************************************/
  1835. /* scsi reselection */
  1836. int int_tul_resel(HCS * pCurHcb)
  1837. {
  1838. SCB *pCurScb;
  1839. TCS *pCurTcb;
  1840. BYTE tag, msg = 0;
  1841. BYTE tar, lun;
  1842. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
  1843. if (pCurScb->SCB_Status & SCB_SELECT) { /* if waiting for selection complete */
  1844. pCurScb->SCB_Status &= ~SCB_SELECT;
  1845. }
  1846. pCurHcb->HCS_ActScb = NULL;
  1847. }
  1848. /* --------- get target id---------------------- */
  1849. tar = TUL_RD(pCurHcb->HCS_Base, TUL_SBusId);
  1850. /* ------ get LUN from Identify message----------- */
  1851. lun = TUL_RD(pCurHcb->HCS_Base, TUL_SIdent) & 0x0F;
  1852. /* 07/22/98 from 0x1F -> 0x0F */
  1853. pCurTcb = &pCurHcb->HCS_Tcs[tar];
  1854. pCurHcb->HCS_ActTcs = pCurTcb;
  1855. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1856. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period);
  1857. /* ------------- tag queueing ? ------------------- */
  1858. if (pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG) {
  1859. if ((tul_msgin_accept(pCurHcb)) == -1)
  1860. return (-1);
  1861. if (pCurHcb->HCS_Phase != MSG_IN)
  1862. goto no_tag;
  1863. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1864. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1865. if ((wait_tulip(pCurHcb)) == -1)
  1866. return (-1);
  1867. msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag Message */
  1868. if ((msg < MSG_STAG) || (msg > MSG_OTAG)) /* Is simple Tag */
  1869. goto no_tag;
  1870. if ((tul_msgin_accept(pCurHcb)) == -1)
  1871. return (-1);
  1872. if (pCurHcb->HCS_Phase != MSG_IN)
  1873. goto no_tag;
  1874. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1875. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1876. if ((wait_tulip(pCurHcb)) == -1)
  1877. return (-1);
  1878. tag = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag ID */
  1879. pCurScb = pCurHcb->HCS_Scb + tag;
  1880. if ((pCurScb->SCB_Target != tar) || (pCurScb->SCB_Lun != lun)) {
  1881. return tul_msgout_abort_tag(pCurHcb);
  1882. }
  1883. if (pCurScb->SCB_Status != SCB_BUSY) { /* 03/24/95 */
  1884. return tul_msgout_abort_tag(pCurHcb);
  1885. }
  1886. pCurHcb->HCS_ActScb = pCurScb;
  1887. if ((tul_msgin_accept(pCurHcb)) == -1)
  1888. return (-1);
  1889. } else { /* No tag */
  1890. no_tag:
  1891. if ((pCurScb = tul_find_busy_scb(pCurHcb, tar | (lun << 8))) == NULL) {
  1892. return tul_msgout_abort_targ(pCurHcb);
  1893. }
  1894. pCurHcb->HCS_ActScb = pCurScb;
  1895. if (!(pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG)) {
  1896. if ((tul_msgin_accept(pCurHcb)) == -1)
  1897. return (-1);
  1898. }
  1899. }
  1900. return 0;
  1901. }
  1902. /***************************************************************************/
  1903. int int_tul_bad_seq(HCS * pCurHcb)
  1904. { /* target wrong phase */
  1905. SCB *pCurScb;
  1906. int i;
  1907. tul_reset_scsi(pCurHcb, 10);
  1908. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  1909. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1910. tul_append_done_scb(pCurHcb, pCurScb);
  1911. }
  1912. for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
  1913. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  1914. }
  1915. return (-1);
  1916. }
  1917. /***************************************************************************/
  1918. int tul_msgout_abort_targ(HCS * pCurHcb)
  1919. {
  1920. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1921. if (tul_msgin_accept(pCurHcb) == -1)
  1922. return (-1);
  1923. if (pCurHcb->HCS_Phase != MSG_OUT)
  1924. return (tul_bad_seq(pCurHcb));
  1925. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT);
  1926. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1927. return tul_wait_disc(pCurHcb);
  1928. }
  1929. /***************************************************************************/
  1930. int tul_msgout_abort_tag(HCS * pCurHcb)
  1931. {
  1932. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1933. if (tul_msgin_accept(pCurHcb) == -1)
  1934. return (-1);
  1935. if (pCurHcb->HCS_Phase != MSG_OUT)
  1936. return (tul_bad_seq(pCurHcb));
  1937. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT_TAG);
  1938. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1939. return tul_wait_disc(pCurHcb);
  1940. }
  1941. /***************************************************************************/
  1942. int tul_msgin(HCS * pCurHcb)
  1943. {
  1944. TCS *pCurTcb;
  1945. for (;;) {
  1946. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1947. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1948. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1949. if ((wait_tulip(pCurHcb)) == -1)
  1950. return (-1);
  1951. switch (TUL_RD(pCurHcb->HCS_Base, TUL_SFifo)) {
  1952. case MSG_DISC: /* Disconnect msg */
  1953. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1954. return tul_wait_disc(pCurHcb);
  1955. case MSG_SDP:
  1956. case MSG_RESTORE:
  1957. case MSG_NOP:
  1958. tul_msgin_accept(pCurHcb);
  1959. break;
  1960. case MSG_REJ: /* Clear ATN first */
  1961. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal,
  1962. (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1963. pCurTcb = pCurHcb->HCS_ActTcs;
  1964. if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync nego */
  1965. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1966. }
  1967. tul_msgin_accept(pCurHcb);
  1968. break;
  1969. case MSG_EXTEND: /* extended msg */
  1970. tul_msgin_extend(pCurHcb);
  1971. break;
  1972. case MSG_IGNOREWIDE:
  1973. tul_msgin_accept(pCurHcb);
  1974. break;
  1975. /* get */
  1976. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1977. if (wait_tulip(pCurHcb) == -1)
  1978. return -1;
  1979. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0); /* put pad */
  1980. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get IGNORE field */
  1981. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get pad */
  1982. tul_msgin_accept(pCurHcb);
  1983. break;
  1984. case MSG_COMP:
  1985. {
  1986. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1987. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1988. return tul_wait_done_disc(pCurHcb);
  1989. }
  1990. default:
  1991. tul_msgout_reject(pCurHcb);
  1992. break;
  1993. }
  1994. if (pCurHcb->HCS_Phase != MSG_IN)
  1995. return (pCurHcb->HCS_Phase);
  1996. }
  1997. /* statement won't reach here */
  1998. }
  1999. /***************************************************************************/
  2000. int tul_msgout_reject(HCS * pCurHcb)
  2001. {
  2002. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2003. if ((tul_msgin_accept(pCurHcb)) == -1)
  2004. return (-1);
  2005. if (pCurHcb->HCS_Phase == MSG_OUT) {
  2006. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_REJ); /* Msg reject */
  2007. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2008. return (wait_tulip(pCurHcb));
  2009. }
  2010. return (pCurHcb->HCS_Phase);
  2011. }
  2012. /***************************************************************************/
  2013. int tul_msgout_ide(HCS * pCurHcb)
  2014. {
  2015. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_IDE); /* Initiator Detected Error */
  2016. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2017. return (wait_tulip(pCurHcb));
  2018. }
  2019. /***************************************************************************/
  2020. int tul_msgin_extend(HCS * pCurHcb)
  2021. {
  2022. BYTE len, idx;
  2023. if (tul_msgin_accept(pCurHcb) != MSG_IN)
  2024. return (pCurHcb->HCS_Phase);
  2025. /* Get extended msg length */
  2026. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  2027. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  2028. if (wait_tulip(pCurHcb) == -1)
  2029. return (-1);
  2030. len = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  2031. pCurHcb->HCS_Msg[0] = len;
  2032. for (idx = 1; len != 0; len--) {
  2033. if ((tul_msgin_accept(pCurHcb)) != MSG_IN)
  2034. return (pCurHcb->HCS_Phase);
  2035. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  2036. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  2037. if (wait_tulip(pCurHcb) == -1)
  2038. return (-1);
  2039. pCurHcb->HCS_Msg[idx++] = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  2040. }
  2041. if (pCurHcb->HCS_Msg[1] == 1) { /* if it's synchronous data transfer request */
  2042. if (pCurHcb->HCS_Msg[0] != 3) /* if length is not right */
  2043. return (tul_msgout_reject(pCurHcb));
  2044. if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_SYNC_NEGO) { /* Set OFFSET=0 to do async, nego back */
  2045. pCurHcb->HCS_Msg[3] = 0;
  2046. } else {
  2047. if ((tul_msgin_sync(pCurHcb) == 0) &&
  2048. (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SYNC_DONE)) {
  2049. tul_sync_done(pCurHcb);
  2050. return (tul_msgin_accept(pCurHcb));
  2051. }
  2052. }
  2053. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2054. if ((tul_msgin_accept(pCurHcb)) != MSG_OUT)
  2055. return (pCurHcb->HCS_Phase);
  2056. /* sync msg out */
  2057. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  2058. tul_sync_done(pCurHcb);
  2059. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  2060. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3);
  2061. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1);
  2062. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]);
  2063. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[3]);
  2064. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2065. return (wait_tulip(pCurHcb));
  2066. }
  2067. if ((pCurHcb->HCS_Msg[0] != 2) || (pCurHcb->HCS_Msg[1] != 3))
  2068. return (tul_msgout_reject(pCurHcb));
  2069. /* if it's WIDE DATA XFER REQ */
  2070. if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) {
  2071. pCurHcb->HCS_Msg[2] = 0;
  2072. } else {
  2073. if (pCurHcb->HCS_Msg[2] > 2) /* > 32 bits */
  2074. return (tul_msgout_reject(pCurHcb));
  2075. if (pCurHcb->HCS_Msg[2] == 2) { /* == 32 */
  2076. pCurHcb->HCS_Msg[2] = 1;
  2077. } else {
  2078. if ((pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) == 0) {
  2079. wdtr_done(pCurHcb);
  2080. if ((pCurHcb->HCS_ActTcs->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0)
  2081. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2082. return (tul_msgin_accept(pCurHcb));
  2083. }
  2084. }
  2085. }
  2086. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2087. if (tul_msgin_accept(pCurHcb) != MSG_OUT)
  2088. return (pCurHcb->HCS_Phase);
  2089. /* WDTR msg out */
  2090. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  2091. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2);
  2092. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3);
  2093. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]);
  2094. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2095. return (wait_tulip(pCurHcb));
  2096. }
  2097. /***************************************************************************/
  2098. int tul_msgin_sync(HCS * pCurHcb)
  2099. {
  2100. char default_period;
  2101. default_period = tul_rate_tbl[pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SCSI_RATE];
  2102. if (pCurHcb->HCS_Msg[3] > MAX_OFFSET) {
  2103. pCurHcb->HCS_Msg[3] = MAX_OFFSET;
  2104. if (pCurHcb->HCS_Msg[2] < default_period) {
  2105. pCurHcb->HCS_Msg[2] = default_period;
  2106. return 1;
  2107. }
  2108. if (pCurHcb->HCS_Msg[2] >= 59) { /* Change to async */
  2109. pCurHcb->HCS_Msg[3] = 0;
  2110. }
  2111. return 1;
  2112. }
  2113. /* offset requests asynchronous transfers ? */
  2114. if (pCurHcb->HCS_Msg[3] == 0) {
  2115. return 0;
  2116. }
  2117. if (pCurHcb->HCS_Msg[2] < default_period) {
  2118. pCurHcb->HCS_Msg[2] = default_period;
  2119. return 1;
  2120. }
  2121. if (pCurHcb->HCS_Msg[2] >= 59) {
  2122. pCurHcb->HCS_Msg[3] = 0;
  2123. return 1;
  2124. }
  2125. return 0;
  2126. }
  2127. /***************************************************************************/
  2128. int wdtr_done(HCS * pCurHcb)
  2129. {
  2130. pCurHcb->HCS_ActTcs->TCS_Flags &= ~TCF_SYNC_DONE;
  2131. pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_WDTR_DONE;
  2132. pCurHcb->HCS_ActTcs->TCS_JS_Period = 0;
  2133. if (pCurHcb->HCS_Msg[2]) { /* if 16 bit */
  2134. pCurHcb->HCS_ActTcs->TCS_JS_Period |= TSC_WIDE_SCSI;
  2135. }
  2136. pCurHcb->HCS_ActTcs->TCS_SConfig0 &= ~TSC_ALT_PERIOD;
  2137. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0);
  2138. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
  2139. return 1;
  2140. }
  2141. /***************************************************************************/
  2142. int tul_sync_done(HCS * pCurHcb)
  2143. {
  2144. int i;
  2145. pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_SYNC_DONE;
  2146. if (pCurHcb->HCS_Msg[3]) {
  2147. pCurHcb->HCS_ActTcs->TCS_JS_Period |= pCurHcb->HCS_Msg[3];
  2148. for (i = 0; i < 8; i++) {
  2149. if (tul_rate_tbl[i] >= pCurHcb->HCS_Msg[2]) /* pick the big one */
  2150. break;
  2151. }
  2152. pCurHcb->HCS_ActTcs->TCS_JS_Period |= (i << 4);
  2153. pCurHcb->HCS_ActTcs->TCS_SConfig0 |= TSC_ALT_PERIOD;
  2154. }
  2155. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0);
  2156. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
  2157. return (-1);
  2158. }
  2159. int tul_post_scsi_rst(HCS * pCurHcb)
  2160. {
  2161. SCB *pCurScb;
  2162. TCS *pCurTcb;
  2163. int i;
  2164. pCurHcb->HCS_ActScb = NULL;
  2165. pCurHcb->HCS_ActTcs = NULL;
  2166. pCurHcb->HCS_Flags = 0;
  2167. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  2168. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  2169. tul_append_done_scb(pCurHcb, pCurScb);
  2170. }
  2171. /* clear sync done flag */
  2172. pCurTcb = &pCurHcb->HCS_Tcs[0];
  2173. for (i = 0; i < pCurHcb->HCS_MaxTar; pCurTcb++, i++) {
  2174. pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  2175. /* Initialize the sync. xfer register values to an asyn xfer */
  2176. pCurTcb->TCS_JS_Period = 0;
  2177. pCurTcb->TCS_SConfig0 = pCurHcb->HCS_SConf1;
  2178. pCurHcb->HCS_ActTags[0] = 0; /* 07/22/98 */
  2179. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY; /* 07/22/98 */
  2180. } /* for */
  2181. return (-1);
  2182. }
  2183. /***************************************************************************/
  2184. void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb)
  2185. {
  2186. pCurScb->SCB_Status |= SCB_SELECT;
  2187. pCurScb->SCB_NxtStat = 0x1;
  2188. pCurHcb->HCS_ActScb = pCurScb;
  2189. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2190. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SELATNSTOP);
  2191. return;
  2192. }
  2193. /***************************************************************************/
  2194. void tul_select_atn(HCS * pCurHcb, SCB * pCurScb)
  2195. {
  2196. int i;
  2197. pCurScb->SCB_Status |= SCB_SELECT;
  2198. pCurScb->SCB_NxtStat = 0x2;
  2199. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  2200. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  2201. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  2202. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2203. pCurHcb->HCS_ActScb = pCurScb;
  2204. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN);
  2205. return;
  2206. }
  2207. /***************************************************************************/
  2208. void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb)
  2209. {
  2210. int i;
  2211. pCurScb->SCB_Status |= SCB_SELECT;
  2212. pCurScb->SCB_NxtStat = 0x2;
  2213. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  2214. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg);
  2215. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId);
  2216. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  2217. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  2218. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2219. pCurHcb->HCS_ActScb = pCurScb;
  2220. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN3);
  2221. return;
  2222. }
  2223. /***************************************************************************/
  2224. /* SCSI Bus Device Reset */
  2225. int tul_bus_device_reset(HCS * pCurHcb)
  2226. {
  2227. SCB *pCurScb = pCurHcb->HCS_ActScb;
  2228. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  2229. SCB *pTmpScb, *pPrevScb;
  2230. BYTE tar;
  2231. if (pCurHcb->HCS_Phase != MSG_OUT) {
  2232. return (int_tul_bad_seq(pCurHcb)); /* Unexpected phase */
  2233. }
  2234. tul_unlink_pend_scb(pCurHcb, pCurScb);
  2235. tul_release_scb(pCurHcb, pCurScb);
  2236. tar = pCurScb->SCB_Target; /* target */
  2237. pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE | TCF_BUSY);
  2238. /* clr sync. nego & WDTR flags 07/22/98 */
  2239. /* abort all SCB with same target */
  2240. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  2241. while (pTmpScb != NULL) {
  2242. if (pTmpScb->SCB_Target == tar) {
  2243. /* unlink it */
  2244. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  2245. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  2246. pCurHcb->HCS_LastBusy = NULL;
  2247. } else {
  2248. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  2249. if (pTmpScb == pCurHcb->HCS_LastBusy)
  2250. pCurHcb->HCS_LastBusy = pPrevScb;
  2251. }
  2252. pTmpScb->SCB_HaStat = HOST_ABORTED;
  2253. tul_append_done_scb(pCurHcb, pTmpScb);
  2254. }
  2255. /* Previous haven't change */
  2256. else {
  2257. pPrevScb = pTmpScb;
  2258. }
  2259. pTmpScb = pTmpScb->SCB_NxtScb;
  2260. }
  2261. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_DEVRST);
  2262. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2263. return tul_wait_disc(pCurHcb);
  2264. }
  2265. /***************************************************************************/
  2266. int tul_msgin_accept(HCS * pCurHcb)
  2267. {
  2268. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  2269. return (wait_tulip(pCurHcb));
  2270. }
  2271. /***************************************************************************/
  2272. int wait_tulip(HCS * pCurHcb)
  2273. {
  2274. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2275. & TSS_INT_PENDING));
  2276. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2277. pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK;
  2278. pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1);
  2279. if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if SCSI bus reset detected */
  2280. return (int_tul_resel(pCurHcb));
  2281. }
  2282. if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) { /* if selected/reselected timeout interrupt */
  2283. return (int_tul_busfree(pCurHcb));
  2284. }
  2285. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2286. return (int_tul_scsi_rst(pCurHcb));
  2287. }
  2288. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2289. if (pCurHcb->HCS_Flags & HCF_EXPECT_DONE_DISC) {
  2290. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2291. tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2292. pCurHcb->HCS_ActScb->SCB_HaStat = 0;
  2293. tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2294. pCurHcb->HCS_ActScb = NULL;
  2295. pCurHcb->HCS_ActTcs = NULL;
  2296. pCurHcb->HCS_Flags &= ~HCF_EXPECT_DONE_DISC;
  2297. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2298. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2299. return (-1);
  2300. }
  2301. if (pCurHcb->HCS_Flags & HCF_EXPECT_DISC) {
  2302. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2303. pCurHcb->HCS_ActScb = NULL;
  2304. pCurHcb->HCS_ActTcs = NULL;
  2305. pCurHcb->HCS_Flags &= ~HCF_EXPECT_DISC;
  2306. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2307. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2308. return (-1);
  2309. }
  2310. return (int_tul_busfree(pCurHcb));
  2311. }
  2312. if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) {
  2313. return (pCurHcb->HCS_Phase);
  2314. }
  2315. return (pCurHcb->HCS_Phase);
  2316. }
  2317. /***************************************************************************/
  2318. int tul_wait_disc(HCS * pCurHcb)
  2319. {
  2320. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2321. & TSS_INT_PENDING));
  2322. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2323. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2324. return (int_tul_scsi_rst(pCurHcb));
  2325. }
  2326. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2327. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2328. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2329. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2330. pCurHcb->HCS_ActScb = NULL;
  2331. return (-1);
  2332. }
  2333. return (tul_bad_seq(pCurHcb));
  2334. }
  2335. /***************************************************************************/
  2336. int tul_wait_done_disc(HCS * pCurHcb)
  2337. {
  2338. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2339. & TSS_INT_PENDING));
  2340. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2341. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2342. return (int_tul_scsi_rst(pCurHcb));
  2343. }
  2344. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2345. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2346. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2347. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2348. tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2349. tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2350. pCurHcb->HCS_ActScb = NULL;
  2351. return (-1);
  2352. }
  2353. return (tul_bad_seq(pCurHcb));
  2354. }
  2355. static irqreturn_t i91u_intr(int irqno, void *dev_id, struct pt_regs *regs)
  2356. {
  2357. struct Scsi_Host *dev = dev_id;
  2358. unsigned long flags;
  2359. spin_lock_irqsave(dev->host_lock, flags);
  2360. tul_isr((HCS *)dev->base);
  2361. spin_unlock_irqrestore(dev->host_lock, flags);
  2362. return IRQ_HANDLED;
  2363. }
  2364. static int tul_NewReturnNumberOfAdapters(void)
  2365. {
  2366. struct pci_dev *pDev = NULL; /* Start from none */
  2367. int iAdapters = 0;
  2368. long dRegValue;
  2369. WORD wBIOS;
  2370. int i = 0;
  2371. init_i91uAdapter_table();
  2372. for (i = 0; i < TULSZ(i91u_pci_devices); i++)
  2373. {
  2374. while ((pDev = pci_find_device(i91u_pci_devices[i].vendor_id, i91u_pci_devices[i].device_id, pDev)) != NULL) {
  2375. if (pci_enable_device(pDev))
  2376. continue;
  2377. pci_read_config_dword(pDev, 0x44, (u32 *) & dRegValue);
  2378. wBIOS = (UWORD) (dRegValue & 0xFF);
  2379. if (((dRegValue & 0xFF00) >> 8) == 0xFF)
  2380. dRegValue = 0;
  2381. wBIOS = (wBIOS << 8) + ((UWORD) ((dRegValue & 0xFF00) >> 8));
  2382. if (pci_set_dma_mask(pDev, 0xffffffff)) {
  2383. printk(KERN_WARNING
  2384. "i91u: Could not set 32 bit DMA mask\n");
  2385. continue;
  2386. }
  2387. if (Addi91u_into_Adapter_table(wBIOS,
  2388. (pDev->resource[0].start),
  2389. pDev->irq,
  2390. pDev->bus->number,
  2391. (pDev->devfn >> 3)
  2392. ) == 0)
  2393. iAdapters++;
  2394. }
  2395. }
  2396. return (iAdapters);
  2397. }
  2398. static int i91u_detect(struct scsi_host_template * tpnt)
  2399. {
  2400. HCS *pHCB;
  2401. struct Scsi_Host *hreg;
  2402. unsigned long i; /* 01/14/98 */
  2403. int ok = 0, iAdapters;
  2404. ULONG dBiosAdr;
  2405. BYTE *pbBiosAdr;
  2406. /* Get total number of adapters in the motherboard */
  2407. iAdapters = tul_NewReturnNumberOfAdapters();
  2408. if (iAdapters == 0) /* If no tulip founded, return */
  2409. return (0);
  2410. tul_num_ch = (iAdapters > tul_num_ch) ? tul_num_ch : iAdapters;
  2411. /* Update actually channel number */
  2412. if (tul_tag_enable) { /* 1.01i */
  2413. tul_num_scb = MAX_TARGETS * i91u_MAXQUEUE;
  2414. } else {
  2415. tul_num_scb = MAX_TARGETS + 3; /* 1-tape, 1-CD_ROM, 1- extra */
  2416. } /* Update actually SCBs per adapter */
  2417. /* Get total memory needed for HCS */
  2418. i = tul_num_ch * sizeof(HCS);
  2419. memset((unsigned char *) &tul_hcs[0], 0, i); /* Initialize tul_hcs 0 */
  2420. /* Get total memory needed for SCB */
  2421. for (; tul_num_scb >= MAX_TARGETS + 3; tul_num_scb--) {
  2422. i = tul_num_ch * tul_num_scb * sizeof(SCB);
  2423. if ((tul_scb = (SCB *) kmalloc(i, GFP_ATOMIC | GFP_DMA)) != NULL)
  2424. break;
  2425. }
  2426. if (tul_scb == NULL) {
  2427. printk("i91u: SCB memory allocation error\n");
  2428. return (0);
  2429. }
  2430. memset((unsigned char *) tul_scb, 0, i);
  2431. for (i = 0, pHCB = &tul_hcs[0]; /* Get pointer for control block */
  2432. i < tul_num_ch;
  2433. i++, pHCB++) {
  2434. get_tulipPCIConfig(pHCB, i);
  2435. dBiosAdr = pHCB->HCS_BIOS;
  2436. dBiosAdr = (dBiosAdr << 4);
  2437. pbBiosAdr = phys_to_virt(dBiosAdr);
  2438. init_tulip(pHCB, tul_scb + (i * tul_num_scb), tul_num_scb, pbBiosAdr, 10);
  2439. request_region(pHCB->HCS_Base, 256, "i91u"); /* Register */
  2440. pHCB->HCS_Index = i; /* 7/29/98 */
  2441. hreg = scsi_register(tpnt, sizeof(HCS));
  2442. if(hreg == NULL) {
  2443. release_region(pHCB->HCS_Base, 256);
  2444. return 0;
  2445. }
  2446. hreg->io_port = pHCB->HCS_Base;
  2447. hreg->n_io_port = 0xff;
  2448. hreg->can_queue = tul_num_scb; /* 03/05/98 */
  2449. hreg->unique_id = pHCB->HCS_Base;
  2450. hreg->max_id = pHCB->HCS_MaxTar;
  2451. hreg->max_lun = 32; /* 10/21/97 */
  2452. hreg->irq = pHCB->HCS_Intr;
  2453. hreg->this_id = pHCB->HCS_SCSI_ID; /* Assign HCS index */
  2454. hreg->base = (unsigned long)pHCB;
  2455. hreg->sg_tablesize = TOTAL_SG_ENTRY; /* Maximun support is 32 */
  2456. /* Initial tulip chip */
  2457. ok = request_irq(pHCB->HCS_Intr, i91u_intr, SA_INTERRUPT | SA_SHIRQ, "i91u", hreg);
  2458. if (ok < 0) {
  2459. printk(KERN_WARNING "i91u: unable to request IRQ %d\n\n", pHCB->HCS_Intr);
  2460. return 0;
  2461. }
  2462. }
  2463. tpnt->this_id = -1;
  2464. tpnt->can_queue = 1;
  2465. return 1;
  2466. }
  2467. static void i91uBuildSCB(HCS * pHCB, SCB * pSCB, struct scsi_cmnd * SCpnt)
  2468. { /* Create corresponding SCB */
  2469. struct scatterlist *pSrbSG;
  2470. SG *pSG; /* Pointer to SG list */
  2471. int i;
  2472. long TotalLen;
  2473. dma_addr_t dma_addr;
  2474. pSCB->SCB_Post = i91uSCBPost; /* i91u's callback routine */
  2475. pSCB->SCB_Srb = SCpnt;
  2476. pSCB->SCB_Opcode = ExecSCSI;
  2477. pSCB->SCB_Flags = SCF_POST; /* After SCSI done, call post routine */
  2478. pSCB->SCB_Target = SCpnt->device->id;
  2479. pSCB->SCB_Lun = SCpnt->device->lun;
  2480. pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW;
  2481. pSCB->SCB_Flags |= SCF_SENSE; /* Turn on auto request sense */
  2482. dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->sense_buffer,
  2483. SENSE_SIZE, DMA_FROM_DEVICE);
  2484. pSCB->SCB_SensePtr = cpu_to_le32((u32)dma_addr);
  2485. pSCB->SCB_SenseLen = cpu_to_le32(SENSE_SIZE);
  2486. SCpnt->SCp.ptr = (char *)(unsigned long)dma_addr;
  2487. pSCB->SCB_CDBLen = SCpnt->cmd_len;
  2488. pSCB->SCB_HaStat = 0;
  2489. pSCB->SCB_TaStat = 0;
  2490. memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, SCpnt->cmd_len);
  2491. if (SCpnt->device->tagged_supported) { /* Tag Support */
  2492. pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG; /* Do simple tag only */
  2493. } else {
  2494. pSCB->SCB_TagMsg = 0; /* No tag support */
  2495. }
  2496. /* todo handle map_sg error */
  2497. if (SCpnt->use_sg) {
  2498. dma_addr = dma_map_single(&pHCB->pci_dev->dev, &pSCB->SCB_SGList[0],
  2499. sizeof(struct SG_Struc) * TOTAL_SG_ENTRY,
  2500. DMA_BIDIRECTIONAL);
  2501. pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr);
  2502. SCpnt->SCp.dma_handle = dma_addr;
  2503. pSrbSG = (struct scatterlist *) SCpnt->request_buffer;
  2504. pSCB->SCB_SGLen = dma_map_sg(&pHCB->pci_dev->dev, pSrbSG,
  2505. SCpnt->use_sg, SCpnt->sc_data_direction);
  2506. pSCB->SCB_Flags |= SCF_SG; /* Turn on SG list flag */
  2507. for (i = 0, TotalLen = 0, pSG = &pSCB->SCB_SGList[0]; /* 1.01g */
  2508. i < pSCB->SCB_SGLen; i++, pSG++, pSrbSG++) {
  2509. pSG->SG_Ptr = cpu_to_le32((u32)sg_dma_address(pSrbSG));
  2510. TotalLen += pSG->SG_Len = cpu_to_le32((u32)sg_dma_len(pSrbSG));
  2511. }
  2512. pSCB->SCB_BufLen = (SCpnt->request_bufflen > TotalLen) ?
  2513. TotalLen : SCpnt->request_bufflen;
  2514. } else if (SCpnt->request_bufflen) { /* Non SG */
  2515. dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->request_buffer,
  2516. SCpnt->request_bufflen,
  2517. SCpnt->sc_data_direction);
  2518. SCpnt->SCp.dma_handle = dma_addr;
  2519. pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr);
  2520. pSCB->SCB_BufLen = cpu_to_le32((u32)SCpnt->request_bufflen);
  2521. pSCB->SCB_SGLen = 0;
  2522. } else {
  2523. pSCB->SCB_BufLen = 0;
  2524. pSCB->SCB_SGLen = 0;
  2525. }
  2526. }
  2527. static int i91u_queuecommand(struct scsi_cmnd *cmd,
  2528. void (*done)(struct scsi_cmnd *))
  2529. {
  2530. HCS *pHCB = (HCS *) cmd->device->host->base;
  2531. register SCB *pSCB;
  2532. cmd->scsi_done = done;
  2533. pSCB = tul_alloc_scb(pHCB);
  2534. if (!pSCB)
  2535. return SCSI_MLQUEUE_HOST_BUSY;
  2536. i91uBuildSCB(pHCB, pSCB, cmd);
  2537. tul_exec_scb(pHCB, pSCB);
  2538. return 0;
  2539. }
  2540. #if 0 /* no new EH yet */
  2541. /*
  2542. * Abort a queued command
  2543. * (commands that are on the bus can't be aborted easily)
  2544. */
  2545. static int i91u_abort(struct scsi_cmnd * SCpnt)
  2546. {
  2547. HCS *pHCB;
  2548. pHCB = (HCS *) SCpnt->device->host->base;
  2549. return tul_abort_srb(pHCB, SCpnt);
  2550. }
  2551. /*
  2552. * Reset registers, reset a hanging bus and
  2553. * kill active and disconnected commands for target w/o soft reset
  2554. */
  2555. static int i91u_reset(struct scsi_cmnd * SCpnt, unsigned int reset_flags)
  2556. { /* I need Host Control Block Information */
  2557. HCS *pHCB;
  2558. pHCB = (HCS *) SCpnt->device->host->base;
  2559. if (reset_flags & (SCSI_RESET_SUGGEST_BUS_RESET | SCSI_RESET_SUGGEST_HOST_RESET))
  2560. return tul_reset_scsi_bus(pHCB);
  2561. else
  2562. return tul_device_reset(pHCB, SCpnt, SCpnt->device->id, reset_flags);
  2563. }
  2564. #endif
  2565. static int i91u_bus_reset(struct scsi_cmnd * SCpnt)
  2566. {
  2567. HCS *pHCB;
  2568. pHCB = (HCS *) SCpnt->device->host->base;
  2569. spin_lock_irq(SCpnt->device->host->host_lock);
  2570. tul_reset_scsi(pHCB, 0);
  2571. spin_unlock_irq(SCpnt->device->host->host_lock);
  2572. return SUCCESS;
  2573. }
  2574. /*
  2575. * Return the "logical geometry"
  2576. */
  2577. static int i91u_biosparam(struct scsi_device *sdev, struct block_device *dev,
  2578. sector_t capacity, int *info_array)
  2579. {
  2580. HCS *pHcb; /* Point to Host adapter control block */
  2581. TCS *pTcb;
  2582. pHcb = (HCS *) sdev->host->base;
  2583. pTcb = &pHcb->HCS_Tcs[sdev->id];
  2584. if (pTcb->TCS_DrvHead) {
  2585. info_array[0] = pTcb->TCS_DrvHead;
  2586. info_array[1] = pTcb->TCS_DrvSector;
  2587. info_array[2] = (unsigned long)capacity / pTcb->TCS_DrvHead / pTcb->TCS_DrvSector;
  2588. } else {
  2589. if (pTcb->TCS_DrvFlags & TCF_DRV_255_63) {
  2590. info_array[0] = 255;
  2591. info_array[1] = 63;
  2592. info_array[2] = (unsigned long)capacity / 255 / 63;
  2593. } else {
  2594. info_array[0] = 64;
  2595. info_array[1] = 32;
  2596. info_array[2] = (unsigned long)capacity >> 11;
  2597. }
  2598. }
  2599. #if defined(DEBUG_BIOSPARAM)
  2600. if (i91u_debug & debug_biosparam) {
  2601. printk("bios geometry: head=%d, sec=%d, cyl=%d\n",
  2602. info_array[0], info_array[1], info_array[2]);
  2603. printk("WARNING: check, if the bios geometry is correct.\n");
  2604. }
  2605. #endif
  2606. return 0;
  2607. }
  2608. static void i91u_unmap_cmnd(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd)
  2609. {
  2610. /* auto sense buffer */
  2611. if (cmnd->SCp.ptr) {
  2612. dma_unmap_single(&pci_dev->dev,
  2613. (dma_addr_t)((unsigned long)cmnd->SCp.ptr),
  2614. SENSE_SIZE, DMA_FROM_DEVICE);
  2615. cmnd->SCp.ptr = NULL;
  2616. }
  2617. /* request buffer */
  2618. if (cmnd->use_sg) {
  2619. dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
  2620. sizeof(struct SG_Struc) * TOTAL_SG_ENTRY,
  2621. DMA_BIDIRECTIONAL);
  2622. dma_unmap_sg(&pci_dev->dev, cmnd->request_buffer,
  2623. cmnd->use_sg,
  2624. cmnd->sc_data_direction);
  2625. } else if (cmnd->request_bufflen) {
  2626. dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
  2627. cmnd->request_bufflen,
  2628. cmnd->sc_data_direction);
  2629. }
  2630. }
  2631. /*****************************************************************************
  2632. Function name : i91uSCBPost
  2633. Description : This is callback routine be called when tulip finish one
  2634. SCSI command.
  2635. Input : pHCB - Pointer to host adapter control block.
  2636. pSCB - Pointer to SCSI control block.
  2637. Output : None.
  2638. Return : None.
  2639. *****************************************************************************/
  2640. static void i91uSCBPost(BYTE * pHcb, BYTE * pScb)
  2641. {
  2642. struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */
  2643. HCS *pHCB;
  2644. SCB *pSCB;
  2645. pHCB = (HCS *) pHcb;
  2646. pSCB = (SCB *) pScb;
  2647. if ((pSRB = pSCB->SCB_Srb) == 0) {
  2648. printk("i91uSCBPost: SRB pointer is empty\n");
  2649. tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */
  2650. return;
  2651. }
  2652. switch (pSCB->SCB_HaStat) {
  2653. case 0x0:
  2654. case 0xa: /* Linked command complete without error and linked normally */
  2655. case 0xb: /* Linked command complete without error interrupt generated */
  2656. pSCB->SCB_HaStat = 0;
  2657. break;
  2658. case 0x11: /* Selection time out-The initiator selection or target
  2659. reselection was not complete within the SCSI Time out period */
  2660. pSCB->SCB_HaStat = DID_TIME_OUT;
  2661. break;
  2662. case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus
  2663. phase sequence was requested by the target. The host adapter
  2664. will generate a SCSI Reset Condition, notifying the host with
  2665. a SCRD interrupt */
  2666. pSCB->SCB_HaStat = DID_RESET;
  2667. break;
  2668. case 0x1a: /* SCB Aborted. 07/21/98 */
  2669. pSCB->SCB_HaStat = DID_ABORT;
  2670. break;
  2671. case 0x12: /* Data overrun/underrun-The target attempted to transfer more data
  2672. than was allocated by the Data Length field or the sum of the
  2673. Scatter / Gather Data Length fields. */
  2674. case 0x13: /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
  2675. case 0x16: /* Invalid SCB Operation Code. */
  2676. default:
  2677. printk("ini9100u: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat);
  2678. pSCB->SCB_HaStat = DID_ERROR; /* Couldn't find any better */
  2679. break;
  2680. }
  2681. pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16);
  2682. if (pSRB == NULL) {
  2683. printk("pSRB is NULL\n");
  2684. }
  2685. i91u_unmap_cmnd(pHCB->pci_dev, pSRB);
  2686. pSRB->scsi_done(pSRB); /* Notify system DONE */
  2687. tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */
  2688. }
  2689. /*
  2690. * Release ressources
  2691. */
  2692. static int i91u_release(struct Scsi_Host *hreg)
  2693. {
  2694. free_irq(hreg->irq, hreg);
  2695. release_region(hreg->io_port, 256);
  2696. return 0;
  2697. }
  2698. MODULE_LICENSE("Dual BSD/GPL");
  2699. static struct scsi_host_template driver_template = {
  2700. .proc_name = "INI9100U",
  2701. .name = i91u_REVID,
  2702. .detect = i91u_detect,
  2703. .release = i91u_release,
  2704. .queuecommand = i91u_queuecommand,
  2705. // .abort = i91u_abort,
  2706. // .reset = i91u_reset,
  2707. .eh_bus_reset_handler = i91u_bus_reset,
  2708. .bios_param = i91u_biosparam,
  2709. .can_queue = 1,
  2710. .this_id = 1,
  2711. .sg_tablesize = SG_ALL,
  2712. .cmd_per_lun = 1,
  2713. .use_clustering = ENABLE_CLUSTERING,
  2714. };
  2715. #include "scsi_module.c"