mpc85xx_mds.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201
  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
  3. *
  4. * Author: Andy Fleming <afleming@freescale.com>
  5. *
  6. * Based on 83xx/mpc8360e_pb.c by:
  7. * Li Yang <LeoLi@freescale.com>
  8. * Yin Olivia <Hong-hua.Yin@freescale.com>
  9. *
  10. * Description:
  11. * MPC85xx MDS board specific routines.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/stddef.h>
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/errno.h>
  22. #include <linux/reboot.h>
  23. #include <linux/pci.h>
  24. #include <linux/kdev_t.h>
  25. #include <linux/major.h>
  26. #include <linux/console.h>
  27. #include <linux/delay.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/initrd.h>
  30. #include <linux/module.h>
  31. #include <linux/fsl_devices.h>
  32. #include <asm/of_device.h>
  33. #include <asm/of_platform.h>
  34. #include <asm/system.h>
  35. #include <asm/atomic.h>
  36. #include <asm/time.h>
  37. #include <asm/io.h>
  38. #include <asm/machdep.h>
  39. #include <asm/pci-bridge.h>
  40. #include <asm/mpc85xx.h>
  41. #include <asm/irq.h>
  42. #include <mm/mmu_decl.h>
  43. #include <asm/prom.h>
  44. #include <asm/udbg.h>
  45. #include <sysdev/fsl_soc.h>
  46. #include <sysdev/fsl_pci.h>
  47. #include <asm/qe.h>
  48. #include <asm/qe_ic.h>
  49. #include <asm/mpic.h>
  50. #include "mpc85xx.h"
  51. #undef DEBUG
  52. #ifdef DEBUG
  53. #define DBG(fmt...) udbg_printf(fmt)
  54. #else
  55. #define DBG(fmt...)
  56. #endif
  57. /* ************************************************************************
  58. *
  59. * Setup the architecture
  60. *
  61. */
  62. static void __init mpc85xx_mds_setup_arch(void)
  63. {
  64. struct device_node *np;
  65. static u8 *bcsr_regs = NULL;
  66. if (ppc_md.progress)
  67. ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
  68. /* Map BCSR area */
  69. np = of_find_node_by_name(NULL, "bcsr");
  70. if (np != NULL) {
  71. struct resource res;
  72. of_address_to_resource(np, 0, &res);
  73. bcsr_regs = ioremap(res.start, res.end - res.start +1);
  74. of_node_put(np);
  75. }
  76. #ifdef CONFIG_PCI
  77. for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
  78. fsl_add_bridge(np, 1);
  79. of_node_put(np);
  80. #endif
  81. #ifdef CONFIG_QUICC_ENGINE
  82. if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
  83. qe_reset();
  84. of_node_put(np);
  85. }
  86. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  87. struct device_node *ucc = NULL;
  88. par_io_init(np);
  89. of_node_put(np);
  90. for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
  91. par_io_of_config(ucc);
  92. of_node_put(ucc);
  93. }
  94. if (bcsr_regs) {
  95. u8 bcsr_phy;
  96. /* Reset the Ethernet PHY */
  97. bcsr_phy = in_be8(&bcsr_regs[9]);
  98. bcsr_phy &= ~0x20;
  99. out_be8(&bcsr_regs[9], bcsr_phy);
  100. udelay(1000);
  101. bcsr_phy = in_be8(&bcsr_regs[9]);
  102. bcsr_phy |= 0x20;
  103. out_be8(&bcsr_regs[9], bcsr_phy);
  104. iounmap(bcsr_regs);
  105. }
  106. #endif /* CONFIG_QUICC_ENGINE */
  107. }
  108. static struct of_device_id mpc85xx_ids[] = {
  109. { .type = "soc", },
  110. { .compatible = "soc", },
  111. { .type = "qe", },
  112. {},
  113. };
  114. static int __init mpc85xx_publish_devices(void)
  115. {
  116. if (!machine_is(mpc85xx_mds))
  117. return 0;
  118. /* Publish the QE devices */
  119. of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
  120. return 0;
  121. }
  122. device_initcall(mpc85xx_publish_devices);
  123. static void __init mpc85xx_mds_pic_init(void)
  124. {
  125. struct mpic *mpic;
  126. struct resource r;
  127. struct device_node *np = NULL;
  128. np = of_find_node_by_type(NULL, "open-pic");
  129. if (!np)
  130. return;
  131. if (of_address_to_resource(np, 0, &r)) {
  132. printk(KERN_ERR "Failed to map mpic register space\n");
  133. of_node_put(np);
  134. return;
  135. }
  136. mpic = mpic_alloc(np, r.start,
  137. MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  138. 0, 256, " OpenPIC ");
  139. BUG_ON(mpic == NULL);
  140. of_node_put(np);
  141. mpic_init(mpic);
  142. #ifdef CONFIG_QUICC_ENGINE
  143. np = of_find_node_by_type(NULL, "qeic");
  144. if (!np)
  145. return;
  146. qe_ic_init(np, 0);
  147. of_node_put(np);
  148. #endif /* CONFIG_QUICC_ENGINE */
  149. }
  150. static int __init mpc85xx_mds_probe(void)
  151. {
  152. unsigned long root = of_get_flat_dt_root();
  153. return of_flat_dt_is_compatible(root, "MPC85xxMDS");
  154. }
  155. define_machine(mpc85xx_mds) {
  156. .name = "MPC85xx MDS",
  157. .probe = mpc85xx_mds_probe,
  158. .setup_arch = mpc85xx_mds_setup_arch,
  159. .init_IRQ = mpc85xx_mds_pic_init,
  160. .get_irq = mpic_get_irq,
  161. .restart = mpc85xx_restart,
  162. .calibrate_decr = generic_calibrate_decr,
  163. .progress = udbg_progress,
  164. #ifdef CONFIG_PCI
  165. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  166. #endif
  167. };