twl4030.c 68 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. unsigned int bypass_state;
  120. unsigned int codec_powered;
  121. unsigned int codec_muted;
  122. struct snd_pcm_substream *master_substream;
  123. struct snd_pcm_substream *slave_substream;
  124. unsigned int configured;
  125. unsigned int rate;
  126. unsigned int sample_bits;
  127. unsigned int channels;
  128. unsigned int sysclk;
  129. /* Headset output state handling */
  130. unsigned int hsl_enabled;
  131. unsigned int hsr_enabled;
  132. };
  133. /*
  134. * read twl4030 register cache
  135. */
  136. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  137. unsigned int reg)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return -EIO;
  142. return cache[reg];
  143. }
  144. /*
  145. * write twl4030 register cache
  146. */
  147. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  148. u8 reg, u8 value)
  149. {
  150. u8 *cache = codec->reg_cache;
  151. if (reg >= TWL4030_CACHEREGNUM)
  152. return;
  153. cache[reg] = value;
  154. }
  155. /*
  156. * write to the twl4030 register space
  157. */
  158. static int twl4030_write(struct snd_soc_codec *codec,
  159. unsigned int reg, unsigned int value)
  160. {
  161. twl4030_write_reg_cache(codec, reg, value);
  162. if (likely(reg < TWL4030_REG_SW_SHADOW))
  163. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  164. reg);
  165. else
  166. return 0;
  167. }
  168. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  169. {
  170. struct twl4030_priv *twl4030 = codec->private_data;
  171. u8 mode;
  172. if (enable == twl4030->codec_powered)
  173. return;
  174. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  175. if (enable)
  176. mode |= TWL4030_CODECPDZ;
  177. else
  178. mode &= ~TWL4030_CODECPDZ;
  179. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  180. twl4030->codec_powered = enable;
  181. /* REVISIT: this delay is present in TI sample drivers */
  182. /* but there seems to be no TRM requirement for it */
  183. udelay(10);
  184. }
  185. static void twl4030_init_chip(struct snd_soc_codec *codec)
  186. {
  187. u8 *cache = codec->reg_cache;
  188. int i;
  189. /* clear CODECPDZ prior to setting register defaults */
  190. twl4030_codec_enable(codec, 0);
  191. /* set all audio section registers to reasonable defaults */
  192. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  193. twl4030_write(codec, i, cache[i]);
  194. }
  195. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  196. {
  197. struct twl4030_priv *twl4030 = codec->private_data;
  198. u8 reg_val;
  199. if (mute == twl4030->codec_muted)
  200. return;
  201. if (mute) {
  202. /* Bypass the reg_cache and mute the volumes
  203. * Headset mute is done in it's own event handler
  204. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  205. */
  206. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  207. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  208. reg_val & (~TWL4030_EAR_GAIN),
  209. TWL4030_REG_EAR_CTL);
  210. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  211. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  212. reg_val & (~TWL4030_PREDL_GAIN),
  213. TWL4030_REG_PREDL_CTL);
  214. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  215. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  216. reg_val & (~TWL4030_PREDR_GAIN),
  217. TWL4030_REG_PREDL_CTL);
  218. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  219. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  220. reg_val & (~TWL4030_PRECKL_GAIN),
  221. TWL4030_REG_PRECKL_CTL);
  222. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  223. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  224. reg_val & (~TWL4030_PRECKR_GAIN),
  225. TWL4030_REG_PRECKR_CTL);
  226. /* Disable PLL */
  227. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  228. reg_val &= ~TWL4030_APLL_EN;
  229. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  230. } else {
  231. /* Restore the volumes
  232. * Headset mute is done in it's own event handler
  233. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  234. */
  235. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  236. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  237. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  238. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  239. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  240. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  241. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  242. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  243. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  244. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  245. /* Enable PLL */
  246. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  247. reg_val |= TWL4030_APLL_EN;
  248. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  249. }
  250. twl4030->codec_muted = mute;
  251. }
  252. static void twl4030_power_up(struct snd_soc_codec *codec)
  253. {
  254. struct twl4030_priv *twl4030 = codec->private_data;
  255. u8 anamicl, regmisc1, byte;
  256. int i = 0;
  257. if (twl4030->codec_powered)
  258. return;
  259. /* set CODECPDZ to turn on codec */
  260. twl4030_codec_enable(codec, 1);
  261. /* initiate offset cancellation */
  262. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  263. twl4030_write(codec, TWL4030_REG_ANAMICL,
  264. anamicl | TWL4030_CNCL_OFFSET_START);
  265. /* wait for offset cancellation to complete */
  266. do {
  267. /* this takes a little while, so don't slam i2c */
  268. udelay(2000);
  269. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  270. TWL4030_REG_ANAMICL);
  271. } while ((i++ < 100) &&
  272. ((byte & TWL4030_CNCL_OFFSET_START) ==
  273. TWL4030_CNCL_OFFSET_START));
  274. /* Make sure that the reg_cache has the same value as the HW */
  275. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  276. /* anti-pop when changing analog gain */
  277. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  278. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  279. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  280. /* toggle CODECPDZ as per TRM */
  281. twl4030_codec_enable(codec, 0);
  282. twl4030_codec_enable(codec, 1);
  283. }
  284. /*
  285. * Unconditional power down
  286. */
  287. static void twl4030_power_down(struct snd_soc_codec *codec)
  288. {
  289. /* power down */
  290. twl4030_codec_enable(codec, 0);
  291. }
  292. /* Earpiece */
  293. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  294. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  295. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  296. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  297. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  298. };
  299. /* PreDrive Left */
  300. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  301. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  302. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  303. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  304. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  305. };
  306. /* PreDrive Right */
  307. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  308. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  309. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  310. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  311. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  312. };
  313. /* Headset Left */
  314. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  315. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  316. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  317. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  318. };
  319. /* Headset Right */
  320. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  321. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  322. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  323. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  324. };
  325. /* Carkit Left */
  326. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  327. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  328. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  329. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  330. };
  331. /* Carkit Right */
  332. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  333. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  334. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  335. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  336. };
  337. /* Handsfree Left */
  338. static const char *twl4030_handsfreel_texts[] =
  339. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  340. static const struct soc_enum twl4030_handsfreel_enum =
  341. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  342. ARRAY_SIZE(twl4030_handsfreel_texts),
  343. twl4030_handsfreel_texts);
  344. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  345. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  346. /* Handsfree Left virtual mute */
  347. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  348. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  349. /* Handsfree Right */
  350. static const char *twl4030_handsfreer_texts[] =
  351. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  352. static const struct soc_enum twl4030_handsfreer_enum =
  353. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  354. ARRAY_SIZE(twl4030_handsfreer_texts),
  355. twl4030_handsfreer_texts);
  356. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  357. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  358. /* Handsfree Right virtual mute */
  359. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  360. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  361. /* Vibra */
  362. /* Vibra audio path selection */
  363. static const char *twl4030_vibra_texts[] =
  364. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  365. static const struct soc_enum twl4030_vibra_enum =
  366. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  367. ARRAY_SIZE(twl4030_vibra_texts),
  368. twl4030_vibra_texts);
  369. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  370. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  371. /* Vibra path selection: local vibrator (PWM) or audio driven */
  372. static const char *twl4030_vibrapath_texts[] =
  373. {"Local vibrator", "Audio"};
  374. static const struct soc_enum twl4030_vibrapath_enum =
  375. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  376. ARRAY_SIZE(twl4030_vibrapath_texts),
  377. twl4030_vibrapath_texts);
  378. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  379. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  380. /* Left analog microphone selection */
  381. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  382. SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
  383. SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
  384. SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
  385. SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
  386. };
  387. /* Right analog microphone selection */
  388. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  389. SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
  390. SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
  391. };
  392. /* TX1 L/R Analog/Digital microphone selection */
  393. static const char *twl4030_micpathtx1_texts[] =
  394. {"Analog", "Digimic0"};
  395. static const struct soc_enum twl4030_micpathtx1_enum =
  396. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  397. ARRAY_SIZE(twl4030_micpathtx1_texts),
  398. twl4030_micpathtx1_texts);
  399. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  400. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  401. /* TX2 L/R Analog/Digital microphone selection */
  402. static const char *twl4030_micpathtx2_texts[] =
  403. {"Analog", "Digimic1"};
  404. static const struct soc_enum twl4030_micpathtx2_enum =
  405. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  406. ARRAY_SIZE(twl4030_micpathtx2_texts),
  407. twl4030_micpathtx2_texts);
  408. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  409. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  410. /* Analog bypass for AudioR1 */
  411. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  412. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  413. /* Analog bypass for AudioL1 */
  414. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  415. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  416. /* Analog bypass for AudioR2 */
  417. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  418. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  419. /* Analog bypass for AudioL2 */
  420. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  421. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  422. /* Analog bypass for Voice */
  423. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  424. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  425. /* Digital bypass gain, 0 mutes the bypass */
  426. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  427. TLV_DB_RANGE_HEAD(2),
  428. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  429. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  430. };
  431. /* Digital bypass left (TX1L -> RX2L) */
  432. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  433. SOC_DAPM_SINGLE_TLV("Volume",
  434. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  435. twl4030_dapm_dbypass_tlv);
  436. /* Digital bypass right (TX1R -> RX2R) */
  437. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  438. SOC_DAPM_SINGLE_TLV("Volume",
  439. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  440. twl4030_dapm_dbypass_tlv);
  441. /*
  442. * Voice Sidetone GAIN volume control:
  443. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  444. */
  445. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  446. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  447. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  448. SOC_DAPM_SINGLE_TLV("Volume",
  449. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  450. twl4030_dapm_dbypassv_tlv);
  451. static int micpath_event(struct snd_soc_dapm_widget *w,
  452. struct snd_kcontrol *kcontrol, int event)
  453. {
  454. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  455. unsigned char adcmicsel, micbias_ctl;
  456. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  457. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  458. /* Prepare the bits for the given TX path:
  459. * shift_l == 0: TX1 microphone path
  460. * shift_l == 2: TX2 microphone path */
  461. if (e->shift_l) {
  462. /* TX2 microphone path */
  463. if (adcmicsel & TWL4030_TX2IN_SEL)
  464. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  465. else
  466. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  467. } else {
  468. /* TX1 microphone path */
  469. if (adcmicsel & TWL4030_TX1IN_SEL)
  470. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  471. else
  472. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  473. }
  474. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  475. return 0;
  476. }
  477. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  478. {
  479. unsigned char hs_ctl;
  480. hs_ctl = twl4030_read_reg_cache(codec, reg);
  481. if (ramp) {
  482. /* HF ramp-up */
  483. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  484. twl4030_write(codec, reg, hs_ctl);
  485. udelay(10);
  486. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  487. twl4030_write(codec, reg, hs_ctl);
  488. udelay(40);
  489. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  490. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  491. twl4030_write(codec, reg, hs_ctl);
  492. } else {
  493. /* HF ramp-down */
  494. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  495. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  496. twl4030_write(codec, reg, hs_ctl);
  497. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  498. twl4030_write(codec, reg, hs_ctl);
  499. udelay(40);
  500. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  501. twl4030_write(codec, reg, hs_ctl);
  502. }
  503. }
  504. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  505. struct snd_kcontrol *kcontrol, int event)
  506. {
  507. switch (event) {
  508. case SND_SOC_DAPM_POST_PMU:
  509. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  510. break;
  511. case SND_SOC_DAPM_POST_PMD:
  512. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  513. break;
  514. }
  515. return 0;
  516. }
  517. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  518. struct snd_kcontrol *kcontrol, int event)
  519. {
  520. switch (event) {
  521. case SND_SOC_DAPM_POST_PMU:
  522. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  523. break;
  524. case SND_SOC_DAPM_POST_PMD:
  525. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  526. break;
  527. }
  528. return 0;
  529. }
  530. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  531. {
  532. struct snd_soc_device *socdev = codec->socdev;
  533. struct twl4030_setup_data *setup = socdev->codec_data;
  534. unsigned char hs_gain, hs_pop;
  535. struct twl4030_priv *twl4030 = codec->private_data;
  536. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  537. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  538. 8388608, 16777216, 33554432, 67108864};
  539. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  540. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  541. /* Enable external mute control, this dramatically reduces
  542. * the pop-noise */
  543. if (setup && setup->hs_extmute) {
  544. if (setup->set_hs_extmute) {
  545. setup->set_hs_extmute(1);
  546. } else {
  547. hs_pop |= TWL4030_EXTMUTE;
  548. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  549. }
  550. }
  551. if (ramp) {
  552. /* Headset ramp-up according to the TRM */
  553. hs_pop |= TWL4030_VMID_EN;
  554. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  555. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  556. hs_pop |= TWL4030_RAMP_EN;
  557. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  558. /* Wait ramp delay time + 1, so the VMID can settle */
  559. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  560. twl4030->sysclk) + 1);
  561. } else {
  562. /* Headset ramp-down _not_ according to
  563. * the TRM, but in a way that it is working */
  564. hs_pop &= ~TWL4030_RAMP_EN;
  565. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  566. /* Wait ramp delay time + 1, so the VMID can settle */
  567. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  568. twl4030->sysclk) + 1);
  569. /* Bypass the reg_cache to mute the headset */
  570. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  571. hs_gain & (~0x0f),
  572. TWL4030_REG_HS_GAIN_SET);
  573. hs_pop &= ~TWL4030_VMID_EN;
  574. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  575. }
  576. /* Disable external mute */
  577. if (setup && setup->hs_extmute) {
  578. if (setup->set_hs_extmute) {
  579. setup->set_hs_extmute(0);
  580. } else {
  581. hs_pop &= ~TWL4030_EXTMUTE;
  582. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  583. }
  584. }
  585. }
  586. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  587. struct snd_kcontrol *kcontrol, int event)
  588. {
  589. struct twl4030_priv *twl4030 = w->codec->private_data;
  590. switch (event) {
  591. case SND_SOC_DAPM_POST_PMU:
  592. /* Do the ramp-up only once */
  593. if (!twl4030->hsr_enabled)
  594. headset_ramp(w->codec, 1);
  595. twl4030->hsl_enabled = 1;
  596. break;
  597. case SND_SOC_DAPM_POST_PMD:
  598. /* Do the ramp-down only if both headsetL/R is disabled */
  599. if (!twl4030->hsr_enabled)
  600. headset_ramp(w->codec, 0);
  601. twl4030->hsl_enabled = 0;
  602. break;
  603. }
  604. return 0;
  605. }
  606. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  607. struct snd_kcontrol *kcontrol, int event)
  608. {
  609. struct twl4030_priv *twl4030 = w->codec->private_data;
  610. switch (event) {
  611. case SND_SOC_DAPM_POST_PMU:
  612. /* Do the ramp-up only once */
  613. if (!twl4030->hsl_enabled)
  614. headset_ramp(w->codec, 1);
  615. twl4030->hsr_enabled = 1;
  616. break;
  617. case SND_SOC_DAPM_POST_PMD:
  618. /* Do the ramp-down only if both headsetL/R is disabled */
  619. if (!twl4030->hsl_enabled)
  620. headset_ramp(w->codec, 0);
  621. twl4030->hsr_enabled = 0;
  622. break;
  623. }
  624. return 0;
  625. }
  626. static int bypass_event(struct snd_soc_dapm_widget *w,
  627. struct snd_kcontrol *kcontrol, int event)
  628. {
  629. struct soc_mixer_control *m =
  630. (struct soc_mixer_control *)w->kcontrols->private_value;
  631. struct twl4030_priv *twl4030 = w->codec->private_data;
  632. unsigned char reg, misc;
  633. reg = twl4030_read_reg_cache(w->codec, m->reg);
  634. /*
  635. * bypass_state[0:3] - analog HiFi bypass
  636. * bypass_state[4] - analog voice bypass
  637. * bypass_state[5] - digital voice bypass
  638. * bypass_state[6:7] - digital HiFi bypass
  639. */
  640. if (m->reg == TWL4030_REG_VSTPGA) {
  641. /* Voice digital bypass */
  642. if (reg)
  643. twl4030->bypass_state |= (1 << 5);
  644. else
  645. twl4030->bypass_state &= ~(1 << 5);
  646. } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  647. /* Analog bypass */
  648. if (reg & (1 << m->shift))
  649. twl4030->bypass_state |=
  650. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  651. else
  652. twl4030->bypass_state &=
  653. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  654. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  655. /* Analog voice bypass */
  656. if (reg & (1 << m->shift))
  657. twl4030->bypass_state |= (1 << 4);
  658. else
  659. twl4030->bypass_state &= ~(1 << 4);
  660. } else {
  661. /* Digital bypass */
  662. if (reg & (0x7 << m->shift))
  663. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  664. else
  665. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  666. }
  667. /* Enable master analog loopback mode if any analog switch is enabled*/
  668. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  669. if (twl4030->bypass_state & 0x1F)
  670. misc |= TWL4030_FMLOOP_EN;
  671. else
  672. misc &= ~TWL4030_FMLOOP_EN;
  673. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  674. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  675. if (twl4030->bypass_state)
  676. twl4030_codec_mute(w->codec, 0);
  677. else
  678. twl4030_codec_mute(w->codec, 1);
  679. }
  680. return 0;
  681. }
  682. /*
  683. * Some of the gain controls in TWL (mostly those which are associated with
  684. * the outputs) are implemented in an interesting way:
  685. * 0x0 : Power down (mute)
  686. * 0x1 : 6dB
  687. * 0x2 : 0 dB
  688. * 0x3 : -6 dB
  689. * Inverting not going to help with these.
  690. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  691. */
  692. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  693. xinvert, tlv_array) \
  694. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  695. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  696. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  697. .tlv.p = (tlv_array), \
  698. .info = snd_soc_info_volsw, \
  699. .get = snd_soc_get_volsw_twl4030, \
  700. .put = snd_soc_put_volsw_twl4030, \
  701. .private_value = (unsigned long)&(struct soc_mixer_control) \
  702. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  703. .max = xmax, .invert = xinvert} }
  704. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  705. xinvert, tlv_array) \
  706. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  707. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  708. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  709. .tlv.p = (tlv_array), \
  710. .info = snd_soc_info_volsw_2r, \
  711. .get = snd_soc_get_volsw_r2_twl4030,\
  712. .put = snd_soc_put_volsw_r2_twl4030, \
  713. .private_value = (unsigned long)&(struct soc_mixer_control) \
  714. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  715. .rshift = xshift, .max = xmax, .invert = xinvert} }
  716. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  717. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  718. xinvert, tlv_array)
  719. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  720. struct snd_ctl_elem_value *ucontrol)
  721. {
  722. struct soc_mixer_control *mc =
  723. (struct soc_mixer_control *)kcontrol->private_value;
  724. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  725. unsigned int reg = mc->reg;
  726. unsigned int shift = mc->shift;
  727. unsigned int rshift = mc->rshift;
  728. int max = mc->max;
  729. int mask = (1 << fls(max)) - 1;
  730. ucontrol->value.integer.value[0] =
  731. (snd_soc_read(codec, reg) >> shift) & mask;
  732. if (ucontrol->value.integer.value[0])
  733. ucontrol->value.integer.value[0] =
  734. max + 1 - ucontrol->value.integer.value[0];
  735. if (shift != rshift) {
  736. ucontrol->value.integer.value[1] =
  737. (snd_soc_read(codec, reg) >> rshift) & mask;
  738. if (ucontrol->value.integer.value[1])
  739. ucontrol->value.integer.value[1] =
  740. max + 1 - ucontrol->value.integer.value[1];
  741. }
  742. return 0;
  743. }
  744. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  745. struct snd_ctl_elem_value *ucontrol)
  746. {
  747. struct soc_mixer_control *mc =
  748. (struct soc_mixer_control *)kcontrol->private_value;
  749. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  750. unsigned int reg = mc->reg;
  751. unsigned int shift = mc->shift;
  752. unsigned int rshift = mc->rshift;
  753. int max = mc->max;
  754. int mask = (1 << fls(max)) - 1;
  755. unsigned short val, val2, val_mask;
  756. val = (ucontrol->value.integer.value[0] & mask);
  757. val_mask = mask << shift;
  758. if (val)
  759. val = max + 1 - val;
  760. val = val << shift;
  761. if (shift != rshift) {
  762. val2 = (ucontrol->value.integer.value[1] & mask);
  763. val_mask |= mask << rshift;
  764. if (val2)
  765. val2 = max + 1 - val2;
  766. val |= val2 << rshift;
  767. }
  768. return snd_soc_update_bits(codec, reg, val_mask, val);
  769. }
  770. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  771. struct snd_ctl_elem_value *ucontrol)
  772. {
  773. struct soc_mixer_control *mc =
  774. (struct soc_mixer_control *)kcontrol->private_value;
  775. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  776. unsigned int reg = mc->reg;
  777. unsigned int reg2 = mc->rreg;
  778. unsigned int shift = mc->shift;
  779. int max = mc->max;
  780. int mask = (1<<fls(max))-1;
  781. ucontrol->value.integer.value[0] =
  782. (snd_soc_read(codec, reg) >> shift) & mask;
  783. ucontrol->value.integer.value[1] =
  784. (snd_soc_read(codec, reg2) >> shift) & mask;
  785. if (ucontrol->value.integer.value[0])
  786. ucontrol->value.integer.value[0] =
  787. max + 1 - ucontrol->value.integer.value[0];
  788. if (ucontrol->value.integer.value[1])
  789. ucontrol->value.integer.value[1] =
  790. max + 1 - ucontrol->value.integer.value[1];
  791. return 0;
  792. }
  793. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  794. struct snd_ctl_elem_value *ucontrol)
  795. {
  796. struct soc_mixer_control *mc =
  797. (struct soc_mixer_control *)kcontrol->private_value;
  798. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  799. unsigned int reg = mc->reg;
  800. unsigned int reg2 = mc->rreg;
  801. unsigned int shift = mc->shift;
  802. int max = mc->max;
  803. int mask = (1 << fls(max)) - 1;
  804. int err;
  805. unsigned short val, val2, val_mask;
  806. val_mask = mask << shift;
  807. val = (ucontrol->value.integer.value[0] & mask);
  808. val2 = (ucontrol->value.integer.value[1] & mask);
  809. if (val)
  810. val = max + 1 - val;
  811. if (val2)
  812. val2 = max + 1 - val2;
  813. val = val << shift;
  814. val2 = val2 << shift;
  815. err = snd_soc_update_bits(codec, reg, val_mask, val);
  816. if (err < 0)
  817. return err;
  818. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  819. return err;
  820. }
  821. /* Codec operation modes */
  822. static const char *twl4030_op_modes_texts[] = {
  823. "Option 2 (voice/audio)", "Option 1 (audio)"
  824. };
  825. static const struct soc_enum twl4030_op_modes_enum =
  826. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  827. ARRAY_SIZE(twl4030_op_modes_texts),
  828. twl4030_op_modes_texts);
  829. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  830. struct snd_ctl_elem_value *ucontrol)
  831. {
  832. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  833. struct twl4030_priv *twl4030 = codec->private_data;
  834. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  835. unsigned short val;
  836. unsigned short mask, bitmask;
  837. if (twl4030->configured) {
  838. printk(KERN_ERR "twl4030 operation mode cannot be "
  839. "changed on-the-fly\n");
  840. return -EBUSY;
  841. }
  842. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  843. ;
  844. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  845. return -EINVAL;
  846. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  847. mask = (bitmask - 1) << e->shift_l;
  848. if (e->shift_l != e->shift_r) {
  849. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  850. return -EINVAL;
  851. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  852. mask |= (bitmask - 1) << e->shift_r;
  853. }
  854. return snd_soc_update_bits(codec, e->reg, mask, val);
  855. }
  856. /*
  857. * FGAIN volume control:
  858. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  859. */
  860. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  861. /*
  862. * CGAIN volume control:
  863. * 0 dB to 12 dB in 6 dB steps
  864. * value 2 and 3 means 12 dB
  865. */
  866. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  867. /*
  868. * Voice Downlink GAIN volume control:
  869. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  870. */
  871. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  872. /*
  873. * Analog playback gain
  874. * -24 dB to 12 dB in 2 dB steps
  875. */
  876. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  877. /*
  878. * Gain controls tied to outputs
  879. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  880. */
  881. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  882. /*
  883. * Gain control for earpiece amplifier
  884. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  885. */
  886. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  887. /*
  888. * Capture gain after the ADCs
  889. * from 0 dB to 31 dB in 1 dB steps
  890. */
  891. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  892. /*
  893. * Gain control for input amplifiers
  894. * 0 dB to 30 dB in 6 dB steps
  895. */
  896. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  897. /* AVADC clock priority */
  898. static const char *twl4030_avadc_clk_priority_texts[] = {
  899. "Voice high priority", "HiFi high priority"
  900. };
  901. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  902. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  903. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  904. twl4030_avadc_clk_priority_texts);
  905. static const char *twl4030_rampdelay_texts[] = {
  906. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  907. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  908. "3495/2581/1748 ms"
  909. };
  910. static const struct soc_enum twl4030_rampdelay_enum =
  911. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  912. ARRAY_SIZE(twl4030_rampdelay_texts),
  913. twl4030_rampdelay_texts);
  914. /* Vibra H-bridge direction mode */
  915. static const char *twl4030_vibradirmode_texts[] = {
  916. "Vibra H-bridge direction", "Audio data MSB",
  917. };
  918. static const struct soc_enum twl4030_vibradirmode_enum =
  919. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  920. ARRAY_SIZE(twl4030_vibradirmode_texts),
  921. twl4030_vibradirmode_texts);
  922. /* Vibra H-bridge direction */
  923. static const char *twl4030_vibradir_texts[] = {
  924. "Positive polarity", "Negative polarity",
  925. };
  926. static const struct soc_enum twl4030_vibradir_enum =
  927. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  928. ARRAY_SIZE(twl4030_vibradir_texts),
  929. twl4030_vibradir_texts);
  930. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  931. /* Codec operation mode control */
  932. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  933. snd_soc_get_enum_double,
  934. snd_soc_put_twl4030_opmode_enum_double),
  935. /* Common playback gain controls */
  936. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  937. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  938. 0, 0x3f, 0, digital_fine_tlv),
  939. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  940. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  941. 0, 0x3f, 0, digital_fine_tlv),
  942. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  943. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  944. 6, 0x2, 0, digital_coarse_tlv),
  945. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  946. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  947. 6, 0x2, 0, digital_coarse_tlv),
  948. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  949. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  950. 3, 0x12, 1, analog_tlv),
  951. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  952. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  953. 3, 0x12, 1, analog_tlv),
  954. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  955. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  956. 1, 1, 0),
  957. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  958. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  959. 1, 1, 0),
  960. /* Common voice downlink gain controls */
  961. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  962. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  963. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  964. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  965. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  966. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  967. /* Separate output gain controls */
  968. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  969. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  970. 4, 3, 0, output_tvl),
  971. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  972. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  973. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  974. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  975. 4, 3, 0, output_tvl),
  976. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  977. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  978. /* Common capture gain controls */
  979. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  980. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  981. 0, 0x1f, 0, digital_capture_tlv),
  982. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  983. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  984. 0, 0x1f, 0, digital_capture_tlv),
  985. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  986. 0, 3, 5, 0, input_gain_tlv),
  987. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  988. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  989. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  990. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  991. };
  992. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  993. /* Left channel inputs */
  994. SND_SOC_DAPM_INPUT("MAINMIC"),
  995. SND_SOC_DAPM_INPUT("HSMIC"),
  996. SND_SOC_DAPM_INPUT("AUXL"),
  997. SND_SOC_DAPM_INPUT("CARKITMIC"),
  998. /* Right channel inputs */
  999. SND_SOC_DAPM_INPUT("SUBMIC"),
  1000. SND_SOC_DAPM_INPUT("AUXR"),
  1001. /* Digital microphones (Stereo) */
  1002. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1003. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1004. /* Outputs */
  1005. SND_SOC_DAPM_OUTPUT("OUTL"),
  1006. SND_SOC_DAPM_OUTPUT("OUTR"),
  1007. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1008. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1009. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1010. SND_SOC_DAPM_OUTPUT("HSOL"),
  1011. SND_SOC_DAPM_OUTPUT("HSOR"),
  1012. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1013. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1014. SND_SOC_DAPM_OUTPUT("HFL"),
  1015. SND_SOC_DAPM_OUTPUT("HFR"),
  1016. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1017. /* DACs */
  1018. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1019. SND_SOC_NOPM, 0, 0),
  1020. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1021. SND_SOC_NOPM, 0, 0),
  1022. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1023. SND_SOC_NOPM, 0, 0),
  1024. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1025. SND_SOC_NOPM, 0, 0),
  1026. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1027. SND_SOC_NOPM, 0, 0),
  1028. /* Analog bypasses */
  1029. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1030. &twl4030_dapm_abypassr1_control, bypass_event,
  1031. SND_SOC_DAPM_POST_REG),
  1032. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1033. &twl4030_dapm_abypassl1_control,
  1034. bypass_event, SND_SOC_DAPM_POST_REG),
  1035. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1036. &twl4030_dapm_abypassr2_control,
  1037. bypass_event, SND_SOC_DAPM_POST_REG),
  1038. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1039. &twl4030_dapm_abypassl2_control,
  1040. bypass_event, SND_SOC_DAPM_POST_REG),
  1041. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1042. &twl4030_dapm_abypassv_control,
  1043. bypass_event, SND_SOC_DAPM_POST_REG),
  1044. /* Digital bypasses */
  1045. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1046. &twl4030_dapm_dbypassl_control, bypass_event,
  1047. SND_SOC_DAPM_POST_REG),
  1048. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1049. &twl4030_dapm_dbypassr_control, bypass_event,
  1050. SND_SOC_DAPM_POST_REG),
  1051. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1052. &twl4030_dapm_dbypassv_control, bypass_event,
  1053. SND_SOC_DAPM_POST_REG),
  1054. /* Digital mixers, power control for the physical DACs */
  1055. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1056. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1057. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1058. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1059. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1060. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1061. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1062. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1063. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1064. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1065. /* Analog mixers, power control for the physical PGAs */
  1066. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1067. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1068. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1069. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1070. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1071. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1072. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1073. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1074. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1075. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1076. /* Output MIXER controls */
  1077. /* Earpiece */
  1078. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1079. &twl4030_dapm_earpiece_controls[0],
  1080. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1081. /* PreDrivL/R */
  1082. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1083. &twl4030_dapm_predrivel_controls[0],
  1084. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1085. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1086. &twl4030_dapm_predriver_controls[0],
  1087. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1088. /* HeadsetL/R */
  1089. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1090. &twl4030_dapm_hsol_controls[0],
  1091. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1092. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1093. 0, 0, NULL, 0, headsetlpga_event,
  1094. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1095. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1096. &twl4030_dapm_hsor_controls[0],
  1097. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1098. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1099. 0, 0, NULL, 0, headsetrpga_event,
  1100. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1101. /* CarkitL/R */
  1102. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_carkitl_controls[0],
  1104. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1105. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1106. &twl4030_dapm_carkitr_controls[0],
  1107. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1108. /* Output MUX controls */
  1109. /* HandsfreeL/R */
  1110. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1111. &twl4030_dapm_handsfreel_control),
  1112. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1113. &twl4030_dapm_handsfreelmute_control),
  1114. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1115. 0, 0, NULL, 0, handsfreelpga_event,
  1116. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1117. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1118. &twl4030_dapm_handsfreer_control),
  1119. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1120. &twl4030_dapm_handsfreermute_control),
  1121. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1122. 0, 0, NULL, 0, handsfreerpga_event,
  1123. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1124. /* Vibra */
  1125. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1126. &twl4030_dapm_vibra_control),
  1127. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1128. &twl4030_dapm_vibrapath_control),
  1129. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1130. capture */
  1131. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1132. SND_SOC_NOPM, 0, 0),
  1133. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1134. SND_SOC_NOPM, 0, 0),
  1135. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1136. SND_SOC_NOPM, 0, 0),
  1137. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1138. SND_SOC_NOPM, 0, 0),
  1139. /* Analog/Digital mic path selection.
  1140. TX1 Left/Right: either analog Left/Right or Digimic0
  1141. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1142. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1143. &twl4030_dapm_micpathtx1_control, micpath_event,
  1144. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1145. SND_SOC_DAPM_POST_REG),
  1146. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1147. &twl4030_dapm_micpathtx2_control, micpath_event,
  1148. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1149. SND_SOC_DAPM_POST_REG),
  1150. /* Analog input mixers for the capture amplifiers */
  1151. SND_SOC_DAPM_MIXER("Analog Left Capture Route",
  1152. TWL4030_REG_ANAMICL, 4, 0,
  1153. &twl4030_dapm_analoglmic_controls[0],
  1154. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1155. SND_SOC_DAPM_MIXER("Analog Right Capture Route",
  1156. TWL4030_REG_ANAMICR, 4, 0,
  1157. &twl4030_dapm_analogrmic_controls[0],
  1158. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1159. SND_SOC_DAPM_PGA("ADC Physical Left",
  1160. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1161. SND_SOC_DAPM_PGA("ADC Physical Right",
  1162. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1163. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1164. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1165. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1166. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1167. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1168. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1169. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1170. };
  1171. static const struct snd_soc_dapm_route intercon[] = {
  1172. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1173. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1174. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1175. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1176. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1177. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1178. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1179. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1180. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1181. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1182. /* Internal playback routings */
  1183. /* Earpiece */
  1184. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1185. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1186. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1187. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1188. /* PreDrivL */
  1189. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1190. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1191. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1192. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1193. /* PreDrivR */
  1194. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1195. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1196. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1197. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1198. /* HeadsetL */
  1199. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1200. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1201. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1202. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1203. /* HeadsetR */
  1204. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1205. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1206. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1207. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1208. /* CarkitL */
  1209. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1210. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1211. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1212. /* CarkitR */
  1213. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1214. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1215. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1216. /* HandsfreeL */
  1217. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1218. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1219. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1220. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1221. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1222. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1223. /* HandsfreeR */
  1224. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1225. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1226. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1227. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1228. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1229. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1230. /* Vibra */
  1231. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1232. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1233. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1234. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1235. /* outputs */
  1236. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1237. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1238. {"EARPIECE", NULL, "Earpiece Mixer"},
  1239. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  1240. {"PREDRIVER", NULL, "PredriveR Mixer"},
  1241. {"HSOL", NULL, "HeadsetL PGA"},
  1242. {"HSOR", NULL, "HeadsetR PGA"},
  1243. {"CARKITL", NULL, "CarkitL Mixer"},
  1244. {"CARKITR", NULL, "CarkitR Mixer"},
  1245. {"HFL", NULL, "HandsfreeL PGA"},
  1246. {"HFR", NULL, "HandsfreeR PGA"},
  1247. {"Vibra Route", "Audio", "Vibra Mux"},
  1248. {"VIBRA", NULL, "Vibra Route"},
  1249. /* Capture path */
  1250. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1251. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1252. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1253. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1254. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1255. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1256. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1257. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1258. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1259. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1260. /* TX1 Left capture path */
  1261. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1262. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1263. /* TX1 Right capture path */
  1264. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1265. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1266. /* TX2 Left capture path */
  1267. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1268. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1269. /* TX2 Right capture path */
  1270. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1271. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1272. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1273. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1274. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1275. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1276. /* Analog bypass routes */
  1277. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1278. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1279. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1280. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1281. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1282. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1283. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1284. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1285. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1286. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1287. /* Digital bypass routes */
  1288. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1289. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1290. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1291. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1292. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1293. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1294. };
  1295. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1296. {
  1297. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1298. ARRAY_SIZE(twl4030_dapm_widgets));
  1299. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1300. snd_soc_dapm_new_widgets(codec);
  1301. return 0;
  1302. }
  1303. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1304. enum snd_soc_bias_level level)
  1305. {
  1306. struct twl4030_priv *twl4030 = codec->private_data;
  1307. switch (level) {
  1308. case SND_SOC_BIAS_ON:
  1309. twl4030_codec_mute(codec, 0);
  1310. break;
  1311. case SND_SOC_BIAS_PREPARE:
  1312. twl4030_power_up(codec);
  1313. if (twl4030->bypass_state)
  1314. twl4030_codec_mute(codec, 0);
  1315. else
  1316. twl4030_codec_mute(codec, 1);
  1317. break;
  1318. case SND_SOC_BIAS_STANDBY:
  1319. twl4030_power_up(codec);
  1320. if (twl4030->bypass_state)
  1321. twl4030_codec_mute(codec, 0);
  1322. else
  1323. twl4030_codec_mute(codec, 1);
  1324. break;
  1325. case SND_SOC_BIAS_OFF:
  1326. twl4030_power_down(codec);
  1327. break;
  1328. }
  1329. codec->bias_level = level;
  1330. return 0;
  1331. }
  1332. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1333. struct snd_pcm_substream *mst_substream)
  1334. {
  1335. struct snd_pcm_substream *slv_substream;
  1336. /* Pick the stream, which need to be constrained */
  1337. if (mst_substream == twl4030->master_substream)
  1338. slv_substream = twl4030->slave_substream;
  1339. else if (mst_substream == twl4030->slave_substream)
  1340. slv_substream = twl4030->master_substream;
  1341. else /* This should not happen.. */
  1342. return;
  1343. /* Set the constraints according to the already configured stream */
  1344. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1345. SNDRV_PCM_HW_PARAM_RATE,
  1346. twl4030->rate,
  1347. twl4030->rate);
  1348. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1349. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1350. twl4030->sample_bits,
  1351. twl4030->sample_bits);
  1352. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1353. SNDRV_PCM_HW_PARAM_CHANNELS,
  1354. twl4030->channels,
  1355. twl4030->channels);
  1356. }
  1357. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1358. * capture has to be enabled/disabled. */
  1359. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1360. int enable)
  1361. {
  1362. u8 reg, mask;
  1363. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1364. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1365. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1366. else
  1367. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1368. if (enable)
  1369. reg |= mask;
  1370. else
  1371. reg &= ~mask;
  1372. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1373. }
  1374. static int twl4030_startup(struct snd_pcm_substream *substream,
  1375. struct snd_soc_dai *dai)
  1376. {
  1377. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1378. struct snd_soc_device *socdev = rtd->socdev;
  1379. struct snd_soc_codec *codec = socdev->card->codec;
  1380. struct twl4030_priv *twl4030 = codec->private_data;
  1381. if (twl4030->master_substream) {
  1382. twl4030->slave_substream = substream;
  1383. /* The DAI has one configuration for playback and capture, so
  1384. * if the DAI has been already configured then constrain this
  1385. * substream to match it. */
  1386. if (twl4030->configured)
  1387. twl4030_constraints(twl4030, twl4030->master_substream);
  1388. } else {
  1389. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1390. TWL4030_OPTION_1)) {
  1391. /* In option2 4 channel is not supported, set the
  1392. * constraint for the first stream for channels, the
  1393. * second stream will 'inherit' this cosntraint */
  1394. snd_pcm_hw_constraint_minmax(substream->runtime,
  1395. SNDRV_PCM_HW_PARAM_CHANNELS,
  1396. 2, 2);
  1397. }
  1398. twl4030->master_substream = substream;
  1399. }
  1400. return 0;
  1401. }
  1402. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1403. struct snd_soc_dai *dai)
  1404. {
  1405. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1406. struct snd_soc_device *socdev = rtd->socdev;
  1407. struct snd_soc_codec *codec = socdev->card->codec;
  1408. struct twl4030_priv *twl4030 = codec->private_data;
  1409. if (twl4030->master_substream == substream)
  1410. twl4030->master_substream = twl4030->slave_substream;
  1411. twl4030->slave_substream = NULL;
  1412. /* If all streams are closed, or the remaining stream has not yet
  1413. * been configured than set the DAI as not configured. */
  1414. if (!twl4030->master_substream)
  1415. twl4030->configured = 0;
  1416. else if (!twl4030->master_substream->runtime->channels)
  1417. twl4030->configured = 0;
  1418. /* If the closing substream had 4 channel, do the necessary cleanup */
  1419. if (substream->runtime->channels == 4)
  1420. twl4030_tdm_enable(codec, substream->stream, 0);
  1421. }
  1422. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1423. struct snd_pcm_hw_params *params,
  1424. struct snd_soc_dai *dai)
  1425. {
  1426. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1427. struct snd_soc_device *socdev = rtd->socdev;
  1428. struct snd_soc_codec *codec = socdev->card->codec;
  1429. struct twl4030_priv *twl4030 = codec->private_data;
  1430. u8 mode, old_mode, format, old_format;
  1431. /* If the substream has 4 channel, do the necessary setup */
  1432. if (params_channels(params) == 4) {
  1433. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1434. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1435. /* Safety check: are we in the correct operating mode and
  1436. * the interface is in TDM mode? */
  1437. if ((mode & TWL4030_OPTION_1) &&
  1438. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1439. twl4030_tdm_enable(codec, substream->stream, 1);
  1440. else
  1441. return -EINVAL;
  1442. }
  1443. if (twl4030->configured)
  1444. /* Ignoring hw_params for already configured DAI */
  1445. return 0;
  1446. /* bit rate */
  1447. old_mode = twl4030_read_reg_cache(codec,
  1448. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1449. mode = old_mode & ~TWL4030_APLL_RATE;
  1450. switch (params_rate(params)) {
  1451. case 8000:
  1452. mode |= TWL4030_APLL_RATE_8000;
  1453. break;
  1454. case 11025:
  1455. mode |= TWL4030_APLL_RATE_11025;
  1456. break;
  1457. case 12000:
  1458. mode |= TWL4030_APLL_RATE_12000;
  1459. break;
  1460. case 16000:
  1461. mode |= TWL4030_APLL_RATE_16000;
  1462. break;
  1463. case 22050:
  1464. mode |= TWL4030_APLL_RATE_22050;
  1465. break;
  1466. case 24000:
  1467. mode |= TWL4030_APLL_RATE_24000;
  1468. break;
  1469. case 32000:
  1470. mode |= TWL4030_APLL_RATE_32000;
  1471. break;
  1472. case 44100:
  1473. mode |= TWL4030_APLL_RATE_44100;
  1474. break;
  1475. case 48000:
  1476. mode |= TWL4030_APLL_RATE_48000;
  1477. break;
  1478. case 96000:
  1479. mode |= TWL4030_APLL_RATE_96000;
  1480. break;
  1481. default:
  1482. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1483. params_rate(params));
  1484. return -EINVAL;
  1485. }
  1486. if (mode != old_mode) {
  1487. /* change rate and set CODECPDZ */
  1488. twl4030_codec_enable(codec, 0);
  1489. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1490. twl4030_codec_enable(codec, 1);
  1491. }
  1492. /* sample size */
  1493. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1494. format = old_format;
  1495. format &= ~TWL4030_DATA_WIDTH;
  1496. switch (params_format(params)) {
  1497. case SNDRV_PCM_FORMAT_S16_LE:
  1498. format |= TWL4030_DATA_WIDTH_16S_16W;
  1499. break;
  1500. case SNDRV_PCM_FORMAT_S24_LE:
  1501. format |= TWL4030_DATA_WIDTH_32S_24W;
  1502. break;
  1503. default:
  1504. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1505. params_format(params));
  1506. return -EINVAL;
  1507. }
  1508. if (format != old_format) {
  1509. /* clear CODECPDZ before changing format (codec requirement) */
  1510. twl4030_codec_enable(codec, 0);
  1511. /* change format */
  1512. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1513. /* set CODECPDZ afterwards */
  1514. twl4030_codec_enable(codec, 1);
  1515. }
  1516. /* Store the important parameters for the DAI configuration and set
  1517. * the DAI as configured */
  1518. twl4030->configured = 1;
  1519. twl4030->rate = params_rate(params);
  1520. twl4030->sample_bits = hw_param_interval(params,
  1521. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1522. twl4030->channels = params_channels(params);
  1523. /* If both playback and capture streams are open, and one of them
  1524. * is setting the hw parameters right now (since we are here), set
  1525. * constraints to the other stream to match the current one. */
  1526. if (twl4030->slave_substream)
  1527. twl4030_constraints(twl4030, substream);
  1528. return 0;
  1529. }
  1530. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1531. int clk_id, unsigned int freq, int dir)
  1532. {
  1533. struct snd_soc_codec *codec = codec_dai->codec;
  1534. struct twl4030_priv *twl4030 = codec->private_data;
  1535. u8 infreq;
  1536. switch (freq) {
  1537. case 19200000:
  1538. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1539. twl4030->sysclk = 19200;
  1540. break;
  1541. case 26000000:
  1542. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1543. twl4030->sysclk = 26000;
  1544. break;
  1545. case 38400000:
  1546. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1547. twl4030->sysclk = 38400;
  1548. break;
  1549. default:
  1550. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1551. freq);
  1552. return -EINVAL;
  1553. }
  1554. infreq |= TWL4030_APLL_EN;
  1555. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1556. return 0;
  1557. }
  1558. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1559. unsigned int fmt)
  1560. {
  1561. struct snd_soc_codec *codec = codec_dai->codec;
  1562. u8 old_format, format;
  1563. /* get format */
  1564. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1565. format = old_format;
  1566. /* set master/slave audio interface */
  1567. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1568. case SND_SOC_DAIFMT_CBM_CFM:
  1569. format &= ~(TWL4030_AIF_SLAVE_EN);
  1570. format &= ~(TWL4030_CLK256FS_EN);
  1571. break;
  1572. case SND_SOC_DAIFMT_CBS_CFS:
  1573. format |= TWL4030_AIF_SLAVE_EN;
  1574. format |= TWL4030_CLK256FS_EN;
  1575. break;
  1576. default:
  1577. return -EINVAL;
  1578. }
  1579. /* interface format */
  1580. format &= ~TWL4030_AIF_FORMAT;
  1581. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1582. case SND_SOC_DAIFMT_I2S:
  1583. format |= TWL4030_AIF_FORMAT_CODEC;
  1584. break;
  1585. case SND_SOC_DAIFMT_DSP_A:
  1586. format |= TWL4030_AIF_FORMAT_TDM;
  1587. break;
  1588. default:
  1589. return -EINVAL;
  1590. }
  1591. if (format != old_format) {
  1592. /* clear CODECPDZ before changing format (codec requirement) */
  1593. twl4030_codec_enable(codec, 0);
  1594. /* change format */
  1595. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1596. /* set CODECPDZ afterwards */
  1597. twl4030_codec_enable(codec, 1);
  1598. }
  1599. return 0;
  1600. }
  1601. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1602. {
  1603. struct snd_soc_codec *codec = dai->codec;
  1604. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1605. if (tristate)
  1606. reg |= TWL4030_AIF_TRI_EN;
  1607. else
  1608. reg &= ~TWL4030_AIF_TRI_EN;
  1609. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1610. }
  1611. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1612. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1613. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1614. int enable)
  1615. {
  1616. u8 reg, mask;
  1617. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1618. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1619. mask = TWL4030_ARXL1_VRX_EN;
  1620. else
  1621. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1622. if (enable)
  1623. reg |= mask;
  1624. else
  1625. reg &= ~mask;
  1626. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1627. }
  1628. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1629. struct snd_soc_dai *dai)
  1630. {
  1631. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1632. struct snd_soc_device *socdev = rtd->socdev;
  1633. struct snd_soc_codec *codec = socdev->card->codec;
  1634. u8 infreq;
  1635. u8 mode;
  1636. /* If the system master clock is not 26MHz, the voice PCM interface is
  1637. * not avilable.
  1638. */
  1639. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1640. & TWL4030_APLL_INFREQ;
  1641. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1642. printk(KERN_ERR "TWL4030 voice startup: "
  1643. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1644. return -EINVAL;
  1645. }
  1646. /* If the codec mode is not option2, the voice PCM interface is not
  1647. * avilable.
  1648. */
  1649. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1650. & TWL4030_OPT_MODE;
  1651. if (mode != TWL4030_OPTION_2) {
  1652. printk(KERN_ERR "TWL4030 voice startup: "
  1653. "the codec mode is not option2\n");
  1654. return -EINVAL;
  1655. }
  1656. return 0;
  1657. }
  1658. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1659. struct snd_soc_dai *dai)
  1660. {
  1661. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1662. struct snd_soc_device *socdev = rtd->socdev;
  1663. struct snd_soc_codec *codec = socdev->card->codec;
  1664. /* Enable voice digital filters */
  1665. twl4030_voice_enable(codec, substream->stream, 0);
  1666. }
  1667. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1668. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1669. {
  1670. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1671. struct snd_soc_device *socdev = rtd->socdev;
  1672. struct snd_soc_codec *codec = socdev->card->codec;
  1673. u8 old_mode, mode;
  1674. /* Enable voice digital filters */
  1675. twl4030_voice_enable(codec, substream->stream, 1);
  1676. /* bit rate */
  1677. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1678. & ~(TWL4030_CODECPDZ);
  1679. mode = old_mode;
  1680. switch (params_rate(params)) {
  1681. case 8000:
  1682. mode &= ~(TWL4030_SEL_16K);
  1683. break;
  1684. case 16000:
  1685. mode |= TWL4030_SEL_16K;
  1686. break;
  1687. default:
  1688. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1689. params_rate(params));
  1690. return -EINVAL;
  1691. }
  1692. if (mode != old_mode) {
  1693. /* change rate and set CODECPDZ */
  1694. twl4030_codec_enable(codec, 0);
  1695. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1696. twl4030_codec_enable(codec, 1);
  1697. }
  1698. return 0;
  1699. }
  1700. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1701. int clk_id, unsigned int freq, int dir)
  1702. {
  1703. struct snd_soc_codec *codec = codec_dai->codec;
  1704. u8 infreq;
  1705. switch (freq) {
  1706. case 26000000:
  1707. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1708. break;
  1709. default:
  1710. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1711. freq);
  1712. return -EINVAL;
  1713. }
  1714. infreq |= TWL4030_APLL_EN;
  1715. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1716. return 0;
  1717. }
  1718. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1719. unsigned int fmt)
  1720. {
  1721. struct snd_soc_codec *codec = codec_dai->codec;
  1722. u8 old_format, format;
  1723. /* get format */
  1724. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1725. format = old_format;
  1726. /* set master/slave audio interface */
  1727. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1728. case SND_SOC_DAIFMT_CBM_CFM:
  1729. format &= ~(TWL4030_VIF_SLAVE_EN);
  1730. break;
  1731. case SND_SOC_DAIFMT_CBS_CFS:
  1732. format |= TWL4030_VIF_SLAVE_EN;
  1733. break;
  1734. default:
  1735. return -EINVAL;
  1736. }
  1737. /* clock inversion */
  1738. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1739. case SND_SOC_DAIFMT_IB_NF:
  1740. format &= ~(TWL4030_VIF_FORMAT);
  1741. break;
  1742. case SND_SOC_DAIFMT_NB_IF:
  1743. format |= TWL4030_VIF_FORMAT;
  1744. break;
  1745. default:
  1746. return -EINVAL;
  1747. }
  1748. if (format != old_format) {
  1749. /* change format and set CODECPDZ */
  1750. twl4030_codec_enable(codec, 0);
  1751. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1752. twl4030_codec_enable(codec, 1);
  1753. }
  1754. return 0;
  1755. }
  1756. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1757. {
  1758. struct snd_soc_codec *codec = dai->codec;
  1759. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1760. if (tristate)
  1761. reg |= TWL4030_VIF_TRI_EN;
  1762. else
  1763. reg &= ~TWL4030_VIF_TRI_EN;
  1764. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1765. }
  1766. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1767. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1768. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1769. .startup = twl4030_startup,
  1770. .shutdown = twl4030_shutdown,
  1771. .hw_params = twl4030_hw_params,
  1772. .set_sysclk = twl4030_set_dai_sysclk,
  1773. .set_fmt = twl4030_set_dai_fmt,
  1774. .set_tristate = twl4030_set_tristate,
  1775. };
  1776. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1777. .startup = twl4030_voice_startup,
  1778. .shutdown = twl4030_voice_shutdown,
  1779. .hw_params = twl4030_voice_hw_params,
  1780. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1781. .set_fmt = twl4030_voice_set_dai_fmt,
  1782. .set_tristate = twl4030_voice_set_tristate,
  1783. };
  1784. struct snd_soc_dai twl4030_dai[] = {
  1785. {
  1786. .name = "twl4030",
  1787. .playback = {
  1788. .stream_name = "HiFi Playback",
  1789. .channels_min = 2,
  1790. .channels_max = 4,
  1791. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1792. .formats = TWL4030_FORMATS,},
  1793. .capture = {
  1794. .stream_name = "Capture",
  1795. .channels_min = 2,
  1796. .channels_max = 4,
  1797. .rates = TWL4030_RATES,
  1798. .formats = TWL4030_FORMATS,},
  1799. .ops = &twl4030_dai_ops,
  1800. },
  1801. {
  1802. .name = "twl4030 Voice",
  1803. .playback = {
  1804. .stream_name = "Voice Playback",
  1805. .channels_min = 1,
  1806. .channels_max = 1,
  1807. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1808. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1809. .capture = {
  1810. .stream_name = "Capture",
  1811. .channels_min = 1,
  1812. .channels_max = 2,
  1813. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1814. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1815. .ops = &twl4030_dai_voice_ops,
  1816. },
  1817. };
  1818. EXPORT_SYMBOL_GPL(twl4030_dai);
  1819. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1820. {
  1821. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1822. struct snd_soc_codec *codec = socdev->card->codec;
  1823. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1824. return 0;
  1825. }
  1826. static int twl4030_resume(struct platform_device *pdev)
  1827. {
  1828. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1829. struct snd_soc_codec *codec = socdev->card->codec;
  1830. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1831. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1832. return 0;
  1833. }
  1834. /*
  1835. * initialize the driver
  1836. * register the mixer and dsp interfaces with the kernel
  1837. */
  1838. static int twl4030_init(struct snd_soc_device *socdev)
  1839. {
  1840. struct snd_soc_codec *codec = socdev->card->codec;
  1841. struct twl4030_setup_data *setup = socdev->codec_data;
  1842. struct twl4030_priv *twl4030 = codec->private_data;
  1843. int ret = 0;
  1844. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1845. codec->name = "twl4030";
  1846. codec->owner = THIS_MODULE;
  1847. codec->read = twl4030_read_reg_cache;
  1848. codec->write = twl4030_write;
  1849. codec->set_bias_level = twl4030_set_bias_level;
  1850. codec->dai = twl4030_dai;
  1851. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1852. codec->reg_cache_size = sizeof(twl4030_reg);
  1853. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1854. GFP_KERNEL);
  1855. if (codec->reg_cache == NULL)
  1856. return -ENOMEM;
  1857. /* Configuration for headset ramp delay from setup data */
  1858. if (setup) {
  1859. unsigned char hs_pop;
  1860. if (setup->sysclk)
  1861. twl4030->sysclk = setup->sysclk;
  1862. else
  1863. twl4030->sysclk = 26000;
  1864. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1865. hs_pop &= ~TWL4030_RAMP_DELAY;
  1866. hs_pop |= (setup->ramp_delay_value << 2);
  1867. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1868. } else {
  1869. twl4030->sysclk = 26000;
  1870. }
  1871. /* register pcms */
  1872. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1873. if (ret < 0) {
  1874. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1875. goto pcm_err;
  1876. }
  1877. twl4030_init_chip(codec);
  1878. /* power on device */
  1879. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1880. snd_soc_add_controls(codec, twl4030_snd_controls,
  1881. ARRAY_SIZE(twl4030_snd_controls));
  1882. twl4030_add_widgets(codec);
  1883. ret = snd_soc_init_card(socdev);
  1884. if (ret < 0) {
  1885. printk(KERN_ERR "twl4030: failed to register card\n");
  1886. goto card_err;
  1887. }
  1888. return ret;
  1889. card_err:
  1890. snd_soc_free_pcms(socdev);
  1891. snd_soc_dapm_free(socdev);
  1892. pcm_err:
  1893. kfree(codec->reg_cache);
  1894. return ret;
  1895. }
  1896. static struct snd_soc_device *twl4030_socdev;
  1897. static int twl4030_probe(struct platform_device *pdev)
  1898. {
  1899. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1900. struct snd_soc_codec *codec;
  1901. struct twl4030_priv *twl4030;
  1902. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1903. if (codec == NULL)
  1904. return -ENOMEM;
  1905. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1906. if (twl4030 == NULL) {
  1907. kfree(codec);
  1908. return -ENOMEM;
  1909. }
  1910. codec->private_data = twl4030;
  1911. socdev->card->codec = codec;
  1912. mutex_init(&codec->mutex);
  1913. INIT_LIST_HEAD(&codec->dapm_widgets);
  1914. INIT_LIST_HEAD(&codec->dapm_paths);
  1915. twl4030_socdev = socdev;
  1916. twl4030_init(socdev);
  1917. return 0;
  1918. }
  1919. static int twl4030_remove(struct platform_device *pdev)
  1920. {
  1921. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1922. struct snd_soc_codec *codec = socdev->card->codec;
  1923. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1924. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1925. snd_soc_free_pcms(socdev);
  1926. snd_soc_dapm_free(socdev);
  1927. kfree(codec->private_data);
  1928. kfree(codec);
  1929. return 0;
  1930. }
  1931. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1932. .probe = twl4030_probe,
  1933. .remove = twl4030_remove,
  1934. .suspend = twl4030_suspend,
  1935. .resume = twl4030_resume,
  1936. };
  1937. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1938. static int __init twl4030_modinit(void)
  1939. {
  1940. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1941. }
  1942. module_init(twl4030_modinit);
  1943. static void __exit twl4030_exit(void)
  1944. {
  1945. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1946. }
  1947. module_exit(twl4030_exit);
  1948. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1949. MODULE_AUTHOR("Steve Sakoman");
  1950. MODULE_LICENSE("GPL");