trinity_dpm.c 55 KB

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  1. /*
  2. * Copyright 2012 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include "drmP.h"
  24. #include "radeon.h"
  25. #include "trinityd.h"
  26. #include "r600_dpm.h"
  27. #include "trinity_dpm.h"
  28. #include <linux/seq_file.h>
  29. #define TRINITY_MAX_DEEPSLEEP_DIVIDER_ID 5
  30. #define TRINITY_MINIMUM_ENGINE_CLOCK 800
  31. #define SCLK_MIN_DIV_INTV_SHIFT 12
  32. #define TRINITY_DISPCLK_BYPASS_THRESHOLD 10000
  33. #ifndef TRINITY_MGCG_SEQUENCE
  34. #define TRINITY_MGCG_SEQUENCE 100
  35. static const u32 trinity_mgcg_shls_default[] =
  36. {
  37. /* Register, Value, Mask */
  38. 0x0000802c, 0xc0000000, 0xffffffff,
  39. 0x00003fc4, 0xc0000000, 0xffffffff,
  40. 0x00005448, 0x00000100, 0xffffffff,
  41. 0x000055e4, 0x00000100, 0xffffffff,
  42. 0x0000160c, 0x00000100, 0xffffffff,
  43. 0x00008984, 0x06000100, 0xffffffff,
  44. 0x0000c164, 0x00000100, 0xffffffff,
  45. 0x00008a18, 0x00000100, 0xffffffff,
  46. 0x0000897c, 0x06000100, 0xffffffff,
  47. 0x00008b28, 0x00000100, 0xffffffff,
  48. 0x00009144, 0x00800200, 0xffffffff,
  49. 0x00009a60, 0x00000100, 0xffffffff,
  50. 0x00009868, 0x00000100, 0xffffffff,
  51. 0x00008d58, 0x00000100, 0xffffffff,
  52. 0x00009510, 0x00000100, 0xffffffff,
  53. 0x0000949c, 0x00000100, 0xffffffff,
  54. 0x00009654, 0x00000100, 0xffffffff,
  55. 0x00009030, 0x00000100, 0xffffffff,
  56. 0x00009034, 0x00000100, 0xffffffff,
  57. 0x00009038, 0x00000100, 0xffffffff,
  58. 0x0000903c, 0x00000100, 0xffffffff,
  59. 0x00009040, 0x00000100, 0xffffffff,
  60. 0x0000a200, 0x00000100, 0xffffffff,
  61. 0x0000a204, 0x00000100, 0xffffffff,
  62. 0x0000a208, 0x00000100, 0xffffffff,
  63. 0x0000a20c, 0x00000100, 0xffffffff,
  64. 0x00009744, 0x00000100, 0xffffffff,
  65. 0x00003f80, 0x00000100, 0xffffffff,
  66. 0x0000a210, 0x00000100, 0xffffffff,
  67. 0x0000a214, 0x00000100, 0xffffffff,
  68. 0x000004d8, 0x00000100, 0xffffffff,
  69. 0x00009664, 0x00000100, 0xffffffff,
  70. 0x00009698, 0x00000100, 0xffffffff,
  71. 0x000004d4, 0x00000200, 0xffffffff,
  72. 0x000004d0, 0x00000000, 0xffffffff,
  73. 0x000030cc, 0x00000104, 0xffffffff,
  74. 0x0000d0c0, 0x00000100, 0xffffffff,
  75. 0x0000d8c0, 0x00000100, 0xffffffff,
  76. 0x0000951c, 0x00010000, 0xffffffff,
  77. 0x00009160, 0x00030002, 0xffffffff,
  78. 0x00009164, 0x00050004, 0xffffffff,
  79. 0x00009168, 0x00070006, 0xffffffff,
  80. 0x00009178, 0x00070000, 0xffffffff,
  81. 0x0000917c, 0x00030002, 0xffffffff,
  82. 0x00009180, 0x00050004, 0xffffffff,
  83. 0x0000918c, 0x00010006, 0xffffffff,
  84. 0x00009190, 0x00090008, 0xffffffff,
  85. 0x00009194, 0x00070000, 0xffffffff,
  86. 0x00009198, 0x00030002, 0xffffffff,
  87. 0x0000919c, 0x00050004, 0xffffffff,
  88. 0x000091a8, 0x00010006, 0xffffffff,
  89. 0x000091ac, 0x00090008, 0xffffffff,
  90. 0x000091b0, 0x00070000, 0xffffffff,
  91. 0x000091b4, 0x00030002, 0xffffffff,
  92. 0x000091b8, 0x00050004, 0xffffffff,
  93. 0x000091c4, 0x00010006, 0xffffffff,
  94. 0x000091c8, 0x00090008, 0xffffffff,
  95. 0x000091cc, 0x00070000, 0xffffffff,
  96. 0x000091d0, 0x00030002, 0xffffffff,
  97. 0x000091d4, 0x00050004, 0xffffffff,
  98. 0x000091e0, 0x00010006, 0xffffffff,
  99. 0x000091e4, 0x00090008, 0xffffffff,
  100. 0x000091e8, 0x00000000, 0xffffffff,
  101. 0x000091ec, 0x00070000, 0xffffffff,
  102. 0x000091f0, 0x00030002, 0xffffffff,
  103. 0x000091f4, 0x00050004, 0xffffffff,
  104. 0x00009200, 0x00010006, 0xffffffff,
  105. 0x00009204, 0x00090008, 0xffffffff,
  106. 0x00009208, 0x00070000, 0xffffffff,
  107. 0x0000920c, 0x00030002, 0xffffffff,
  108. 0x00009210, 0x00050004, 0xffffffff,
  109. 0x0000921c, 0x00010006, 0xffffffff,
  110. 0x00009220, 0x00090008, 0xffffffff,
  111. 0x00009294, 0x00000000, 0xffffffff
  112. };
  113. static const u32 trinity_mgcg_shls_enable[] =
  114. {
  115. /* Register, Value, Mask */
  116. 0x0000802c, 0xc0000000, 0xffffffff,
  117. 0x000008f8, 0x00000000, 0xffffffff,
  118. 0x000008fc, 0x00000000, 0x000133FF,
  119. 0x000008f8, 0x00000001, 0xffffffff,
  120. 0x000008fc, 0x00000000, 0xE00B03FC,
  121. 0x00009150, 0x96944200, 0xffffffff
  122. };
  123. static const u32 trinity_mgcg_shls_disable[] =
  124. {
  125. /* Register, Value, Mask */
  126. 0x0000802c, 0xc0000000, 0xffffffff,
  127. 0x00009150, 0x00600000, 0xffffffff,
  128. 0x000008f8, 0x00000000, 0xffffffff,
  129. 0x000008fc, 0xffffffff, 0x000133FF,
  130. 0x000008f8, 0x00000001, 0xffffffff,
  131. 0x000008fc, 0xffffffff, 0xE00B03FC
  132. };
  133. #endif
  134. #ifndef TRINITY_SYSLS_SEQUENCE
  135. #define TRINITY_SYSLS_SEQUENCE 100
  136. static const u32 trinity_sysls_default[] =
  137. {
  138. /* Register, Value, Mask */
  139. 0x000055e8, 0x00000000, 0xffffffff,
  140. 0x0000d0bc, 0x00000000, 0xffffffff,
  141. 0x0000d8bc, 0x00000000, 0xffffffff,
  142. 0x000015c0, 0x000c1401, 0xffffffff,
  143. 0x0000264c, 0x000c0400, 0xffffffff,
  144. 0x00002648, 0x000c0400, 0xffffffff,
  145. 0x00002650, 0x000c0400, 0xffffffff,
  146. 0x000020b8, 0x000c0400, 0xffffffff,
  147. 0x000020bc, 0x000c0400, 0xffffffff,
  148. 0x000020c0, 0x000c0c80, 0xffffffff,
  149. 0x0000f4a0, 0x000000c0, 0xffffffff,
  150. 0x0000f4a4, 0x00680fff, 0xffffffff,
  151. 0x00002f50, 0x00000404, 0xffffffff,
  152. 0x000004c8, 0x00000001, 0xffffffff,
  153. 0x0000641c, 0x00000000, 0xffffffff,
  154. 0x00000c7c, 0x00000000, 0xffffffff,
  155. 0x00006dfc, 0x00000000, 0xffffffff
  156. };
  157. static const u32 trinity_sysls_disable[] =
  158. {
  159. /* Register, Value, Mask */
  160. 0x0000d0c0, 0x00000000, 0xffffffff,
  161. 0x0000d8c0, 0x00000000, 0xffffffff,
  162. 0x000055e8, 0x00000000, 0xffffffff,
  163. 0x0000d0bc, 0x00000000, 0xffffffff,
  164. 0x0000d8bc, 0x00000000, 0xffffffff,
  165. 0x000015c0, 0x00041401, 0xffffffff,
  166. 0x0000264c, 0x00040400, 0xffffffff,
  167. 0x00002648, 0x00040400, 0xffffffff,
  168. 0x00002650, 0x00040400, 0xffffffff,
  169. 0x000020b8, 0x00040400, 0xffffffff,
  170. 0x000020bc, 0x00040400, 0xffffffff,
  171. 0x000020c0, 0x00040c80, 0xffffffff,
  172. 0x0000f4a0, 0x000000c0, 0xffffffff,
  173. 0x0000f4a4, 0x00680000, 0xffffffff,
  174. 0x00002f50, 0x00000404, 0xffffffff,
  175. 0x000004c8, 0x00000001, 0xffffffff,
  176. 0x0000641c, 0x00007ffd, 0xffffffff,
  177. 0x00000c7c, 0x0000ff00, 0xffffffff,
  178. 0x00006dfc, 0x0000007f, 0xffffffff
  179. };
  180. static const u32 trinity_sysls_enable[] =
  181. {
  182. /* Register, Value, Mask */
  183. 0x000055e8, 0x00000001, 0xffffffff,
  184. 0x0000d0bc, 0x00000100, 0xffffffff,
  185. 0x0000d8bc, 0x00000100, 0xffffffff,
  186. 0x000015c0, 0x000c1401, 0xffffffff,
  187. 0x0000264c, 0x000c0400, 0xffffffff,
  188. 0x00002648, 0x000c0400, 0xffffffff,
  189. 0x00002650, 0x000c0400, 0xffffffff,
  190. 0x000020b8, 0x000c0400, 0xffffffff,
  191. 0x000020bc, 0x000c0400, 0xffffffff,
  192. 0x000020c0, 0x000c0c80, 0xffffffff,
  193. 0x0000f4a0, 0x000000c0, 0xffffffff,
  194. 0x0000f4a4, 0x00680fff, 0xffffffff,
  195. 0x00002f50, 0x00000903, 0xffffffff,
  196. 0x000004c8, 0x00000000, 0xffffffff,
  197. 0x0000641c, 0x00000000, 0xffffffff,
  198. 0x00000c7c, 0x00000000, 0xffffffff,
  199. 0x00006dfc, 0x00000000, 0xffffffff
  200. };
  201. #endif
  202. static const u32 trinity_override_mgpg_sequences[] =
  203. {
  204. /* Register, Value */
  205. 0x00000200, 0xE030032C,
  206. 0x00000204, 0x00000FFF,
  207. 0x00000200, 0xE0300058,
  208. 0x00000204, 0x00030301,
  209. 0x00000200, 0xE0300054,
  210. 0x00000204, 0x500010FF,
  211. 0x00000200, 0xE0300074,
  212. 0x00000204, 0x00030301,
  213. 0x00000200, 0xE0300070,
  214. 0x00000204, 0x500010FF,
  215. 0x00000200, 0xE0300090,
  216. 0x00000204, 0x00030301,
  217. 0x00000200, 0xE030008C,
  218. 0x00000204, 0x500010FF,
  219. 0x00000200, 0xE03000AC,
  220. 0x00000204, 0x00030301,
  221. 0x00000200, 0xE03000A8,
  222. 0x00000204, 0x500010FF,
  223. 0x00000200, 0xE03000C8,
  224. 0x00000204, 0x00030301,
  225. 0x00000200, 0xE03000C4,
  226. 0x00000204, 0x500010FF,
  227. 0x00000200, 0xE03000E4,
  228. 0x00000204, 0x00030301,
  229. 0x00000200, 0xE03000E0,
  230. 0x00000204, 0x500010FF,
  231. 0x00000200, 0xE0300100,
  232. 0x00000204, 0x00030301,
  233. 0x00000200, 0xE03000FC,
  234. 0x00000204, 0x500010FF,
  235. 0x00000200, 0xE0300058,
  236. 0x00000204, 0x00030303,
  237. 0x00000200, 0xE0300054,
  238. 0x00000204, 0x600010FF,
  239. 0x00000200, 0xE0300074,
  240. 0x00000204, 0x00030303,
  241. 0x00000200, 0xE0300070,
  242. 0x00000204, 0x600010FF,
  243. 0x00000200, 0xE0300090,
  244. 0x00000204, 0x00030303,
  245. 0x00000200, 0xE030008C,
  246. 0x00000204, 0x600010FF,
  247. 0x00000200, 0xE03000AC,
  248. 0x00000204, 0x00030303,
  249. 0x00000200, 0xE03000A8,
  250. 0x00000204, 0x600010FF,
  251. 0x00000200, 0xE03000C8,
  252. 0x00000204, 0x00030303,
  253. 0x00000200, 0xE03000C4,
  254. 0x00000204, 0x600010FF,
  255. 0x00000200, 0xE03000E4,
  256. 0x00000204, 0x00030303,
  257. 0x00000200, 0xE03000E0,
  258. 0x00000204, 0x600010FF,
  259. 0x00000200, 0xE0300100,
  260. 0x00000204, 0x00030303,
  261. 0x00000200, 0xE03000FC,
  262. 0x00000204, 0x600010FF,
  263. 0x00000200, 0xE0300058,
  264. 0x00000204, 0x00030303,
  265. 0x00000200, 0xE0300054,
  266. 0x00000204, 0x700010FF,
  267. 0x00000200, 0xE0300074,
  268. 0x00000204, 0x00030303,
  269. 0x00000200, 0xE0300070,
  270. 0x00000204, 0x700010FF,
  271. 0x00000200, 0xE0300090,
  272. 0x00000204, 0x00030303,
  273. 0x00000200, 0xE030008C,
  274. 0x00000204, 0x700010FF,
  275. 0x00000200, 0xE03000AC,
  276. 0x00000204, 0x00030303,
  277. 0x00000200, 0xE03000A8,
  278. 0x00000204, 0x700010FF,
  279. 0x00000200, 0xE03000C8,
  280. 0x00000204, 0x00030303,
  281. 0x00000200, 0xE03000C4,
  282. 0x00000204, 0x700010FF,
  283. 0x00000200, 0xE03000E4,
  284. 0x00000204, 0x00030303,
  285. 0x00000200, 0xE03000E0,
  286. 0x00000204, 0x700010FF,
  287. 0x00000200, 0xE0300100,
  288. 0x00000204, 0x00030303,
  289. 0x00000200, 0xE03000FC,
  290. 0x00000204, 0x700010FF,
  291. 0x00000200, 0xE0300058,
  292. 0x00000204, 0x00010303,
  293. 0x00000200, 0xE0300054,
  294. 0x00000204, 0x800010FF,
  295. 0x00000200, 0xE0300074,
  296. 0x00000204, 0x00010303,
  297. 0x00000200, 0xE0300070,
  298. 0x00000204, 0x800010FF,
  299. 0x00000200, 0xE0300090,
  300. 0x00000204, 0x00010303,
  301. 0x00000200, 0xE030008C,
  302. 0x00000204, 0x800010FF,
  303. 0x00000200, 0xE03000AC,
  304. 0x00000204, 0x00010303,
  305. 0x00000200, 0xE03000A8,
  306. 0x00000204, 0x800010FF,
  307. 0x00000200, 0xE03000C4,
  308. 0x00000204, 0x800010FF,
  309. 0x00000200, 0xE03000C8,
  310. 0x00000204, 0x00010303,
  311. 0x00000200, 0xE03000E4,
  312. 0x00000204, 0x00010303,
  313. 0x00000200, 0xE03000E0,
  314. 0x00000204, 0x800010FF,
  315. 0x00000200, 0xE0300100,
  316. 0x00000204, 0x00010303,
  317. 0x00000200, 0xE03000FC,
  318. 0x00000204, 0x800010FF,
  319. 0x00000200, 0x0001f198,
  320. 0x00000204, 0x0003ffff,
  321. 0x00000200, 0x0001f19C,
  322. 0x00000204, 0x3fffffff,
  323. 0x00000200, 0xE030032C,
  324. 0x00000204, 0x00000000,
  325. };
  326. static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev,
  327. const u32 *seq, u32 count);
  328. static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev);
  329. static void trinity_apply_state_adjust_rules(struct radeon_device *rdev,
  330. struct radeon_ps *new_rps,
  331. struct radeon_ps *old_rps);
  332. struct trinity_ps *trinity_get_ps(struct radeon_ps *rps)
  333. {
  334. struct trinity_ps *ps = rps->ps_priv;
  335. return ps;
  336. }
  337. struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev)
  338. {
  339. struct trinity_power_info *pi = rdev->pm.dpm.priv;
  340. return pi;
  341. }
  342. static void trinity_gfx_powergating_initialize(struct radeon_device *rdev)
  343. {
  344. struct trinity_power_info *pi = trinity_get_pi(rdev);
  345. u32 p, u;
  346. u32 value;
  347. struct atom_clock_dividers dividers;
  348. u32 xclk = radeon_get_xclk(rdev);
  349. u32 sssd = 1;
  350. int ret;
  351. u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
  352. ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
  353. 25000, false, &dividers);
  354. if (ret)
  355. return;
  356. value = RREG32_SMC(GFX_POWER_GATING_CNTL);
  357. value &= ~(SSSD_MASK | PDS_DIV_MASK);
  358. if (sssd)
  359. value |= SSSD(1);
  360. value |= PDS_DIV(dividers.post_div);
  361. WREG32_SMC(GFX_POWER_GATING_CNTL, value);
  362. r600_calculate_u_and_p(500, xclk, 16, &p, &u);
  363. WREG32(CG_PG_CTRL, SP(p) | SU(u));
  364. WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK);
  365. /* XXX double check hw_rev */
  366. if (pi->override_dynamic_mgpg && (hw_rev == 0))
  367. trinity_override_dynamic_mg_powergating(rdev);
  368. }
  369. #define CGCG_CGTT_LOCAL0_MASK 0xFFFF33FF
  370. #define CGCG_CGTT_LOCAL1_MASK 0xFFFB0FFE
  371. #define CGTS_SM_CTRL_REG_DISABLE 0x00600000
  372. #define CGTS_SM_CTRL_REG_ENABLE 0x96944200
  373. static void trinity_mg_clockgating_enable(struct radeon_device *rdev,
  374. bool enable)
  375. {
  376. u32 local0;
  377. u32 local1;
  378. if (enable) {
  379. local0 = RREG32_CG(CG_CGTT_LOCAL_0);
  380. local1 = RREG32_CG(CG_CGTT_LOCAL_1);
  381. WREG32_CG(CG_CGTT_LOCAL_0,
  382. (0x00380000 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
  383. WREG32_CG(CG_CGTT_LOCAL_1,
  384. (0x0E000000 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
  385. WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE);
  386. } else {
  387. WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE);
  388. local0 = RREG32_CG(CG_CGTT_LOCAL_0);
  389. local1 = RREG32_CG(CG_CGTT_LOCAL_1);
  390. WREG32_CG(CG_CGTT_LOCAL_0,
  391. CGCG_CGTT_LOCAL0_MASK | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
  392. WREG32_CG(CG_CGTT_LOCAL_1,
  393. CGCG_CGTT_LOCAL1_MASK | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
  394. }
  395. }
  396. static void trinity_mg_clockgating_initialize(struct radeon_device *rdev)
  397. {
  398. u32 count;
  399. const u32 *seq = NULL;
  400. seq = &trinity_mgcg_shls_default[0];
  401. count = sizeof(trinity_mgcg_shls_default) / (3 * sizeof(u32));
  402. trinity_program_clk_gating_hw_sequence(rdev, seq, count);
  403. }
  404. static void trinity_gfx_clockgating_enable(struct radeon_device *rdev,
  405. bool enable)
  406. {
  407. if (enable) {
  408. WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
  409. } else {
  410. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  411. WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
  412. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
  413. RREG32(GB_ADDR_CONFIG);
  414. }
  415. }
  416. static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev,
  417. const u32 *seq, u32 count)
  418. {
  419. u32 i, length = count * 3;
  420. for (i = 0; i < length; i += 3)
  421. WREG32_P(seq[i], seq[i+1], ~seq[i+2]);
  422. }
  423. static void trinity_program_override_mgpg_sequences(struct radeon_device *rdev,
  424. const u32 *seq, u32 count)
  425. {
  426. u32 i, length = count * 2;
  427. for (i = 0; i < length; i += 2)
  428. WREG32(seq[i], seq[i+1]);
  429. }
  430. static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev)
  431. {
  432. u32 count;
  433. const u32 *seq = NULL;
  434. seq = &trinity_override_mgpg_sequences[0];
  435. count = sizeof(trinity_override_mgpg_sequences) / (2 * sizeof(u32));
  436. trinity_program_override_mgpg_sequences(rdev, seq, count);
  437. }
  438. static void trinity_ls_clockgating_enable(struct radeon_device *rdev,
  439. bool enable)
  440. {
  441. u32 count;
  442. const u32 *seq = NULL;
  443. if (enable) {
  444. seq = &trinity_sysls_enable[0];
  445. count = sizeof(trinity_sysls_enable) / (3 * sizeof(u32));
  446. } else {
  447. seq = &trinity_sysls_disable[0];
  448. count = sizeof(trinity_sysls_disable) / (3 * sizeof(u32));
  449. }
  450. trinity_program_clk_gating_hw_sequence(rdev, seq, count);
  451. }
  452. static void trinity_gfx_powergating_enable(struct radeon_device *rdev,
  453. bool enable)
  454. {
  455. if (enable) {
  456. if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)
  457. WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));
  458. WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
  459. } else {
  460. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);
  461. RREG32(GB_ADDR_CONFIG);
  462. }
  463. }
  464. static void trinity_gfx_dynamic_mgpg_enable(struct radeon_device *rdev,
  465. bool enable)
  466. {
  467. u32 value;
  468. if (enable) {
  469. value = RREG32_SMC(PM_I_CNTL_1);
  470. value &= ~DS_PG_CNTL_MASK;
  471. value |= DS_PG_CNTL(1);
  472. WREG32_SMC(PM_I_CNTL_1, value);
  473. value = RREG32_SMC(SMU_S_PG_CNTL);
  474. value &= ~DS_PG_EN_MASK;
  475. value |= DS_PG_EN(1);
  476. WREG32_SMC(SMU_S_PG_CNTL, value);
  477. } else {
  478. value = RREG32_SMC(SMU_S_PG_CNTL);
  479. value &= ~DS_PG_EN_MASK;
  480. WREG32_SMC(SMU_S_PG_CNTL, value);
  481. value = RREG32_SMC(PM_I_CNTL_1);
  482. value &= ~DS_PG_CNTL_MASK;
  483. WREG32_SMC(PM_I_CNTL_1, value);
  484. }
  485. trinity_gfx_dynamic_mgpg_config(rdev);
  486. }
  487. static void trinity_enable_clock_power_gating(struct radeon_device *rdev)
  488. {
  489. struct trinity_power_info *pi = trinity_get_pi(rdev);
  490. if (pi->enable_gfx_clock_gating)
  491. sumo_gfx_clockgating_initialize(rdev);
  492. if (pi->enable_mg_clock_gating)
  493. trinity_mg_clockgating_initialize(rdev);
  494. if (pi->enable_gfx_power_gating)
  495. trinity_gfx_powergating_initialize(rdev);
  496. if (pi->enable_mg_clock_gating) {
  497. trinity_ls_clockgating_enable(rdev, true);
  498. trinity_mg_clockgating_enable(rdev, true);
  499. }
  500. if (pi->enable_gfx_clock_gating)
  501. trinity_gfx_clockgating_enable(rdev, true);
  502. if (pi->enable_gfx_dynamic_mgpg)
  503. trinity_gfx_dynamic_mgpg_enable(rdev, true);
  504. if (pi->enable_gfx_power_gating)
  505. trinity_gfx_powergating_enable(rdev, true);
  506. }
  507. static void trinity_disable_clock_power_gating(struct radeon_device *rdev)
  508. {
  509. struct trinity_power_info *pi = trinity_get_pi(rdev);
  510. if (pi->enable_gfx_power_gating)
  511. trinity_gfx_powergating_enable(rdev, false);
  512. if (pi->enable_gfx_dynamic_mgpg)
  513. trinity_gfx_dynamic_mgpg_enable(rdev, false);
  514. if (pi->enable_gfx_clock_gating)
  515. trinity_gfx_clockgating_enable(rdev, false);
  516. if (pi->enable_mg_clock_gating) {
  517. trinity_mg_clockgating_enable(rdev, false);
  518. trinity_ls_clockgating_enable(rdev, false);
  519. }
  520. }
  521. static void trinity_set_divider_value(struct radeon_device *rdev,
  522. u32 index, u32 sclk)
  523. {
  524. struct atom_clock_dividers dividers;
  525. int ret;
  526. u32 value;
  527. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  528. ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
  529. sclk, false, &dividers);
  530. if (ret)
  531. return;
  532. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
  533. value &= ~CLK_DIVIDER_MASK;
  534. value |= CLK_DIVIDER(dividers.post_div);
  535. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
  536. ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
  537. sclk/2, false, &dividers);
  538. if (ret)
  539. return;
  540. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
  541. value &= ~PD_SCLK_DIVIDER_MASK;
  542. value |= PD_SCLK_DIVIDER(dividers.post_div);
  543. WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
  544. }
  545. static void trinity_set_ds_dividers(struct radeon_device *rdev,
  546. u32 index, u32 divider)
  547. {
  548. u32 value;
  549. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  550. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
  551. value &= ~DS_DIV_MASK;
  552. value |= DS_DIV(divider);
  553. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
  554. }
  555. static void trinity_set_ss_dividers(struct radeon_device *rdev,
  556. u32 index, u32 divider)
  557. {
  558. u32 value;
  559. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  560. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
  561. value &= ~DS_SH_DIV_MASK;
  562. value |= DS_SH_DIV(divider);
  563. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
  564. }
  565. static void trinity_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
  566. {
  567. struct trinity_power_info *pi = trinity_get_pi(rdev);
  568. u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid);
  569. u32 value;
  570. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  571. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
  572. value &= ~VID_MASK;
  573. value |= VID(vid_7bit);
  574. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
  575. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
  576. value &= ~LVRT_MASK;
  577. value |= LVRT(0);
  578. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
  579. }
  580. static void trinity_set_allos_gnb_slow(struct radeon_device *rdev,
  581. u32 index, u32 gnb_slow)
  582. {
  583. u32 value;
  584. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  585. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
  586. value &= ~GNB_SLOW_MASK;
  587. value |= GNB_SLOW(gnb_slow);
  588. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
  589. }
  590. static void trinity_set_force_nbp_state(struct radeon_device *rdev,
  591. u32 index, u32 force_nbp_state)
  592. {
  593. u32 value;
  594. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  595. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
  596. value &= ~FORCE_NBPS1_MASK;
  597. value |= FORCE_NBPS1(force_nbp_state);
  598. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
  599. }
  600. static void trinity_set_display_wm(struct radeon_device *rdev,
  601. u32 index, u32 wm)
  602. {
  603. u32 value;
  604. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  605. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
  606. value &= ~DISPLAY_WM_MASK;
  607. value |= DISPLAY_WM(wm);
  608. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
  609. }
  610. static void trinity_set_vce_wm(struct radeon_device *rdev,
  611. u32 index, u32 wm)
  612. {
  613. u32 value;
  614. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  615. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
  616. value &= ~VCE_WM_MASK;
  617. value |= VCE_WM(wm);
  618. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
  619. }
  620. static void trinity_set_at(struct radeon_device *rdev,
  621. u32 index, u32 at)
  622. {
  623. u32 value;
  624. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  625. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);
  626. value &= ~AT_MASK;
  627. value |= AT(at);
  628. WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);
  629. }
  630. static void trinity_program_power_level(struct radeon_device *rdev,
  631. struct trinity_pl *pl, u32 index)
  632. {
  633. struct trinity_power_info *pi = trinity_get_pi(rdev);
  634. if (index >= SUMO_MAX_HARDWARE_POWERLEVELS)
  635. return;
  636. trinity_set_divider_value(rdev, index, pl->sclk);
  637. trinity_set_vid(rdev, index, pl->vddc_index);
  638. trinity_set_ss_dividers(rdev, index, pl->ss_divider_index);
  639. trinity_set_ds_dividers(rdev, index, pl->ds_divider_index);
  640. trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
  641. trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state);
  642. trinity_set_display_wm(rdev, index, pl->display_wm);
  643. trinity_set_vce_wm(rdev, index, pl->vce_wm);
  644. trinity_set_at(rdev, index, pi->at[index]);
  645. }
  646. static void trinity_power_level_enable_disable(struct radeon_device *rdev,
  647. u32 index, bool enable)
  648. {
  649. u32 value;
  650. u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE;
  651. value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
  652. value &= ~STATE_VALID_MASK;
  653. if (enable)
  654. value |= STATE_VALID(1);
  655. WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
  656. }
  657. static bool trinity_dpm_enabled(struct radeon_device *rdev)
  658. {
  659. if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1))
  660. return true;
  661. else
  662. return false;
  663. }
  664. static void trinity_start_dpm(struct radeon_device *rdev)
  665. {
  666. u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);
  667. value &= ~(SCLK_DPM_EN_MASK | SCLK_DPM_BOOT_STATE_MASK | VOLTAGE_CHG_EN_MASK);
  668. value |= SCLK_DPM_EN(1) | SCLK_DPM_BOOT_STATE(0) | VOLTAGE_CHG_EN(1);
  669. WREG32_SMC(SMU_SCLK_DPM_CNTL, value);
  670. WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
  671. WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN);
  672. trinity_dpm_config(rdev, true);
  673. }
  674. static void trinity_wait_for_dpm_enabled(struct radeon_device *rdev)
  675. {
  676. int i;
  677. for (i = 0; i < rdev->usec_timeout; i++) {
  678. if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
  679. break;
  680. udelay(1);
  681. }
  682. for (i = 0; i < rdev->usec_timeout; i++) {
  683. if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0)
  684. break;
  685. udelay(1);
  686. }
  687. for (i = 0; i < rdev->usec_timeout; i++) {
  688. if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
  689. break;
  690. udelay(1);
  691. }
  692. }
  693. static void trinity_stop_dpm(struct radeon_device *rdev)
  694. {
  695. u32 sclk_dpm_cntl;
  696. WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN);
  697. sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL);
  698. sclk_dpm_cntl &= ~(SCLK_DPM_EN_MASK | VOLTAGE_CHG_EN_MASK);
  699. WREG32_SMC(SMU_SCLK_DPM_CNTL, sclk_dpm_cntl);
  700. trinity_dpm_config(rdev, false);
  701. }
  702. static void trinity_start_am(struct radeon_device *rdev)
  703. {
  704. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
  705. }
  706. static void trinity_reset_am(struct radeon_device *rdev)
  707. {
  708. WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
  709. ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
  710. }
  711. static void trinity_wait_for_level_0(struct radeon_device *rdev)
  712. {
  713. int i;
  714. for (i = 0; i < rdev->usec_timeout; i++) {
  715. if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
  716. break;
  717. udelay(1);
  718. }
  719. }
  720. static void trinity_enable_power_level_0(struct radeon_device *rdev)
  721. {
  722. trinity_power_level_enable_disable(rdev, 0, true);
  723. }
  724. static void trinity_force_level_0(struct radeon_device *rdev)
  725. {
  726. trinity_dpm_force_state(rdev, 0);
  727. }
  728. static void trinity_unforce_levels(struct radeon_device *rdev)
  729. {
  730. trinity_dpm_no_forced_level(rdev);
  731. }
  732. static void trinity_program_power_levels_0_to_n(struct radeon_device *rdev,
  733. struct radeon_ps *new_rps,
  734. struct radeon_ps *old_rps)
  735. {
  736. struct trinity_ps *new_ps = trinity_get_ps(new_rps);
  737. struct trinity_ps *old_ps = trinity_get_ps(old_rps);
  738. u32 i;
  739. u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
  740. for (i = 0; i < new_ps->num_levels; i++) {
  741. trinity_program_power_level(rdev, &new_ps->levels[i], i);
  742. trinity_power_level_enable_disable(rdev, i, true);
  743. }
  744. for (i = new_ps->num_levels; i < n_current_state_levels; i++)
  745. trinity_power_level_enable_disable(rdev, i, false);
  746. }
  747. static void trinity_program_bootup_state(struct radeon_device *rdev)
  748. {
  749. struct trinity_power_info *pi = trinity_get_pi(rdev);
  750. u32 i;
  751. trinity_program_power_level(rdev, &pi->boot_pl, 0);
  752. trinity_power_level_enable_disable(rdev, 0, true);
  753. for (i = 1; i < 8; i++)
  754. trinity_power_level_enable_disable(rdev, i, false);
  755. }
  756. static void trinity_setup_uvd_clock_table(struct radeon_device *rdev,
  757. struct radeon_ps *rps)
  758. {
  759. struct trinity_ps *ps = trinity_get_ps(rps);
  760. u32 uvdstates = (ps->vclk_low_divider |
  761. ps->vclk_high_divider << 8 |
  762. ps->dclk_low_divider << 16 |
  763. ps->dclk_high_divider << 24);
  764. WREG32_SMC(SMU_UVD_DPM_STATES, uvdstates);
  765. }
  766. static void trinity_setup_uvd_dpm_interval(struct radeon_device *rdev,
  767. u32 interval)
  768. {
  769. u32 p, u;
  770. u32 tp = RREG32_SMC(PM_TP);
  771. u32 val;
  772. u32 xclk = radeon_get_xclk(rdev);
  773. r600_calculate_u_and_p(interval, xclk, 16, &p, &u);
  774. val = (p + tp - 1) / tp;
  775. WREG32_SMC(SMU_UVD_DPM_CNTL, val);
  776. }
  777. static bool trinity_uvd_clocks_zero(struct radeon_ps *rps)
  778. {
  779. if ((rps->vclk == 0) && (rps->dclk == 0))
  780. return true;
  781. else
  782. return false;
  783. }
  784. static bool trinity_uvd_clocks_equal(struct radeon_ps *rps1,
  785. struct radeon_ps *rps2)
  786. {
  787. struct trinity_ps *ps1 = trinity_get_ps(rps1);
  788. struct trinity_ps *ps2 = trinity_get_ps(rps2);
  789. if ((rps1->vclk == rps2->vclk) &&
  790. (rps1->dclk == rps2->dclk) &&
  791. (ps1->vclk_low_divider == ps2->vclk_low_divider) &&
  792. (ps1->vclk_high_divider == ps2->vclk_high_divider) &&
  793. (ps1->dclk_low_divider == ps2->dclk_low_divider) &&
  794. (ps1->dclk_high_divider == ps2->dclk_high_divider))
  795. return true;
  796. else
  797. return false;
  798. }
  799. static void trinity_setup_uvd_clocks(struct radeon_device *rdev,
  800. struct radeon_ps *new_rps,
  801. struct radeon_ps *old_rps)
  802. {
  803. struct trinity_power_info *pi = trinity_get_pi(rdev);
  804. if (pi->enable_gfx_power_gating) {
  805. trinity_gfx_powergating_enable(rdev, false);
  806. }
  807. if (pi->uvd_dpm) {
  808. if (trinity_uvd_clocks_zero(new_rps) &&
  809. !trinity_uvd_clocks_zero(old_rps)) {
  810. trinity_setup_uvd_dpm_interval(rdev, 0);
  811. } else if (!trinity_uvd_clocks_zero(new_rps)) {
  812. trinity_setup_uvd_clock_table(rdev, new_rps);
  813. if (trinity_uvd_clocks_zero(old_rps)) {
  814. u32 tmp = RREG32(CG_MISC_REG);
  815. tmp &= 0xfffffffd;
  816. WREG32(CG_MISC_REG, tmp);
  817. radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
  818. trinity_setup_uvd_dpm_interval(rdev, 3000);
  819. }
  820. }
  821. trinity_uvd_dpm_config(rdev);
  822. } else {
  823. if (trinity_uvd_clocks_zero(new_rps) ||
  824. trinity_uvd_clocks_equal(new_rps, old_rps))
  825. return;
  826. radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
  827. }
  828. if (pi->enable_gfx_power_gating) {
  829. trinity_gfx_powergating_enable(rdev, true);
  830. }
  831. }
  832. static void trinity_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
  833. struct radeon_ps *new_rps,
  834. struct radeon_ps *old_rps)
  835. {
  836. struct trinity_ps *new_ps = trinity_get_ps(new_rps);
  837. struct trinity_ps *current_ps = trinity_get_ps(new_rps);
  838. if (new_ps->levels[new_ps->num_levels - 1].sclk >=
  839. current_ps->levels[current_ps->num_levels - 1].sclk)
  840. return;
  841. trinity_setup_uvd_clocks(rdev, new_rps, old_rps);
  842. }
  843. static void trinity_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
  844. struct radeon_ps *new_rps,
  845. struct radeon_ps *old_rps)
  846. {
  847. struct trinity_ps *new_ps = trinity_get_ps(new_rps);
  848. struct trinity_ps *current_ps = trinity_get_ps(old_rps);
  849. if (new_ps->levels[new_ps->num_levels - 1].sclk <
  850. current_ps->levels[current_ps->num_levels - 1].sclk)
  851. return;
  852. trinity_setup_uvd_clocks(rdev, new_rps, old_rps);
  853. }
  854. static void trinity_program_ttt(struct radeon_device *rdev)
  855. {
  856. struct trinity_power_info *pi = trinity_get_pi(rdev);
  857. u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);
  858. value &= ~(HT_MASK | LT_MASK);
  859. value |= HT((pi->thermal_auto_throttling + 49) * 8);
  860. value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8);
  861. WREG32_SMC(SMU_SCLK_DPM_TTT, value);
  862. }
  863. static void trinity_enable_att(struct radeon_device *rdev)
  864. {
  865. u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);
  866. value &= ~SCLK_TT_EN_MASK;
  867. value |= SCLK_TT_EN(1);
  868. WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value);
  869. }
  870. static void trinity_program_sclk_dpm(struct radeon_device *rdev)
  871. {
  872. u32 p, u;
  873. u32 tp = RREG32_SMC(PM_TP);
  874. u32 ni;
  875. u32 xclk = radeon_get_xclk(rdev);
  876. u32 value;
  877. r600_calculate_u_and_p(400, xclk, 16, &p, &u);
  878. ni = (p + tp - 1) / tp;
  879. value = RREG32_SMC(PM_I_CNTL_1);
  880. value &= ~SCLK_DPM_MASK;
  881. value |= SCLK_DPM(ni);
  882. WREG32_SMC(PM_I_CNTL_1, value);
  883. }
  884. static int trinity_set_thermal_temperature_range(struct radeon_device *rdev,
  885. int min_temp, int max_temp)
  886. {
  887. int low_temp = 0 * 1000;
  888. int high_temp = 255 * 1000;
  889. if (low_temp < min_temp)
  890. low_temp = min_temp;
  891. if (high_temp > max_temp)
  892. high_temp = max_temp;
  893. if (high_temp < low_temp) {
  894. DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
  895. return -EINVAL;
  896. }
  897. WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
  898. WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
  899. rdev->pm.dpm.thermal.min_temp = low_temp;
  900. rdev->pm.dpm.thermal.max_temp = high_temp;
  901. return 0;
  902. }
  903. static void trinity_update_current_ps(struct radeon_device *rdev,
  904. struct radeon_ps *rps)
  905. {
  906. struct trinity_ps *new_ps = trinity_get_ps(rps);
  907. struct trinity_power_info *pi = trinity_get_pi(rdev);
  908. pi->current_rps = *rps;
  909. pi->current_ps = *new_ps;
  910. pi->current_rps.ps_priv = &pi->current_ps;
  911. }
  912. static void trinity_update_requested_ps(struct radeon_device *rdev,
  913. struct radeon_ps *rps)
  914. {
  915. struct trinity_ps *new_ps = trinity_get_ps(rps);
  916. struct trinity_power_info *pi = trinity_get_pi(rdev);
  917. pi->requested_rps = *rps;
  918. pi->requested_ps = *new_ps;
  919. pi->requested_rps.ps_priv = &pi->requested_ps;
  920. }
  921. int trinity_dpm_enable(struct radeon_device *rdev)
  922. {
  923. struct trinity_power_info *pi = trinity_get_pi(rdev);
  924. int ret;
  925. trinity_acquire_mutex(rdev);
  926. if (trinity_dpm_enabled(rdev)) {
  927. trinity_release_mutex(rdev);
  928. return -EINVAL;
  929. }
  930. trinity_enable_clock_power_gating(rdev);
  931. trinity_program_bootup_state(rdev);
  932. sumo_program_vc(rdev, 0x00C00033);
  933. trinity_start_am(rdev);
  934. if (pi->enable_auto_thermal_throttling) {
  935. trinity_program_ttt(rdev);
  936. trinity_enable_att(rdev);
  937. }
  938. trinity_program_sclk_dpm(rdev);
  939. trinity_start_dpm(rdev);
  940. trinity_wait_for_dpm_enabled(rdev);
  941. trinity_release_mutex(rdev);
  942. if (rdev->irq.installed &&
  943. r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
  944. ret = trinity_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
  945. if (ret) {
  946. trinity_release_mutex(rdev);
  947. return ret;
  948. }
  949. rdev->irq.dpm_thermal = true;
  950. radeon_irq_set(rdev);
  951. }
  952. trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
  953. return 0;
  954. }
  955. void trinity_dpm_disable(struct radeon_device *rdev)
  956. {
  957. trinity_acquire_mutex(rdev);
  958. if (!trinity_dpm_enabled(rdev)) {
  959. trinity_release_mutex(rdev);
  960. return;
  961. }
  962. trinity_disable_clock_power_gating(rdev);
  963. sumo_clear_vc(rdev);
  964. trinity_wait_for_level_0(rdev);
  965. trinity_stop_dpm(rdev);
  966. trinity_reset_am(rdev);
  967. trinity_release_mutex(rdev);
  968. if (rdev->irq.installed &&
  969. r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
  970. rdev->irq.dpm_thermal = false;
  971. radeon_irq_set(rdev);
  972. }
  973. trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
  974. }
  975. static void trinity_get_min_sclk_divider(struct radeon_device *rdev)
  976. {
  977. struct trinity_power_info *pi = trinity_get_pi(rdev);
  978. pi->min_sclk_did =
  979. (RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT;
  980. }
  981. static void trinity_setup_nbp_sim(struct radeon_device *rdev,
  982. struct radeon_ps *rps)
  983. {
  984. struct trinity_power_info *pi = trinity_get_pi(rdev);
  985. struct trinity_ps *new_ps = trinity_get_ps(rps);
  986. u32 nbpsconfig;
  987. if (pi->sys_info.nb_dpm_enable) {
  988. nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG);
  989. nbpsconfig &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
  990. nbpsconfig |= (Dpm0PgNbPsLo(new_ps->Dpm0PgNbPsLo) |
  991. Dpm0PgNbPsHi(new_ps->Dpm0PgNbPsHi) |
  992. DpmXNbPsLo(new_ps->DpmXNbPsLo) |
  993. DpmXNbPsHi(new_ps->DpmXNbPsHi));
  994. WREG32_SMC(NB_PSTATE_CONFIG, nbpsconfig);
  995. }
  996. }
  997. int trinity_dpm_pre_set_power_state(struct radeon_device *rdev)
  998. {
  999. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1000. struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
  1001. struct radeon_ps *new_ps = &requested_ps;
  1002. trinity_update_requested_ps(rdev, new_ps);
  1003. trinity_apply_state_adjust_rules(rdev,
  1004. &pi->requested_rps,
  1005. &pi->current_rps);
  1006. return 0;
  1007. }
  1008. int trinity_dpm_set_power_state(struct radeon_device *rdev)
  1009. {
  1010. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1011. struct radeon_ps *new_ps = &pi->requested_rps;
  1012. struct radeon_ps *old_ps = &pi->current_rps;
  1013. trinity_acquire_mutex(rdev);
  1014. if (pi->enable_dpm) {
  1015. trinity_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
  1016. trinity_enable_power_level_0(rdev);
  1017. trinity_force_level_0(rdev);
  1018. trinity_wait_for_level_0(rdev);
  1019. trinity_setup_nbp_sim(rdev, new_ps);
  1020. trinity_program_power_levels_0_to_n(rdev, new_ps, old_ps);
  1021. trinity_force_level_0(rdev);
  1022. trinity_unforce_levels(rdev);
  1023. trinity_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
  1024. }
  1025. trinity_release_mutex(rdev);
  1026. return 0;
  1027. }
  1028. void trinity_dpm_post_set_power_state(struct radeon_device *rdev)
  1029. {
  1030. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1031. struct radeon_ps *new_ps = &pi->requested_rps;
  1032. trinity_update_current_ps(rdev, new_ps);
  1033. }
  1034. void trinity_dpm_setup_asic(struct radeon_device *rdev)
  1035. {
  1036. trinity_acquire_mutex(rdev);
  1037. sumo_program_sstp(rdev);
  1038. sumo_take_smu_control(rdev, true);
  1039. trinity_get_min_sclk_divider(rdev);
  1040. trinity_release_mutex(rdev);
  1041. }
  1042. void trinity_dpm_reset_asic(struct radeon_device *rdev)
  1043. {
  1044. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1045. trinity_acquire_mutex(rdev);
  1046. if (pi->enable_dpm) {
  1047. trinity_enable_power_level_0(rdev);
  1048. trinity_force_level_0(rdev);
  1049. trinity_wait_for_level_0(rdev);
  1050. trinity_program_bootup_state(rdev);
  1051. trinity_force_level_0(rdev);
  1052. trinity_unforce_levels(rdev);
  1053. }
  1054. trinity_release_mutex(rdev);
  1055. }
  1056. static u16 trinity_convert_voltage_index_to_value(struct radeon_device *rdev,
  1057. u32 vid_2bit)
  1058. {
  1059. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1060. u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
  1061. u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;
  1062. u32 step = (svi_mode == 0) ? 1250 : 625;
  1063. u32 delta = vid_7bit * step + 50;
  1064. if (delta > 155000)
  1065. return 0;
  1066. return (155000 - delta) / 100;
  1067. }
  1068. static void trinity_patch_boot_state(struct radeon_device *rdev,
  1069. struct trinity_ps *ps)
  1070. {
  1071. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1072. ps->num_levels = 1;
  1073. ps->nbps_flags = 0;
  1074. ps->bapm_flags = 0;
  1075. ps->levels[0] = pi->boot_pl;
  1076. }
  1077. static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)
  1078. {
  1079. if (sclk < 20000)
  1080. return 1;
  1081. return 0;
  1082. }
  1083. static void trinity_construct_boot_state(struct radeon_device *rdev)
  1084. {
  1085. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1086. pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
  1087. pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
  1088. pi->boot_pl.ds_divider_index = 0;
  1089. pi->boot_pl.ss_divider_index = 0;
  1090. pi->boot_pl.allow_gnb_slow = 1;
  1091. pi->boot_pl.force_nbp_state = 0;
  1092. pi->boot_pl.display_wm = 0;
  1093. pi->boot_pl.vce_wm = 0;
  1094. pi->current_ps.num_levels = 1;
  1095. pi->current_ps.levels[0] = pi->boot_pl;
  1096. }
  1097. static u8 trinity_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
  1098. u32 sclk, u32 min_sclk_in_sr)
  1099. {
  1100. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1101. u32 i;
  1102. u32 temp;
  1103. u32 min = (min_sclk_in_sr > TRINITY_MINIMUM_ENGINE_CLOCK) ?
  1104. min_sclk_in_sr : TRINITY_MINIMUM_ENGINE_CLOCK;
  1105. if (sclk < min)
  1106. return 0;
  1107. if (!pi->enable_sclk_ds)
  1108. return 0;
  1109. for (i = TRINITY_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
  1110. temp = sclk / sumo_get_sleep_divider_from_id(i);
  1111. if (temp >= min || i == 0)
  1112. break;
  1113. }
  1114. return (u8)i;
  1115. }
  1116. static u32 trinity_get_valid_engine_clock(struct radeon_device *rdev,
  1117. u32 lower_limit)
  1118. {
  1119. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1120. u32 i;
  1121. for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
  1122. if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
  1123. return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
  1124. }
  1125. if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries)
  1126. DRM_ERROR("engine clock out of range!");
  1127. return 0;
  1128. }
  1129. static void trinity_patch_thermal_state(struct radeon_device *rdev,
  1130. struct trinity_ps *ps,
  1131. struct trinity_ps *current_ps)
  1132. {
  1133. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1134. u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
  1135. u32 current_vddc;
  1136. u32 current_sclk;
  1137. u32 current_index = 0;
  1138. if (current_ps) {
  1139. current_vddc = current_ps->levels[current_index].vddc_index;
  1140. current_sclk = current_ps->levels[current_index].sclk;
  1141. } else {
  1142. current_vddc = pi->boot_pl.vddc_index;
  1143. current_sclk = pi->boot_pl.sclk;
  1144. }
  1145. ps->levels[0].vddc_index = current_vddc;
  1146. if (ps->levels[0].sclk > current_sclk)
  1147. ps->levels[0].sclk = current_sclk;
  1148. ps->levels[0].ds_divider_index =
  1149. trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
  1150. ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index;
  1151. ps->levels[0].allow_gnb_slow = 1;
  1152. ps->levels[0].force_nbp_state = 0;
  1153. ps->levels[0].display_wm = 0;
  1154. ps->levels[0].vce_wm =
  1155. trinity_calculate_vce_wm(rdev, ps->levels[0].sclk);
  1156. }
  1157. static u8 trinity_calculate_display_wm(struct radeon_device *rdev,
  1158. struct trinity_ps *ps, u32 index)
  1159. {
  1160. if (ps == NULL || ps->num_levels <= 1)
  1161. return 0;
  1162. else if (ps->num_levels == 2) {
  1163. if (index == 0)
  1164. return 0;
  1165. else
  1166. return 1;
  1167. } else {
  1168. if (index == 0)
  1169. return 0;
  1170. else if (ps->levels[index].sclk < 30000)
  1171. return 0;
  1172. else
  1173. return 1;
  1174. }
  1175. }
  1176. static u32 trinity_get_uvd_clock_index(struct radeon_device *rdev,
  1177. struct radeon_ps *rps)
  1178. {
  1179. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1180. u32 i = 0;
  1181. for (i = 0; i < 4; i++) {
  1182. if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) &&
  1183. (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
  1184. break;
  1185. }
  1186. if (i >= 4) {
  1187. DRM_ERROR("UVD clock index not found!\n");
  1188. i = 3;
  1189. }
  1190. return i;
  1191. }
  1192. static void trinity_adjust_uvd_state(struct radeon_device *rdev,
  1193. struct radeon_ps *rps)
  1194. {
  1195. struct trinity_ps *ps = trinity_get_ps(rps);
  1196. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1197. u32 high_index = 0;
  1198. u32 low_index = 0;
  1199. if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) {
  1200. high_index = trinity_get_uvd_clock_index(rdev, rps);
  1201. switch(high_index) {
  1202. case 3:
  1203. case 2:
  1204. low_index = 1;
  1205. break;
  1206. case 1:
  1207. case 0:
  1208. default:
  1209. low_index = 0;
  1210. break;
  1211. }
  1212. ps->vclk_low_divider =
  1213. pi->sys_info.uvd_clock_table_entries[high_index].vclk_did;
  1214. ps->dclk_low_divider =
  1215. pi->sys_info.uvd_clock_table_entries[high_index].dclk_did;
  1216. ps->vclk_high_divider =
  1217. pi->sys_info.uvd_clock_table_entries[low_index].vclk_did;
  1218. ps->dclk_high_divider =
  1219. pi->sys_info.uvd_clock_table_entries[low_index].dclk_did;
  1220. }
  1221. }
  1222. static void trinity_apply_state_adjust_rules(struct radeon_device *rdev,
  1223. struct radeon_ps *new_rps,
  1224. struct radeon_ps *old_rps)
  1225. {
  1226. struct trinity_ps *ps = trinity_get_ps(new_rps);
  1227. struct trinity_ps *current_ps = trinity_get_ps(old_rps);
  1228. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1229. u32 min_voltage = 0; /* ??? */
  1230. u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
  1231. u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
  1232. u32 i;
  1233. bool force_high;
  1234. u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;
  1235. if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
  1236. return trinity_patch_thermal_state(rdev, ps, current_ps);
  1237. trinity_adjust_uvd_state(rdev, new_rps);
  1238. for (i = 0; i < ps->num_levels; i++) {
  1239. if (ps->levels[i].vddc_index < min_voltage)
  1240. ps->levels[i].vddc_index = min_voltage;
  1241. if (ps->levels[i].sclk < min_sclk)
  1242. ps->levels[i].sclk =
  1243. trinity_get_valid_engine_clock(rdev, min_sclk);
  1244. ps->levels[i].ds_divider_index =
  1245. sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
  1246. ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index;
  1247. ps->levels[i].allow_gnb_slow = 1;
  1248. ps->levels[i].force_nbp_state = 0;
  1249. ps->levels[i].display_wm =
  1250. trinity_calculate_display_wm(rdev, ps, i);
  1251. ps->levels[i].vce_wm =
  1252. trinity_calculate_vce_wm(rdev, ps->levels[0].sclk);
  1253. }
  1254. if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) ||
  1255. ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY))
  1256. ps->bapm_flags |= TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE;
  1257. if (pi->sys_info.nb_dpm_enable) {
  1258. ps->Dpm0PgNbPsLo = 0x1;
  1259. ps->Dpm0PgNbPsHi = 0x0;
  1260. ps->DpmXNbPsLo = 0x2;
  1261. ps->DpmXNbPsHi = 0x1;
  1262. if ((new_rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) ||
  1263. ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) {
  1264. force_high = ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) ||
  1265. ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) &&
  1266. (pi->sys_info.uma_channel_number == 1)));
  1267. force_high = (num_active_displays >= 3) || force_high;
  1268. ps->Dpm0PgNbPsLo = force_high ? 0x2 : 0x3;
  1269. ps->Dpm0PgNbPsHi = 0x1;
  1270. ps->DpmXNbPsLo = force_high ? 0x2 : 0x3;
  1271. ps->DpmXNbPsHi = 0x2;
  1272. ps->levels[ps->num_levels - 1].allow_gnb_slow = 0;
  1273. }
  1274. }
  1275. }
  1276. static void trinity_cleanup_asic(struct radeon_device *rdev)
  1277. {
  1278. sumo_take_smu_control(rdev, false);
  1279. }
  1280. #if 0
  1281. static void trinity_pre_display_configuration_change(struct radeon_device *rdev)
  1282. {
  1283. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1284. if (pi->voltage_drop_in_dce)
  1285. trinity_dce_enable_voltage_adjustment(rdev, false);
  1286. }
  1287. #endif
  1288. static void trinity_add_dccac_value(struct radeon_device *rdev)
  1289. {
  1290. u32 gpu_cac_avrg_cntl_window_size;
  1291. u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;
  1292. u64 disp_clk = rdev->clock.default_dispclk / 100;
  1293. u32 dc_cac_value;
  1294. gpu_cac_avrg_cntl_window_size =
  1295. (RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT;
  1296. dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >>
  1297. (32 - gpu_cac_avrg_cntl_window_size));
  1298. WREG32_SMC(DC_CAC_VALUE, dc_cac_value);
  1299. }
  1300. void trinity_dpm_display_configuration_changed(struct radeon_device *rdev)
  1301. {
  1302. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1303. if (pi->voltage_drop_in_dce)
  1304. trinity_dce_enable_voltage_adjustment(rdev, true);
  1305. trinity_add_dccac_value(rdev);
  1306. }
  1307. union power_info {
  1308. struct _ATOM_POWERPLAY_INFO info;
  1309. struct _ATOM_POWERPLAY_INFO_V2 info_2;
  1310. struct _ATOM_POWERPLAY_INFO_V3 info_3;
  1311. struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  1312. struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  1313. struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  1314. };
  1315. union pplib_clock_info {
  1316. struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  1317. struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  1318. struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  1319. struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  1320. };
  1321. union pplib_power_state {
  1322. struct _ATOM_PPLIB_STATE v1;
  1323. struct _ATOM_PPLIB_STATE_V2 v2;
  1324. };
  1325. static void trinity_parse_pplib_non_clock_info(struct radeon_device *rdev,
  1326. struct radeon_ps *rps,
  1327. struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
  1328. u8 table_rev)
  1329. {
  1330. struct trinity_ps *ps = trinity_get_ps(rps);
  1331. rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
  1332. rps->class = le16_to_cpu(non_clock_info->usClassification);
  1333. rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
  1334. if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
  1335. rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
  1336. rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
  1337. } else {
  1338. rps->vclk = 0;
  1339. rps->dclk = 0;
  1340. }
  1341. if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
  1342. rdev->pm.dpm.boot_ps = rps;
  1343. trinity_patch_boot_state(rdev, ps);
  1344. }
  1345. if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
  1346. rdev->pm.dpm.uvd_ps = rps;
  1347. }
  1348. static void trinity_parse_pplib_clock_info(struct radeon_device *rdev,
  1349. struct radeon_ps *rps, int index,
  1350. union pplib_clock_info *clock_info)
  1351. {
  1352. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1353. struct trinity_ps *ps = trinity_get_ps(rps);
  1354. struct trinity_pl *pl = &ps->levels[index];
  1355. u32 sclk;
  1356. sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
  1357. sclk |= clock_info->sumo.ucEngineClockHigh << 16;
  1358. pl->sclk = sclk;
  1359. pl->vddc_index = clock_info->sumo.vddcIndex;
  1360. ps->num_levels = index + 1;
  1361. if (pi->enable_sclk_ds) {
  1362. pl->ds_divider_index = 5;
  1363. pl->ss_divider_index = 5;
  1364. }
  1365. }
  1366. static int trinity_parse_power_table(struct radeon_device *rdev)
  1367. {
  1368. struct radeon_mode_info *mode_info = &rdev->mode_info;
  1369. struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
  1370. union pplib_power_state *power_state;
  1371. int i, j, k, non_clock_array_index, clock_array_index;
  1372. union pplib_clock_info *clock_info;
  1373. struct _StateArray *state_array;
  1374. struct _ClockInfoArray *clock_info_array;
  1375. struct _NonClockInfoArray *non_clock_info_array;
  1376. union power_info *power_info;
  1377. int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
  1378. u16 data_offset;
  1379. u8 frev, crev;
  1380. u8 *power_state_offset;
  1381. struct sumo_ps *ps;
  1382. if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
  1383. &frev, &crev, &data_offset))
  1384. return -EINVAL;
  1385. power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
  1386. state_array = (struct _StateArray *)
  1387. (mode_info->atom_context->bios + data_offset +
  1388. le16_to_cpu(power_info->pplib.usStateArrayOffset));
  1389. clock_info_array = (struct _ClockInfoArray *)
  1390. (mode_info->atom_context->bios + data_offset +
  1391. le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
  1392. non_clock_info_array = (struct _NonClockInfoArray *)
  1393. (mode_info->atom_context->bios + data_offset +
  1394. le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
  1395. rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
  1396. state_array->ucNumEntries, GFP_KERNEL);
  1397. if (!rdev->pm.dpm.ps)
  1398. return -ENOMEM;
  1399. power_state_offset = (u8 *)state_array->states;
  1400. rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
  1401. rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
  1402. rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
  1403. for (i = 0; i < state_array->ucNumEntries; i++) {
  1404. power_state = (union pplib_power_state *)power_state_offset;
  1405. non_clock_array_index = power_state->v2.nonClockInfoIndex;
  1406. non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
  1407. &non_clock_info_array->nonClockInfo[non_clock_array_index];
  1408. if (!rdev->pm.power_state[i].clock_info)
  1409. return -EINVAL;
  1410. ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
  1411. if (ps == NULL) {
  1412. kfree(rdev->pm.dpm.ps);
  1413. return -ENOMEM;
  1414. }
  1415. rdev->pm.dpm.ps[i].ps_priv = ps;
  1416. k = 0;
  1417. for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
  1418. clock_array_index = power_state->v2.clockInfoIndex[j];
  1419. if (clock_array_index >= clock_info_array->ucNumEntries)
  1420. continue;
  1421. if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
  1422. break;
  1423. clock_info = (union pplib_clock_info *)
  1424. &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
  1425. trinity_parse_pplib_clock_info(rdev,
  1426. &rdev->pm.dpm.ps[i], k,
  1427. clock_info);
  1428. k++;
  1429. }
  1430. trinity_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
  1431. non_clock_info,
  1432. non_clock_info_array->ucEntrySize);
  1433. power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
  1434. }
  1435. rdev->pm.dpm.num_ps = state_array->ucNumEntries;
  1436. return 0;
  1437. }
  1438. union igp_info {
  1439. struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  1440. struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
  1441. struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
  1442. struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
  1443. struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
  1444. };
  1445. static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)
  1446. {
  1447. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1448. u32 divider;
  1449. if (did >= 8 && did <= 0x3f)
  1450. divider = did * 25;
  1451. else if (did > 0x3f && did <= 0x5f)
  1452. divider = (did - 64) * 50 + 1600;
  1453. else if (did > 0x5f && did <= 0x7e)
  1454. divider = (did - 96) * 100 + 3200;
  1455. else if (did == 0x7f)
  1456. divider = 128 * 100;
  1457. else
  1458. return 10000;
  1459. return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider;
  1460. }
  1461. static int trinity_parse_sys_info_table(struct radeon_device *rdev)
  1462. {
  1463. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1464. struct radeon_mode_info *mode_info = &rdev->mode_info;
  1465. int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
  1466. union igp_info *igp_info;
  1467. u8 frev, crev;
  1468. u16 data_offset;
  1469. int i;
  1470. if (atom_parse_data_header(mode_info->atom_context, index, NULL,
  1471. &frev, &crev, &data_offset)) {
  1472. igp_info = (union igp_info *)(mode_info->atom_context->bios +
  1473. data_offset);
  1474. if (crev != 7) {
  1475. DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
  1476. return -EINVAL;
  1477. }
  1478. pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock);
  1479. pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock);
  1480. pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock);
  1481. pi->sys_info.dentist_vco_freq = le32_to_cpu(igp_info->info_7.ulDentistVCOFreq);
  1482. pi->sys_info.bootup_nb_voltage_index =
  1483. le16_to_cpu(igp_info->info_7.usBootUpNBVoltage);
  1484. if (igp_info->info_7.ucHtcTmpLmt == 0)
  1485. pi->sys_info.htc_tmp_lmt = 203;
  1486. else
  1487. pi->sys_info.htc_tmp_lmt = igp_info->info_7.ucHtcTmpLmt;
  1488. if (igp_info->info_7.ucHtcHystLmt == 0)
  1489. pi->sys_info.htc_hyst_lmt = 5;
  1490. else
  1491. pi->sys_info.htc_hyst_lmt = igp_info->info_7.ucHtcHystLmt;
  1492. if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
  1493. DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
  1494. }
  1495. if (pi->enable_nbps_policy)
  1496. pi->sys_info.nb_dpm_enable = igp_info->info_7.ucNBDPMEnable;
  1497. else
  1498. pi->sys_info.nb_dpm_enable = 0;
  1499. for (i = 0; i < TRINITY_NUM_NBPSTATES; i++) {
  1500. pi->sys_info.nbp_mclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateMemclkFreq[i]);
  1501. pi->sys_info.nbp_nclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateNClkFreq[i]);
  1502. }
  1503. pi->sys_info.nbp_voltage_index[0] = le16_to_cpu(igp_info->info_7.usNBP0Voltage);
  1504. pi->sys_info.nbp_voltage_index[1] = le16_to_cpu(igp_info->info_7.usNBP1Voltage);
  1505. pi->sys_info.nbp_voltage_index[2] = le16_to_cpu(igp_info->info_7.usNBP2Voltage);
  1506. pi->sys_info.nbp_voltage_index[3] = le16_to_cpu(igp_info->info_7.usNBP3Voltage);
  1507. if (!pi->sys_info.nb_dpm_enable) {
  1508. for (i = 1; i < TRINITY_NUM_NBPSTATES; i++) {
  1509. pi->sys_info.nbp_mclk[i] = pi->sys_info.nbp_mclk[0];
  1510. pi->sys_info.nbp_nclk[i] = pi->sys_info.nbp_nclk[0];
  1511. pi->sys_info.nbp_voltage_index[i] = pi->sys_info.nbp_voltage_index[0];
  1512. }
  1513. }
  1514. pi->sys_info.uma_channel_number = igp_info->info_7.ucUMAChannelNumber;
  1515. sumo_construct_sclk_voltage_mapping_table(rdev,
  1516. &pi->sys_info.sclk_voltage_mapping_table,
  1517. igp_info->info_7.sAvail_SCLK);
  1518. sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
  1519. igp_info->info_7.sAvail_SCLK);
  1520. pi->sys_info.uvd_clock_table_entries[0].vclk_did =
  1521. igp_info->info_7.ucDPMState0VclkFid;
  1522. pi->sys_info.uvd_clock_table_entries[1].vclk_did =
  1523. igp_info->info_7.ucDPMState1VclkFid;
  1524. pi->sys_info.uvd_clock_table_entries[2].vclk_did =
  1525. igp_info->info_7.ucDPMState2VclkFid;
  1526. pi->sys_info.uvd_clock_table_entries[3].vclk_did =
  1527. igp_info->info_7.ucDPMState3VclkFid;
  1528. pi->sys_info.uvd_clock_table_entries[0].dclk_did =
  1529. igp_info->info_7.ucDPMState0DclkFid;
  1530. pi->sys_info.uvd_clock_table_entries[1].dclk_did =
  1531. igp_info->info_7.ucDPMState1DclkFid;
  1532. pi->sys_info.uvd_clock_table_entries[2].dclk_did =
  1533. igp_info->info_7.ucDPMState2DclkFid;
  1534. pi->sys_info.uvd_clock_table_entries[3].dclk_did =
  1535. igp_info->info_7.ucDPMState3DclkFid;
  1536. for (i = 0; i < 4; i++) {
  1537. pi->sys_info.uvd_clock_table_entries[i].vclk =
  1538. trinity_convert_did_to_freq(rdev,
  1539. pi->sys_info.uvd_clock_table_entries[i].vclk_did);
  1540. pi->sys_info.uvd_clock_table_entries[i].dclk =
  1541. trinity_convert_did_to_freq(rdev,
  1542. pi->sys_info.uvd_clock_table_entries[i].dclk_did);
  1543. }
  1544. }
  1545. return 0;
  1546. }
  1547. int trinity_dpm_init(struct radeon_device *rdev)
  1548. {
  1549. struct trinity_power_info *pi;
  1550. int ret, i;
  1551. pi = kzalloc(sizeof(struct trinity_power_info), GFP_KERNEL);
  1552. if (pi == NULL)
  1553. return -ENOMEM;
  1554. rdev->pm.dpm.priv = pi;
  1555. for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
  1556. pi->at[i] = TRINITY_AT_DFLT;
  1557. pi->enable_nbps_policy = true;
  1558. pi->enable_sclk_ds = true;
  1559. pi->enable_gfx_power_gating = true;
  1560. pi->enable_gfx_clock_gating = true;
  1561. pi->enable_mg_clock_gating = true;
  1562. pi->enable_gfx_dynamic_mgpg = true; /* ??? */
  1563. pi->override_dynamic_mgpg = true;
  1564. pi->enable_auto_thermal_throttling = true;
  1565. pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */
  1566. pi->uvd_dpm = true; /* ??? */
  1567. ret = trinity_parse_sys_info_table(rdev);
  1568. if (ret)
  1569. return ret;
  1570. trinity_construct_boot_state(rdev);
  1571. ret = trinity_parse_power_table(rdev);
  1572. if (ret)
  1573. return ret;
  1574. pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
  1575. pi->enable_dpm = true;
  1576. return 0;
  1577. }
  1578. void trinity_dpm_print_power_state(struct radeon_device *rdev,
  1579. struct radeon_ps *rps)
  1580. {
  1581. int i;
  1582. struct trinity_ps *ps = trinity_get_ps(rps);
  1583. r600_dpm_print_class_info(rps->class, rps->class2);
  1584. r600_dpm_print_cap_info(rps->caps);
  1585. printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
  1586. for (i = 0; i < ps->num_levels; i++) {
  1587. struct trinity_pl *pl = &ps->levels[i];
  1588. printk("\t\tpower level %d sclk: %u vddc: %u\n",
  1589. i, pl->sclk,
  1590. trinity_convert_voltage_index_to_value(rdev, pl->vddc_index));
  1591. }
  1592. r600_dpm_print_ps_status(rdev, rps);
  1593. }
  1594. void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
  1595. struct seq_file *m)
  1596. {
  1597. struct radeon_ps *rps = rdev->pm.dpm.current_ps;
  1598. struct trinity_ps *ps = trinity_get_ps(rps);
  1599. struct trinity_pl *pl;
  1600. u32 current_index =
  1601. (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
  1602. CURRENT_STATE_SHIFT;
  1603. if (current_index >= ps->num_levels) {
  1604. seq_printf(m, "invalid dpm profile %d\n", current_index);
  1605. } else {
  1606. pl = &ps->levels[current_index];
  1607. seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
  1608. seq_printf(m, "power level %d sclk: %u vddc: %u\n",
  1609. current_index, pl->sclk,
  1610. trinity_convert_voltage_index_to_value(rdev, pl->vddc_index));
  1611. }
  1612. }
  1613. void trinity_dpm_fini(struct radeon_device *rdev)
  1614. {
  1615. int i;
  1616. trinity_cleanup_asic(rdev); /* ??? */
  1617. for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
  1618. kfree(rdev->pm.dpm.ps[i].ps_priv);
  1619. }
  1620. kfree(rdev->pm.dpm.ps);
  1621. kfree(rdev->pm.dpm.priv);
  1622. }
  1623. u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low)
  1624. {
  1625. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1626. struct trinity_ps *requested_state = trinity_get_ps(&pi->requested_rps);
  1627. if (low)
  1628. return requested_state->levels[0].sclk;
  1629. else
  1630. return requested_state->levels[requested_state->num_levels - 1].sclk;
  1631. }
  1632. u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low)
  1633. {
  1634. struct trinity_power_info *pi = trinity_get_pi(rdev);
  1635. return pi->sys_info.bootup_uma_clk;
  1636. }