arizona-core.c 21 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <linux/mfd/arizona/core.h>
  23. #include <linux/mfd/arizona/registers.h>
  24. #include "arizona.h"
  25. static const char *wm5102_core_supplies[] = {
  26. "AVDD",
  27. "DBVDD1",
  28. };
  29. int arizona_clk32k_enable(struct arizona *arizona)
  30. {
  31. int ret = 0;
  32. mutex_lock(&arizona->clk_lock);
  33. arizona->clk32k_ref++;
  34. if (arizona->clk32k_ref == 1) {
  35. switch (arizona->pdata.clk32k_src) {
  36. case ARIZONA_32KZ_MCLK1:
  37. ret = pm_runtime_get_sync(arizona->dev);
  38. if (ret != 0)
  39. goto out;
  40. break;
  41. }
  42. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  43. ARIZONA_CLK_32K_ENA,
  44. ARIZONA_CLK_32K_ENA);
  45. }
  46. out:
  47. if (ret != 0)
  48. arizona->clk32k_ref--;
  49. mutex_unlock(&arizona->clk_lock);
  50. return ret;
  51. }
  52. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  53. int arizona_clk32k_disable(struct arizona *arizona)
  54. {
  55. int ret = 0;
  56. mutex_lock(&arizona->clk_lock);
  57. BUG_ON(arizona->clk32k_ref <= 0);
  58. arizona->clk32k_ref--;
  59. if (arizona->clk32k_ref == 0) {
  60. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  61. ARIZONA_CLK_32K_ENA, 0);
  62. switch (arizona->pdata.clk32k_src) {
  63. case ARIZONA_32KZ_MCLK1:
  64. pm_runtime_put_sync(arizona->dev);
  65. break;
  66. }
  67. }
  68. mutex_unlock(&arizona->clk_lock);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  72. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  73. {
  74. struct arizona *arizona = data;
  75. dev_err(arizona->dev, "CLKGEN error\n");
  76. return IRQ_HANDLED;
  77. }
  78. static irqreturn_t arizona_underclocked(int irq, void *data)
  79. {
  80. struct arizona *arizona = data;
  81. unsigned int val;
  82. int ret;
  83. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  84. &val);
  85. if (ret != 0) {
  86. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  87. ret);
  88. return IRQ_NONE;
  89. }
  90. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  91. dev_err(arizona->dev, "AIF3 underclocked\n");
  92. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  93. dev_err(arizona->dev, "AIF2 underclocked\n");
  94. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF1 underclocked\n");
  96. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "ISRC2 underclocked\n");
  98. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "ISRC1 underclocked\n");
  100. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "FX underclocked\n");
  102. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ASRC underclocked\n");
  104. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "DAC underclocked\n");
  106. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "ADC underclocked\n");
  108. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "Mixer dropped sample\n");
  110. return IRQ_HANDLED;
  111. }
  112. static irqreturn_t arizona_overclocked(int irq, void *data)
  113. {
  114. struct arizona *arizona = data;
  115. unsigned int val[2];
  116. int ret;
  117. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  118. &val[0], 2);
  119. if (ret != 0) {
  120. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  121. ret);
  122. return IRQ_NONE;
  123. }
  124. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  125. dev_err(arizona->dev, "PWM overclocked\n");
  126. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  127. dev_err(arizona->dev, "FX core overclocked\n");
  128. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  129. dev_err(arizona->dev, "DAC SYS overclocked\n");
  130. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "DAC WARP overclocked\n");
  132. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "ADC overclocked\n");
  134. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "Mixer overclocked\n");
  136. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "AIF3 overclocked\n");
  138. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "AIF2 overclocked\n");
  140. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "AIF1 overclocked\n");
  142. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "Pad control overclocked\n");
  144. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  146. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "Slimbus async overclocked\n");
  148. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  150. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "ASRC async system overclocked\n");
  152. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  154. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  158. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "DSP1 overclocked\n");
  160. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ISRC2 overclocked\n");
  162. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "ISRC1 overclocked\n");
  164. return IRQ_HANDLED;
  165. }
  166. static int arizona_poll_reg(struct arizona *arizona,
  167. int timeout, unsigned int reg,
  168. unsigned int mask, unsigned int target)
  169. {
  170. unsigned int val = 0;
  171. int ret, i;
  172. for (i = 0; i < timeout; i++) {
  173. ret = regmap_read(arizona->regmap, reg, &val);
  174. if (ret != 0) {
  175. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  176. reg, ret);
  177. continue;
  178. }
  179. if ((val & mask) == target)
  180. return 0;
  181. msleep(1);
  182. }
  183. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  184. return -ETIMEDOUT;
  185. }
  186. static int arizona_wait_for_boot(struct arizona *arizona)
  187. {
  188. int ret;
  189. /*
  190. * We can't use an interrupt as we need to runtime resume to do so,
  191. * we won't race with the interrupt handler as it'll be blocked on
  192. * runtime resume.
  193. */
  194. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  195. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  196. if (!ret)
  197. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  198. ARIZONA_BOOT_DONE_STS);
  199. pm_runtime_mark_last_busy(arizona->dev);
  200. return ret;
  201. }
  202. static int arizona_apply_hardware_patch(struct arizona* arizona)
  203. {
  204. unsigned int fll, sysclk;
  205. int ret, err;
  206. regcache_cache_bypass(arizona->regmap, true);
  207. /* Cache existing FLL and SYSCLK settings */
  208. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll);
  209. if (ret != 0) {
  210. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  211. ret);
  212. return ret;
  213. }
  214. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk);
  215. if (ret != 0) {
  216. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  217. ret);
  218. return ret;
  219. }
  220. /* Start up SYSCLK using the FLL in free running mode */
  221. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  222. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  223. if (ret != 0) {
  224. dev_err(arizona->dev,
  225. "Failed to start FLL in freerunning mode: %d\n",
  226. ret);
  227. return ret;
  228. }
  229. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  230. ARIZONA_FLL1_CLOCK_OK_STS,
  231. ARIZONA_FLL1_CLOCK_OK_STS);
  232. if (ret != 0) {
  233. ret = -ETIMEDOUT;
  234. goto err_fll;
  235. }
  236. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  237. if (ret != 0) {
  238. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  239. goto err_fll;
  240. }
  241. /* Start the write sequencer and wait for it to finish */
  242. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  243. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  244. if (ret != 0) {
  245. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  246. ret);
  247. goto err_sysclk;
  248. }
  249. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  250. ARIZONA_WSEQ_BUSY, 0);
  251. if (ret != 0) {
  252. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  253. ARIZONA_WSEQ_ABORT);
  254. ret = -ETIMEDOUT;
  255. }
  256. err_sysclk:
  257. err = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk);
  258. if (err != 0) {
  259. dev_err(arizona->dev,
  260. "Failed to re-apply old SYSCLK settings: %d\n",
  261. err);
  262. }
  263. err_fll:
  264. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll);
  265. if (err != 0) {
  266. dev_err(arizona->dev,
  267. "Failed to re-apply old FLL settings: %d\n",
  268. err);
  269. }
  270. regcache_cache_bypass(arizona->regmap, false);
  271. if (ret != 0)
  272. return ret;
  273. else
  274. return err;
  275. }
  276. #ifdef CONFIG_PM_RUNTIME
  277. static int arizona_runtime_resume(struct device *dev)
  278. {
  279. struct arizona *arizona = dev_get_drvdata(dev);
  280. int ret;
  281. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  282. ret = regulator_enable(arizona->dcvdd);
  283. if (ret != 0) {
  284. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  285. return ret;
  286. }
  287. regcache_cache_only(arizona->regmap, false);
  288. switch (arizona->type) {
  289. case WM5102:
  290. ret = wm5102_patch(arizona);
  291. if (ret != 0) {
  292. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  293. ret);
  294. goto err;
  295. }
  296. ret = arizona_apply_hardware_patch(arizona);
  297. if (ret != 0) {
  298. dev_err(arizona->dev,
  299. "Failed to apply hardware patch: %d\n",
  300. ret);
  301. goto err;
  302. }
  303. break;
  304. default:
  305. ret = arizona_wait_for_boot(arizona);
  306. if (ret != 0) {
  307. goto err;
  308. }
  309. break;
  310. }
  311. switch (arizona->type) {
  312. case WM5102:
  313. ret = wm5102_patch(arizona);
  314. if (ret != 0) {
  315. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  316. ret);
  317. goto err;
  318. }
  319. default:
  320. break;
  321. }
  322. ret = regcache_sync(arizona->regmap);
  323. if (ret != 0) {
  324. dev_err(arizona->dev, "Failed to restore register cache\n");
  325. goto err;
  326. }
  327. return 0;
  328. err:
  329. regcache_cache_only(arizona->regmap, true);
  330. regulator_disable(arizona->dcvdd);
  331. return ret;
  332. }
  333. static int arizona_runtime_suspend(struct device *dev)
  334. {
  335. struct arizona *arizona = dev_get_drvdata(dev);
  336. dev_dbg(arizona->dev, "Entering AoD mode\n");
  337. regulator_disable(arizona->dcvdd);
  338. regcache_cache_only(arizona->regmap, true);
  339. regcache_mark_dirty(arizona->regmap);
  340. return 0;
  341. }
  342. #endif
  343. #ifdef CONFIG_PM_SLEEP
  344. static int arizona_suspend(struct device *dev)
  345. {
  346. struct arizona *arizona = dev_get_drvdata(dev);
  347. dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
  348. disable_irq(arizona->irq);
  349. return 0;
  350. }
  351. static int arizona_suspend_late(struct device *dev)
  352. {
  353. struct arizona *arizona = dev_get_drvdata(dev);
  354. dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
  355. enable_irq(arizona->irq);
  356. return 0;
  357. }
  358. static int arizona_resume_noirq(struct device *dev)
  359. {
  360. struct arizona *arizona = dev_get_drvdata(dev);
  361. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  362. disable_irq(arizona->irq);
  363. return 0;
  364. }
  365. static int arizona_resume(struct device *dev)
  366. {
  367. struct arizona *arizona = dev_get_drvdata(dev);
  368. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  369. enable_irq(arizona->irq);
  370. return 0;
  371. }
  372. #endif
  373. const struct dev_pm_ops arizona_pm_ops = {
  374. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  375. arizona_runtime_resume,
  376. NULL)
  377. SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
  378. #ifdef CONFIG_PM_SLEEP
  379. .suspend_late = arizona_suspend_late,
  380. .resume_noirq = arizona_resume_noirq,
  381. #endif
  382. };
  383. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  384. static struct mfd_cell early_devs[] = {
  385. { .name = "arizona-ldo1" },
  386. };
  387. static struct mfd_cell wm5102_devs[] = {
  388. { .name = "arizona-micsupp" },
  389. { .name = "arizona-extcon" },
  390. { .name = "arizona-gpio" },
  391. { .name = "arizona-haptics" },
  392. { .name = "arizona-pwm" },
  393. { .name = "wm5102-codec" },
  394. };
  395. static struct mfd_cell wm5110_devs[] = {
  396. { .name = "arizona-micsupp" },
  397. { .name = "arizona-extcon" },
  398. { .name = "arizona-gpio" },
  399. { .name = "arizona-haptics" },
  400. { .name = "arizona-pwm" },
  401. { .name = "wm5110-codec" },
  402. };
  403. int arizona_dev_init(struct arizona *arizona)
  404. {
  405. struct device *dev = arizona->dev;
  406. const char *type_name;
  407. unsigned int reg, val;
  408. int (*apply_patch)(struct arizona *) = NULL;
  409. int ret, i;
  410. dev_set_drvdata(arizona->dev, arizona);
  411. mutex_init(&arizona->clk_lock);
  412. if (dev_get_platdata(arizona->dev))
  413. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  414. sizeof(arizona->pdata));
  415. regcache_cache_only(arizona->regmap, true);
  416. switch (arizona->type) {
  417. case WM5102:
  418. case WM5110:
  419. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  420. arizona->core_supplies[i].supply
  421. = wm5102_core_supplies[i];
  422. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  423. break;
  424. default:
  425. dev_err(arizona->dev, "Unknown device type %d\n",
  426. arizona->type);
  427. return -EINVAL;
  428. }
  429. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  430. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  431. if (ret != 0) {
  432. dev_err(dev, "Failed to add early children: %d\n", ret);
  433. return ret;
  434. }
  435. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  436. arizona->core_supplies);
  437. if (ret != 0) {
  438. dev_err(dev, "Failed to request core supplies: %d\n",
  439. ret);
  440. goto err_early;
  441. }
  442. arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
  443. if (IS_ERR(arizona->dcvdd)) {
  444. ret = PTR_ERR(arizona->dcvdd);
  445. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  446. goto err_early;
  447. }
  448. if (arizona->pdata.reset) {
  449. /* Start out with /RESET low to put the chip into reset */
  450. ret = gpio_request_one(arizona->pdata.reset,
  451. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  452. "arizona /RESET");
  453. if (ret != 0) {
  454. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  455. goto err_early;
  456. }
  457. }
  458. ret = regulator_bulk_enable(arizona->num_core_supplies,
  459. arizona->core_supplies);
  460. if (ret != 0) {
  461. dev_err(dev, "Failed to enable core supplies: %d\n",
  462. ret);
  463. goto err_early;
  464. }
  465. ret = regulator_enable(arizona->dcvdd);
  466. if (ret != 0) {
  467. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  468. goto err_enable;
  469. }
  470. if (arizona->pdata.reset) {
  471. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  472. msleep(1);
  473. }
  474. regcache_cache_only(arizona->regmap, false);
  475. /* Verify that this is a chip we know about */
  476. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  477. if (ret != 0) {
  478. dev_err(dev, "Failed to read ID register: %d\n", ret);
  479. goto err_reset;
  480. }
  481. switch (reg) {
  482. case 0x5102:
  483. case 0x5110:
  484. break;
  485. default:
  486. dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
  487. goto err_reset;
  488. }
  489. /* If we have a /RESET GPIO we'll already be reset */
  490. if (!arizona->pdata.reset) {
  491. regcache_mark_dirty(arizona->regmap);
  492. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  493. if (ret != 0) {
  494. dev_err(dev, "Failed to reset device: %d\n", ret);
  495. goto err_reset;
  496. }
  497. msleep(1);
  498. ret = regcache_sync(arizona->regmap);
  499. if (ret != 0) {
  500. dev_err(dev, "Failed to sync device: %d\n", ret);
  501. goto err_reset;
  502. }
  503. }
  504. /* Ensure device startup is complete */
  505. switch (arizona->type) {
  506. case WM5102:
  507. ret = regmap_read(arizona->regmap, 0x19, &val);
  508. if (ret != 0)
  509. dev_err(dev,
  510. "Failed to check write sequencer state: %d\n",
  511. ret);
  512. else if (val & 0x01)
  513. break;
  514. /* Fall through */
  515. default:
  516. ret = arizona_wait_for_boot(arizona);
  517. if (ret != 0) {
  518. dev_err(arizona->dev,
  519. "Device failed initial boot: %d\n", ret);
  520. goto err_reset;
  521. }
  522. break;
  523. }
  524. /* Read the device ID information & do device specific stuff */
  525. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  526. if (ret != 0) {
  527. dev_err(dev, "Failed to read ID register: %d\n", ret);
  528. goto err_reset;
  529. }
  530. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  531. &arizona->rev);
  532. if (ret != 0) {
  533. dev_err(dev, "Failed to read revision register: %d\n", ret);
  534. goto err_reset;
  535. }
  536. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  537. switch (reg) {
  538. #ifdef CONFIG_MFD_WM5102
  539. case 0x5102:
  540. type_name = "WM5102";
  541. if (arizona->type != WM5102) {
  542. dev_err(arizona->dev, "WM5102 registered as %d\n",
  543. arizona->type);
  544. arizona->type = WM5102;
  545. }
  546. apply_patch = wm5102_patch;
  547. arizona->rev &= 0x7;
  548. break;
  549. #endif
  550. #ifdef CONFIG_MFD_WM5110
  551. case 0x5110:
  552. type_name = "WM5110";
  553. if (arizona->type != WM5110) {
  554. dev_err(arizona->dev, "WM5110 registered as %d\n",
  555. arizona->type);
  556. arizona->type = WM5110;
  557. }
  558. apply_patch = wm5110_patch;
  559. break;
  560. #endif
  561. default:
  562. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  563. goto err_reset;
  564. }
  565. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  566. if (apply_patch) {
  567. ret = apply_patch(arizona);
  568. if (ret != 0) {
  569. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  570. ret);
  571. goto err_reset;
  572. }
  573. switch (arizona->type) {
  574. case WM5102:
  575. ret = arizona_apply_hardware_patch(arizona);
  576. if (ret != 0) {
  577. dev_err(arizona->dev,
  578. "Failed to apply hardware patch: %d\n",
  579. ret);
  580. goto err_reset;
  581. }
  582. break;
  583. default:
  584. break;
  585. }
  586. }
  587. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  588. if (!arizona->pdata.gpio_defaults[i])
  589. continue;
  590. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  591. arizona->pdata.gpio_defaults[i]);
  592. }
  593. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  594. pm_runtime_use_autosuspend(arizona->dev);
  595. pm_runtime_enable(arizona->dev);
  596. /* Chip default */
  597. if (!arizona->pdata.clk32k_src)
  598. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  599. switch (arizona->pdata.clk32k_src) {
  600. case ARIZONA_32KZ_MCLK1:
  601. case ARIZONA_32KZ_MCLK2:
  602. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  603. ARIZONA_CLK_32K_SRC_MASK,
  604. arizona->pdata.clk32k_src - 1);
  605. arizona_clk32k_enable(arizona);
  606. break;
  607. case ARIZONA_32KZ_NONE:
  608. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  609. ARIZONA_CLK_32K_SRC_MASK, 2);
  610. break;
  611. default:
  612. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  613. arizona->pdata.clk32k_src);
  614. ret = -EINVAL;
  615. goto err_reset;
  616. }
  617. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  618. if (!arizona->pdata.micbias[i].mV &&
  619. !arizona->pdata.micbias[i].bypass)
  620. continue;
  621. /* Apply default for bypass mode */
  622. if (!arizona->pdata.micbias[i].mV)
  623. arizona->pdata.micbias[i].mV = 2800;
  624. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  625. val <<= ARIZONA_MICB1_LVL_SHIFT;
  626. if (arizona->pdata.micbias[i].ext_cap)
  627. val |= ARIZONA_MICB1_EXT_CAP;
  628. if (arizona->pdata.micbias[i].discharge)
  629. val |= ARIZONA_MICB1_DISCH;
  630. if (arizona->pdata.micbias[i].fast_start)
  631. val |= ARIZONA_MICB1_RATE;
  632. if (arizona->pdata.micbias[i].bypass)
  633. val |= ARIZONA_MICB1_BYPASS;
  634. regmap_update_bits(arizona->regmap,
  635. ARIZONA_MIC_BIAS_CTRL_1 + i,
  636. ARIZONA_MICB1_LVL_MASK |
  637. ARIZONA_MICB1_DISCH |
  638. ARIZONA_MICB1_BYPASS |
  639. ARIZONA_MICB1_RATE, val);
  640. }
  641. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  642. /* Default for both is 0 so noop with defaults */
  643. val = arizona->pdata.dmic_ref[i]
  644. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  645. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  646. regmap_update_bits(arizona->regmap,
  647. ARIZONA_IN1L_CONTROL + (i * 8),
  648. ARIZONA_IN1_DMIC_SUP_MASK |
  649. ARIZONA_IN1_MODE_MASK, val);
  650. }
  651. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  652. /* Default is 0 so noop with defaults */
  653. if (arizona->pdata.out_mono[i])
  654. val = ARIZONA_OUT1_MONO;
  655. else
  656. val = 0;
  657. regmap_update_bits(arizona->regmap,
  658. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  659. ARIZONA_OUT1_MONO, val);
  660. }
  661. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  662. if (arizona->pdata.spk_mute[i])
  663. regmap_update_bits(arizona->regmap,
  664. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  665. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  666. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  667. arizona->pdata.spk_mute[i]);
  668. if (arizona->pdata.spk_fmt[i])
  669. regmap_update_bits(arizona->regmap,
  670. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  671. ARIZONA_SPK1_FMT_MASK,
  672. arizona->pdata.spk_fmt[i]);
  673. }
  674. /* Set up for interrupts */
  675. ret = arizona_irq_init(arizona);
  676. if (ret != 0)
  677. goto err_reset;
  678. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  679. arizona_clkgen_err, arizona);
  680. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  681. arizona_overclocked, arizona);
  682. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  683. arizona_underclocked, arizona);
  684. switch (arizona->type) {
  685. case WM5102:
  686. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  687. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  688. break;
  689. case WM5110:
  690. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  691. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  692. break;
  693. }
  694. if (ret != 0) {
  695. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  696. goto err_irq;
  697. }
  698. #ifdef CONFIG_PM_RUNTIME
  699. regulator_disable(arizona->dcvdd);
  700. #endif
  701. return 0;
  702. err_irq:
  703. arizona_irq_exit(arizona);
  704. err_reset:
  705. if (arizona->pdata.reset) {
  706. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  707. gpio_free(arizona->pdata.reset);
  708. }
  709. regulator_disable(arizona->dcvdd);
  710. err_enable:
  711. regulator_bulk_disable(arizona->num_core_supplies,
  712. arizona->core_supplies);
  713. err_early:
  714. mfd_remove_devices(dev);
  715. return ret;
  716. }
  717. EXPORT_SYMBOL_GPL(arizona_dev_init);
  718. int arizona_dev_exit(struct arizona *arizona)
  719. {
  720. mfd_remove_devices(arizona->dev);
  721. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  722. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  723. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  724. pm_runtime_disable(arizona->dev);
  725. arizona_irq_exit(arizona);
  726. if (arizona->pdata.reset)
  727. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  728. regulator_disable(arizona->dcvdd);
  729. regulator_bulk_disable(ARRAY_SIZE(arizona->core_supplies),
  730. arizona->core_supplies);
  731. return 0;
  732. }
  733. EXPORT_SYMBOL_GPL(arizona_dev_exit);