netxen_nic_init.c 37 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. if (recv_ctx->rds_rings == NULL)
  163. goto skip_rds;
  164. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  165. rds_ring = &recv_ctx->rds_rings[ring];
  166. vfree(rds_ring->rx_buf_arr);
  167. rds_ring->rx_buf_arr = NULL;
  168. }
  169. kfree(recv_ctx->rds_rings);
  170. skip_rds:
  171. if (adapter->tx_ring == NULL)
  172. return;
  173. tx_ring = adapter->tx_ring;
  174. vfree(tx_ring->cmd_buf_arr);
  175. }
  176. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  177. {
  178. struct netxen_recv_context *recv_ctx;
  179. struct nx_host_rds_ring *rds_ring;
  180. struct nx_host_sds_ring *sds_ring;
  181. struct nx_host_tx_ring *tx_ring;
  182. struct netxen_rx_buffer *rx_buf;
  183. int ring, i, size;
  184. struct netxen_cmd_buffer *cmd_buf_arr;
  185. struct net_device *netdev = adapter->netdev;
  186. struct pci_dev *pdev = adapter->pdev;
  187. size = sizeof(struct nx_host_tx_ring);
  188. tx_ring = kzalloc(size, GFP_KERNEL);
  189. if (tx_ring == NULL) {
  190. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  191. netdev->name);
  192. return -ENOMEM;
  193. }
  194. adapter->tx_ring = tx_ring;
  195. tx_ring->num_desc = adapter->num_txd;
  196. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. return -ENOMEM;
  201. }
  202. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  203. tx_ring->cmd_buf_arr = cmd_buf_arr;
  204. recv_ctx = &adapter->recv_ctx;
  205. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  206. rds_ring = kzalloc(size, GFP_KERNEL);
  207. if (rds_ring == NULL) {
  208. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  209. netdev->name);
  210. return -ENOMEM;
  211. }
  212. recv_ctx->rds_rings = rds_ring;
  213. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  214. rds_ring = &recv_ctx->rds_rings[ring];
  215. switch (ring) {
  216. case RCV_RING_NORMAL:
  217. rds_ring->num_desc = adapter->num_rxd;
  218. if (adapter->ahw.cut_through) {
  219. rds_ring->dma_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. rds_ring->skb_size =
  222. NX_CT_DEFAULT_RX_BUF_LEN;
  223. } else {
  224. rds_ring->dma_size = RX_DMA_MAP_LEN;
  225. rds_ring->skb_size =
  226. MAX_RX_BUFFER_LENGTH;
  227. }
  228. break;
  229. case RCV_RING_JUMBO:
  230. rds_ring->num_desc = adapter->num_jumbo_rxd;
  231. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  232. rds_ring->dma_size =
  233. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  234. else
  235. rds_ring->dma_size =
  236. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  237. rds_ring->skb_size =
  238. rds_ring->dma_size + NET_IP_ALIGN;
  239. break;
  240. case RCV_RING_LRO:
  241. rds_ring->num_desc = adapter->num_lro_rxd;
  242. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  243. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  244. break;
  245. }
  246. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  247. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  248. if (rds_ring->rx_buf_arr == NULL) {
  249. printk(KERN_ERR "%s: Failed to allocate "
  250. "rx buffer ring %d\n",
  251. netdev->name, ring);
  252. /* free whatever was already allocated */
  253. goto err_out;
  254. }
  255. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  256. INIT_LIST_HEAD(&rds_ring->free_list);
  257. /*
  258. * Now go through all of them, set reference handles
  259. * and put them in the queues.
  260. */
  261. rx_buf = rds_ring->rx_buf_arr;
  262. for (i = 0; i < rds_ring->num_desc; i++) {
  263. list_add_tail(&rx_buf->list,
  264. &rds_ring->free_list);
  265. rx_buf->ref_handle = i;
  266. rx_buf->state = NETXEN_BUFFER_FREE;
  267. rx_buf++;
  268. }
  269. spin_lock_init(&rds_ring->lock);
  270. }
  271. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  272. sds_ring = &recv_ctx->sds_rings[ring];
  273. sds_ring->irq = adapter->msix_entries[ring].vector;
  274. sds_ring->adapter = adapter;
  275. sds_ring->num_desc = adapter->num_rxd;
  276. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  277. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  278. }
  279. return 0;
  280. err_out:
  281. netxen_free_sw_resources(adapter);
  282. return -ENOMEM;
  283. }
  284. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  285. {
  286. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  287. adapter->set_multi = netxen_p2_nic_set_multi;
  288. switch (adapter->ahw.port_type) {
  289. case NETXEN_NIC_GBE:
  290. adapter->enable_phy_interrupts =
  291. netxen_niu_gbe_enable_phy_interrupts;
  292. adapter->disable_phy_interrupts =
  293. netxen_niu_gbe_disable_phy_interrupts;
  294. adapter->set_mtu = netxen_nic_set_mtu_gb;
  295. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  296. adapter->phy_read = netxen_niu_gbe_phy_read;
  297. adapter->phy_write = netxen_niu_gbe_phy_write;
  298. adapter->init_port = netxen_niu_gbe_init_port;
  299. adapter->stop_port = netxen_niu_disable_gbe_port;
  300. break;
  301. case NETXEN_NIC_XGBE:
  302. adapter->enable_phy_interrupts =
  303. netxen_niu_xgbe_enable_phy_interrupts;
  304. adapter->disable_phy_interrupts =
  305. netxen_niu_xgbe_disable_phy_interrupts;
  306. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  307. adapter->init_port = netxen_niu_xg_init_port;
  308. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  309. adapter->stop_port = netxen_niu_disable_xg_port;
  310. break;
  311. default:
  312. break;
  313. }
  314. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  315. adapter->set_mtu = nx_fw_cmd_set_mtu;
  316. adapter->set_promisc = netxen_p3_nic_set_promisc;
  317. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  318. adapter->set_multi = netxen_p3_nic_set_multi;
  319. }
  320. }
  321. /*
  322. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  323. * address to external PCI CRB address.
  324. */
  325. static u32 netxen_decode_crb_addr(u32 addr)
  326. {
  327. int i;
  328. u32 base_addr, offset, pci_base;
  329. crb_addr_transform_setup();
  330. pci_base = NETXEN_ADDR_ERROR;
  331. base_addr = addr & 0xfff00000;
  332. offset = addr & 0x000fffff;
  333. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  334. if (crb_addr_xform[i] == base_addr) {
  335. pci_base = i << 20;
  336. break;
  337. }
  338. }
  339. if (pci_base == NETXEN_ADDR_ERROR)
  340. return pci_base;
  341. else
  342. return (pci_base + offset);
  343. }
  344. static long rom_max_timeout = 100;
  345. static long rom_lock_timeout = 10000;
  346. static int rom_lock(struct netxen_adapter *adapter)
  347. {
  348. int iter;
  349. u32 done = 0;
  350. int timeout = 0;
  351. while (!done) {
  352. /* acquire semaphore2 from PCI HW block */
  353. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  354. if (done == 1)
  355. break;
  356. if (timeout >= rom_lock_timeout)
  357. return -EIO;
  358. timeout++;
  359. /*
  360. * Yield CPU
  361. */
  362. if (!in_atomic())
  363. schedule();
  364. else {
  365. for (iter = 0; iter < 20; iter++)
  366. cpu_relax(); /*This a nop instr on i386 */
  367. }
  368. }
  369. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  370. return 0;
  371. }
  372. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  373. {
  374. long timeout = 0;
  375. long done = 0;
  376. cond_resched();
  377. while (done == 0) {
  378. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  379. done &= 2;
  380. timeout++;
  381. if (timeout >= rom_max_timeout) {
  382. printk("Timeout reached waiting for rom done");
  383. return -EIO;
  384. }
  385. }
  386. return 0;
  387. }
  388. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  389. {
  390. /* release semaphore2 */
  391. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  392. }
  393. static int do_rom_fast_read(struct netxen_adapter *adapter,
  394. int addr, int *valp)
  395. {
  396. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  397. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  398. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  399. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  400. if (netxen_wait_rom_done(adapter)) {
  401. printk("Error waiting for rom done\n");
  402. return -EIO;
  403. }
  404. /* reset abyte_cnt and dummy_byte_cnt */
  405. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  406. udelay(10);
  407. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  408. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  409. return 0;
  410. }
  411. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  412. u8 *bytes, size_t size)
  413. {
  414. int addridx;
  415. int ret = 0;
  416. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  417. int v;
  418. ret = do_rom_fast_read(adapter, addridx, &v);
  419. if (ret != 0)
  420. break;
  421. *(__le32 *)bytes = cpu_to_le32(v);
  422. bytes += 4;
  423. }
  424. return ret;
  425. }
  426. int
  427. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  428. u8 *bytes, size_t size)
  429. {
  430. int ret;
  431. ret = rom_lock(adapter);
  432. if (ret < 0)
  433. return ret;
  434. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  435. netxen_rom_unlock(adapter);
  436. return ret;
  437. }
  438. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  439. {
  440. int ret;
  441. if (rom_lock(adapter) != 0)
  442. return -EIO;
  443. ret = do_rom_fast_read(adapter, addr, valp);
  444. netxen_rom_unlock(adapter);
  445. return ret;
  446. }
  447. #define NETXEN_BOARDTYPE 0x4008
  448. #define NETXEN_BOARDNUM 0x400c
  449. #define NETXEN_CHIPNUM 0x4010
  450. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  451. {
  452. int addr, val;
  453. int i, n, init_delay = 0;
  454. struct crb_addr_pair *buf;
  455. unsigned offset;
  456. u32 off;
  457. /* resetall */
  458. rom_lock(adapter);
  459. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  460. netxen_rom_unlock(adapter);
  461. if (verbose) {
  462. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  463. printk("P2 ROM board type: 0x%08x\n", val);
  464. else
  465. printk("Could not read board type\n");
  466. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  467. printk("P2 ROM board num: 0x%08x\n", val);
  468. else
  469. printk("Could not read board number\n");
  470. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  471. printk("P2 ROM chip num: 0x%08x\n", val);
  472. else
  473. printk("Could not read chip number\n");
  474. }
  475. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  476. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  477. (n != 0xcafecafe) ||
  478. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  479. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  480. "n: %08x\n", netxen_nic_driver_name, n);
  481. return -EIO;
  482. }
  483. offset = n & 0xffffU;
  484. n = (n >> 16) & 0xffffU;
  485. } else {
  486. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  487. !(n & 0x80000000)) {
  488. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  489. "n: %08x\n", netxen_nic_driver_name, n);
  490. return -EIO;
  491. }
  492. offset = 1;
  493. n &= ~0x80000000;
  494. }
  495. if (n < 1024) {
  496. if (verbose)
  497. printk(KERN_DEBUG "%s: %d CRB init values found"
  498. " in ROM.\n", netxen_nic_driver_name, n);
  499. } else {
  500. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  501. " initialized.\n", __func__, n);
  502. return -EIO;
  503. }
  504. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  505. if (buf == NULL) {
  506. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  507. netxen_nic_driver_name);
  508. return -ENOMEM;
  509. }
  510. for (i = 0; i < n; i++) {
  511. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  512. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  513. kfree(buf);
  514. return -EIO;
  515. }
  516. buf[i].addr = addr;
  517. buf[i].data = val;
  518. if (verbose)
  519. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  520. netxen_nic_driver_name,
  521. (u32)netxen_decode_crb_addr(addr), val);
  522. }
  523. for (i = 0; i < n; i++) {
  524. off = netxen_decode_crb_addr(buf[i].addr);
  525. if (off == NETXEN_ADDR_ERROR) {
  526. printk(KERN_ERR"CRB init value out of range %x\n",
  527. buf[i].addr);
  528. continue;
  529. }
  530. off += NETXEN_PCI_CRBSPACE;
  531. /* skipping cold reboot MAGIC */
  532. if (off == NETXEN_CAM_RAM(0x1fc))
  533. continue;
  534. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  535. /* do not reset PCI */
  536. if (off == (ROMUSB_GLB + 0xbc))
  537. continue;
  538. if (off == (ROMUSB_GLB + 0xa8))
  539. continue;
  540. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  541. continue;
  542. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  543. continue;
  544. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  545. continue;
  546. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  547. buf[i].data = 0x1020;
  548. /* skip the function enable register */
  549. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  550. continue;
  551. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  552. continue;
  553. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  554. continue;
  555. }
  556. if (off == NETXEN_ADDR_ERROR) {
  557. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  558. netxen_nic_driver_name, buf[i].addr);
  559. continue;
  560. }
  561. init_delay = 1;
  562. /* After writing this register, HW needs time for CRB */
  563. /* to quiet down (else crb_window returns 0xffffffff) */
  564. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  565. init_delay = 1000;
  566. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  567. /* hold xdma in reset also */
  568. buf[i].data = NETXEN_NIC_XDMA_RESET;
  569. buf[i].data = 0x8000ff;
  570. }
  571. }
  572. NXWR32(adapter, off, buf[i].data);
  573. msleep(init_delay);
  574. }
  575. kfree(buf);
  576. /* disable_peg_cache_all */
  577. /* unreset_net_cache */
  578. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  579. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  580. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  581. }
  582. /* p2dn replyCount */
  583. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  584. /* disable_peg_cache 0 */
  585. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  586. /* disable_peg_cache 1 */
  587. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  588. /* peg_clr_all */
  589. /* peg_clr 0 */
  590. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  591. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  592. /* peg_clr 1 */
  593. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  594. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  595. /* peg_clr 2 */
  596. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  597. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  598. /* peg_clr 3 */
  599. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  600. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  601. return 0;
  602. }
  603. int
  604. netxen_need_fw_reset(struct netxen_adapter *adapter)
  605. {
  606. u32 count, old_count;
  607. u32 val, version, major, minor, build;
  608. int i, timeout;
  609. u8 fw_type;
  610. /* NX2031 firmware doesn't support heartbit */
  611. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  612. return 1;
  613. /* last attempt had failed */
  614. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  615. return 1;
  616. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  617. for (i = 0; i < 10; i++) {
  618. timeout = msleep_interruptible(200);
  619. if (timeout) {
  620. NXWR32(adapter, CRB_CMDPEG_STATE,
  621. PHAN_INITIALIZE_FAILED);
  622. return -EINTR;
  623. }
  624. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  625. if (count != old_count)
  626. break;
  627. }
  628. /* firmware is dead */
  629. if (count == old_count)
  630. return 1;
  631. /* check if we have got newer or different file firmware */
  632. if (adapter->fw) {
  633. const struct firmware *fw = adapter->fw;
  634. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  635. version = NETXEN_DECODE_VERSION(val);
  636. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  637. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  638. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  639. if (version > NETXEN_VERSION_CODE(major, minor, build))
  640. return 1;
  641. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  642. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  643. fw_type = (val & 0x4) ?
  644. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  645. if (adapter->fw_type != fw_type)
  646. return 1;
  647. }
  648. }
  649. return 0;
  650. }
  651. static char *fw_name[] = {
  652. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  653. };
  654. int
  655. netxen_load_firmware(struct netxen_adapter *adapter)
  656. {
  657. u64 *ptr64;
  658. u32 i, flashaddr, size;
  659. const struct firmware *fw = adapter->fw;
  660. struct pci_dev *pdev = adapter->pdev;
  661. dev_info(&pdev->dev, "loading firmware from %s\n",
  662. fw_name[adapter->fw_type]);
  663. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  664. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  665. if (fw) {
  666. __le64 data;
  667. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  668. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  669. flashaddr = NETXEN_BOOTLD_START;
  670. for (i = 0; i < size; i++) {
  671. data = cpu_to_le64(ptr64[i]);
  672. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  673. flashaddr += 8;
  674. }
  675. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  676. size = (__force u32)cpu_to_le32(size) / 8;
  677. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  678. flashaddr = NETXEN_IMAGE_START;
  679. for (i = 0; i < size; i++) {
  680. data = cpu_to_le64(ptr64[i]);
  681. if (adapter->pci_mem_write(adapter,
  682. flashaddr, &data, 8))
  683. return -EIO;
  684. flashaddr += 8;
  685. }
  686. } else {
  687. u32 data;
  688. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  689. flashaddr = NETXEN_BOOTLD_START;
  690. for (i = 0; i < size; i++) {
  691. if (netxen_rom_fast_read(adapter,
  692. flashaddr, (int *)&data) != 0)
  693. return -EIO;
  694. if (adapter->pci_mem_write(adapter,
  695. flashaddr, &data, 4))
  696. return -EIO;
  697. flashaddr += 4;
  698. }
  699. }
  700. msleep(1);
  701. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  702. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  703. else {
  704. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  705. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  706. }
  707. return 0;
  708. }
  709. static int
  710. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  711. {
  712. __le32 val;
  713. u32 ver, min_ver, bios;
  714. struct pci_dev *pdev = adapter->pdev;
  715. const struct firmware *fw = adapter->fw;
  716. if (fw->size < NX_FW_MIN_SIZE)
  717. return -EINVAL;
  718. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  719. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  720. return -EINVAL;
  721. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  722. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  723. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  724. else
  725. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  726. ver = NETXEN_DECODE_VERSION(val);
  727. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  728. dev_err(&pdev->dev,
  729. "%s: firmware version %d.%d.%d unsupported\n",
  730. fwname, _major(ver), _minor(ver), _build(ver));
  731. return -EINVAL;
  732. }
  733. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  734. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  735. if ((__force u32)val != bios) {
  736. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  737. fwname);
  738. return -EINVAL;
  739. }
  740. /* check if flashed firmware is newer */
  741. if (netxen_rom_fast_read(adapter,
  742. NX_FW_VERSION_OFFSET, (int *)&val))
  743. return -EIO;
  744. val = NETXEN_DECODE_VERSION(val);
  745. if (val > ver) {
  746. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  747. fwname);
  748. return -EINVAL;
  749. }
  750. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  751. return 0;
  752. }
  753. void netxen_request_firmware(struct netxen_adapter *adapter)
  754. {
  755. u32 capability, flashed_ver;
  756. u8 fw_type;
  757. struct pci_dev *pdev = adapter->pdev;
  758. int rc = 0;
  759. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  760. fw_type = NX_P2_MN_ROMIMAGE;
  761. goto request_fw;
  762. } else {
  763. fw_type = NX_P3_CT_ROMIMAGE;
  764. goto request_fw;
  765. }
  766. request_mn:
  767. capability = 0;
  768. netxen_rom_fast_read(adapter,
  769. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  770. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  771. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  772. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  773. if (capability & NX_PEG_TUNE_MN_PRESENT) {
  774. fw_type = NX_P3_MN_ROMIMAGE;
  775. goto request_fw;
  776. }
  777. }
  778. fw_type = NX_FLASH_ROMIMAGE;
  779. adapter->fw = NULL;
  780. goto done;
  781. request_fw:
  782. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  783. if (rc != 0) {
  784. if (fw_type == NX_P3_CT_ROMIMAGE) {
  785. msleep(1);
  786. goto request_mn;
  787. }
  788. fw_type = NX_FLASH_ROMIMAGE;
  789. adapter->fw = NULL;
  790. goto done;
  791. }
  792. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  793. if (rc != 0) {
  794. release_firmware(adapter->fw);
  795. if (fw_type == NX_P3_CT_ROMIMAGE) {
  796. msleep(1);
  797. goto request_mn;
  798. }
  799. fw_type = NX_FLASH_ROMIMAGE;
  800. adapter->fw = NULL;
  801. goto done;
  802. }
  803. done:
  804. adapter->fw_type = fw_type;
  805. }
  806. void
  807. netxen_release_firmware(struct netxen_adapter *adapter)
  808. {
  809. if (adapter->fw)
  810. release_firmware(adapter->fw);
  811. }
  812. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  813. {
  814. uint64_t addr;
  815. uint32_t hi;
  816. uint32_t lo;
  817. adapter->dummy_dma.addr =
  818. pci_alloc_consistent(adapter->pdev,
  819. NETXEN_HOST_DUMMY_DMA_SIZE,
  820. &adapter->dummy_dma.phys_addr);
  821. if (adapter->dummy_dma.addr == NULL) {
  822. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  823. __func__);
  824. return -ENOMEM;
  825. }
  826. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  827. hi = (addr >> 32) & 0xffffffff;
  828. lo = addr & 0xffffffff;
  829. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  830. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  831. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  832. uint32_t temp = 0;
  833. NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp);
  834. }
  835. return 0;
  836. }
  837. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  838. {
  839. int i = 100;
  840. if (!adapter->dummy_dma.addr)
  841. return;
  842. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  843. do {
  844. if (dma_watchdog_shutdown_request(adapter) == 1)
  845. break;
  846. msleep(50);
  847. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  848. break;
  849. } while (--i);
  850. }
  851. if (i) {
  852. pci_free_consistent(adapter->pdev,
  853. NETXEN_HOST_DUMMY_DMA_SIZE,
  854. adapter->dummy_dma.addr,
  855. adapter->dummy_dma.phys_addr);
  856. adapter->dummy_dma.addr = NULL;
  857. } else {
  858. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  859. adapter->netdev->name);
  860. }
  861. }
  862. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  863. {
  864. u32 val = 0;
  865. int retries = 60;
  866. if (pegtune_val)
  867. return 0;
  868. do {
  869. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  870. switch (val) {
  871. case PHAN_INITIALIZE_COMPLETE:
  872. case PHAN_INITIALIZE_ACK:
  873. return 0;
  874. case PHAN_INITIALIZE_FAILED:
  875. goto out_err;
  876. default:
  877. break;
  878. }
  879. msleep(500);
  880. } while (--retries);
  881. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  882. out_err:
  883. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  884. return -EIO;
  885. }
  886. static int
  887. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  888. {
  889. u32 val = 0;
  890. int retries = 2000;
  891. do {
  892. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  893. if (val == PHAN_PEG_RCV_INITIALIZED)
  894. return 0;
  895. msleep(10);
  896. } while (--retries);
  897. if (!retries) {
  898. printk(KERN_ERR "Receive Peg initialization not "
  899. "complete, state: 0x%x.\n", val);
  900. return -EIO;
  901. }
  902. return 0;
  903. }
  904. int netxen_init_firmware(struct netxen_adapter *adapter)
  905. {
  906. int err;
  907. err = netxen_receive_peg_ready(adapter);
  908. if (err)
  909. return err;
  910. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  911. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  912. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  913. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  914. if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) {
  915. adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
  916. }
  917. return err;
  918. }
  919. static void
  920. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  921. {
  922. u32 cable_OUI;
  923. u16 cable_len;
  924. u16 link_speed;
  925. u8 link_status, module, duplex, autoneg;
  926. struct net_device *netdev = adapter->netdev;
  927. adapter->has_link_events = 1;
  928. cable_OUI = msg->body[1] & 0xffffffff;
  929. cable_len = (msg->body[1] >> 32) & 0xffff;
  930. link_speed = (msg->body[1] >> 48) & 0xffff;
  931. link_status = msg->body[2] & 0xff;
  932. duplex = (msg->body[2] >> 16) & 0xff;
  933. autoneg = (msg->body[2] >> 24) & 0xff;
  934. module = (msg->body[2] >> 8) & 0xff;
  935. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  936. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  937. netdev->name, cable_OUI, cable_len);
  938. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  939. printk(KERN_INFO "%s: unsupported cable length %d\n",
  940. netdev->name, cable_len);
  941. }
  942. netxen_advert_link_change(adapter, link_status);
  943. /* update link parameters */
  944. if (duplex == LINKEVENT_FULL_DUPLEX)
  945. adapter->link_duplex = DUPLEX_FULL;
  946. else
  947. adapter->link_duplex = DUPLEX_HALF;
  948. adapter->module_type = module;
  949. adapter->link_autoneg = autoneg;
  950. adapter->link_speed = link_speed;
  951. }
  952. static void
  953. netxen_handle_fw_message(int desc_cnt, int index,
  954. struct nx_host_sds_ring *sds_ring)
  955. {
  956. nx_fw_msg_t msg;
  957. struct status_desc *desc;
  958. int i = 0, opcode;
  959. while (desc_cnt > 0 && i < 8) {
  960. desc = &sds_ring->desc_head[index];
  961. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  962. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  963. index = get_next_index(index, sds_ring->num_desc);
  964. desc_cnt--;
  965. }
  966. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  967. switch (opcode) {
  968. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  969. netxen_handle_linkevent(sds_ring->adapter, &msg);
  970. break;
  971. default:
  972. break;
  973. }
  974. }
  975. static int
  976. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  977. struct nx_host_rds_ring *rds_ring,
  978. struct netxen_rx_buffer *buffer)
  979. {
  980. struct sk_buff *skb;
  981. dma_addr_t dma;
  982. struct pci_dev *pdev = adapter->pdev;
  983. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  984. if (!buffer->skb)
  985. return 1;
  986. skb = buffer->skb;
  987. if (!adapter->ahw.cut_through)
  988. skb_reserve(skb, 2);
  989. dma = pci_map_single(pdev, skb->data,
  990. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  991. if (pci_dma_mapping_error(pdev, dma)) {
  992. dev_kfree_skb_any(skb);
  993. buffer->skb = NULL;
  994. return 1;
  995. }
  996. buffer->skb = skb;
  997. buffer->dma = dma;
  998. buffer->state = NETXEN_BUFFER_BUSY;
  999. return 0;
  1000. }
  1001. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1002. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1003. {
  1004. struct netxen_rx_buffer *buffer;
  1005. struct sk_buff *skb;
  1006. buffer = &rds_ring->rx_buf_arr[index];
  1007. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1008. PCI_DMA_FROMDEVICE);
  1009. skb = buffer->skb;
  1010. if (!skb)
  1011. goto no_skb;
  1012. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1013. adapter->stats.csummed++;
  1014. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1015. } else
  1016. skb->ip_summed = CHECKSUM_NONE;
  1017. skb->dev = adapter->netdev;
  1018. buffer->skb = NULL;
  1019. no_skb:
  1020. buffer->state = NETXEN_BUFFER_FREE;
  1021. return skb;
  1022. }
  1023. static struct netxen_rx_buffer *
  1024. netxen_process_rcv(struct netxen_adapter *adapter,
  1025. int ring, int index, int length, int cksum, int pkt_offset,
  1026. struct nx_host_sds_ring *sds_ring)
  1027. {
  1028. struct net_device *netdev = adapter->netdev;
  1029. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1030. struct netxen_rx_buffer *buffer;
  1031. struct sk_buff *skb;
  1032. struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
  1033. if (unlikely(index > rds_ring->num_desc))
  1034. return NULL;
  1035. buffer = &rds_ring->rx_buf_arr[index];
  1036. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1037. if (!skb)
  1038. return buffer;
  1039. if (length > rds_ring->skb_size)
  1040. skb_put(skb, rds_ring->skb_size);
  1041. else
  1042. skb_put(skb, length);
  1043. if (pkt_offset)
  1044. skb_pull(skb, pkt_offset);
  1045. skb->protocol = eth_type_trans(skb, netdev);
  1046. napi_gro_receive(&sds_ring->napi, skb);
  1047. adapter->stats.no_rcv++;
  1048. adapter->stats.rxbytes += length;
  1049. return buffer;
  1050. }
  1051. #define netxen_merge_rx_buffers(list, head) \
  1052. do { list_splice_tail_init(list, head); } while (0);
  1053. int
  1054. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1055. {
  1056. struct netxen_adapter *adapter = sds_ring->adapter;
  1057. struct list_head *cur;
  1058. struct status_desc *desc;
  1059. struct netxen_rx_buffer *rxbuf;
  1060. u32 consumer = sds_ring->consumer;
  1061. int count = 0;
  1062. u64 sts_data;
  1063. int opcode, ring, index, length, cksum, pkt_offset, desc_cnt;
  1064. while (count < max) {
  1065. desc = &sds_ring->desc_head[consumer];
  1066. sts_data = le64_to_cpu(desc->status_desc_data[0]);
  1067. if (!(sts_data & STATUS_OWNER_HOST))
  1068. break;
  1069. desc_cnt = netxen_get_sts_desc_cnt(sts_data);
  1070. ring = netxen_get_sts_type(sts_data);
  1071. if (ring > RCV_RING_JUMBO)
  1072. goto skip;
  1073. opcode = netxen_get_sts_opcode(sts_data);
  1074. switch (opcode) {
  1075. case NETXEN_NIC_RXPKT_DESC:
  1076. case NETXEN_OLD_RXPKT_DESC:
  1077. break;
  1078. case NETXEN_NIC_RESPONSE_DESC:
  1079. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1080. default:
  1081. goto skip;
  1082. }
  1083. WARN_ON(desc_cnt > 1);
  1084. index = netxen_get_sts_refhandle(sts_data);
  1085. length = netxen_get_sts_totallength(sts_data);
  1086. cksum = netxen_get_sts_status(sts_data);
  1087. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1088. rxbuf = netxen_process_rcv(adapter, ring, index,
  1089. length, cksum, pkt_offset, sds_ring);
  1090. if (rxbuf)
  1091. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1092. skip:
  1093. for (; desc_cnt > 0; desc_cnt--) {
  1094. desc = &sds_ring->desc_head[consumer];
  1095. desc->status_desc_data[0] =
  1096. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1097. consumer = get_next_index(consumer, sds_ring->num_desc);
  1098. }
  1099. count++;
  1100. }
  1101. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1102. struct nx_host_rds_ring *rds_ring =
  1103. &adapter->recv_ctx.rds_rings[ring];
  1104. if (!list_empty(&sds_ring->free_list[ring])) {
  1105. list_for_each(cur, &sds_ring->free_list[ring]) {
  1106. rxbuf = list_entry(cur,
  1107. struct netxen_rx_buffer, list);
  1108. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1109. }
  1110. spin_lock(&rds_ring->lock);
  1111. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1112. &rds_ring->free_list);
  1113. spin_unlock(&rds_ring->lock);
  1114. }
  1115. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1116. }
  1117. if (count) {
  1118. sds_ring->consumer = consumer;
  1119. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1120. }
  1121. return count;
  1122. }
  1123. /* Process Command status ring */
  1124. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1125. {
  1126. u32 sw_consumer, hw_consumer;
  1127. int count = 0, i;
  1128. struct netxen_cmd_buffer *buffer;
  1129. struct pci_dev *pdev = adapter->pdev;
  1130. struct net_device *netdev = adapter->netdev;
  1131. struct netxen_skb_frag *frag;
  1132. int done = 0;
  1133. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1134. if (!spin_trylock(&adapter->tx_clean_lock))
  1135. return 1;
  1136. sw_consumer = tx_ring->sw_consumer;
  1137. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1138. while (sw_consumer != hw_consumer) {
  1139. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1140. if (buffer->skb) {
  1141. frag = &buffer->frag_array[0];
  1142. pci_unmap_single(pdev, frag->dma, frag->length,
  1143. PCI_DMA_TODEVICE);
  1144. frag->dma = 0ULL;
  1145. for (i = 1; i < buffer->frag_count; i++) {
  1146. frag++; /* Get the next frag */
  1147. pci_unmap_page(pdev, frag->dma, frag->length,
  1148. PCI_DMA_TODEVICE);
  1149. frag->dma = 0ULL;
  1150. }
  1151. adapter->stats.xmitfinished++;
  1152. dev_kfree_skb_any(buffer->skb);
  1153. buffer->skb = NULL;
  1154. }
  1155. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1156. if (++count >= MAX_STATUS_HANDLE)
  1157. break;
  1158. }
  1159. if (count && netif_running(netdev)) {
  1160. tx_ring->sw_consumer = sw_consumer;
  1161. smp_mb();
  1162. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1163. netif_tx_lock(netdev);
  1164. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1165. netif_wake_queue(netdev);
  1166. netif_tx_unlock(netdev);
  1167. }
  1168. }
  1169. /*
  1170. * If everything is freed up to consumer then check if the ring is full
  1171. * If the ring is full then check if more needs to be freed and
  1172. * schedule the call back again.
  1173. *
  1174. * This happens when there are 2 CPUs. One could be freeing and the
  1175. * other filling it. If the ring is full when we get out of here and
  1176. * the card has already interrupted the host then the host can miss the
  1177. * interrupt.
  1178. *
  1179. * There is still a possible race condition and the host could miss an
  1180. * interrupt. The card has to take care of this.
  1181. */
  1182. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1183. done = (sw_consumer == hw_consumer);
  1184. spin_unlock(&adapter->tx_clean_lock);
  1185. return (done);
  1186. }
  1187. void
  1188. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1189. struct nx_host_rds_ring *rds_ring)
  1190. {
  1191. struct rcv_desc *pdesc;
  1192. struct netxen_rx_buffer *buffer;
  1193. int producer, count = 0;
  1194. netxen_ctx_msg msg = 0;
  1195. struct list_head *head;
  1196. producer = rds_ring->producer;
  1197. spin_lock(&rds_ring->lock);
  1198. head = &rds_ring->free_list;
  1199. while (!list_empty(head)) {
  1200. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1201. if (!buffer->skb) {
  1202. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1203. break;
  1204. }
  1205. count++;
  1206. list_del(&buffer->list);
  1207. /* make a rcv descriptor */
  1208. pdesc = &rds_ring->desc_head[producer];
  1209. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1210. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1211. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1212. producer = get_next_index(producer, rds_ring->num_desc);
  1213. }
  1214. spin_unlock(&rds_ring->lock);
  1215. if (count) {
  1216. rds_ring->producer = producer;
  1217. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1218. (producer-1) & (rds_ring->num_desc-1));
  1219. if (adapter->fw_major < 4) {
  1220. /*
  1221. * Write a doorbell msg to tell phanmon of change in
  1222. * receive ring producer
  1223. * Only for firmware version < 4.0.0
  1224. */
  1225. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1226. netxen_set_msg_privid(msg);
  1227. netxen_set_msg_count(msg,
  1228. ((producer - 1) &
  1229. (rds_ring->num_desc - 1)));
  1230. netxen_set_msg_ctxid(msg, adapter->portnum);
  1231. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1232. writel(msg,
  1233. DB_NORMALIZE(adapter,
  1234. NETXEN_RCV_PRODUCER_OFFSET));
  1235. }
  1236. }
  1237. }
  1238. static void
  1239. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1240. struct nx_host_rds_ring *rds_ring)
  1241. {
  1242. struct rcv_desc *pdesc;
  1243. struct netxen_rx_buffer *buffer;
  1244. int producer, count = 0;
  1245. struct list_head *head;
  1246. producer = rds_ring->producer;
  1247. if (!spin_trylock(&rds_ring->lock))
  1248. return;
  1249. head = &rds_ring->free_list;
  1250. while (!list_empty(head)) {
  1251. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1252. if (!buffer->skb) {
  1253. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1254. break;
  1255. }
  1256. count++;
  1257. list_del(&buffer->list);
  1258. /* make a rcv descriptor */
  1259. pdesc = &rds_ring->desc_head[producer];
  1260. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1261. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1262. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1263. producer = get_next_index(producer, rds_ring->num_desc);
  1264. }
  1265. if (count) {
  1266. rds_ring->producer = producer;
  1267. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1268. (producer - 1) & (rds_ring->num_desc - 1));
  1269. }
  1270. spin_unlock(&rds_ring->lock);
  1271. }
  1272. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1273. {
  1274. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1275. return;
  1276. }