qla_isr.c 81 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2012 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. #include "qla_target.h"
  15. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  16. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  17. struct req_que *, uint32_t);
  18. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  19. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  20. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  21. sts_entry_t *);
  22. /**
  23. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  24. * @irq:
  25. * @dev_id: SCSI driver HA context
  26. *
  27. * Called by system whenever the host adapter generates an interrupt.
  28. *
  29. * Returns handled flag.
  30. */
  31. irqreturn_t
  32. qla2100_intr_handler(int irq, void *dev_id)
  33. {
  34. scsi_qla_host_t *vha;
  35. struct qla_hw_data *ha;
  36. struct device_reg_2xxx __iomem *reg;
  37. int status;
  38. unsigned long iter;
  39. uint16_t hccr;
  40. uint16_t mb[4];
  41. struct rsp_que *rsp;
  42. unsigned long flags;
  43. rsp = (struct rsp_que *) dev_id;
  44. if (!rsp) {
  45. ql_log(ql_log_info, NULL, 0x505d,
  46. "%s: NULL response queue pointer.\n", __func__);
  47. return (IRQ_NONE);
  48. }
  49. ha = rsp->hw;
  50. reg = &ha->iobase->isp;
  51. status = 0;
  52. spin_lock_irqsave(&ha->hardware_lock, flags);
  53. vha = pci_get_drvdata(ha->pdev);
  54. for (iter = 50; iter--; ) {
  55. hccr = RD_REG_WORD(&reg->hccr);
  56. if (hccr & HCCR_RISC_PAUSE) {
  57. if (pci_channel_offline(ha->pdev))
  58. break;
  59. /*
  60. * Issue a "HARD" reset in order for the RISC interrupt
  61. * bit to be cleared. Schedule a big hammer to get
  62. * out of the RISC PAUSED state.
  63. */
  64. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  65. RD_REG_WORD(&reg->hccr);
  66. ha->isp_ops->fw_dump(vha, 1);
  67. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  68. break;
  69. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  70. break;
  71. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  72. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  73. RD_REG_WORD(&reg->hccr);
  74. /* Get mailbox data. */
  75. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  76. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  77. qla2x00_mbx_completion(vha, mb[0]);
  78. status |= MBX_INTERRUPT;
  79. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  80. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  81. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  82. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  83. qla2x00_async_event(vha, rsp, mb);
  84. } else {
  85. /*EMPTY*/
  86. ql_dbg(ql_dbg_async, vha, 0x5025,
  87. "Unrecognized interrupt type (%d).\n",
  88. mb[0]);
  89. }
  90. /* Release mailbox registers. */
  91. WRT_REG_WORD(&reg->semaphore, 0);
  92. RD_REG_WORD(&reg->semaphore);
  93. } else {
  94. qla2x00_process_response_queue(rsp);
  95. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  96. RD_REG_WORD(&reg->hccr);
  97. }
  98. }
  99. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  100. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  101. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  102. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  103. complete(&ha->mbx_intr_comp);
  104. }
  105. return (IRQ_HANDLED);
  106. }
  107. /**
  108. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  109. * @irq:
  110. * @dev_id: SCSI driver HA context
  111. *
  112. * Called by system whenever the host adapter generates an interrupt.
  113. *
  114. * Returns handled flag.
  115. */
  116. irqreturn_t
  117. qla2300_intr_handler(int irq, void *dev_id)
  118. {
  119. scsi_qla_host_t *vha;
  120. struct device_reg_2xxx __iomem *reg;
  121. int status;
  122. unsigned long iter;
  123. uint32_t stat;
  124. uint16_t hccr;
  125. uint16_t mb[4];
  126. struct rsp_que *rsp;
  127. struct qla_hw_data *ha;
  128. unsigned long flags;
  129. rsp = (struct rsp_que *) dev_id;
  130. if (!rsp) {
  131. ql_log(ql_log_info, NULL, 0x5058,
  132. "%s: NULL response queue pointer.\n", __func__);
  133. return (IRQ_NONE);
  134. }
  135. ha = rsp->hw;
  136. reg = &ha->iobase->isp;
  137. status = 0;
  138. spin_lock_irqsave(&ha->hardware_lock, flags);
  139. vha = pci_get_drvdata(ha->pdev);
  140. for (iter = 50; iter--; ) {
  141. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  142. if (stat & HSR_RISC_PAUSED) {
  143. if (unlikely(pci_channel_offline(ha->pdev)))
  144. break;
  145. hccr = RD_REG_WORD(&reg->hccr);
  146. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  147. ql_log(ql_log_warn, vha, 0x5026,
  148. "Parity error -- HCCR=%x, Dumping "
  149. "firmware.\n", hccr);
  150. else
  151. ql_log(ql_log_warn, vha, 0x5027,
  152. "RISC paused -- HCCR=%x, Dumping "
  153. "firmware.\n", hccr);
  154. /*
  155. * Issue a "HARD" reset in order for the RISC
  156. * interrupt bit to be cleared. Schedule a big
  157. * hammer to get out of the RISC PAUSED state.
  158. */
  159. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  160. RD_REG_WORD(&reg->hccr);
  161. ha->isp_ops->fw_dump(vha, 1);
  162. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  163. break;
  164. } else if ((stat & HSR_RISC_INT) == 0)
  165. break;
  166. switch (stat & 0xff) {
  167. case 0x1:
  168. case 0x2:
  169. case 0x10:
  170. case 0x11:
  171. qla2x00_mbx_completion(vha, MSW(stat));
  172. status |= MBX_INTERRUPT;
  173. /* Release mailbox registers. */
  174. WRT_REG_WORD(&reg->semaphore, 0);
  175. break;
  176. case 0x12:
  177. mb[0] = MSW(stat);
  178. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  179. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  180. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  181. qla2x00_async_event(vha, rsp, mb);
  182. break;
  183. case 0x13:
  184. qla2x00_process_response_queue(rsp);
  185. break;
  186. case 0x15:
  187. mb[0] = MBA_CMPLT_1_16BIT;
  188. mb[1] = MSW(stat);
  189. qla2x00_async_event(vha, rsp, mb);
  190. break;
  191. case 0x16:
  192. mb[0] = MBA_SCSI_COMPLETION;
  193. mb[1] = MSW(stat);
  194. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  195. qla2x00_async_event(vha, rsp, mb);
  196. break;
  197. default:
  198. ql_dbg(ql_dbg_async, vha, 0x5028,
  199. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  200. break;
  201. }
  202. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  203. RD_REG_WORD_RELAXED(&reg->hccr);
  204. }
  205. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  206. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  207. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  208. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  209. complete(&ha->mbx_intr_comp);
  210. }
  211. return (IRQ_HANDLED);
  212. }
  213. /**
  214. * qla2x00_mbx_completion() - Process mailbox command completions.
  215. * @ha: SCSI driver HA context
  216. * @mb0: Mailbox0 register
  217. */
  218. static void
  219. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  220. {
  221. uint16_t cnt;
  222. uint32_t mboxes;
  223. uint16_t __iomem *wptr;
  224. struct qla_hw_data *ha = vha->hw;
  225. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  226. /* Read all mbox registers? */
  227. mboxes = (1 << ha->mbx_count) - 1;
  228. if (!ha->mcp)
  229. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  230. else
  231. mboxes = ha->mcp->in_mb;
  232. /* Load return mailbox registers. */
  233. ha->flags.mbox_int = 1;
  234. ha->mailbox_out[0] = mb0;
  235. mboxes >>= 1;
  236. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  237. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  238. if (IS_QLA2200(ha) && cnt == 8)
  239. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  240. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  241. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  242. else if (mboxes & BIT_0)
  243. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  244. wptr++;
  245. mboxes >>= 1;
  246. }
  247. }
  248. static void
  249. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  250. {
  251. static char *event[] =
  252. { "Complete", "Request Notification", "Time Extension" };
  253. int rval;
  254. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  255. uint16_t __iomem *wptr;
  256. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  257. /* Seed data -- mailbox1 -> mailbox7. */
  258. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  259. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  260. mb[cnt] = RD_REG_WORD(wptr);
  261. ql_dbg(ql_dbg_async, vha, 0x5021,
  262. "Inter-Driver Communication %s -- "
  263. "%04x %04x %04x %04x %04x %04x %04x.\n",
  264. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  265. mb[4], mb[5], mb[6]);
  266. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  267. vha->hw->flags.idc_compl_status = 1;
  268. if (vha->hw->notify_dcbx_comp)
  269. complete(&vha->hw->dcbx_comp);
  270. }
  271. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  272. timeout = (descr >> 8) & 0xf;
  273. if (aen != MBA_IDC_NOTIFY || !timeout)
  274. return;
  275. ql_dbg(ql_dbg_async, vha, 0x5022,
  276. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  277. vha->host_no, event[aen & 0xff], timeout);
  278. rval = qla2x00_post_idc_ack_work(vha, mb);
  279. if (rval != QLA_SUCCESS)
  280. ql_log(ql_log_warn, vha, 0x5023,
  281. "IDC failed to post ACK.\n");
  282. }
  283. #define LS_UNKNOWN 2
  284. const char *
  285. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  286. {
  287. static const char * const link_speeds[] = {
  288. "1", "2", "?", "4", "8", "16", "10"
  289. };
  290. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  291. return link_speeds[0];
  292. else if (speed == 0x13)
  293. return link_speeds[6];
  294. else if (speed < 6)
  295. return link_speeds[speed];
  296. else
  297. return link_speeds[LS_UNKNOWN];
  298. }
  299. static void
  300. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  301. {
  302. struct qla_hw_data *ha = vha->hw;
  303. /*
  304. * 8200 AEN Interpretation:
  305. * mb[0] = AEN code
  306. * mb[1] = AEN Reason code
  307. * mb[2] = LSW of Peg-Halt Status-1 Register
  308. * mb[6] = MSW of Peg-Halt Status-1 Register
  309. * mb[3] = LSW of Peg-Halt Status-2 register
  310. * mb[7] = MSW of Peg-Halt Status-2 register
  311. * mb[4] = IDC Device-State Register value
  312. * mb[5] = IDC Driver-Presence Register value
  313. */
  314. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  315. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  316. mb[0], mb[1], mb[2], mb[6]);
  317. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  318. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  319. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  320. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  321. IDC_HEARTBEAT_FAILURE)) {
  322. ha->flags.nic_core_hung = 1;
  323. ql_log(ql_log_warn, vha, 0x5060,
  324. "83XX: F/W Error Reported: Check if reset required.\n");
  325. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  326. uint32_t protocol_engine_id, fw_err_code, err_level;
  327. /*
  328. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  329. * - PEG-Halt Status-1 Register:
  330. * (LSW = mb[2], MSW = mb[6])
  331. * Bits 0-7 = protocol-engine ID
  332. * Bits 8-28 = f/w error code
  333. * Bits 29-31 = Error-level
  334. * Error-level 0x1 = Non-Fatal error
  335. * Error-level 0x2 = Recoverable Fatal error
  336. * Error-level 0x4 = UnRecoverable Fatal error
  337. * - PEG-Halt Status-2 Register:
  338. * (LSW = mb[3], MSW = mb[7])
  339. */
  340. protocol_engine_id = (mb[2] & 0xff);
  341. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  342. ((mb[6] & 0x1fff) << 8));
  343. err_level = ((mb[6] & 0xe000) >> 13);
  344. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  345. "Register: protocol_engine_id=0x%x "
  346. "fw_err_code=0x%x err_level=0x%x.\n",
  347. protocol_engine_id, fw_err_code, err_level);
  348. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  349. "Register: 0x%x%x.\n", mb[7], mb[3]);
  350. if (err_level == ERR_LEVEL_NON_FATAL) {
  351. ql_log(ql_log_warn, vha, 0x5063,
  352. "Not a fatal error, f/w has recovered "
  353. "iteself.\n");
  354. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  355. ql_log(ql_log_fatal, vha, 0x5064,
  356. "Recoverable Fatal error: Chip reset "
  357. "required.\n");
  358. qla83xx_schedule_work(vha,
  359. QLA83XX_NIC_CORE_RESET);
  360. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  361. ql_log(ql_log_fatal, vha, 0x5065,
  362. "Unrecoverable Fatal error: Set FAILED "
  363. "state, reboot required.\n");
  364. qla83xx_schedule_work(vha,
  365. QLA83XX_NIC_CORE_UNRECOVERABLE);
  366. }
  367. }
  368. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  369. uint16_t peg_fw_state, nw_interface_link_up;
  370. uint16_t nw_interface_signal_detect, sfp_status;
  371. uint16_t htbt_counter, htbt_monitor_enable;
  372. uint16_t sfp_additonal_info, sfp_multirate;
  373. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  374. /*
  375. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  376. * - PEG-to-FC Status Register:
  377. * (LSW = mb[2], MSW = mb[6])
  378. * Bits 0-7 = Peg-Firmware state
  379. * Bit 8 = N/W Interface Link-up
  380. * Bit 9 = N/W Interface signal detected
  381. * Bits 10-11 = SFP Status
  382. * SFP Status 0x0 = SFP+ transceiver not expected
  383. * SFP Status 0x1 = SFP+ transceiver not present
  384. * SFP Status 0x2 = SFP+ transceiver invalid
  385. * SFP Status 0x3 = SFP+ transceiver present and
  386. * valid
  387. * Bits 12-14 = Heartbeat Counter
  388. * Bit 15 = Heartbeat Monitor Enable
  389. * Bits 16-17 = SFP Additional Info
  390. * SFP info 0x0 = Unregocnized transceiver for
  391. * Ethernet
  392. * SFP info 0x1 = SFP+ brand validation failed
  393. * SFP info 0x2 = SFP+ speed validation failed
  394. * SFP info 0x3 = SFP+ access error
  395. * Bit 18 = SFP Multirate
  396. * Bit 19 = SFP Tx Fault
  397. * Bits 20-22 = Link Speed
  398. * Bits 23-27 = Reserved
  399. * Bits 28-30 = DCBX Status
  400. * DCBX Status 0x0 = DCBX Disabled
  401. * DCBX Status 0x1 = DCBX Enabled
  402. * DCBX Status 0x2 = DCBX Exchange error
  403. * Bit 31 = Reserved
  404. */
  405. peg_fw_state = (mb[2] & 0x00ff);
  406. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  407. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  408. sfp_status = ((mb[2] & 0x0c00) >> 10);
  409. htbt_counter = ((mb[2] & 0x7000) >> 12);
  410. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  411. sfp_additonal_info = (mb[6] & 0x0003);
  412. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  413. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  414. link_speed = ((mb[6] & 0x0070) >> 4);
  415. dcbx_status = ((mb[6] & 0x7000) >> 12);
  416. ql_log(ql_log_warn, vha, 0x5066,
  417. "Peg-to-Fc Status Register:\n"
  418. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  419. "nw_interface_signal_detect=0x%x"
  420. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  421. nw_interface_link_up, nw_interface_signal_detect,
  422. sfp_status);
  423. ql_log(ql_log_warn, vha, 0x5067,
  424. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  425. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  426. htbt_counter, htbt_monitor_enable,
  427. sfp_additonal_info, sfp_multirate);
  428. ql_log(ql_log_warn, vha, 0x5068,
  429. "sfp_tx_fault=0x%x, link_state=0x%x, "
  430. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  431. dcbx_status);
  432. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  433. }
  434. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  435. ql_log(ql_log_warn, vha, 0x5069,
  436. "Heartbeat Failure encountered, chip reset "
  437. "required.\n");
  438. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  439. }
  440. }
  441. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  442. ql_log(ql_log_info, vha, 0x506a,
  443. "IDC Device-State changed = 0x%x.\n", mb[4]);
  444. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  445. }
  446. }
  447. /**
  448. * qla2x00_async_event() - Process aynchronous events.
  449. * @ha: SCSI driver HA context
  450. * @mb: Mailbox registers (0 - 3)
  451. */
  452. void
  453. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  454. {
  455. uint16_t handle_cnt;
  456. uint16_t cnt, mbx;
  457. uint32_t handles[5];
  458. struct qla_hw_data *ha = vha->hw;
  459. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  460. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  461. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  462. uint32_t rscn_entry, host_pid;
  463. unsigned long flags;
  464. /* Setup to process RIO completion. */
  465. handle_cnt = 0;
  466. if (IS_CNA_CAPABLE(ha))
  467. goto skip_rio;
  468. switch (mb[0]) {
  469. case MBA_SCSI_COMPLETION:
  470. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  471. handle_cnt = 1;
  472. break;
  473. case MBA_CMPLT_1_16BIT:
  474. handles[0] = mb[1];
  475. handle_cnt = 1;
  476. mb[0] = MBA_SCSI_COMPLETION;
  477. break;
  478. case MBA_CMPLT_2_16BIT:
  479. handles[0] = mb[1];
  480. handles[1] = mb[2];
  481. handle_cnt = 2;
  482. mb[0] = MBA_SCSI_COMPLETION;
  483. break;
  484. case MBA_CMPLT_3_16BIT:
  485. handles[0] = mb[1];
  486. handles[1] = mb[2];
  487. handles[2] = mb[3];
  488. handle_cnt = 3;
  489. mb[0] = MBA_SCSI_COMPLETION;
  490. break;
  491. case MBA_CMPLT_4_16BIT:
  492. handles[0] = mb[1];
  493. handles[1] = mb[2];
  494. handles[2] = mb[3];
  495. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  496. handle_cnt = 4;
  497. mb[0] = MBA_SCSI_COMPLETION;
  498. break;
  499. case MBA_CMPLT_5_16BIT:
  500. handles[0] = mb[1];
  501. handles[1] = mb[2];
  502. handles[2] = mb[3];
  503. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  504. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  505. handle_cnt = 5;
  506. mb[0] = MBA_SCSI_COMPLETION;
  507. break;
  508. case MBA_CMPLT_2_32BIT:
  509. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  510. handles[1] = le32_to_cpu(
  511. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  512. RD_MAILBOX_REG(ha, reg, 6));
  513. handle_cnt = 2;
  514. mb[0] = MBA_SCSI_COMPLETION;
  515. break;
  516. default:
  517. break;
  518. }
  519. skip_rio:
  520. switch (mb[0]) {
  521. case MBA_SCSI_COMPLETION: /* Fast Post */
  522. if (!vha->flags.online)
  523. break;
  524. for (cnt = 0; cnt < handle_cnt; cnt++)
  525. qla2x00_process_completed_request(vha, rsp->req,
  526. handles[cnt]);
  527. break;
  528. case MBA_RESET: /* Reset */
  529. ql_dbg(ql_dbg_async, vha, 0x5002,
  530. "Asynchronous RESET.\n");
  531. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  532. break;
  533. case MBA_SYSTEM_ERR: /* System Error */
  534. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  535. RD_REG_WORD(&reg24->mailbox7) : 0;
  536. ql_log(ql_log_warn, vha, 0x5003,
  537. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  538. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  539. ha->isp_ops->fw_dump(vha, 1);
  540. if (IS_FWI2_CAPABLE(ha)) {
  541. if (mb[1] == 0 && mb[2] == 0) {
  542. ql_log(ql_log_fatal, vha, 0x5004,
  543. "Unrecoverable Hardware Error: adapter "
  544. "marked OFFLINE!\n");
  545. vha->flags.online = 0;
  546. vha->device_flags |= DFLG_DEV_FAILED;
  547. } else {
  548. /* Check to see if MPI timeout occurred */
  549. if ((mbx & MBX_3) && (ha->flags.port0))
  550. set_bit(MPI_RESET_NEEDED,
  551. &vha->dpc_flags);
  552. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  553. }
  554. } else if (mb[1] == 0) {
  555. ql_log(ql_log_fatal, vha, 0x5005,
  556. "Unrecoverable Hardware Error: adapter marked "
  557. "OFFLINE!\n");
  558. vha->flags.online = 0;
  559. vha->device_flags |= DFLG_DEV_FAILED;
  560. } else
  561. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  562. break;
  563. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  564. ql_log(ql_log_warn, vha, 0x5006,
  565. "ISP Request Transfer Error (%x).\n", mb[1]);
  566. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  567. break;
  568. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  569. ql_log(ql_log_warn, vha, 0x5007,
  570. "ISP Response Transfer Error.\n");
  571. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  572. break;
  573. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  574. ql_dbg(ql_dbg_async, vha, 0x5008,
  575. "Asynchronous WAKEUP_THRES.\n");
  576. break;
  577. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  578. ql_dbg(ql_dbg_async, vha, 0x5009,
  579. "LIP occurred (%x).\n", mb[1]);
  580. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  581. atomic_set(&vha->loop_state, LOOP_DOWN);
  582. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  583. qla2x00_mark_all_devices_lost(vha, 1);
  584. }
  585. if (vha->vp_idx) {
  586. atomic_set(&vha->vp_state, VP_FAILED);
  587. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  588. }
  589. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  590. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  591. vha->flags.management_server_logged_in = 0;
  592. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  593. break;
  594. case MBA_LOOP_UP: /* Loop Up Event */
  595. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  596. ha->link_data_rate = PORT_SPEED_1GB;
  597. else
  598. ha->link_data_rate = mb[1];
  599. ql_dbg(ql_dbg_async, vha, 0x500a,
  600. "LOOP UP detected (%s Gbps).\n",
  601. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  602. vha->flags.management_server_logged_in = 0;
  603. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  604. break;
  605. case MBA_LOOP_DOWN: /* Loop Down Event */
  606. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  607. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  608. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  609. ql_dbg(ql_dbg_async, vha, 0x500b,
  610. "LOOP DOWN detected (%x %x %x %x).\n",
  611. mb[1], mb[2], mb[3], mbx);
  612. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  613. atomic_set(&vha->loop_state, LOOP_DOWN);
  614. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  615. vha->device_flags |= DFLG_NO_CABLE;
  616. qla2x00_mark_all_devices_lost(vha, 1);
  617. }
  618. if (vha->vp_idx) {
  619. atomic_set(&vha->vp_state, VP_FAILED);
  620. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  621. }
  622. vha->flags.management_server_logged_in = 0;
  623. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  624. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  625. break;
  626. case MBA_LIP_RESET: /* LIP reset occurred */
  627. ql_dbg(ql_dbg_async, vha, 0x500c,
  628. "LIP reset occurred (%x).\n", mb[1]);
  629. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  630. atomic_set(&vha->loop_state, LOOP_DOWN);
  631. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  632. qla2x00_mark_all_devices_lost(vha, 1);
  633. }
  634. if (vha->vp_idx) {
  635. atomic_set(&vha->vp_state, VP_FAILED);
  636. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  637. }
  638. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  639. ha->operating_mode = LOOP;
  640. vha->flags.management_server_logged_in = 0;
  641. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  642. break;
  643. /* case MBA_DCBX_COMPLETE: */
  644. case MBA_POINT_TO_POINT: /* Point-to-Point */
  645. if (IS_QLA2100(ha))
  646. break;
  647. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  648. ql_dbg(ql_dbg_async, vha, 0x500d,
  649. "DCBX Completed -- %04x %04x %04x.\n",
  650. mb[1], mb[2], mb[3]);
  651. if (ha->notify_dcbx_comp)
  652. complete(&ha->dcbx_comp);
  653. } else
  654. ql_dbg(ql_dbg_async, vha, 0x500e,
  655. "Asynchronous P2P MODE received.\n");
  656. /*
  657. * Until there's a transition from loop down to loop up, treat
  658. * this as loop down only.
  659. */
  660. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  661. atomic_set(&vha->loop_state, LOOP_DOWN);
  662. if (!atomic_read(&vha->loop_down_timer))
  663. atomic_set(&vha->loop_down_timer,
  664. LOOP_DOWN_TIME);
  665. qla2x00_mark_all_devices_lost(vha, 1);
  666. }
  667. if (vha->vp_idx) {
  668. atomic_set(&vha->vp_state, VP_FAILED);
  669. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  670. }
  671. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  672. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  673. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  674. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  675. ha->flags.gpsc_supported = 1;
  676. vha->flags.management_server_logged_in = 0;
  677. break;
  678. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  679. if (IS_QLA2100(ha))
  680. break;
  681. ql_dbg(ql_dbg_async, vha, 0x500f,
  682. "Configuration change detected: value=%x.\n", mb[1]);
  683. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  684. atomic_set(&vha->loop_state, LOOP_DOWN);
  685. if (!atomic_read(&vha->loop_down_timer))
  686. atomic_set(&vha->loop_down_timer,
  687. LOOP_DOWN_TIME);
  688. qla2x00_mark_all_devices_lost(vha, 1);
  689. }
  690. if (vha->vp_idx) {
  691. atomic_set(&vha->vp_state, VP_FAILED);
  692. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  693. }
  694. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  695. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  696. break;
  697. case MBA_PORT_UPDATE: /* Port database update */
  698. /*
  699. * Handle only global and vn-port update events
  700. *
  701. * Relevant inputs:
  702. * mb[1] = N_Port handle of changed port
  703. * OR 0xffff for global event
  704. * mb[2] = New login state
  705. * 7 = Port logged out
  706. * mb[3] = LSB is vp_idx, 0xff = all vps
  707. *
  708. * Skip processing if:
  709. * Event is global, vp_idx is NOT all vps,
  710. * vp_idx does not match
  711. * Event is not global, vp_idx does not match
  712. */
  713. if (IS_QLA2XXX_MIDTYPE(ha) &&
  714. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  715. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  716. break;
  717. /* Global event -- port logout or port unavailable. */
  718. if (mb[1] == 0xffff && mb[2] == 0x7) {
  719. ql_dbg(ql_dbg_async, vha, 0x5010,
  720. "Port unavailable %04x %04x %04x.\n",
  721. mb[1], mb[2], mb[3]);
  722. ql_log(ql_log_warn, vha, 0x505e,
  723. "Link is offline.\n");
  724. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  725. atomic_set(&vha->loop_state, LOOP_DOWN);
  726. atomic_set(&vha->loop_down_timer,
  727. LOOP_DOWN_TIME);
  728. vha->device_flags |= DFLG_NO_CABLE;
  729. qla2x00_mark_all_devices_lost(vha, 1);
  730. }
  731. if (vha->vp_idx) {
  732. atomic_set(&vha->vp_state, VP_FAILED);
  733. fc_vport_set_state(vha->fc_vport,
  734. FC_VPORT_FAILED);
  735. qla2x00_mark_all_devices_lost(vha, 1);
  736. }
  737. vha->flags.management_server_logged_in = 0;
  738. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  739. break;
  740. }
  741. /*
  742. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  743. * event etc. earlier indicating loop is down) then process
  744. * it. Otherwise ignore it and Wait for RSCN to come in.
  745. */
  746. atomic_set(&vha->loop_down_timer, 0);
  747. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  748. ql_dbg(ql_dbg_async, vha, 0x5011,
  749. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  750. mb[1], mb[2], mb[3]);
  751. qlt_async_event(mb[0], vha, mb);
  752. break;
  753. }
  754. ql_dbg(ql_dbg_async, vha, 0x5012,
  755. "Port database changed %04x %04x %04x.\n",
  756. mb[1], mb[2], mb[3]);
  757. ql_log(ql_log_warn, vha, 0x505f,
  758. "Link is operational (%s Gbps).\n",
  759. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  760. /*
  761. * Mark all devices as missing so we will login again.
  762. */
  763. atomic_set(&vha->loop_state, LOOP_UP);
  764. qla2x00_mark_all_devices_lost(vha, 1);
  765. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  766. set_bit(SCR_PENDING, &vha->dpc_flags);
  767. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  768. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  769. qlt_async_event(mb[0], vha, mb);
  770. break;
  771. case MBA_RSCN_UPDATE: /* State Change Registration */
  772. /* Check if the Vport has issued a SCR */
  773. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  774. break;
  775. /* Only handle SCNs for our Vport index. */
  776. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  777. break;
  778. ql_dbg(ql_dbg_async, vha, 0x5013,
  779. "RSCN database changed -- %04x %04x %04x.\n",
  780. mb[1], mb[2], mb[3]);
  781. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  782. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  783. | vha->d_id.b.al_pa;
  784. if (rscn_entry == host_pid) {
  785. ql_dbg(ql_dbg_async, vha, 0x5014,
  786. "Ignoring RSCN update to local host "
  787. "port ID (%06x).\n", host_pid);
  788. break;
  789. }
  790. /* Ignore reserved bits from RSCN-payload. */
  791. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  792. atomic_set(&vha->loop_down_timer, 0);
  793. vha->flags.management_server_logged_in = 0;
  794. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  795. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  796. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  797. break;
  798. /* case MBA_RIO_RESPONSE: */
  799. case MBA_ZIO_RESPONSE:
  800. ql_dbg(ql_dbg_async, vha, 0x5015,
  801. "[R|Z]IO update completion.\n");
  802. if (IS_FWI2_CAPABLE(ha))
  803. qla24xx_process_response_queue(vha, rsp);
  804. else
  805. qla2x00_process_response_queue(rsp);
  806. break;
  807. case MBA_DISCARD_RND_FRAME:
  808. ql_dbg(ql_dbg_async, vha, 0x5016,
  809. "Discard RND Frame -- %04x %04x %04x.\n",
  810. mb[1], mb[2], mb[3]);
  811. break;
  812. case MBA_TRACE_NOTIFICATION:
  813. ql_dbg(ql_dbg_async, vha, 0x5017,
  814. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  815. break;
  816. case MBA_ISP84XX_ALERT:
  817. ql_dbg(ql_dbg_async, vha, 0x5018,
  818. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  819. mb[1], mb[2], mb[3]);
  820. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  821. switch (mb[1]) {
  822. case A84_PANIC_RECOVERY:
  823. ql_log(ql_log_info, vha, 0x5019,
  824. "Alert 84XX: panic recovery %04x %04x.\n",
  825. mb[2], mb[3]);
  826. break;
  827. case A84_OP_LOGIN_COMPLETE:
  828. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  829. ql_log(ql_log_info, vha, 0x501a,
  830. "Alert 84XX: firmware version %x.\n",
  831. ha->cs84xx->op_fw_version);
  832. break;
  833. case A84_DIAG_LOGIN_COMPLETE:
  834. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  835. ql_log(ql_log_info, vha, 0x501b,
  836. "Alert 84XX: diagnostic firmware version %x.\n",
  837. ha->cs84xx->diag_fw_version);
  838. break;
  839. case A84_GOLD_LOGIN_COMPLETE:
  840. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  841. ha->cs84xx->fw_update = 1;
  842. ql_log(ql_log_info, vha, 0x501c,
  843. "Alert 84XX: gold firmware version %x.\n",
  844. ha->cs84xx->gold_fw_version);
  845. break;
  846. default:
  847. ql_log(ql_log_warn, vha, 0x501d,
  848. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  849. mb[1], mb[2], mb[3]);
  850. }
  851. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  852. break;
  853. case MBA_DCBX_START:
  854. ql_dbg(ql_dbg_async, vha, 0x501e,
  855. "DCBX Started -- %04x %04x %04x.\n",
  856. mb[1], mb[2], mb[3]);
  857. break;
  858. case MBA_DCBX_PARAM_UPDATE:
  859. ql_dbg(ql_dbg_async, vha, 0x501f,
  860. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  861. mb[1], mb[2], mb[3]);
  862. break;
  863. case MBA_FCF_CONF_ERR:
  864. ql_dbg(ql_dbg_async, vha, 0x5020,
  865. "FCF Configuration Error -- %04x %04x %04x.\n",
  866. mb[1], mb[2], mb[3]);
  867. break;
  868. case MBA_IDC_NOTIFY:
  869. if (IS_QLA8031(vha->hw)) {
  870. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  871. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  872. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  873. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  874. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  875. /*
  876. * Extend loop down timer since port is active.
  877. */
  878. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  879. atomic_set(&vha->loop_down_timer,
  880. LOOP_DOWN_TIME);
  881. qla2xxx_wake_dpc(vha);
  882. }
  883. }
  884. case MBA_IDC_COMPLETE:
  885. case MBA_IDC_TIME_EXT:
  886. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  887. qla81xx_idc_event(vha, mb[0], mb[1]);
  888. break;
  889. case MBA_IDC_AEN:
  890. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  891. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  892. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  893. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  894. qla83xx_handle_8200_aen(vha, mb);
  895. break;
  896. default:
  897. ql_dbg(ql_dbg_async, vha, 0x5057,
  898. "Unknown AEN:%04x %04x %04x %04x\n",
  899. mb[0], mb[1], mb[2], mb[3]);
  900. }
  901. qlt_async_event(mb[0], vha, mb);
  902. if (!vha->vp_idx && ha->num_vhosts)
  903. qla2x00_alert_all_vps(rsp, mb);
  904. }
  905. /**
  906. * qla2x00_process_completed_request() - Process a Fast Post response.
  907. * @ha: SCSI driver HA context
  908. * @index: SRB index
  909. */
  910. static void
  911. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  912. struct req_que *req, uint32_t index)
  913. {
  914. srb_t *sp;
  915. struct qla_hw_data *ha = vha->hw;
  916. /* Validate handle. */
  917. if (index >= req->num_outstanding_cmds) {
  918. ql_log(ql_log_warn, vha, 0x3014,
  919. "Invalid SCSI command index (%x).\n", index);
  920. if (IS_QLA82XX(ha))
  921. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  922. else
  923. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  924. return;
  925. }
  926. sp = req->outstanding_cmds[index];
  927. if (sp) {
  928. /* Free outstanding command slot. */
  929. req->outstanding_cmds[index] = NULL;
  930. /* Save ISP completion status */
  931. sp->done(ha, sp, DID_OK << 16);
  932. } else {
  933. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  934. if (IS_QLA82XX(ha))
  935. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  936. else
  937. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  938. }
  939. }
  940. static srb_t *
  941. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  942. struct req_que *req, void *iocb)
  943. {
  944. struct qla_hw_data *ha = vha->hw;
  945. sts_entry_t *pkt = iocb;
  946. srb_t *sp = NULL;
  947. uint16_t index;
  948. index = LSW(pkt->handle);
  949. if (index >= req->num_outstanding_cmds) {
  950. ql_log(ql_log_warn, vha, 0x5031,
  951. "Invalid command index (%x).\n", index);
  952. if (IS_QLA82XX(ha))
  953. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  954. else
  955. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  956. goto done;
  957. }
  958. sp = req->outstanding_cmds[index];
  959. if (!sp) {
  960. ql_log(ql_log_warn, vha, 0x5032,
  961. "Invalid completion handle (%x) -- timed-out.\n", index);
  962. return sp;
  963. }
  964. if (sp->handle != index) {
  965. ql_log(ql_log_warn, vha, 0x5033,
  966. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  967. return NULL;
  968. }
  969. req->outstanding_cmds[index] = NULL;
  970. done:
  971. return sp;
  972. }
  973. static void
  974. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  975. struct mbx_entry *mbx)
  976. {
  977. const char func[] = "MBX-IOCB";
  978. const char *type;
  979. fc_port_t *fcport;
  980. srb_t *sp;
  981. struct srb_iocb *lio;
  982. uint16_t *data;
  983. uint16_t status;
  984. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  985. if (!sp)
  986. return;
  987. lio = &sp->u.iocb_cmd;
  988. type = sp->name;
  989. fcport = sp->fcport;
  990. data = lio->u.logio.data;
  991. data[0] = MBS_COMMAND_ERROR;
  992. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  993. QLA_LOGIO_LOGIN_RETRIED : 0;
  994. if (mbx->entry_status) {
  995. ql_dbg(ql_dbg_async, vha, 0x5043,
  996. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  997. "entry-status=%x status=%x state-flag=%x "
  998. "status-flags=%x.\n", type, sp->handle,
  999. fcport->d_id.b.domain, fcport->d_id.b.area,
  1000. fcport->d_id.b.al_pa, mbx->entry_status,
  1001. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1002. le16_to_cpu(mbx->status_flags));
  1003. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1004. (uint8_t *)mbx, sizeof(*mbx));
  1005. goto logio_done;
  1006. }
  1007. status = le16_to_cpu(mbx->status);
  1008. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1009. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1010. status = 0;
  1011. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1012. ql_dbg(ql_dbg_async, vha, 0x5045,
  1013. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1014. type, sp->handle, fcport->d_id.b.domain,
  1015. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1016. le16_to_cpu(mbx->mb1));
  1017. data[0] = MBS_COMMAND_COMPLETE;
  1018. if (sp->type == SRB_LOGIN_CMD) {
  1019. fcport->port_type = FCT_TARGET;
  1020. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1021. fcport->port_type = FCT_INITIATOR;
  1022. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1023. fcport->flags |= FCF_FCP2_DEVICE;
  1024. }
  1025. goto logio_done;
  1026. }
  1027. data[0] = le16_to_cpu(mbx->mb0);
  1028. switch (data[0]) {
  1029. case MBS_PORT_ID_USED:
  1030. data[1] = le16_to_cpu(mbx->mb1);
  1031. break;
  1032. case MBS_LOOP_ID_USED:
  1033. break;
  1034. default:
  1035. data[0] = MBS_COMMAND_ERROR;
  1036. break;
  1037. }
  1038. ql_log(ql_log_warn, vha, 0x5046,
  1039. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1040. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1041. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1042. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1043. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1044. le16_to_cpu(mbx->mb7));
  1045. logio_done:
  1046. sp->done(vha, sp, 0);
  1047. }
  1048. static void
  1049. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1050. sts_entry_t *pkt, int iocb_type)
  1051. {
  1052. const char func[] = "CT_IOCB";
  1053. const char *type;
  1054. srb_t *sp;
  1055. struct fc_bsg_job *bsg_job;
  1056. uint16_t comp_status;
  1057. int res;
  1058. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1059. if (!sp)
  1060. return;
  1061. bsg_job = sp->u.bsg_job;
  1062. type = "ct pass-through";
  1063. comp_status = le16_to_cpu(pkt->comp_status);
  1064. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1065. * fc payload to the caller
  1066. */
  1067. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1068. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1069. if (comp_status != CS_COMPLETE) {
  1070. if (comp_status == CS_DATA_UNDERRUN) {
  1071. res = DID_OK << 16;
  1072. bsg_job->reply->reply_payload_rcv_len =
  1073. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1074. ql_log(ql_log_warn, vha, 0x5048,
  1075. "CT pass-through-%s error "
  1076. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1077. type, comp_status,
  1078. bsg_job->reply->reply_payload_rcv_len);
  1079. } else {
  1080. ql_log(ql_log_warn, vha, 0x5049,
  1081. "CT pass-through-%s error "
  1082. "comp_status-status=0x%x.\n", type, comp_status);
  1083. res = DID_ERROR << 16;
  1084. bsg_job->reply->reply_payload_rcv_len = 0;
  1085. }
  1086. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1087. (uint8_t *)pkt, sizeof(*pkt));
  1088. } else {
  1089. res = DID_OK << 16;
  1090. bsg_job->reply->reply_payload_rcv_len =
  1091. bsg_job->reply_payload.payload_len;
  1092. bsg_job->reply_len = 0;
  1093. }
  1094. sp->done(vha, sp, res);
  1095. }
  1096. static void
  1097. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1098. struct sts_entry_24xx *pkt, int iocb_type)
  1099. {
  1100. const char func[] = "ELS_CT_IOCB";
  1101. const char *type;
  1102. srb_t *sp;
  1103. struct fc_bsg_job *bsg_job;
  1104. uint16_t comp_status;
  1105. uint32_t fw_status[3];
  1106. uint8_t* fw_sts_ptr;
  1107. int res;
  1108. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1109. if (!sp)
  1110. return;
  1111. bsg_job = sp->u.bsg_job;
  1112. type = NULL;
  1113. switch (sp->type) {
  1114. case SRB_ELS_CMD_RPT:
  1115. case SRB_ELS_CMD_HST:
  1116. type = "els";
  1117. break;
  1118. case SRB_CT_CMD:
  1119. type = "ct pass-through";
  1120. break;
  1121. default:
  1122. ql_dbg(ql_dbg_user, vha, 0x503e,
  1123. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1124. return;
  1125. }
  1126. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1127. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1128. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1129. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1130. * fc payload to the caller
  1131. */
  1132. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1133. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1134. if (comp_status != CS_COMPLETE) {
  1135. if (comp_status == CS_DATA_UNDERRUN) {
  1136. res = DID_OK << 16;
  1137. bsg_job->reply->reply_payload_rcv_len =
  1138. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1139. ql_dbg(ql_dbg_user, vha, 0x503f,
  1140. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1141. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1142. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1143. le16_to_cpu(((struct els_sts_entry_24xx *)
  1144. pkt)->total_byte_count));
  1145. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1146. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1147. }
  1148. else {
  1149. ql_dbg(ql_dbg_user, vha, 0x5040,
  1150. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1151. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1152. type, sp->handle, comp_status,
  1153. le16_to_cpu(((struct els_sts_entry_24xx *)
  1154. pkt)->error_subcode_1),
  1155. le16_to_cpu(((struct els_sts_entry_24xx *)
  1156. pkt)->error_subcode_2));
  1157. res = DID_ERROR << 16;
  1158. bsg_job->reply->reply_payload_rcv_len = 0;
  1159. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1160. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1161. }
  1162. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1163. (uint8_t *)pkt, sizeof(*pkt));
  1164. }
  1165. else {
  1166. res = DID_OK << 16;
  1167. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1168. bsg_job->reply_len = 0;
  1169. }
  1170. sp->done(vha, sp, res);
  1171. }
  1172. static void
  1173. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1174. struct logio_entry_24xx *logio)
  1175. {
  1176. const char func[] = "LOGIO-IOCB";
  1177. const char *type;
  1178. fc_port_t *fcport;
  1179. srb_t *sp;
  1180. struct srb_iocb *lio;
  1181. uint16_t *data;
  1182. uint32_t iop[2];
  1183. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1184. if (!sp)
  1185. return;
  1186. lio = &sp->u.iocb_cmd;
  1187. type = sp->name;
  1188. fcport = sp->fcport;
  1189. data = lio->u.logio.data;
  1190. data[0] = MBS_COMMAND_ERROR;
  1191. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1192. QLA_LOGIO_LOGIN_RETRIED : 0;
  1193. if (logio->entry_status) {
  1194. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1195. "Async-%s error entry - hdl=%x"
  1196. "portid=%02x%02x%02x entry-status=%x.\n",
  1197. type, sp->handle, fcport->d_id.b.domain,
  1198. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1199. logio->entry_status);
  1200. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1201. (uint8_t *)logio, sizeof(*logio));
  1202. goto logio_done;
  1203. }
  1204. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1205. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1206. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1207. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1208. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1209. le32_to_cpu(logio->io_parameter[0]));
  1210. data[0] = MBS_COMMAND_COMPLETE;
  1211. if (sp->type != SRB_LOGIN_CMD)
  1212. goto logio_done;
  1213. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1214. if (iop[0] & BIT_4) {
  1215. fcport->port_type = FCT_TARGET;
  1216. if (iop[0] & BIT_8)
  1217. fcport->flags |= FCF_FCP2_DEVICE;
  1218. } else if (iop[0] & BIT_5)
  1219. fcport->port_type = FCT_INITIATOR;
  1220. if (iop[0] & BIT_7)
  1221. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1222. if (logio->io_parameter[7] || logio->io_parameter[8])
  1223. fcport->supported_classes |= FC_COS_CLASS2;
  1224. if (logio->io_parameter[9] || logio->io_parameter[10])
  1225. fcport->supported_classes |= FC_COS_CLASS3;
  1226. goto logio_done;
  1227. }
  1228. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1229. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1230. switch (iop[0]) {
  1231. case LSC_SCODE_PORTID_USED:
  1232. data[0] = MBS_PORT_ID_USED;
  1233. data[1] = LSW(iop[1]);
  1234. break;
  1235. case LSC_SCODE_NPORT_USED:
  1236. data[0] = MBS_LOOP_ID_USED;
  1237. break;
  1238. default:
  1239. data[0] = MBS_COMMAND_ERROR;
  1240. break;
  1241. }
  1242. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1243. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1244. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1245. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1246. le16_to_cpu(logio->comp_status),
  1247. le32_to_cpu(logio->io_parameter[0]),
  1248. le32_to_cpu(logio->io_parameter[1]));
  1249. logio_done:
  1250. sp->done(vha, sp, 0);
  1251. }
  1252. static void
  1253. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1254. struct tsk_mgmt_entry *tsk)
  1255. {
  1256. const char func[] = "TMF-IOCB";
  1257. const char *type;
  1258. fc_port_t *fcport;
  1259. srb_t *sp;
  1260. struct srb_iocb *iocb;
  1261. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1262. int error = 1;
  1263. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1264. if (!sp)
  1265. return;
  1266. iocb = &sp->u.iocb_cmd;
  1267. type = sp->name;
  1268. fcport = sp->fcport;
  1269. if (sts->entry_status) {
  1270. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1271. "Async-%s error - hdl=%x entry-status(%x).\n",
  1272. type, sp->handle, sts->entry_status);
  1273. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1274. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1275. "Async-%s error - hdl=%x completion status(%x).\n",
  1276. type, sp->handle, sts->comp_status);
  1277. } else if (!(le16_to_cpu(sts->scsi_status) &
  1278. SS_RESPONSE_INFO_LEN_VALID)) {
  1279. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1280. "Async-%s error - hdl=%x no response info(%x).\n",
  1281. type, sp->handle, sts->scsi_status);
  1282. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1283. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1284. "Async-%s error - hdl=%x not enough response(%d).\n",
  1285. type, sp->handle, sts->rsp_data_len);
  1286. } else if (sts->data[3]) {
  1287. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1288. "Async-%s error - hdl=%x response(%x).\n",
  1289. type, sp->handle, sts->data[3]);
  1290. } else {
  1291. error = 0;
  1292. }
  1293. if (error) {
  1294. iocb->u.tmf.data = error;
  1295. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1296. (uint8_t *)sts, sizeof(*sts));
  1297. }
  1298. sp->done(vha, sp, 0);
  1299. }
  1300. /**
  1301. * qla2x00_process_response_queue() - Process response queue entries.
  1302. * @ha: SCSI driver HA context
  1303. */
  1304. void
  1305. qla2x00_process_response_queue(struct rsp_que *rsp)
  1306. {
  1307. struct scsi_qla_host *vha;
  1308. struct qla_hw_data *ha = rsp->hw;
  1309. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1310. sts_entry_t *pkt;
  1311. uint16_t handle_cnt;
  1312. uint16_t cnt;
  1313. vha = pci_get_drvdata(ha->pdev);
  1314. if (!vha->flags.online)
  1315. return;
  1316. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1317. pkt = (sts_entry_t *)rsp->ring_ptr;
  1318. rsp->ring_index++;
  1319. if (rsp->ring_index == rsp->length) {
  1320. rsp->ring_index = 0;
  1321. rsp->ring_ptr = rsp->ring;
  1322. } else {
  1323. rsp->ring_ptr++;
  1324. }
  1325. if (pkt->entry_status != 0) {
  1326. qla2x00_error_entry(vha, rsp, pkt);
  1327. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1328. wmb();
  1329. continue;
  1330. }
  1331. switch (pkt->entry_type) {
  1332. case STATUS_TYPE:
  1333. qla2x00_status_entry(vha, rsp, pkt);
  1334. break;
  1335. case STATUS_TYPE_21:
  1336. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1337. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1338. qla2x00_process_completed_request(vha, rsp->req,
  1339. ((sts21_entry_t *)pkt)->handle[cnt]);
  1340. }
  1341. break;
  1342. case STATUS_TYPE_22:
  1343. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1344. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1345. qla2x00_process_completed_request(vha, rsp->req,
  1346. ((sts22_entry_t *)pkt)->handle[cnt]);
  1347. }
  1348. break;
  1349. case STATUS_CONT_TYPE:
  1350. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1351. break;
  1352. case MBX_IOCB_TYPE:
  1353. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1354. (struct mbx_entry *)pkt);
  1355. break;
  1356. case CT_IOCB_TYPE:
  1357. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1358. break;
  1359. default:
  1360. /* Type Not Supported. */
  1361. ql_log(ql_log_warn, vha, 0x504a,
  1362. "Received unknown response pkt type %x "
  1363. "entry status=%x.\n",
  1364. pkt->entry_type, pkt->entry_status);
  1365. break;
  1366. }
  1367. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1368. wmb();
  1369. }
  1370. /* Adjust ring index */
  1371. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1372. }
  1373. static inline void
  1374. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1375. uint32_t sense_len, struct rsp_que *rsp, int res)
  1376. {
  1377. struct scsi_qla_host *vha = sp->fcport->vha;
  1378. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1379. uint32_t track_sense_len;
  1380. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1381. sense_len = SCSI_SENSE_BUFFERSIZE;
  1382. SET_CMD_SENSE_LEN(sp, sense_len);
  1383. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1384. track_sense_len = sense_len;
  1385. if (sense_len > par_sense_len)
  1386. sense_len = par_sense_len;
  1387. memcpy(cp->sense_buffer, sense_data, sense_len);
  1388. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1389. track_sense_len -= sense_len;
  1390. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1391. if (track_sense_len != 0) {
  1392. rsp->status_srb = sp;
  1393. cp->result = res;
  1394. }
  1395. if (sense_len) {
  1396. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1397. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1398. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1399. cp);
  1400. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1401. cp->sense_buffer, sense_len);
  1402. }
  1403. }
  1404. struct scsi_dif_tuple {
  1405. __be16 guard; /* Checksum */
  1406. __be16 app_tag; /* APPL identifier */
  1407. __be32 ref_tag; /* Target LBA or indirect LBA */
  1408. };
  1409. /*
  1410. * Checks the guard or meta-data for the type of error
  1411. * detected by the HBA. In case of errors, we set the
  1412. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1413. * to indicate to the kernel that the HBA detected error.
  1414. */
  1415. static inline int
  1416. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1417. {
  1418. struct scsi_qla_host *vha = sp->fcport->vha;
  1419. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1420. uint8_t *ap = &sts24->data[12];
  1421. uint8_t *ep = &sts24->data[20];
  1422. uint32_t e_ref_tag, a_ref_tag;
  1423. uint16_t e_app_tag, a_app_tag;
  1424. uint16_t e_guard, a_guard;
  1425. /*
  1426. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1427. * would make guard field appear at offset 2
  1428. */
  1429. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1430. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1431. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1432. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1433. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1434. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1435. ql_dbg(ql_dbg_io, vha, 0x3023,
  1436. "iocb(s) %p Returned STATUS.\n", sts24);
  1437. ql_dbg(ql_dbg_io, vha, 0x3024,
  1438. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1439. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1440. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1441. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1442. a_app_tag, e_app_tag, a_guard, e_guard);
  1443. /*
  1444. * Ignore sector if:
  1445. * For type 3: ref & app tag is all 'f's
  1446. * For type 0,1,2: app tag is all 'f's
  1447. */
  1448. if ((a_app_tag == 0xffff) &&
  1449. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1450. (a_ref_tag == 0xffffffff))) {
  1451. uint32_t blocks_done, resid;
  1452. sector_t lba_s = scsi_get_lba(cmd);
  1453. /* 2TB boundary case covered automatically with this */
  1454. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1455. resid = scsi_bufflen(cmd) - (blocks_done *
  1456. cmd->device->sector_size);
  1457. scsi_set_resid(cmd, resid);
  1458. cmd->result = DID_OK << 16;
  1459. /* Update protection tag */
  1460. if (scsi_prot_sg_count(cmd)) {
  1461. uint32_t i, j = 0, k = 0, num_ent;
  1462. struct scatterlist *sg;
  1463. struct sd_dif_tuple *spt;
  1464. /* Patch the corresponding protection tags */
  1465. scsi_for_each_prot_sg(cmd, sg,
  1466. scsi_prot_sg_count(cmd), i) {
  1467. num_ent = sg_dma_len(sg) / 8;
  1468. if (k + num_ent < blocks_done) {
  1469. k += num_ent;
  1470. continue;
  1471. }
  1472. j = blocks_done - k - 1;
  1473. k = blocks_done;
  1474. break;
  1475. }
  1476. if (k != blocks_done) {
  1477. ql_log(ql_log_warn, vha, 0x302f,
  1478. "unexpected tag values tag:lba=%x:%llx)\n",
  1479. e_ref_tag, (unsigned long long)lba_s);
  1480. return 1;
  1481. }
  1482. spt = page_address(sg_page(sg)) + sg->offset;
  1483. spt += j;
  1484. spt->app_tag = 0xffff;
  1485. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1486. spt->ref_tag = 0xffffffff;
  1487. }
  1488. return 0;
  1489. }
  1490. /* check guard */
  1491. if (e_guard != a_guard) {
  1492. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1493. 0x10, 0x1);
  1494. set_driver_byte(cmd, DRIVER_SENSE);
  1495. set_host_byte(cmd, DID_ABORT);
  1496. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1497. return 1;
  1498. }
  1499. /* check ref tag */
  1500. if (e_ref_tag != a_ref_tag) {
  1501. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1502. 0x10, 0x3);
  1503. set_driver_byte(cmd, DRIVER_SENSE);
  1504. set_host_byte(cmd, DID_ABORT);
  1505. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1506. return 1;
  1507. }
  1508. /* check appl tag */
  1509. if (e_app_tag != a_app_tag) {
  1510. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1511. 0x10, 0x2);
  1512. set_driver_byte(cmd, DRIVER_SENSE);
  1513. set_host_byte(cmd, DID_ABORT);
  1514. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1515. return 1;
  1516. }
  1517. return 1;
  1518. }
  1519. static void
  1520. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1521. struct req_que *req, uint32_t index)
  1522. {
  1523. struct qla_hw_data *ha = vha->hw;
  1524. srb_t *sp;
  1525. uint16_t comp_status;
  1526. uint16_t scsi_status;
  1527. uint16_t thread_id;
  1528. uint32_t rval = EXT_STATUS_OK;
  1529. struct fc_bsg_job *bsg_job = NULL;
  1530. sts_entry_t *sts;
  1531. struct sts_entry_24xx *sts24;
  1532. sts = (sts_entry_t *) pkt;
  1533. sts24 = (struct sts_entry_24xx *) pkt;
  1534. /* Validate handle. */
  1535. if (index >= req->num_outstanding_cmds) {
  1536. ql_log(ql_log_warn, vha, 0x70af,
  1537. "Invalid SCSI completion handle 0x%x.\n", index);
  1538. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1539. return;
  1540. }
  1541. sp = req->outstanding_cmds[index];
  1542. if (sp) {
  1543. /* Free outstanding command slot. */
  1544. req->outstanding_cmds[index] = NULL;
  1545. bsg_job = sp->u.bsg_job;
  1546. } else {
  1547. ql_log(ql_log_warn, vha, 0x70b0,
  1548. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1549. req->id, index);
  1550. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1551. return;
  1552. }
  1553. if (IS_FWI2_CAPABLE(ha)) {
  1554. comp_status = le16_to_cpu(sts24->comp_status);
  1555. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1556. } else {
  1557. comp_status = le16_to_cpu(sts->comp_status);
  1558. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1559. }
  1560. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1561. switch (comp_status) {
  1562. case CS_COMPLETE:
  1563. if (scsi_status == 0) {
  1564. bsg_job->reply->reply_payload_rcv_len =
  1565. bsg_job->reply_payload.payload_len;
  1566. rval = EXT_STATUS_OK;
  1567. }
  1568. goto done;
  1569. case CS_DATA_OVERRUN:
  1570. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1571. "Command completed with date overrun thread_id=%d\n",
  1572. thread_id);
  1573. rval = EXT_STATUS_DATA_OVERRUN;
  1574. break;
  1575. case CS_DATA_UNDERRUN:
  1576. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1577. "Command completed with date underrun thread_id=%d\n",
  1578. thread_id);
  1579. rval = EXT_STATUS_DATA_UNDERRUN;
  1580. break;
  1581. case CS_BIDIR_RD_OVERRUN:
  1582. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1583. "Command completed with read data overrun thread_id=%d\n",
  1584. thread_id);
  1585. rval = EXT_STATUS_DATA_OVERRUN;
  1586. break;
  1587. case CS_BIDIR_RD_WR_OVERRUN:
  1588. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1589. "Command completed with read and write data overrun "
  1590. "thread_id=%d\n", thread_id);
  1591. rval = EXT_STATUS_DATA_OVERRUN;
  1592. break;
  1593. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1594. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1595. "Command completed with read data over and write data "
  1596. "underrun thread_id=%d\n", thread_id);
  1597. rval = EXT_STATUS_DATA_OVERRUN;
  1598. break;
  1599. case CS_BIDIR_RD_UNDERRUN:
  1600. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1601. "Command completed with read data data underrun "
  1602. "thread_id=%d\n", thread_id);
  1603. rval = EXT_STATUS_DATA_UNDERRUN;
  1604. break;
  1605. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1606. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1607. "Command completed with read data under and write data "
  1608. "overrun thread_id=%d\n", thread_id);
  1609. rval = EXT_STATUS_DATA_UNDERRUN;
  1610. break;
  1611. case CS_BIDIR_RD_WR_UNDERRUN:
  1612. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1613. "Command completed with read and write data underrun "
  1614. "thread_id=%d\n", thread_id);
  1615. rval = EXT_STATUS_DATA_UNDERRUN;
  1616. break;
  1617. case CS_BIDIR_DMA:
  1618. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1619. "Command completed with data DMA error thread_id=%d\n",
  1620. thread_id);
  1621. rval = EXT_STATUS_DMA_ERR;
  1622. break;
  1623. case CS_TIMEOUT:
  1624. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1625. "Command completed with timeout thread_id=%d\n",
  1626. thread_id);
  1627. rval = EXT_STATUS_TIMEOUT;
  1628. break;
  1629. default:
  1630. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1631. "Command completed with completion status=0x%x "
  1632. "thread_id=%d\n", comp_status, thread_id);
  1633. rval = EXT_STATUS_ERR;
  1634. break;
  1635. }
  1636. bsg_job->reply->reply_payload_rcv_len = 0;
  1637. done:
  1638. /* Return the vendor specific reply to API */
  1639. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1640. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1641. /* Always return DID_OK, bsg will send the vendor specific response
  1642. * in this case only */
  1643. sp->done(vha, sp, (DID_OK << 6));
  1644. }
  1645. /**
  1646. * qla2x00_status_entry() - Process a Status IOCB entry.
  1647. * @ha: SCSI driver HA context
  1648. * @pkt: Entry pointer
  1649. */
  1650. static void
  1651. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1652. {
  1653. srb_t *sp;
  1654. fc_port_t *fcport;
  1655. struct scsi_cmnd *cp;
  1656. sts_entry_t *sts;
  1657. struct sts_entry_24xx *sts24;
  1658. uint16_t comp_status;
  1659. uint16_t scsi_status;
  1660. uint16_t ox_id;
  1661. uint8_t lscsi_status;
  1662. int32_t resid;
  1663. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1664. fw_resid_len;
  1665. uint8_t *rsp_info, *sense_data;
  1666. struct qla_hw_data *ha = vha->hw;
  1667. uint32_t handle;
  1668. uint16_t que;
  1669. struct req_que *req;
  1670. int logit = 1;
  1671. int res = 0;
  1672. uint16_t state_flags = 0;
  1673. sts = (sts_entry_t *) pkt;
  1674. sts24 = (struct sts_entry_24xx *) pkt;
  1675. if (IS_FWI2_CAPABLE(ha)) {
  1676. comp_status = le16_to_cpu(sts24->comp_status);
  1677. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1678. state_flags = le16_to_cpu(sts24->state_flags);
  1679. } else {
  1680. comp_status = le16_to_cpu(sts->comp_status);
  1681. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1682. }
  1683. handle = (uint32_t) LSW(sts->handle);
  1684. que = MSW(sts->handle);
  1685. req = ha->req_q_map[que];
  1686. /* Validate handle. */
  1687. if (handle < req->num_outstanding_cmds)
  1688. sp = req->outstanding_cmds[handle];
  1689. else
  1690. sp = NULL;
  1691. if (sp == NULL) {
  1692. ql_dbg(ql_dbg_io, vha, 0x3017,
  1693. "Invalid status handle (0x%x).\n", sts->handle);
  1694. if (IS_QLA82XX(ha))
  1695. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1696. else
  1697. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1698. qla2xxx_wake_dpc(vha);
  1699. return;
  1700. }
  1701. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1702. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1703. return;
  1704. }
  1705. /* Fast path completion. */
  1706. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1707. qla2x00_do_host_ramp_up(vha);
  1708. qla2x00_process_completed_request(vha, req, handle);
  1709. return;
  1710. }
  1711. req->outstanding_cmds[handle] = NULL;
  1712. cp = GET_CMD_SP(sp);
  1713. if (cp == NULL) {
  1714. ql_dbg(ql_dbg_io, vha, 0x3018,
  1715. "Command already returned (0x%x/%p).\n",
  1716. sts->handle, sp);
  1717. return;
  1718. }
  1719. lscsi_status = scsi_status & STATUS_MASK;
  1720. fcport = sp->fcport;
  1721. ox_id = 0;
  1722. sense_len = par_sense_len = rsp_info_len = resid_len =
  1723. fw_resid_len = 0;
  1724. if (IS_FWI2_CAPABLE(ha)) {
  1725. if (scsi_status & SS_SENSE_LEN_VALID)
  1726. sense_len = le32_to_cpu(sts24->sense_len);
  1727. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1728. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1729. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1730. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1731. if (comp_status == CS_DATA_UNDERRUN)
  1732. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1733. rsp_info = sts24->data;
  1734. sense_data = sts24->data;
  1735. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1736. ox_id = le16_to_cpu(sts24->ox_id);
  1737. par_sense_len = sizeof(sts24->data);
  1738. } else {
  1739. if (scsi_status & SS_SENSE_LEN_VALID)
  1740. sense_len = le16_to_cpu(sts->req_sense_length);
  1741. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1742. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1743. resid_len = le32_to_cpu(sts->residual_length);
  1744. rsp_info = sts->rsp_info;
  1745. sense_data = sts->req_sense_data;
  1746. par_sense_len = sizeof(sts->req_sense_data);
  1747. }
  1748. /* Check for any FCP transport errors. */
  1749. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1750. /* Sense data lies beyond any FCP RESPONSE data. */
  1751. if (IS_FWI2_CAPABLE(ha)) {
  1752. sense_data += rsp_info_len;
  1753. par_sense_len -= rsp_info_len;
  1754. }
  1755. if (rsp_info_len > 3 && rsp_info[3]) {
  1756. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1757. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1758. rsp_info_len, rsp_info[3]);
  1759. res = DID_BUS_BUSY << 16;
  1760. goto out;
  1761. }
  1762. }
  1763. /* Check for overrun. */
  1764. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1765. scsi_status & SS_RESIDUAL_OVER)
  1766. comp_status = CS_DATA_OVERRUN;
  1767. /*
  1768. * Based on Host and scsi status generate status code for Linux
  1769. */
  1770. switch (comp_status) {
  1771. case CS_COMPLETE:
  1772. case CS_QUEUE_FULL:
  1773. if (scsi_status == 0) {
  1774. res = DID_OK << 16;
  1775. break;
  1776. }
  1777. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1778. resid = resid_len;
  1779. scsi_set_resid(cp, resid);
  1780. if (!lscsi_status &&
  1781. ((unsigned)(scsi_bufflen(cp) - resid) <
  1782. cp->underflow)) {
  1783. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1784. "Mid-layer underflow "
  1785. "detected (0x%x of 0x%x bytes).\n",
  1786. resid, scsi_bufflen(cp));
  1787. res = DID_ERROR << 16;
  1788. break;
  1789. }
  1790. }
  1791. res = DID_OK << 16 | lscsi_status;
  1792. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1793. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1794. "QUEUE FULL detected.\n");
  1795. break;
  1796. }
  1797. logit = 0;
  1798. if (lscsi_status != SS_CHECK_CONDITION)
  1799. break;
  1800. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1801. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1802. break;
  1803. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1804. rsp, res);
  1805. break;
  1806. case CS_DATA_UNDERRUN:
  1807. /* Use F/W calculated residual length. */
  1808. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1809. scsi_set_resid(cp, resid);
  1810. if (scsi_status & SS_RESIDUAL_UNDER) {
  1811. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1812. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1813. "Dropped frame(s) detected "
  1814. "(0x%x of 0x%x bytes).\n",
  1815. resid, scsi_bufflen(cp));
  1816. res = DID_ERROR << 16 | lscsi_status;
  1817. goto check_scsi_status;
  1818. }
  1819. if (!lscsi_status &&
  1820. ((unsigned)(scsi_bufflen(cp) - resid) <
  1821. cp->underflow)) {
  1822. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1823. "Mid-layer underflow "
  1824. "detected (0x%x of 0x%x bytes).\n",
  1825. resid, scsi_bufflen(cp));
  1826. res = DID_ERROR << 16;
  1827. break;
  1828. }
  1829. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1830. lscsi_status != SAM_STAT_BUSY) {
  1831. /*
  1832. * scsi status of task set and busy are considered to be
  1833. * task not completed.
  1834. */
  1835. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1836. "Dropped frame(s) detected (0x%x "
  1837. "of 0x%x bytes).\n", resid,
  1838. scsi_bufflen(cp));
  1839. res = DID_ERROR << 16 | lscsi_status;
  1840. goto check_scsi_status;
  1841. } else {
  1842. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1843. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1844. scsi_status, lscsi_status);
  1845. }
  1846. res = DID_OK << 16 | lscsi_status;
  1847. logit = 0;
  1848. check_scsi_status:
  1849. /*
  1850. * Check to see if SCSI Status is non zero. If so report SCSI
  1851. * Status.
  1852. */
  1853. if (lscsi_status != 0) {
  1854. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1855. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1856. "QUEUE FULL detected.\n");
  1857. logit = 1;
  1858. break;
  1859. }
  1860. if (lscsi_status != SS_CHECK_CONDITION)
  1861. break;
  1862. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1863. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1864. break;
  1865. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1866. sense_len, rsp, res);
  1867. }
  1868. break;
  1869. case CS_PORT_LOGGED_OUT:
  1870. case CS_PORT_CONFIG_CHG:
  1871. case CS_PORT_BUSY:
  1872. case CS_INCOMPLETE:
  1873. case CS_PORT_UNAVAILABLE:
  1874. case CS_TIMEOUT:
  1875. case CS_RESET:
  1876. /*
  1877. * We are going to have the fc class block the rport
  1878. * while we try to recover so instruct the mid layer
  1879. * to requeue until the class decides how to handle this.
  1880. */
  1881. res = DID_TRANSPORT_DISRUPTED << 16;
  1882. if (comp_status == CS_TIMEOUT) {
  1883. if (IS_FWI2_CAPABLE(ha))
  1884. break;
  1885. else if ((le16_to_cpu(sts->status_flags) &
  1886. SF_LOGOUT_SENT) == 0)
  1887. break;
  1888. }
  1889. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1890. "Port down status: port-state=0x%x.\n",
  1891. atomic_read(&fcport->state));
  1892. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1893. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1894. break;
  1895. case CS_ABORTED:
  1896. res = DID_RESET << 16;
  1897. break;
  1898. case CS_DIF_ERROR:
  1899. logit = qla2x00_handle_dif_error(sp, sts24);
  1900. res = cp->result;
  1901. break;
  1902. case CS_TRANSPORT:
  1903. res = DID_ERROR << 16;
  1904. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1905. break;
  1906. if (state_flags & BIT_4)
  1907. scmd_printk(KERN_WARNING, cp,
  1908. "Unsupported device '%s' found.\n",
  1909. cp->device->vendor);
  1910. break;
  1911. default:
  1912. res = DID_ERROR << 16;
  1913. break;
  1914. }
  1915. out:
  1916. if (logit)
  1917. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1918. "FCP command status: 0x%x-0x%x (0x%x) "
  1919. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1920. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1921. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1922. comp_status, scsi_status, res, vha->host_no,
  1923. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1924. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1925. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1926. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1927. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1928. resid_len, fw_resid_len);
  1929. if (!res)
  1930. qla2x00_do_host_ramp_up(vha);
  1931. if (rsp->status_srb == NULL)
  1932. sp->done(ha, sp, res);
  1933. }
  1934. /**
  1935. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1936. * @ha: SCSI driver HA context
  1937. * @pkt: Entry pointer
  1938. *
  1939. * Extended sense data.
  1940. */
  1941. static void
  1942. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1943. {
  1944. uint8_t sense_sz = 0;
  1945. struct qla_hw_data *ha = rsp->hw;
  1946. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1947. srb_t *sp = rsp->status_srb;
  1948. struct scsi_cmnd *cp;
  1949. uint32_t sense_len;
  1950. uint8_t *sense_ptr;
  1951. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1952. return;
  1953. sense_len = GET_CMD_SENSE_LEN(sp);
  1954. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1955. cp = GET_CMD_SP(sp);
  1956. if (cp == NULL) {
  1957. ql_log(ql_log_warn, vha, 0x3025,
  1958. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1959. rsp->status_srb = NULL;
  1960. return;
  1961. }
  1962. if (sense_len > sizeof(pkt->data))
  1963. sense_sz = sizeof(pkt->data);
  1964. else
  1965. sense_sz = sense_len;
  1966. /* Move sense data. */
  1967. if (IS_FWI2_CAPABLE(ha))
  1968. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1969. memcpy(sense_ptr, pkt->data, sense_sz);
  1970. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1971. sense_ptr, sense_sz);
  1972. sense_len -= sense_sz;
  1973. sense_ptr += sense_sz;
  1974. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1975. SET_CMD_SENSE_LEN(sp, sense_len);
  1976. /* Place command on done queue. */
  1977. if (sense_len == 0) {
  1978. rsp->status_srb = NULL;
  1979. sp->done(ha, sp, cp->result);
  1980. }
  1981. }
  1982. /**
  1983. * qla2x00_error_entry() - Process an error entry.
  1984. * @ha: SCSI driver HA context
  1985. * @pkt: Entry pointer
  1986. */
  1987. static void
  1988. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  1989. {
  1990. srb_t *sp;
  1991. struct qla_hw_data *ha = vha->hw;
  1992. const char func[] = "ERROR-IOCB";
  1993. uint16_t que = MSW(pkt->handle);
  1994. struct req_que *req = NULL;
  1995. int res = DID_ERROR << 16;
  1996. ql_dbg(ql_dbg_async, vha, 0x502a,
  1997. "type of error status in response: 0x%x\n", pkt->entry_status);
  1998. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  1999. goto fatal;
  2000. req = ha->req_q_map[que];
  2001. if (pkt->entry_status & RF_BUSY)
  2002. res = DID_BUS_BUSY << 16;
  2003. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2004. if (sp) {
  2005. sp->done(ha, sp, res);
  2006. return;
  2007. }
  2008. fatal:
  2009. ql_log(ql_log_warn, vha, 0x5030,
  2010. "Error entry - invalid handle/queue.\n");
  2011. if (IS_QLA82XX(ha))
  2012. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2013. else
  2014. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2015. qla2xxx_wake_dpc(vha);
  2016. }
  2017. /**
  2018. * qla24xx_mbx_completion() - Process mailbox command completions.
  2019. * @ha: SCSI driver HA context
  2020. * @mb0: Mailbox0 register
  2021. */
  2022. static void
  2023. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2024. {
  2025. uint16_t cnt;
  2026. uint32_t mboxes;
  2027. uint16_t __iomem *wptr;
  2028. struct qla_hw_data *ha = vha->hw;
  2029. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2030. /* Read all mbox registers? */
  2031. mboxes = (1 << ha->mbx_count) - 1;
  2032. if (!ha->mcp)
  2033. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2034. else
  2035. mboxes = ha->mcp->in_mb;
  2036. /* Load return mailbox registers. */
  2037. ha->flags.mbox_int = 1;
  2038. ha->mailbox_out[0] = mb0;
  2039. mboxes >>= 1;
  2040. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2041. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2042. if (mboxes & BIT_0)
  2043. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2044. mboxes >>= 1;
  2045. wptr++;
  2046. }
  2047. }
  2048. /**
  2049. * qla24xx_process_response_queue() - Process response queue entries.
  2050. * @ha: SCSI driver HA context
  2051. */
  2052. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2053. struct rsp_que *rsp)
  2054. {
  2055. struct sts_entry_24xx *pkt;
  2056. struct qla_hw_data *ha = vha->hw;
  2057. if (!vha->flags.online)
  2058. return;
  2059. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2060. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2061. rsp->ring_index++;
  2062. if (rsp->ring_index == rsp->length) {
  2063. rsp->ring_index = 0;
  2064. rsp->ring_ptr = rsp->ring;
  2065. } else {
  2066. rsp->ring_ptr++;
  2067. }
  2068. if (pkt->entry_status != 0) {
  2069. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2070. (void)qlt_24xx_process_response_error(vha, pkt);
  2071. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2072. wmb();
  2073. continue;
  2074. }
  2075. switch (pkt->entry_type) {
  2076. case STATUS_TYPE:
  2077. qla2x00_status_entry(vha, rsp, pkt);
  2078. break;
  2079. case STATUS_CONT_TYPE:
  2080. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2081. break;
  2082. case VP_RPT_ID_IOCB_TYPE:
  2083. qla24xx_report_id_acquisition(vha,
  2084. (struct vp_rpt_id_entry_24xx *)pkt);
  2085. break;
  2086. case LOGINOUT_PORT_IOCB_TYPE:
  2087. qla24xx_logio_entry(vha, rsp->req,
  2088. (struct logio_entry_24xx *)pkt);
  2089. break;
  2090. case TSK_MGMT_IOCB_TYPE:
  2091. qla24xx_tm_iocb_entry(vha, rsp->req,
  2092. (struct tsk_mgmt_entry *)pkt);
  2093. break;
  2094. case CT_IOCB_TYPE:
  2095. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2096. break;
  2097. case ELS_IOCB_TYPE:
  2098. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2099. break;
  2100. case ABTS_RECV_24XX:
  2101. /* ensure that the ATIO queue is empty */
  2102. qlt_24xx_process_atio_queue(vha);
  2103. case ABTS_RESP_24XX:
  2104. case CTIO_TYPE7:
  2105. case NOTIFY_ACK_TYPE:
  2106. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2107. break;
  2108. case MARKER_TYPE:
  2109. /* Do nothing in this case, this check is to prevent it
  2110. * from falling into default case
  2111. */
  2112. break;
  2113. default:
  2114. /* Type Not Supported. */
  2115. ql_dbg(ql_dbg_async, vha, 0x5042,
  2116. "Received unknown response pkt type %x "
  2117. "entry status=%x.\n",
  2118. pkt->entry_type, pkt->entry_status);
  2119. break;
  2120. }
  2121. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2122. wmb();
  2123. }
  2124. /* Adjust ring index */
  2125. if (IS_QLA82XX(ha)) {
  2126. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2127. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2128. } else
  2129. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2130. }
  2131. static void
  2132. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2133. {
  2134. int rval;
  2135. uint32_t cnt;
  2136. struct qla_hw_data *ha = vha->hw;
  2137. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2138. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2139. return;
  2140. rval = QLA_SUCCESS;
  2141. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2142. RD_REG_DWORD(&reg->iobase_addr);
  2143. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2144. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2145. rval == QLA_SUCCESS; cnt--) {
  2146. if (cnt) {
  2147. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2148. udelay(10);
  2149. } else
  2150. rval = QLA_FUNCTION_TIMEOUT;
  2151. }
  2152. if (rval == QLA_SUCCESS)
  2153. goto next_test;
  2154. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2155. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2156. rval == QLA_SUCCESS; cnt--) {
  2157. if (cnt) {
  2158. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2159. udelay(10);
  2160. } else
  2161. rval = QLA_FUNCTION_TIMEOUT;
  2162. }
  2163. if (rval != QLA_SUCCESS)
  2164. goto done;
  2165. next_test:
  2166. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2167. ql_log(ql_log_info, vha, 0x504c,
  2168. "Additional code -- 0x55AA.\n");
  2169. done:
  2170. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2171. RD_REG_DWORD(&reg->iobase_window);
  2172. }
  2173. /**
  2174. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2175. * @irq:
  2176. * @dev_id: SCSI driver HA context
  2177. *
  2178. * Called by system whenever the host adapter generates an interrupt.
  2179. *
  2180. * Returns handled flag.
  2181. */
  2182. irqreturn_t
  2183. qla24xx_intr_handler(int irq, void *dev_id)
  2184. {
  2185. scsi_qla_host_t *vha;
  2186. struct qla_hw_data *ha;
  2187. struct device_reg_24xx __iomem *reg;
  2188. int status;
  2189. unsigned long iter;
  2190. uint32_t stat;
  2191. uint32_t hccr;
  2192. uint16_t mb[8];
  2193. struct rsp_que *rsp;
  2194. unsigned long flags;
  2195. rsp = (struct rsp_que *) dev_id;
  2196. if (!rsp) {
  2197. ql_log(ql_log_info, NULL, 0x5059,
  2198. "%s: NULL response queue pointer.\n", __func__);
  2199. return IRQ_NONE;
  2200. }
  2201. ha = rsp->hw;
  2202. reg = &ha->iobase->isp24;
  2203. status = 0;
  2204. if (unlikely(pci_channel_offline(ha->pdev)))
  2205. return IRQ_HANDLED;
  2206. spin_lock_irqsave(&ha->hardware_lock, flags);
  2207. vha = pci_get_drvdata(ha->pdev);
  2208. for (iter = 50; iter--; ) {
  2209. stat = RD_REG_DWORD(&reg->host_status);
  2210. if (stat & HSRX_RISC_PAUSED) {
  2211. if (unlikely(pci_channel_offline(ha->pdev)))
  2212. break;
  2213. hccr = RD_REG_DWORD(&reg->hccr);
  2214. ql_log(ql_log_warn, vha, 0x504b,
  2215. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2216. hccr);
  2217. qla2xxx_check_risc_status(vha);
  2218. ha->isp_ops->fw_dump(vha, 1);
  2219. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2220. break;
  2221. } else if ((stat & HSRX_RISC_INT) == 0)
  2222. break;
  2223. switch (stat & 0xff) {
  2224. case INTR_ROM_MB_SUCCESS:
  2225. case INTR_ROM_MB_FAILED:
  2226. case INTR_MB_SUCCESS:
  2227. case INTR_MB_FAILED:
  2228. qla24xx_mbx_completion(vha, MSW(stat));
  2229. status |= MBX_INTERRUPT;
  2230. break;
  2231. case INTR_ASYNC_EVENT:
  2232. mb[0] = MSW(stat);
  2233. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2234. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2235. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2236. qla2x00_async_event(vha, rsp, mb);
  2237. break;
  2238. case INTR_RSP_QUE_UPDATE:
  2239. case INTR_RSP_QUE_UPDATE_83XX:
  2240. qla24xx_process_response_queue(vha, rsp);
  2241. break;
  2242. case INTR_ATIO_QUE_UPDATE:
  2243. qlt_24xx_process_atio_queue(vha);
  2244. break;
  2245. case INTR_ATIO_RSP_QUE_UPDATE:
  2246. qlt_24xx_process_atio_queue(vha);
  2247. qla24xx_process_response_queue(vha, rsp);
  2248. break;
  2249. default:
  2250. ql_dbg(ql_dbg_async, vha, 0x504f,
  2251. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2252. break;
  2253. }
  2254. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2255. RD_REG_DWORD_RELAXED(&reg->hccr);
  2256. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2257. ndelay(3500);
  2258. }
  2259. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2260. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2261. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2262. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2263. complete(&ha->mbx_intr_comp);
  2264. }
  2265. return IRQ_HANDLED;
  2266. }
  2267. static irqreturn_t
  2268. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2269. {
  2270. struct qla_hw_data *ha;
  2271. struct rsp_que *rsp;
  2272. struct device_reg_24xx __iomem *reg;
  2273. struct scsi_qla_host *vha;
  2274. unsigned long flags;
  2275. rsp = (struct rsp_que *) dev_id;
  2276. if (!rsp) {
  2277. ql_log(ql_log_info, NULL, 0x505a,
  2278. "%s: NULL response queue pointer.\n", __func__);
  2279. return IRQ_NONE;
  2280. }
  2281. ha = rsp->hw;
  2282. reg = &ha->iobase->isp24;
  2283. spin_lock_irqsave(&ha->hardware_lock, flags);
  2284. vha = pci_get_drvdata(ha->pdev);
  2285. qla24xx_process_response_queue(vha, rsp);
  2286. if (!ha->flags.disable_msix_handshake) {
  2287. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2288. RD_REG_DWORD_RELAXED(&reg->hccr);
  2289. }
  2290. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2291. return IRQ_HANDLED;
  2292. }
  2293. static irqreturn_t
  2294. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2295. {
  2296. struct qla_hw_data *ha;
  2297. struct rsp_que *rsp;
  2298. struct device_reg_24xx __iomem *reg;
  2299. unsigned long flags;
  2300. rsp = (struct rsp_que *) dev_id;
  2301. if (!rsp) {
  2302. ql_log(ql_log_info, NULL, 0x505b,
  2303. "%s: NULL response queue pointer.\n", __func__);
  2304. return IRQ_NONE;
  2305. }
  2306. ha = rsp->hw;
  2307. /* Clear the interrupt, if enabled, for this response queue */
  2308. if (!ha->flags.disable_msix_handshake) {
  2309. reg = &ha->iobase->isp24;
  2310. spin_lock_irqsave(&ha->hardware_lock, flags);
  2311. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2312. RD_REG_DWORD_RELAXED(&reg->hccr);
  2313. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2314. }
  2315. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2316. return IRQ_HANDLED;
  2317. }
  2318. static irqreturn_t
  2319. qla24xx_msix_default(int irq, void *dev_id)
  2320. {
  2321. scsi_qla_host_t *vha;
  2322. struct qla_hw_data *ha;
  2323. struct rsp_que *rsp;
  2324. struct device_reg_24xx __iomem *reg;
  2325. int status;
  2326. uint32_t stat;
  2327. uint32_t hccr;
  2328. uint16_t mb[8];
  2329. unsigned long flags;
  2330. rsp = (struct rsp_que *) dev_id;
  2331. if (!rsp) {
  2332. ql_log(ql_log_info, NULL, 0x505c,
  2333. "%s: NULL response queue pointer.\n", __func__);
  2334. return IRQ_NONE;
  2335. }
  2336. ha = rsp->hw;
  2337. reg = &ha->iobase->isp24;
  2338. status = 0;
  2339. spin_lock_irqsave(&ha->hardware_lock, flags);
  2340. vha = pci_get_drvdata(ha->pdev);
  2341. do {
  2342. stat = RD_REG_DWORD(&reg->host_status);
  2343. if (stat & HSRX_RISC_PAUSED) {
  2344. if (unlikely(pci_channel_offline(ha->pdev)))
  2345. break;
  2346. hccr = RD_REG_DWORD(&reg->hccr);
  2347. ql_log(ql_log_info, vha, 0x5050,
  2348. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2349. hccr);
  2350. qla2xxx_check_risc_status(vha);
  2351. ha->isp_ops->fw_dump(vha, 1);
  2352. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2353. break;
  2354. } else if ((stat & HSRX_RISC_INT) == 0)
  2355. break;
  2356. switch (stat & 0xff) {
  2357. case INTR_ROM_MB_SUCCESS:
  2358. case INTR_ROM_MB_FAILED:
  2359. case INTR_MB_SUCCESS:
  2360. case INTR_MB_FAILED:
  2361. qla24xx_mbx_completion(vha, MSW(stat));
  2362. status |= MBX_INTERRUPT;
  2363. break;
  2364. case INTR_ASYNC_EVENT:
  2365. mb[0] = MSW(stat);
  2366. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2367. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2368. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2369. qla2x00_async_event(vha, rsp, mb);
  2370. break;
  2371. case INTR_RSP_QUE_UPDATE:
  2372. case INTR_RSP_QUE_UPDATE_83XX:
  2373. qla24xx_process_response_queue(vha, rsp);
  2374. break;
  2375. case INTR_ATIO_QUE_UPDATE:
  2376. qlt_24xx_process_atio_queue(vha);
  2377. break;
  2378. case INTR_ATIO_RSP_QUE_UPDATE:
  2379. qlt_24xx_process_atio_queue(vha);
  2380. qla24xx_process_response_queue(vha, rsp);
  2381. break;
  2382. default:
  2383. ql_dbg(ql_dbg_async, vha, 0x5051,
  2384. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2385. break;
  2386. }
  2387. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2388. } while (0);
  2389. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2390. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2391. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2392. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2393. complete(&ha->mbx_intr_comp);
  2394. }
  2395. return IRQ_HANDLED;
  2396. }
  2397. /* Interrupt handling helpers. */
  2398. struct qla_init_msix_entry {
  2399. const char *name;
  2400. irq_handler_t handler;
  2401. };
  2402. static struct qla_init_msix_entry msix_entries[3] = {
  2403. { "qla2xxx (default)", qla24xx_msix_default },
  2404. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2405. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2406. };
  2407. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2408. { "qla2xxx (default)", qla82xx_msix_default },
  2409. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2410. };
  2411. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2412. { "qla2xxx (default)", qla24xx_msix_default },
  2413. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2414. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2415. };
  2416. static void
  2417. qla24xx_disable_msix(struct qla_hw_data *ha)
  2418. {
  2419. int i;
  2420. struct qla_msix_entry *qentry;
  2421. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2422. for (i = 0; i < ha->msix_count; i++) {
  2423. qentry = &ha->msix_entries[i];
  2424. if (qentry->have_irq)
  2425. free_irq(qentry->vector, qentry->rsp);
  2426. }
  2427. pci_disable_msix(ha->pdev);
  2428. kfree(ha->msix_entries);
  2429. ha->msix_entries = NULL;
  2430. ha->flags.msix_enabled = 0;
  2431. ql_dbg(ql_dbg_init, vha, 0x0042,
  2432. "Disabled the MSI.\n");
  2433. }
  2434. static int
  2435. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2436. {
  2437. #define MIN_MSIX_COUNT 2
  2438. int i, ret;
  2439. struct msix_entry *entries;
  2440. struct qla_msix_entry *qentry;
  2441. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2442. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2443. GFP_KERNEL);
  2444. if (!entries) {
  2445. ql_log(ql_log_warn, vha, 0x00bc,
  2446. "Failed to allocate memory for msix_entry.\n");
  2447. return -ENOMEM;
  2448. }
  2449. for (i = 0; i < ha->msix_count; i++)
  2450. entries[i].entry = i;
  2451. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2452. if (ret) {
  2453. if (ret < MIN_MSIX_COUNT)
  2454. goto msix_failed;
  2455. ql_log(ql_log_warn, vha, 0x00c6,
  2456. "MSI-X: Failed to enable support "
  2457. "-- %d/%d\n Retry with %d vectors.\n",
  2458. ha->msix_count, ret, ret);
  2459. ha->msix_count = ret;
  2460. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2461. if (ret) {
  2462. msix_failed:
  2463. ql_log(ql_log_fatal, vha, 0x00c7,
  2464. "MSI-X: Failed to enable support, "
  2465. "giving up -- %d/%d.\n",
  2466. ha->msix_count, ret);
  2467. goto msix_out;
  2468. }
  2469. ha->max_rsp_queues = ha->msix_count - 1;
  2470. }
  2471. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2472. ha->msix_count, GFP_KERNEL);
  2473. if (!ha->msix_entries) {
  2474. ql_log(ql_log_fatal, vha, 0x00c8,
  2475. "Failed to allocate memory for ha->msix_entries.\n");
  2476. ret = -ENOMEM;
  2477. goto msix_out;
  2478. }
  2479. ha->flags.msix_enabled = 1;
  2480. for (i = 0; i < ha->msix_count; i++) {
  2481. qentry = &ha->msix_entries[i];
  2482. qentry->vector = entries[i].vector;
  2483. qentry->entry = entries[i].entry;
  2484. qentry->have_irq = 0;
  2485. qentry->rsp = NULL;
  2486. }
  2487. /* Enable MSI-X vectors for the base queue */
  2488. for (i = 0; i < ha->msix_count; i++) {
  2489. qentry = &ha->msix_entries[i];
  2490. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2491. ret = request_irq(qentry->vector,
  2492. qla83xx_msix_entries[i].handler,
  2493. 0, qla83xx_msix_entries[i].name, rsp);
  2494. } else if (IS_QLA82XX(ha)) {
  2495. ret = request_irq(qentry->vector,
  2496. qla82xx_msix_entries[i].handler,
  2497. 0, qla82xx_msix_entries[i].name, rsp);
  2498. } else {
  2499. ret = request_irq(qentry->vector,
  2500. msix_entries[i].handler,
  2501. 0, msix_entries[i].name, rsp);
  2502. }
  2503. if (ret) {
  2504. ql_log(ql_log_fatal, vha, 0x00cb,
  2505. "MSI-X: unable to register handler -- %x/%d.\n",
  2506. qentry->vector, ret);
  2507. qla24xx_disable_msix(ha);
  2508. ha->mqenable = 0;
  2509. goto msix_out;
  2510. }
  2511. qentry->have_irq = 1;
  2512. qentry->rsp = rsp;
  2513. rsp->msix = qentry;
  2514. }
  2515. /* Enable MSI-X vector for response queue update for queue 0 */
  2516. if (IS_QLA83XX(ha)) {
  2517. if (ha->msixbase && ha->mqiobase &&
  2518. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2519. ha->mqenable = 1;
  2520. } else
  2521. if (ha->mqiobase
  2522. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2523. ha->mqenable = 1;
  2524. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2525. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2526. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2527. ql_dbg(ql_dbg_init, vha, 0x0055,
  2528. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2529. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2530. msix_out:
  2531. kfree(entries);
  2532. return ret;
  2533. }
  2534. int
  2535. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2536. {
  2537. int ret;
  2538. device_reg_t __iomem *reg = ha->iobase;
  2539. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2540. /* If possible, enable MSI-X. */
  2541. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2542. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2543. goto skip_msi;
  2544. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2545. (ha->pdev->subsystem_device == 0x7040 ||
  2546. ha->pdev->subsystem_device == 0x7041 ||
  2547. ha->pdev->subsystem_device == 0x1705)) {
  2548. ql_log(ql_log_warn, vha, 0x0034,
  2549. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2550. ha->pdev->subsystem_vendor,
  2551. ha->pdev->subsystem_device);
  2552. goto skip_msi;
  2553. }
  2554. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2555. ql_log(ql_log_warn, vha, 0x0035,
  2556. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2557. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2558. goto skip_msix;
  2559. }
  2560. ret = qla24xx_enable_msix(ha, rsp);
  2561. if (!ret) {
  2562. ql_dbg(ql_dbg_init, vha, 0x0036,
  2563. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2564. ha->chip_revision, ha->fw_attributes);
  2565. goto clear_risc_ints;
  2566. }
  2567. ql_log(ql_log_info, vha, 0x0037,
  2568. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2569. skip_msix:
  2570. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2571. !IS_QLA8001(ha) && !IS_QLA82XX(ha))
  2572. goto skip_msi;
  2573. ret = pci_enable_msi(ha->pdev);
  2574. if (!ret) {
  2575. ql_dbg(ql_dbg_init, vha, 0x0038,
  2576. "MSI: Enabled.\n");
  2577. ha->flags.msi_enabled = 1;
  2578. } else
  2579. ql_log(ql_log_warn, vha, 0x0039,
  2580. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2581. /* Skip INTx on ISP82xx. */
  2582. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2583. return QLA_FUNCTION_FAILED;
  2584. skip_msi:
  2585. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2586. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2587. QLA2XXX_DRIVER_NAME, rsp);
  2588. if (ret) {
  2589. ql_log(ql_log_warn, vha, 0x003a,
  2590. "Failed to reserve interrupt %d already in use.\n",
  2591. ha->pdev->irq);
  2592. goto fail;
  2593. } else if (!ha->flags.msi_enabled)
  2594. ql_dbg(ql_dbg_init, vha, 0x0125,
  2595. "INTa mode: Enabled.\n");
  2596. clear_risc_ints:
  2597. spin_lock_irq(&ha->hardware_lock);
  2598. if (!IS_FWI2_CAPABLE(ha))
  2599. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2600. spin_unlock_irq(&ha->hardware_lock);
  2601. fail:
  2602. return ret;
  2603. }
  2604. void
  2605. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2606. {
  2607. struct qla_hw_data *ha = vha->hw;
  2608. struct rsp_que *rsp;
  2609. /*
  2610. * We need to check that ha->rsp_q_map is valid in case we are called
  2611. * from a probe failure context.
  2612. */
  2613. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2614. return;
  2615. rsp = ha->rsp_q_map[0];
  2616. if (ha->flags.msix_enabled)
  2617. qla24xx_disable_msix(ha);
  2618. else if (ha->flags.msi_enabled) {
  2619. free_irq(ha->pdev->irq, rsp);
  2620. pci_disable_msi(ha->pdev);
  2621. } else
  2622. free_irq(ha->pdev->irq, rsp);
  2623. }
  2624. int qla25xx_request_irq(struct rsp_que *rsp)
  2625. {
  2626. struct qla_hw_data *ha = rsp->hw;
  2627. struct qla_init_msix_entry *intr = &msix_entries[2];
  2628. struct qla_msix_entry *msix = rsp->msix;
  2629. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2630. int ret;
  2631. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2632. if (ret) {
  2633. ql_log(ql_log_fatal, vha, 0x00e6,
  2634. "MSI-X: Unable to register handler -- %x/%d.\n",
  2635. msix->vector, ret);
  2636. return ret;
  2637. }
  2638. msix->have_irq = 1;
  2639. msix->rsp = rsp;
  2640. return ret;
  2641. }