events.c 41 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816
  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/page.h>
  39. #include <asm/xen/pci.h>
  40. #include <asm/xen/hypercall.h>
  41. #include <asm/xen/hypervisor.h>
  42. #include <xen/xen.h>
  43. #include <xen/hvm.h>
  44. #include <xen/xen-ops.h>
  45. #include <xen/events.h>
  46. #include <xen/interface/xen.h>
  47. #include <xen/interface/event_channel.h>
  48. #include <xen/interface/hvm/hvm_op.h>
  49. #include <xen/interface/hvm/params.h>
  50. /*
  51. * This lock protects updates to the following mapping and reference-count
  52. * arrays. The lock does not need to be acquired to read the mapping tables.
  53. */
  54. static DEFINE_MUTEX(irq_mapping_update_lock);
  55. static LIST_HEAD(xen_irq_list_head);
  56. /* IRQ <-> VIRQ mapping. */
  57. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  58. /* IRQ <-> IPI mapping */
  59. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  60. /* Interrupt types. */
  61. enum xen_irq_type {
  62. IRQT_UNBOUND = 0,
  63. IRQT_PIRQ,
  64. IRQT_VIRQ,
  65. IRQT_IPI,
  66. IRQT_EVTCHN
  67. };
  68. /*
  69. * Packed IRQ information:
  70. * type - enum xen_irq_type
  71. * event channel - irq->event channel mapping
  72. * cpu - cpu this event channel is bound to
  73. * index - type-specific information:
  74. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  75. * guest, or GSI (real passthrough IRQ) of the device.
  76. * VIRQ - virq number
  77. * IPI - IPI vector
  78. * EVTCHN -
  79. */
  80. struct irq_info {
  81. struct list_head list;
  82. int refcnt;
  83. enum xen_irq_type type; /* type */
  84. unsigned irq;
  85. unsigned short evtchn; /* event channel */
  86. unsigned short cpu; /* cpu bound */
  87. union {
  88. unsigned short virq;
  89. enum ipi_vector ipi;
  90. struct {
  91. unsigned short pirq;
  92. unsigned short gsi;
  93. unsigned char vector;
  94. unsigned char flags;
  95. uint16_t domid;
  96. } pirq;
  97. } u;
  98. };
  99. #define PIRQ_NEEDS_EOI (1 << 0)
  100. #define PIRQ_SHAREABLE (1 << 1)
  101. static int *evtchn_to_irq;
  102. static unsigned long *pirq_eoi_map;
  103. static bool (*pirq_needs_eoi)(unsigned irq);
  104. static DEFINE_PER_CPU(unsigned long [NR_EVENT_CHANNELS/BITS_PER_LONG],
  105. cpu_evtchn_mask);
  106. /* Xen will never allocate port zero for any purpose. */
  107. #define VALID_EVTCHN(chn) ((chn) != 0)
  108. static struct irq_chip xen_dynamic_chip;
  109. static struct irq_chip xen_percpu_chip;
  110. static struct irq_chip xen_pirq_chip;
  111. static void enable_dynirq(struct irq_data *data);
  112. static void disable_dynirq(struct irq_data *data);
  113. /* Get info for IRQ */
  114. static struct irq_info *info_for_irq(unsigned irq)
  115. {
  116. return irq_get_handler_data(irq);
  117. }
  118. /* Constructors for packed IRQ information. */
  119. static void xen_irq_info_common_init(struct irq_info *info,
  120. unsigned irq,
  121. enum xen_irq_type type,
  122. unsigned short evtchn,
  123. unsigned short cpu)
  124. {
  125. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  126. info->type = type;
  127. info->irq = irq;
  128. info->evtchn = evtchn;
  129. info->cpu = cpu;
  130. evtchn_to_irq[evtchn] = irq;
  131. }
  132. static void xen_irq_info_evtchn_init(unsigned irq,
  133. unsigned short evtchn)
  134. {
  135. struct irq_info *info = info_for_irq(irq);
  136. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  137. }
  138. static void xen_irq_info_ipi_init(unsigned cpu,
  139. unsigned irq,
  140. unsigned short evtchn,
  141. enum ipi_vector ipi)
  142. {
  143. struct irq_info *info = info_for_irq(irq);
  144. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  145. info->u.ipi = ipi;
  146. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  147. }
  148. static void xen_irq_info_virq_init(unsigned cpu,
  149. unsigned irq,
  150. unsigned short evtchn,
  151. unsigned short virq)
  152. {
  153. struct irq_info *info = info_for_irq(irq);
  154. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  155. info->u.virq = virq;
  156. per_cpu(virq_to_irq, cpu)[virq] = irq;
  157. }
  158. static void xen_irq_info_pirq_init(unsigned irq,
  159. unsigned short evtchn,
  160. unsigned short pirq,
  161. unsigned short gsi,
  162. unsigned short vector,
  163. uint16_t domid,
  164. unsigned char flags)
  165. {
  166. struct irq_info *info = info_for_irq(irq);
  167. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  168. info->u.pirq.pirq = pirq;
  169. info->u.pirq.gsi = gsi;
  170. info->u.pirq.vector = vector;
  171. info->u.pirq.domid = domid;
  172. info->u.pirq.flags = flags;
  173. }
  174. /*
  175. * Accessors for packed IRQ information.
  176. */
  177. static unsigned int evtchn_from_irq(unsigned irq)
  178. {
  179. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  180. return 0;
  181. return info_for_irq(irq)->evtchn;
  182. }
  183. unsigned irq_from_evtchn(unsigned int evtchn)
  184. {
  185. return evtchn_to_irq[evtchn];
  186. }
  187. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  188. static enum ipi_vector ipi_from_irq(unsigned irq)
  189. {
  190. struct irq_info *info = info_for_irq(irq);
  191. BUG_ON(info == NULL);
  192. BUG_ON(info->type != IRQT_IPI);
  193. return info->u.ipi;
  194. }
  195. static unsigned virq_from_irq(unsigned irq)
  196. {
  197. struct irq_info *info = info_for_irq(irq);
  198. BUG_ON(info == NULL);
  199. BUG_ON(info->type != IRQT_VIRQ);
  200. return info->u.virq;
  201. }
  202. static unsigned pirq_from_irq(unsigned irq)
  203. {
  204. struct irq_info *info = info_for_irq(irq);
  205. BUG_ON(info == NULL);
  206. BUG_ON(info->type != IRQT_PIRQ);
  207. return info->u.pirq.pirq;
  208. }
  209. static enum xen_irq_type type_from_irq(unsigned irq)
  210. {
  211. return info_for_irq(irq)->type;
  212. }
  213. static unsigned cpu_from_irq(unsigned irq)
  214. {
  215. return info_for_irq(irq)->cpu;
  216. }
  217. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  218. {
  219. int irq = evtchn_to_irq[evtchn];
  220. unsigned ret = 0;
  221. if (irq != -1)
  222. ret = cpu_from_irq(irq);
  223. return ret;
  224. }
  225. static bool pirq_check_eoi_map(unsigned irq)
  226. {
  227. return test_bit(irq, pirq_eoi_map);
  228. }
  229. static bool pirq_needs_eoi_flag(unsigned irq)
  230. {
  231. struct irq_info *info = info_for_irq(irq);
  232. BUG_ON(info->type != IRQT_PIRQ);
  233. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  234. }
  235. static inline unsigned long active_evtchns(unsigned int cpu,
  236. struct shared_info *sh,
  237. unsigned int idx)
  238. {
  239. return sh->evtchn_pending[idx] &
  240. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  241. ~sh->evtchn_mask[idx];
  242. }
  243. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  244. {
  245. int irq = evtchn_to_irq[chn];
  246. BUG_ON(irq == -1);
  247. #ifdef CONFIG_SMP
  248. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  249. #endif
  250. clear_bit(chn, per_cpu(cpu_evtchn_mask, cpu_from_irq(irq)));
  251. set_bit(chn, per_cpu(cpu_evtchn_mask, cpu));
  252. info_for_irq(irq)->cpu = cpu;
  253. }
  254. static void init_evtchn_cpu_bindings(void)
  255. {
  256. int i;
  257. #ifdef CONFIG_SMP
  258. struct irq_info *info;
  259. /* By default all event channels notify CPU#0. */
  260. list_for_each_entry(info, &xen_irq_list_head, list) {
  261. struct irq_desc *desc = irq_to_desc(info->irq);
  262. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  263. }
  264. #endif
  265. for_each_possible_cpu(i)
  266. memset(per_cpu(cpu_evtchn_mask, i),
  267. (i == 0) ? ~0 : 0, sizeof(*per_cpu(cpu_evtchn_mask, i)));
  268. }
  269. static inline void clear_evtchn(int port)
  270. {
  271. struct shared_info *s = HYPERVISOR_shared_info;
  272. sync_clear_bit(port, &s->evtchn_pending[0]);
  273. }
  274. static inline void set_evtchn(int port)
  275. {
  276. struct shared_info *s = HYPERVISOR_shared_info;
  277. sync_set_bit(port, &s->evtchn_pending[0]);
  278. }
  279. static inline int test_evtchn(int port)
  280. {
  281. struct shared_info *s = HYPERVISOR_shared_info;
  282. return sync_test_bit(port, &s->evtchn_pending[0]);
  283. }
  284. /**
  285. * notify_remote_via_irq - send event to remote end of event channel via irq
  286. * @irq: irq of event channel to send event to
  287. *
  288. * Unlike notify_remote_via_evtchn(), this is safe to use across
  289. * save/restore. Notifications on a broken connection are silently
  290. * dropped.
  291. */
  292. void notify_remote_via_irq(int irq)
  293. {
  294. int evtchn = evtchn_from_irq(irq);
  295. if (VALID_EVTCHN(evtchn))
  296. notify_remote_via_evtchn(evtchn);
  297. }
  298. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  299. static void mask_evtchn(int port)
  300. {
  301. struct shared_info *s = HYPERVISOR_shared_info;
  302. sync_set_bit(port, &s->evtchn_mask[0]);
  303. }
  304. static void unmask_evtchn(int port)
  305. {
  306. struct shared_info *s = HYPERVISOR_shared_info;
  307. unsigned int cpu = get_cpu();
  308. BUG_ON(!irqs_disabled());
  309. /* Slow path (hypercall) if this is a non-local port. */
  310. if (unlikely(cpu != cpu_from_evtchn(port))) {
  311. struct evtchn_unmask unmask = { .port = port };
  312. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  313. } else {
  314. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  315. sync_clear_bit(port, &s->evtchn_mask[0]);
  316. /*
  317. * The following is basically the equivalent of
  318. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  319. * the interrupt edge' if the channel is masked.
  320. */
  321. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  322. !sync_test_and_set_bit(port / BITS_PER_LONG,
  323. &vcpu_info->evtchn_pending_sel))
  324. vcpu_info->evtchn_upcall_pending = 1;
  325. }
  326. put_cpu();
  327. }
  328. static void xen_irq_init(unsigned irq)
  329. {
  330. struct irq_info *info;
  331. #ifdef CONFIG_SMP
  332. struct irq_desc *desc = irq_to_desc(irq);
  333. /* By default all event channels notify CPU#0. */
  334. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  335. #endif
  336. info = kzalloc(sizeof(*info), GFP_KERNEL);
  337. if (info == NULL)
  338. panic("Unable to allocate metadata for IRQ%d\n", irq);
  339. info->type = IRQT_UNBOUND;
  340. info->refcnt = -1;
  341. irq_set_handler_data(irq, info);
  342. list_add_tail(&info->list, &xen_irq_list_head);
  343. }
  344. static int __must_check xen_allocate_irq_dynamic(void)
  345. {
  346. int first = 0;
  347. int irq;
  348. #ifdef CONFIG_X86_IO_APIC
  349. /*
  350. * For an HVM guest or domain 0 which see "real" (emulated or
  351. * actual respectively) GSIs we allocate dynamic IRQs
  352. * e.g. those corresponding to event channels or MSIs
  353. * etc. from the range above those "real" GSIs to avoid
  354. * collisions.
  355. */
  356. if (xen_initial_domain() || xen_hvm_domain())
  357. first = get_nr_irqs_gsi();
  358. #endif
  359. irq = irq_alloc_desc_from(first, -1);
  360. if (irq >= 0)
  361. xen_irq_init(irq);
  362. return irq;
  363. }
  364. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  365. {
  366. int irq;
  367. /*
  368. * A PV guest has no concept of a GSI (since it has no ACPI
  369. * nor access to/knowledge of the physical APICs). Therefore
  370. * all IRQs are dynamically allocated from the entire IRQ
  371. * space.
  372. */
  373. if (xen_pv_domain() && !xen_initial_domain())
  374. return xen_allocate_irq_dynamic();
  375. /* Legacy IRQ descriptors are already allocated by the arch. */
  376. if (gsi < NR_IRQS_LEGACY)
  377. irq = gsi;
  378. else
  379. irq = irq_alloc_desc_at(gsi, -1);
  380. xen_irq_init(irq);
  381. return irq;
  382. }
  383. static void xen_free_irq(unsigned irq)
  384. {
  385. struct irq_info *info = irq_get_handler_data(irq);
  386. list_del(&info->list);
  387. irq_set_handler_data(irq, NULL);
  388. WARN_ON(info->refcnt > 0);
  389. kfree(info);
  390. /* Legacy IRQ descriptors are managed by the arch. */
  391. if (irq < NR_IRQS_LEGACY)
  392. return;
  393. irq_free_desc(irq);
  394. }
  395. static void pirq_query_unmask(int irq)
  396. {
  397. struct physdev_irq_status_query irq_status;
  398. struct irq_info *info = info_for_irq(irq);
  399. BUG_ON(info->type != IRQT_PIRQ);
  400. irq_status.irq = pirq_from_irq(irq);
  401. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  402. irq_status.flags = 0;
  403. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  404. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  405. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  406. }
  407. static bool probing_irq(int irq)
  408. {
  409. struct irq_desc *desc = irq_to_desc(irq);
  410. return desc && desc->action == NULL;
  411. }
  412. static void eoi_pirq(struct irq_data *data)
  413. {
  414. int evtchn = evtchn_from_irq(data->irq);
  415. struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
  416. int rc = 0;
  417. irq_move_irq(data);
  418. if (VALID_EVTCHN(evtchn))
  419. clear_evtchn(evtchn);
  420. if (pirq_needs_eoi(data->irq)) {
  421. rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  422. WARN_ON(rc);
  423. }
  424. }
  425. static void mask_ack_pirq(struct irq_data *data)
  426. {
  427. disable_dynirq(data);
  428. eoi_pirq(data);
  429. }
  430. static unsigned int __startup_pirq(unsigned int irq)
  431. {
  432. struct evtchn_bind_pirq bind_pirq;
  433. struct irq_info *info = info_for_irq(irq);
  434. int evtchn = evtchn_from_irq(irq);
  435. int rc;
  436. BUG_ON(info->type != IRQT_PIRQ);
  437. if (VALID_EVTCHN(evtchn))
  438. goto out;
  439. bind_pirq.pirq = pirq_from_irq(irq);
  440. /* NB. We are happy to share unless we are probing. */
  441. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  442. BIND_PIRQ__WILL_SHARE : 0;
  443. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  444. if (rc != 0) {
  445. if (!probing_irq(irq))
  446. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  447. irq);
  448. return 0;
  449. }
  450. evtchn = bind_pirq.port;
  451. pirq_query_unmask(irq);
  452. evtchn_to_irq[evtchn] = irq;
  453. bind_evtchn_to_cpu(evtchn, 0);
  454. info->evtchn = evtchn;
  455. out:
  456. unmask_evtchn(evtchn);
  457. eoi_pirq(irq_get_irq_data(irq));
  458. return 0;
  459. }
  460. static unsigned int startup_pirq(struct irq_data *data)
  461. {
  462. return __startup_pirq(data->irq);
  463. }
  464. static void shutdown_pirq(struct irq_data *data)
  465. {
  466. struct evtchn_close close;
  467. unsigned int irq = data->irq;
  468. struct irq_info *info = info_for_irq(irq);
  469. int evtchn = evtchn_from_irq(irq);
  470. BUG_ON(info->type != IRQT_PIRQ);
  471. if (!VALID_EVTCHN(evtchn))
  472. return;
  473. mask_evtchn(evtchn);
  474. close.port = evtchn;
  475. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  476. BUG();
  477. bind_evtchn_to_cpu(evtchn, 0);
  478. evtchn_to_irq[evtchn] = -1;
  479. info->evtchn = 0;
  480. }
  481. static void enable_pirq(struct irq_data *data)
  482. {
  483. startup_pirq(data);
  484. }
  485. static void disable_pirq(struct irq_data *data)
  486. {
  487. disable_dynirq(data);
  488. }
  489. static int find_irq_by_gsi(unsigned gsi)
  490. {
  491. struct irq_info *info;
  492. list_for_each_entry(info, &xen_irq_list_head, list) {
  493. if (info->type != IRQT_PIRQ)
  494. continue;
  495. if (info->u.pirq.gsi == gsi)
  496. return info->irq;
  497. }
  498. return -1;
  499. }
  500. /*
  501. * Do not make any assumptions regarding the relationship between the
  502. * IRQ number returned here and the Xen pirq argument.
  503. *
  504. * Note: We don't assign an event channel until the irq actually started
  505. * up. Return an existing irq if we've already got one for the gsi.
  506. *
  507. * Shareable implies level triggered, not shareable implies edge
  508. * triggered here.
  509. */
  510. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  511. unsigned pirq, int shareable, char *name)
  512. {
  513. int irq = -1;
  514. struct physdev_irq irq_op;
  515. mutex_lock(&irq_mapping_update_lock);
  516. irq = find_irq_by_gsi(gsi);
  517. if (irq != -1) {
  518. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  519. irq, gsi);
  520. goto out;
  521. }
  522. irq = xen_allocate_irq_gsi(gsi);
  523. if (irq < 0)
  524. goto out;
  525. irq_op.irq = irq;
  526. irq_op.vector = 0;
  527. /* Only the privileged domain can do this. For non-priv, the pcifront
  528. * driver provides a PCI bus that does the call to do exactly
  529. * this in the priv domain. */
  530. if (xen_initial_domain() &&
  531. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  532. xen_free_irq(irq);
  533. irq = -ENOSPC;
  534. goto out;
  535. }
  536. xen_irq_info_pirq_init(irq, 0, pirq, gsi, irq_op.vector, DOMID_SELF,
  537. shareable ? PIRQ_SHAREABLE : 0);
  538. pirq_query_unmask(irq);
  539. /* We try to use the handler with the appropriate semantic for the
  540. * type of interrupt: if the interrupt is an edge triggered
  541. * interrupt we use handle_edge_irq.
  542. *
  543. * On the other hand if the interrupt is level triggered we use
  544. * handle_fasteoi_irq like the native code does for this kind of
  545. * interrupts.
  546. *
  547. * Depending on the Xen version, pirq_needs_eoi might return true
  548. * not only for level triggered interrupts but for edge triggered
  549. * interrupts too. In any case Xen always honors the eoi mechanism,
  550. * not injecting any more pirqs of the same kind if the first one
  551. * hasn't received an eoi yet. Therefore using the fasteoi handler
  552. * is the right choice either way.
  553. */
  554. if (shareable)
  555. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  556. handle_fasteoi_irq, name);
  557. else
  558. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  559. handle_edge_irq, name);
  560. out:
  561. mutex_unlock(&irq_mapping_update_lock);
  562. return irq;
  563. }
  564. #ifdef CONFIG_PCI_MSI
  565. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  566. {
  567. int rc;
  568. struct physdev_get_free_pirq op_get_free_pirq;
  569. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  570. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  571. WARN_ONCE(rc == -ENOSYS,
  572. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  573. return rc ? -1 : op_get_free_pirq.pirq;
  574. }
  575. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  576. int pirq, int vector, const char *name,
  577. domid_t domid)
  578. {
  579. int irq, ret;
  580. mutex_lock(&irq_mapping_update_lock);
  581. irq = xen_allocate_irq_dynamic();
  582. if (irq < 0)
  583. goto out;
  584. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
  585. name);
  586. xen_irq_info_pirq_init(irq, 0, pirq, 0, vector, domid, 0);
  587. ret = irq_set_msi_desc(irq, msidesc);
  588. if (ret < 0)
  589. goto error_irq;
  590. out:
  591. mutex_unlock(&irq_mapping_update_lock);
  592. return irq;
  593. error_irq:
  594. mutex_unlock(&irq_mapping_update_lock);
  595. xen_free_irq(irq);
  596. return ret;
  597. }
  598. #endif
  599. int xen_destroy_irq(int irq)
  600. {
  601. struct irq_desc *desc;
  602. struct physdev_unmap_pirq unmap_irq;
  603. struct irq_info *info = info_for_irq(irq);
  604. int rc = -ENOENT;
  605. mutex_lock(&irq_mapping_update_lock);
  606. desc = irq_to_desc(irq);
  607. if (!desc)
  608. goto out;
  609. if (xen_initial_domain()) {
  610. unmap_irq.pirq = info->u.pirq.pirq;
  611. unmap_irq.domid = info->u.pirq.domid;
  612. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  613. /* If another domain quits without making the pci_disable_msix
  614. * call, the Xen hypervisor takes care of freeing the PIRQs
  615. * (free_domain_pirqs).
  616. */
  617. if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
  618. printk(KERN_INFO "domain %d does not have %d anymore\n",
  619. info->u.pirq.domid, info->u.pirq.pirq);
  620. else if (rc) {
  621. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  622. goto out;
  623. }
  624. }
  625. xen_free_irq(irq);
  626. out:
  627. mutex_unlock(&irq_mapping_update_lock);
  628. return rc;
  629. }
  630. int xen_irq_from_pirq(unsigned pirq)
  631. {
  632. int irq;
  633. struct irq_info *info;
  634. mutex_lock(&irq_mapping_update_lock);
  635. list_for_each_entry(info, &xen_irq_list_head, list) {
  636. if (info->type != IRQT_PIRQ)
  637. continue;
  638. irq = info->irq;
  639. if (info->u.pirq.pirq == pirq)
  640. goto out;
  641. }
  642. irq = -1;
  643. out:
  644. mutex_unlock(&irq_mapping_update_lock);
  645. return irq;
  646. }
  647. int xen_pirq_from_irq(unsigned irq)
  648. {
  649. return pirq_from_irq(irq);
  650. }
  651. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  652. int bind_evtchn_to_irq(unsigned int evtchn)
  653. {
  654. int irq;
  655. mutex_lock(&irq_mapping_update_lock);
  656. irq = evtchn_to_irq[evtchn];
  657. if (irq == -1) {
  658. irq = xen_allocate_irq_dynamic();
  659. if (irq == -1)
  660. goto out;
  661. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  662. handle_edge_irq, "event");
  663. xen_irq_info_evtchn_init(irq, evtchn);
  664. }
  665. out:
  666. mutex_unlock(&irq_mapping_update_lock);
  667. return irq;
  668. }
  669. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  670. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  671. {
  672. struct evtchn_bind_ipi bind_ipi;
  673. int evtchn, irq;
  674. mutex_lock(&irq_mapping_update_lock);
  675. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  676. if (irq == -1) {
  677. irq = xen_allocate_irq_dynamic();
  678. if (irq < 0)
  679. goto out;
  680. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  681. handle_percpu_irq, "ipi");
  682. bind_ipi.vcpu = cpu;
  683. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  684. &bind_ipi) != 0)
  685. BUG();
  686. evtchn = bind_ipi.port;
  687. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  688. bind_evtchn_to_cpu(evtchn, cpu);
  689. }
  690. out:
  691. mutex_unlock(&irq_mapping_update_lock);
  692. return irq;
  693. }
  694. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  695. unsigned int remote_port)
  696. {
  697. struct evtchn_bind_interdomain bind_interdomain;
  698. int err;
  699. bind_interdomain.remote_dom = remote_domain;
  700. bind_interdomain.remote_port = remote_port;
  701. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  702. &bind_interdomain);
  703. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  704. }
  705. static int find_virq(unsigned int virq, unsigned int cpu)
  706. {
  707. struct evtchn_status status;
  708. int port, rc = -ENOENT;
  709. memset(&status, 0, sizeof(status));
  710. for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
  711. status.dom = DOMID_SELF;
  712. status.port = port;
  713. rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
  714. if (rc < 0)
  715. continue;
  716. if (status.status != EVTCHNSTAT_virq)
  717. continue;
  718. if (status.u.virq == virq && status.vcpu == cpu) {
  719. rc = port;
  720. break;
  721. }
  722. }
  723. return rc;
  724. }
  725. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  726. {
  727. struct evtchn_bind_virq bind_virq;
  728. int evtchn, irq, ret;
  729. mutex_lock(&irq_mapping_update_lock);
  730. irq = per_cpu(virq_to_irq, cpu)[virq];
  731. if (irq == -1) {
  732. irq = xen_allocate_irq_dynamic();
  733. if (irq == -1)
  734. goto out;
  735. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  736. handle_percpu_irq, "virq");
  737. bind_virq.virq = virq;
  738. bind_virq.vcpu = cpu;
  739. ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  740. &bind_virq);
  741. if (ret == 0)
  742. evtchn = bind_virq.port;
  743. else {
  744. if (ret == -EEXIST)
  745. ret = find_virq(virq, cpu);
  746. BUG_ON(ret < 0);
  747. evtchn = ret;
  748. }
  749. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  750. bind_evtchn_to_cpu(evtchn, cpu);
  751. }
  752. out:
  753. mutex_unlock(&irq_mapping_update_lock);
  754. return irq;
  755. }
  756. static void unbind_from_irq(unsigned int irq)
  757. {
  758. struct evtchn_close close;
  759. int evtchn = evtchn_from_irq(irq);
  760. struct irq_info *info = irq_get_handler_data(irq);
  761. mutex_lock(&irq_mapping_update_lock);
  762. if (info->refcnt > 0) {
  763. info->refcnt--;
  764. if (info->refcnt != 0)
  765. goto done;
  766. }
  767. if (VALID_EVTCHN(evtchn)) {
  768. close.port = evtchn;
  769. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  770. BUG();
  771. switch (type_from_irq(irq)) {
  772. case IRQT_VIRQ:
  773. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  774. [virq_from_irq(irq)] = -1;
  775. break;
  776. case IRQT_IPI:
  777. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  778. [ipi_from_irq(irq)] = -1;
  779. break;
  780. default:
  781. break;
  782. }
  783. /* Closed ports are implicitly re-bound to VCPU0. */
  784. bind_evtchn_to_cpu(evtchn, 0);
  785. evtchn_to_irq[evtchn] = -1;
  786. }
  787. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  788. xen_free_irq(irq);
  789. done:
  790. mutex_unlock(&irq_mapping_update_lock);
  791. }
  792. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  793. irq_handler_t handler,
  794. unsigned long irqflags,
  795. const char *devname, void *dev_id)
  796. {
  797. int irq, retval;
  798. irq = bind_evtchn_to_irq(evtchn);
  799. if (irq < 0)
  800. return irq;
  801. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  802. if (retval != 0) {
  803. unbind_from_irq(irq);
  804. return retval;
  805. }
  806. return irq;
  807. }
  808. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  809. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  810. unsigned int remote_port,
  811. irq_handler_t handler,
  812. unsigned long irqflags,
  813. const char *devname,
  814. void *dev_id)
  815. {
  816. int irq, retval;
  817. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  818. if (irq < 0)
  819. return irq;
  820. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  821. if (retval != 0) {
  822. unbind_from_irq(irq);
  823. return retval;
  824. }
  825. return irq;
  826. }
  827. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  828. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  829. irq_handler_t handler,
  830. unsigned long irqflags, const char *devname, void *dev_id)
  831. {
  832. int irq, retval;
  833. irq = bind_virq_to_irq(virq, cpu);
  834. if (irq < 0)
  835. return irq;
  836. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  837. if (retval != 0) {
  838. unbind_from_irq(irq);
  839. return retval;
  840. }
  841. return irq;
  842. }
  843. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  844. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  845. unsigned int cpu,
  846. irq_handler_t handler,
  847. unsigned long irqflags,
  848. const char *devname,
  849. void *dev_id)
  850. {
  851. int irq, retval;
  852. irq = bind_ipi_to_irq(ipi, cpu);
  853. if (irq < 0)
  854. return irq;
  855. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
  856. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  857. if (retval != 0) {
  858. unbind_from_irq(irq);
  859. return retval;
  860. }
  861. return irq;
  862. }
  863. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  864. {
  865. free_irq(irq, dev_id);
  866. unbind_from_irq(irq);
  867. }
  868. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  869. int evtchn_make_refcounted(unsigned int evtchn)
  870. {
  871. int irq = evtchn_to_irq[evtchn];
  872. struct irq_info *info;
  873. if (irq == -1)
  874. return -ENOENT;
  875. info = irq_get_handler_data(irq);
  876. if (!info)
  877. return -ENOENT;
  878. WARN_ON(info->refcnt != -1);
  879. info->refcnt = 1;
  880. return 0;
  881. }
  882. EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
  883. int evtchn_get(unsigned int evtchn)
  884. {
  885. int irq;
  886. struct irq_info *info;
  887. int err = -ENOENT;
  888. if (evtchn >= NR_EVENT_CHANNELS)
  889. return -EINVAL;
  890. mutex_lock(&irq_mapping_update_lock);
  891. irq = evtchn_to_irq[evtchn];
  892. if (irq == -1)
  893. goto done;
  894. info = irq_get_handler_data(irq);
  895. if (!info)
  896. goto done;
  897. err = -EINVAL;
  898. if (info->refcnt <= 0)
  899. goto done;
  900. info->refcnt++;
  901. err = 0;
  902. done:
  903. mutex_unlock(&irq_mapping_update_lock);
  904. return err;
  905. }
  906. EXPORT_SYMBOL_GPL(evtchn_get);
  907. void evtchn_put(unsigned int evtchn)
  908. {
  909. int irq = evtchn_to_irq[evtchn];
  910. if (WARN_ON(irq == -1))
  911. return;
  912. unbind_from_irq(irq);
  913. }
  914. EXPORT_SYMBOL_GPL(evtchn_put);
  915. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  916. {
  917. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  918. BUG_ON(irq < 0);
  919. notify_remote_via_irq(irq);
  920. }
  921. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  922. {
  923. struct shared_info *sh = HYPERVISOR_shared_info;
  924. int cpu = smp_processor_id();
  925. unsigned long *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  926. int i;
  927. unsigned long flags;
  928. static DEFINE_SPINLOCK(debug_lock);
  929. struct vcpu_info *v;
  930. spin_lock_irqsave(&debug_lock, flags);
  931. printk("\nvcpu %d\n ", cpu);
  932. for_each_online_cpu(i) {
  933. int pending;
  934. v = per_cpu(xen_vcpu, i);
  935. pending = (get_irq_regs() && i == cpu)
  936. ? xen_irqs_disabled(get_irq_regs())
  937. : v->evtchn_upcall_mask;
  938. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  939. pending, v->evtchn_upcall_pending,
  940. (int)(sizeof(v->evtchn_pending_sel)*2),
  941. v->evtchn_pending_sel);
  942. }
  943. v = per_cpu(xen_vcpu, cpu);
  944. printk("\npending:\n ");
  945. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  946. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  947. sh->evtchn_pending[i],
  948. i % 8 == 0 ? "\n " : " ");
  949. printk("\nglobal mask:\n ");
  950. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  951. printk("%0*lx%s",
  952. (int)(sizeof(sh->evtchn_mask[0])*2),
  953. sh->evtchn_mask[i],
  954. i % 8 == 0 ? "\n " : " ");
  955. printk("\nglobally unmasked:\n ");
  956. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  957. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  958. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  959. i % 8 == 0 ? "\n " : " ");
  960. printk("\nlocal cpu%d mask:\n ", cpu);
  961. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  962. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  963. cpu_evtchn[i],
  964. i % 8 == 0 ? "\n " : " ");
  965. printk("\nlocally unmasked:\n ");
  966. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  967. unsigned long pending = sh->evtchn_pending[i]
  968. & ~sh->evtchn_mask[i]
  969. & cpu_evtchn[i];
  970. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  971. pending, i % 8 == 0 ? "\n " : " ");
  972. }
  973. printk("\npending list:\n");
  974. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  975. if (sync_test_bit(i, sh->evtchn_pending)) {
  976. int word_idx = i / BITS_PER_LONG;
  977. printk(" %d: event %d -> irq %d%s%s%s\n",
  978. cpu_from_evtchn(i), i,
  979. evtchn_to_irq[i],
  980. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  981. ? "" : " l2-clear",
  982. !sync_test_bit(i, sh->evtchn_mask)
  983. ? "" : " globally-masked",
  984. sync_test_bit(i, cpu_evtchn)
  985. ? "" : " locally-masked");
  986. }
  987. }
  988. spin_unlock_irqrestore(&debug_lock, flags);
  989. return IRQ_HANDLED;
  990. }
  991. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  992. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  993. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  994. /*
  995. * Mask out the i least significant bits of w
  996. */
  997. #define MASK_LSBS(w, i) (w & ((~0UL) << i))
  998. /*
  999. * Search the CPUs pending events bitmasks. For each one found, map
  1000. * the event number to an irq, and feed it into do_IRQ() for
  1001. * handling.
  1002. *
  1003. * Xen uses a two-level bitmap to speed searching. The first level is
  1004. * a bitset of words which contain pending event bits. The second
  1005. * level is a bitset of pending events themselves.
  1006. */
  1007. static void __xen_evtchn_do_upcall(void)
  1008. {
  1009. int start_word_idx, start_bit_idx;
  1010. int word_idx, bit_idx;
  1011. int i;
  1012. int cpu = get_cpu();
  1013. struct shared_info *s = HYPERVISOR_shared_info;
  1014. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  1015. unsigned count;
  1016. do {
  1017. unsigned long pending_words;
  1018. vcpu_info->evtchn_upcall_pending = 0;
  1019. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  1020. goto out;
  1021. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  1022. /* Clear master flag /before/ clearing selector flag. */
  1023. wmb();
  1024. #endif
  1025. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  1026. start_word_idx = __this_cpu_read(current_word_idx);
  1027. start_bit_idx = __this_cpu_read(current_bit_idx);
  1028. word_idx = start_word_idx;
  1029. for (i = 0; pending_words != 0; i++) {
  1030. unsigned long pending_bits;
  1031. unsigned long words;
  1032. words = MASK_LSBS(pending_words, word_idx);
  1033. /*
  1034. * If we masked out all events, wrap to beginning.
  1035. */
  1036. if (words == 0) {
  1037. word_idx = 0;
  1038. bit_idx = 0;
  1039. continue;
  1040. }
  1041. word_idx = __ffs(words);
  1042. pending_bits = active_evtchns(cpu, s, word_idx);
  1043. bit_idx = 0; /* usually scan entire word from start */
  1044. if (word_idx == start_word_idx) {
  1045. /* We scan the starting word in two parts */
  1046. if (i == 0)
  1047. /* 1st time: start in the middle */
  1048. bit_idx = start_bit_idx;
  1049. else
  1050. /* 2nd time: mask bits done already */
  1051. bit_idx &= (1UL << start_bit_idx) - 1;
  1052. }
  1053. do {
  1054. unsigned long bits;
  1055. int port, irq;
  1056. struct irq_desc *desc;
  1057. bits = MASK_LSBS(pending_bits, bit_idx);
  1058. /* If we masked out all events, move on. */
  1059. if (bits == 0)
  1060. break;
  1061. bit_idx = __ffs(bits);
  1062. /* Process port. */
  1063. port = (word_idx * BITS_PER_LONG) + bit_idx;
  1064. irq = evtchn_to_irq[port];
  1065. if (irq != -1) {
  1066. desc = irq_to_desc(irq);
  1067. if (desc)
  1068. generic_handle_irq_desc(irq, desc);
  1069. }
  1070. bit_idx = (bit_idx + 1) % BITS_PER_LONG;
  1071. /* Next caller starts at last processed + 1 */
  1072. __this_cpu_write(current_word_idx,
  1073. bit_idx ? word_idx :
  1074. (word_idx+1) % BITS_PER_LONG);
  1075. __this_cpu_write(current_bit_idx, bit_idx);
  1076. } while (bit_idx != 0);
  1077. /* Scan start_l1i twice; all others once. */
  1078. if ((word_idx != start_word_idx) || (i != 0))
  1079. pending_words &= ~(1UL << word_idx);
  1080. word_idx = (word_idx + 1) % BITS_PER_LONG;
  1081. }
  1082. BUG_ON(!irqs_disabled());
  1083. count = __this_cpu_read(xed_nesting_count);
  1084. __this_cpu_write(xed_nesting_count, 0);
  1085. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  1086. out:
  1087. put_cpu();
  1088. }
  1089. void xen_evtchn_do_upcall(struct pt_regs *regs)
  1090. {
  1091. struct pt_regs *old_regs = set_irq_regs(regs);
  1092. exit_idle();
  1093. irq_enter();
  1094. __xen_evtchn_do_upcall();
  1095. irq_exit();
  1096. set_irq_regs(old_regs);
  1097. }
  1098. void xen_hvm_evtchn_do_upcall(void)
  1099. {
  1100. __xen_evtchn_do_upcall();
  1101. }
  1102. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  1103. /* Rebind a new event channel to an existing irq. */
  1104. void rebind_evtchn_irq(int evtchn, int irq)
  1105. {
  1106. struct irq_info *info = info_for_irq(irq);
  1107. /* Make sure the irq is masked, since the new event channel
  1108. will also be masked. */
  1109. disable_irq(irq);
  1110. mutex_lock(&irq_mapping_update_lock);
  1111. /* After resume the irq<->evtchn mappings are all cleared out */
  1112. BUG_ON(evtchn_to_irq[evtchn] != -1);
  1113. /* Expect irq to have been bound before,
  1114. so there should be a proper type */
  1115. BUG_ON(info->type == IRQT_UNBOUND);
  1116. xen_irq_info_evtchn_init(irq, evtchn);
  1117. mutex_unlock(&irq_mapping_update_lock);
  1118. /* new event channels are always bound to cpu 0 */
  1119. irq_set_affinity(irq, cpumask_of(0));
  1120. /* Unmask the event channel. */
  1121. enable_irq(irq);
  1122. }
  1123. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1124. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1125. {
  1126. struct evtchn_bind_vcpu bind_vcpu;
  1127. int evtchn = evtchn_from_irq(irq);
  1128. if (!VALID_EVTCHN(evtchn))
  1129. return -1;
  1130. /*
  1131. * Events delivered via platform PCI interrupts are always
  1132. * routed to vcpu 0 and hence cannot be rebound.
  1133. */
  1134. if (xen_hvm_domain() && !xen_have_vector_callback)
  1135. return -1;
  1136. /* Send future instances of this interrupt to other vcpu. */
  1137. bind_vcpu.port = evtchn;
  1138. bind_vcpu.vcpu = tcpu;
  1139. /*
  1140. * If this fails, it usually just indicates that we're dealing with a
  1141. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1142. * it, but don't do the xenlinux-level rebind in that case.
  1143. */
  1144. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1145. bind_evtchn_to_cpu(evtchn, tcpu);
  1146. return 0;
  1147. }
  1148. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1149. bool force)
  1150. {
  1151. unsigned tcpu = cpumask_first(dest);
  1152. return rebind_irq_to_cpu(data->irq, tcpu);
  1153. }
  1154. int resend_irq_on_evtchn(unsigned int irq)
  1155. {
  1156. int masked, evtchn = evtchn_from_irq(irq);
  1157. struct shared_info *s = HYPERVISOR_shared_info;
  1158. if (!VALID_EVTCHN(evtchn))
  1159. return 1;
  1160. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  1161. sync_set_bit(evtchn, s->evtchn_pending);
  1162. if (!masked)
  1163. unmask_evtchn(evtchn);
  1164. return 1;
  1165. }
  1166. static void enable_dynirq(struct irq_data *data)
  1167. {
  1168. int evtchn = evtchn_from_irq(data->irq);
  1169. if (VALID_EVTCHN(evtchn))
  1170. unmask_evtchn(evtchn);
  1171. }
  1172. static void disable_dynirq(struct irq_data *data)
  1173. {
  1174. int evtchn = evtchn_from_irq(data->irq);
  1175. if (VALID_EVTCHN(evtchn))
  1176. mask_evtchn(evtchn);
  1177. }
  1178. static void ack_dynirq(struct irq_data *data)
  1179. {
  1180. int evtchn = evtchn_from_irq(data->irq);
  1181. irq_move_irq(data);
  1182. if (VALID_EVTCHN(evtchn))
  1183. clear_evtchn(evtchn);
  1184. }
  1185. static void mask_ack_dynirq(struct irq_data *data)
  1186. {
  1187. disable_dynirq(data);
  1188. ack_dynirq(data);
  1189. }
  1190. static int retrigger_dynirq(struct irq_data *data)
  1191. {
  1192. int evtchn = evtchn_from_irq(data->irq);
  1193. struct shared_info *sh = HYPERVISOR_shared_info;
  1194. int ret = 0;
  1195. if (VALID_EVTCHN(evtchn)) {
  1196. int masked;
  1197. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1198. sync_set_bit(evtchn, sh->evtchn_pending);
  1199. if (!masked)
  1200. unmask_evtchn(evtchn);
  1201. ret = 1;
  1202. }
  1203. return ret;
  1204. }
  1205. static void restore_pirqs(void)
  1206. {
  1207. int pirq, rc, irq, gsi;
  1208. struct physdev_map_pirq map_irq;
  1209. struct irq_info *info;
  1210. list_for_each_entry(info, &xen_irq_list_head, list) {
  1211. if (info->type != IRQT_PIRQ)
  1212. continue;
  1213. pirq = info->u.pirq.pirq;
  1214. gsi = info->u.pirq.gsi;
  1215. irq = info->irq;
  1216. /* save/restore of PT devices doesn't work, so at this point the
  1217. * only devices present are GSI based emulated devices */
  1218. if (!gsi)
  1219. continue;
  1220. map_irq.domid = DOMID_SELF;
  1221. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1222. map_irq.index = gsi;
  1223. map_irq.pirq = pirq;
  1224. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1225. if (rc) {
  1226. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1227. gsi, irq, pirq, rc);
  1228. xen_free_irq(irq);
  1229. continue;
  1230. }
  1231. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1232. __startup_pirq(irq);
  1233. }
  1234. }
  1235. static void restore_cpu_virqs(unsigned int cpu)
  1236. {
  1237. struct evtchn_bind_virq bind_virq;
  1238. int virq, irq, evtchn;
  1239. for (virq = 0; virq < NR_VIRQS; virq++) {
  1240. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1241. continue;
  1242. BUG_ON(virq_from_irq(irq) != virq);
  1243. /* Get a new binding from Xen. */
  1244. bind_virq.virq = virq;
  1245. bind_virq.vcpu = cpu;
  1246. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1247. &bind_virq) != 0)
  1248. BUG();
  1249. evtchn = bind_virq.port;
  1250. /* Record the new mapping. */
  1251. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1252. bind_evtchn_to_cpu(evtchn, cpu);
  1253. }
  1254. }
  1255. static void restore_cpu_ipis(unsigned int cpu)
  1256. {
  1257. struct evtchn_bind_ipi bind_ipi;
  1258. int ipi, irq, evtchn;
  1259. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1260. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1261. continue;
  1262. BUG_ON(ipi_from_irq(irq) != ipi);
  1263. /* Get a new binding from Xen. */
  1264. bind_ipi.vcpu = cpu;
  1265. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1266. &bind_ipi) != 0)
  1267. BUG();
  1268. evtchn = bind_ipi.port;
  1269. /* Record the new mapping. */
  1270. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1271. bind_evtchn_to_cpu(evtchn, cpu);
  1272. }
  1273. }
  1274. /* Clear an irq's pending state, in preparation for polling on it */
  1275. void xen_clear_irq_pending(int irq)
  1276. {
  1277. int evtchn = evtchn_from_irq(irq);
  1278. if (VALID_EVTCHN(evtchn))
  1279. clear_evtchn(evtchn);
  1280. }
  1281. EXPORT_SYMBOL(xen_clear_irq_pending);
  1282. void xen_set_irq_pending(int irq)
  1283. {
  1284. int evtchn = evtchn_from_irq(irq);
  1285. if (VALID_EVTCHN(evtchn))
  1286. set_evtchn(evtchn);
  1287. }
  1288. bool xen_test_irq_pending(int irq)
  1289. {
  1290. int evtchn = evtchn_from_irq(irq);
  1291. bool ret = false;
  1292. if (VALID_EVTCHN(evtchn))
  1293. ret = test_evtchn(evtchn);
  1294. return ret;
  1295. }
  1296. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1297. * the irq will be disabled so it won't deliver an interrupt. */
  1298. void xen_poll_irq_timeout(int irq, u64 timeout)
  1299. {
  1300. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1301. if (VALID_EVTCHN(evtchn)) {
  1302. struct sched_poll poll;
  1303. poll.nr_ports = 1;
  1304. poll.timeout = timeout;
  1305. set_xen_guest_handle(poll.ports, &evtchn);
  1306. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1307. BUG();
  1308. }
  1309. }
  1310. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1311. /* Poll waiting for an irq to become pending. In the usual case, the
  1312. * irq will be disabled so it won't deliver an interrupt. */
  1313. void xen_poll_irq(int irq)
  1314. {
  1315. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1316. }
  1317. /* Check whether the IRQ line is shared with other guests. */
  1318. int xen_test_irq_shared(int irq)
  1319. {
  1320. struct irq_info *info = info_for_irq(irq);
  1321. struct physdev_irq_status_query irq_status = { .irq = info->u.pirq.pirq };
  1322. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1323. return 0;
  1324. return !(irq_status.flags & XENIRQSTAT_shared);
  1325. }
  1326. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1327. void xen_irq_resume(void)
  1328. {
  1329. unsigned int cpu, evtchn;
  1330. struct irq_info *info;
  1331. init_evtchn_cpu_bindings();
  1332. /* New event-channel space is not 'live' yet. */
  1333. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1334. mask_evtchn(evtchn);
  1335. /* No IRQ <-> event-channel mappings. */
  1336. list_for_each_entry(info, &xen_irq_list_head, list)
  1337. info->evtchn = 0; /* zap event-channel binding */
  1338. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1339. evtchn_to_irq[evtchn] = -1;
  1340. for_each_possible_cpu(cpu) {
  1341. restore_cpu_virqs(cpu);
  1342. restore_cpu_ipis(cpu);
  1343. }
  1344. restore_pirqs();
  1345. }
  1346. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1347. .name = "xen-dyn",
  1348. .irq_disable = disable_dynirq,
  1349. .irq_mask = disable_dynirq,
  1350. .irq_unmask = enable_dynirq,
  1351. .irq_ack = ack_dynirq,
  1352. .irq_mask_ack = mask_ack_dynirq,
  1353. .irq_set_affinity = set_affinity_irq,
  1354. .irq_retrigger = retrigger_dynirq,
  1355. };
  1356. static struct irq_chip xen_pirq_chip __read_mostly = {
  1357. .name = "xen-pirq",
  1358. .irq_startup = startup_pirq,
  1359. .irq_shutdown = shutdown_pirq,
  1360. .irq_enable = enable_pirq,
  1361. .irq_disable = disable_pirq,
  1362. .irq_mask = disable_dynirq,
  1363. .irq_unmask = enable_dynirq,
  1364. .irq_ack = eoi_pirq,
  1365. .irq_eoi = eoi_pirq,
  1366. .irq_mask_ack = mask_ack_pirq,
  1367. .irq_set_affinity = set_affinity_irq,
  1368. .irq_retrigger = retrigger_dynirq,
  1369. };
  1370. static struct irq_chip xen_percpu_chip __read_mostly = {
  1371. .name = "xen-percpu",
  1372. .irq_disable = disable_dynirq,
  1373. .irq_mask = disable_dynirq,
  1374. .irq_unmask = enable_dynirq,
  1375. .irq_ack = ack_dynirq,
  1376. };
  1377. int xen_set_callback_via(uint64_t via)
  1378. {
  1379. struct xen_hvm_param a;
  1380. a.domid = DOMID_SELF;
  1381. a.index = HVM_PARAM_CALLBACK_IRQ;
  1382. a.value = via;
  1383. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1384. }
  1385. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1386. #ifdef CONFIG_XEN_PVHVM
  1387. /* Vector callbacks are better than PCI interrupts to receive event
  1388. * channel notifications because we can receive vector callbacks on any
  1389. * vcpu and we don't need PCI support or APIC interactions. */
  1390. void xen_callback_vector(void)
  1391. {
  1392. int rc;
  1393. uint64_t callback_via;
  1394. if (xen_have_vector_callback) {
  1395. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1396. rc = xen_set_callback_via(callback_via);
  1397. if (rc) {
  1398. printk(KERN_ERR "Request for Xen HVM callback vector"
  1399. " failed.\n");
  1400. xen_have_vector_callback = 0;
  1401. return;
  1402. }
  1403. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1404. "enabled\n");
  1405. /* in the restore case the vector has already been allocated */
  1406. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1407. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1408. }
  1409. }
  1410. #else
  1411. void xen_callback_vector(void) {}
  1412. #endif
  1413. void __init xen_init_IRQ(void)
  1414. {
  1415. int i, rc;
  1416. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1417. GFP_KERNEL);
  1418. BUG_ON(!evtchn_to_irq);
  1419. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1420. evtchn_to_irq[i] = -1;
  1421. init_evtchn_cpu_bindings();
  1422. /* No event channels are 'live' right now. */
  1423. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1424. mask_evtchn(i);
  1425. pirq_needs_eoi = pirq_needs_eoi_flag;
  1426. if (xen_hvm_domain()) {
  1427. xen_callback_vector();
  1428. native_init_IRQ();
  1429. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1430. * __acpi_register_gsi can point at the right function */
  1431. pci_xen_hvm_init();
  1432. } else {
  1433. struct physdev_pirq_eoi_gmfn eoi_gmfn;
  1434. irq_ctx_init(smp_processor_id());
  1435. if (xen_initial_domain())
  1436. pci_xen_initial_domain();
  1437. pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
  1438. eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
  1439. rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
  1440. if (rc != 0) {
  1441. free_page((unsigned long) pirq_eoi_map);
  1442. pirq_eoi_map = NULL;
  1443. } else
  1444. pirq_needs_eoi = pirq_check_eoi_map;
  1445. }
  1446. }