dpi.c 8.3 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dpi.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "DPI"
  23. #include <linux/kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/export.h>
  26. #include <linux/err.h>
  27. #include <linux/errno.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <video/omapdss.h>
  31. #include <plat/cpu.h>
  32. #include "dss.h"
  33. static struct {
  34. struct regulator *vdds_dsi_reg;
  35. struct platform_device *dsidev;
  36. } dpi;
  37. static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
  38. {
  39. int dsi_module;
  40. dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
  41. return dsi_get_dsidev_from_id(dsi_module);
  42. }
  43. static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
  44. {
  45. if (dssdev->clocks.dispc.dispc_fclk_src ==
  46. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  47. dssdev->clocks.dispc.dispc_fclk_src ==
  48. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
  49. dssdev->clocks.dispc.channel.lcd_clk_src ==
  50. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
  51. dssdev->clocks.dispc.channel.lcd_clk_src ==
  52. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
  53. return true;
  54. else
  55. return false;
  56. }
  57. static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
  58. unsigned long pck_req, unsigned long *fck, int *lck_div,
  59. int *pck_div)
  60. {
  61. struct dsi_clock_info dsi_cinfo;
  62. struct dispc_clock_info dispc_cinfo;
  63. int r;
  64. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
  65. &dsi_cinfo, &dispc_cinfo);
  66. if (r)
  67. return r;
  68. r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
  69. if (r)
  70. return r;
  71. dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
  72. r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  73. if (r) {
  74. dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
  75. return r;
  76. }
  77. *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  78. *lck_div = dispc_cinfo.lck_div;
  79. *pck_div = dispc_cinfo.pck_div;
  80. return 0;
  81. }
  82. static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
  83. unsigned long pck_req, unsigned long *fck, int *lck_div,
  84. int *pck_div)
  85. {
  86. struct dss_clock_info dss_cinfo;
  87. struct dispc_clock_info dispc_cinfo;
  88. int r;
  89. r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
  90. if (r)
  91. return r;
  92. r = dss_set_clock_div(&dss_cinfo);
  93. if (r)
  94. return r;
  95. r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
  96. if (r)
  97. return r;
  98. *fck = dss_cinfo.fck;
  99. *lck_div = dispc_cinfo.lck_div;
  100. *pck_div = dispc_cinfo.pck_div;
  101. return 0;
  102. }
  103. static int dpi_set_mode(struct omap_dss_device *dssdev)
  104. {
  105. struct omap_video_timings *t = &dssdev->panel.timings;
  106. int lck_div = 0, pck_div = 0;
  107. unsigned long fck = 0;
  108. unsigned long pck;
  109. bool is_tft;
  110. int r = 0;
  111. dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
  112. dssdev->panel.acbi, dssdev->panel.acb);
  113. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  114. if (dpi_use_dsi_pll(dssdev))
  115. r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
  116. &fck, &lck_div, &pck_div);
  117. else
  118. r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
  119. &fck, &lck_div, &pck_div);
  120. if (r)
  121. return r;
  122. pck = fck / lck_div / pck_div / 1000;
  123. if (pck != t->pixel_clock) {
  124. DSSWARN("Could not find exact pixel clock. "
  125. "Requested %d kHz, got %lu kHz\n",
  126. t->pixel_clock, pck);
  127. t->pixel_clock = pck;
  128. }
  129. dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
  130. return 0;
  131. }
  132. static void dpi_basic_init(struct omap_dss_device *dssdev)
  133. {
  134. bool is_tft;
  135. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  136. dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
  137. dispc_mgr_enable_stallmode(dssdev->manager->id, false);
  138. dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
  139. OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
  140. dispc_mgr_set_tft_data_lines(dssdev->manager->id,
  141. dssdev->phy.dpi.data_lines);
  142. }
  143. int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
  144. {
  145. int r;
  146. if (cpu_is_omap34xx() && !dpi.vdds_dsi_reg) {
  147. DSSERR("no VDSS_DSI regulator\n");
  148. return -ENODEV;
  149. }
  150. if (dssdev->manager == NULL) {
  151. DSSERR("failed to enable display: no manager\n");
  152. return -ENODEV;
  153. }
  154. r = omap_dss_start_device(dssdev);
  155. if (r) {
  156. DSSERR("failed to start device\n");
  157. goto err_start_dev;
  158. }
  159. if (cpu_is_omap34xx()) {
  160. r = regulator_enable(dpi.vdds_dsi_reg);
  161. if (r)
  162. goto err_reg_enable;
  163. }
  164. r = dss_runtime_get();
  165. if (r)
  166. goto err_get_dss;
  167. r = dispc_runtime_get();
  168. if (r)
  169. goto err_get_dispc;
  170. dpi_basic_init(dssdev);
  171. if (dpi_use_dsi_pll(dssdev)) {
  172. r = dsi_runtime_get(dpi.dsidev);
  173. if (r)
  174. goto err_get_dsi;
  175. r = dsi_pll_init(dpi.dsidev, 0, 1);
  176. if (r)
  177. goto err_dsi_pll_init;
  178. }
  179. r = dpi_set_mode(dssdev);
  180. if (r)
  181. goto err_set_mode;
  182. mdelay(2);
  183. r = dss_mgr_enable(dssdev->manager);
  184. if (r)
  185. goto err_mgr_enable;
  186. return 0;
  187. err_mgr_enable:
  188. err_set_mode:
  189. if (dpi_use_dsi_pll(dssdev))
  190. dsi_pll_uninit(dpi.dsidev, true);
  191. err_dsi_pll_init:
  192. if (dpi_use_dsi_pll(dssdev))
  193. dsi_runtime_put(dpi.dsidev);
  194. err_get_dsi:
  195. dispc_runtime_put();
  196. err_get_dispc:
  197. dss_runtime_put();
  198. err_get_dss:
  199. if (cpu_is_omap34xx())
  200. regulator_disable(dpi.vdds_dsi_reg);
  201. err_reg_enable:
  202. omap_dss_stop_device(dssdev);
  203. err_start_dev:
  204. return r;
  205. }
  206. EXPORT_SYMBOL(omapdss_dpi_display_enable);
  207. void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
  208. {
  209. dss_mgr_disable(dssdev->manager);
  210. if (dpi_use_dsi_pll(dssdev)) {
  211. dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
  212. dsi_pll_uninit(dpi.dsidev, true);
  213. dsi_runtime_put(dpi.dsidev);
  214. }
  215. dispc_runtime_put();
  216. dss_runtime_put();
  217. if (cpu_is_omap34xx())
  218. regulator_disable(dpi.vdds_dsi_reg);
  219. omap_dss_stop_device(dssdev);
  220. }
  221. EXPORT_SYMBOL(omapdss_dpi_display_disable);
  222. void dpi_set_timings(struct omap_dss_device *dssdev,
  223. struct omap_video_timings *timings)
  224. {
  225. int r;
  226. DSSDBG("dpi_set_timings\n");
  227. dssdev->panel.timings = *timings;
  228. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  229. r = dss_runtime_get();
  230. if (r)
  231. return;
  232. r = dispc_runtime_get();
  233. if (r) {
  234. dss_runtime_put();
  235. return;
  236. }
  237. dpi_set_mode(dssdev);
  238. dispc_mgr_go(dssdev->manager->id);
  239. dispc_runtime_put();
  240. dss_runtime_put();
  241. }
  242. }
  243. EXPORT_SYMBOL(dpi_set_timings);
  244. int dpi_check_timings(struct omap_dss_device *dssdev,
  245. struct omap_video_timings *timings)
  246. {
  247. bool is_tft;
  248. int r;
  249. int lck_div, pck_div;
  250. unsigned long fck;
  251. unsigned long pck;
  252. struct dispc_clock_info dispc_cinfo;
  253. if (!dispc_lcd_timings_ok(timings))
  254. return -EINVAL;
  255. if (timings->pixel_clock == 0)
  256. return -EINVAL;
  257. is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
  258. if (dpi_use_dsi_pll(dssdev)) {
  259. struct dsi_clock_info dsi_cinfo;
  260. r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
  261. timings->pixel_clock * 1000,
  262. &dsi_cinfo, &dispc_cinfo);
  263. if (r)
  264. return r;
  265. fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
  266. } else {
  267. struct dss_clock_info dss_cinfo;
  268. r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
  269. &dss_cinfo, &dispc_cinfo);
  270. if (r)
  271. return r;
  272. fck = dss_cinfo.fck;
  273. }
  274. lck_div = dispc_cinfo.lck_div;
  275. pck_div = dispc_cinfo.pck_div;
  276. pck = fck / lck_div / pck_div / 1000;
  277. timings->pixel_clock = pck;
  278. return 0;
  279. }
  280. EXPORT_SYMBOL(dpi_check_timings);
  281. int dpi_init_display(struct omap_dss_device *dssdev)
  282. {
  283. DSSDBG("init_display\n");
  284. if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
  285. struct regulator *vdds_dsi;
  286. vdds_dsi = dss_get_vdds_dsi();
  287. if (IS_ERR(vdds_dsi)) {
  288. DSSERR("can't get VDDS_DSI regulator\n");
  289. return PTR_ERR(vdds_dsi);
  290. }
  291. dpi.vdds_dsi_reg = vdds_dsi;
  292. }
  293. if (dpi_use_dsi_pll(dssdev)) {
  294. enum omap_dss_clk_source dispc_fclk_src =
  295. dssdev->clocks.dispc.dispc_fclk_src;
  296. dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
  297. }
  298. return 0;
  299. }
  300. int dpi_init(void)
  301. {
  302. return 0;
  303. }
  304. void dpi_exit(void)
  305. {
  306. }