panel-n8x0.c 16 KB

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  1. /* #define DEBUG */
  2. #include <linux/module.h>
  3. #include <linux/delay.h>
  4. #include <linux/slab.h>
  5. #include <linux/gpio.h>
  6. #include <linux/spi/spi.h>
  7. #include <linux/backlight.h>
  8. #include <linux/fb.h>
  9. #include <video/omapdss.h>
  10. #include <video/omap-panel-n8x0.h>
  11. #define BLIZZARD_REV_CODE 0x00
  12. #define BLIZZARD_CONFIG 0x02
  13. #define BLIZZARD_PLL_DIV 0x04
  14. #define BLIZZARD_PLL_LOCK_RANGE 0x06
  15. #define BLIZZARD_PLL_CLOCK_SYNTH_0 0x08
  16. #define BLIZZARD_PLL_CLOCK_SYNTH_1 0x0a
  17. #define BLIZZARD_PLL_MODE 0x0c
  18. #define BLIZZARD_CLK_SRC 0x0e
  19. #define BLIZZARD_MEM_BANK0_ACTIVATE 0x10
  20. #define BLIZZARD_MEM_BANK0_STATUS 0x14
  21. #define BLIZZARD_PANEL_CONFIGURATION 0x28
  22. #define BLIZZARD_HDISP 0x2a
  23. #define BLIZZARD_HNDP 0x2c
  24. #define BLIZZARD_VDISP0 0x2e
  25. #define BLIZZARD_VDISP1 0x30
  26. #define BLIZZARD_VNDP 0x32
  27. #define BLIZZARD_HSW 0x34
  28. #define BLIZZARD_VSW 0x38
  29. #define BLIZZARD_DISPLAY_MODE 0x68
  30. #define BLIZZARD_INPUT_WIN_X_START_0 0x6c
  31. #define BLIZZARD_DATA_SOURCE_SELECT 0x8e
  32. #define BLIZZARD_DISP_MEM_DATA_PORT 0x90
  33. #define BLIZZARD_DISP_MEM_READ_ADDR0 0x92
  34. #define BLIZZARD_POWER_SAVE 0xE6
  35. #define BLIZZARD_NDISP_CTRL_STATUS 0xE8
  36. /* Data source select */
  37. /* For S1D13745 */
  38. #define BLIZZARD_SRC_WRITE_LCD_BACKGROUND 0x00
  39. #define BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE 0x01
  40. #define BLIZZARD_SRC_WRITE_OVERLAY_ENABLE 0x04
  41. #define BLIZZARD_SRC_DISABLE_OVERLAY 0x05
  42. /* For S1D13744 */
  43. #define BLIZZARD_SRC_WRITE_LCD 0x00
  44. #define BLIZZARD_SRC_BLT_LCD 0x06
  45. #define BLIZZARD_COLOR_RGB565 0x01
  46. #define BLIZZARD_COLOR_YUV420 0x09
  47. #define BLIZZARD_VERSION_S1D13745 0x01 /* Hailstorm */
  48. #define BLIZZARD_VERSION_S1D13744 0x02 /* Blizzard */
  49. #define MIPID_CMD_READ_DISP_ID 0x04
  50. #define MIPID_CMD_READ_RED 0x06
  51. #define MIPID_CMD_READ_GREEN 0x07
  52. #define MIPID_CMD_READ_BLUE 0x08
  53. #define MIPID_CMD_READ_DISP_STATUS 0x09
  54. #define MIPID_CMD_RDDSDR 0x0F
  55. #define MIPID_CMD_SLEEP_IN 0x10
  56. #define MIPID_CMD_SLEEP_OUT 0x11
  57. #define MIPID_CMD_DISP_OFF 0x28
  58. #define MIPID_CMD_DISP_ON 0x29
  59. static struct panel_drv_data {
  60. struct mutex lock;
  61. struct omap_dss_device *dssdev;
  62. struct spi_device *spidev;
  63. struct backlight_device *bldev;
  64. int blizzard_ver;
  65. } s_drv_data;
  66. static inline
  67. struct panel_n8x0_data *get_board_data(const struct omap_dss_device *dssdev)
  68. {
  69. return dssdev->data;
  70. }
  71. static inline
  72. struct panel_drv_data *get_drv_data(const struct omap_dss_device *dssdev)
  73. {
  74. return &s_drv_data;
  75. }
  76. static inline void blizzard_cmd(u8 cmd)
  77. {
  78. omap_rfbi_write_command(&cmd, 1);
  79. }
  80. static inline void blizzard_write(u8 cmd, const u8 *buf, int len)
  81. {
  82. omap_rfbi_write_command(&cmd, 1);
  83. omap_rfbi_write_data(buf, len);
  84. }
  85. static inline void blizzard_read(u8 cmd, u8 *buf, int len)
  86. {
  87. omap_rfbi_write_command(&cmd, 1);
  88. omap_rfbi_read_data(buf, len);
  89. }
  90. static u8 blizzard_read_reg(u8 cmd)
  91. {
  92. u8 data;
  93. blizzard_read(cmd, &data, 1);
  94. return data;
  95. }
  96. static void blizzard_ctrl_setup_update(struct omap_dss_device *dssdev,
  97. int x, int y, int w, int h)
  98. {
  99. struct panel_drv_data *ddata = get_drv_data(dssdev);
  100. u8 tmp[18];
  101. int x_end, y_end;
  102. x_end = x + w - 1;
  103. y_end = y + h - 1;
  104. tmp[0] = x;
  105. tmp[1] = x >> 8;
  106. tmp[2] = y;
  107. tmp[3] = y >> 8;
  108. tmp[4] = x_end;
  109. tmp[5] = x_end >> 8;
  110. tmp[6] = y_end;
  111. tmp[7] = y_end >> 8;
  112. /* scaling? */
  113. tmp[8] = x;
  114. tmp[9] = x >> 8;
  115. tmp[10] = y;
  116. tmp[11] = y >> 8;
  117. tmp[12] = x_end;
  118. tmp[13] = x_end >> 8;
  119. tmp[14] = y_end;
  120. tmp[15] = y_end >> 8;
  121. tmp[16] = BLIZZARD_COLOR_RGB565;
  122. if (ddata->blizzard_ver == BLIZZARD_VERSION_S1D13745)
  123. tmp[17] = BLIZZARD_SRC_WRITE_LCD_BACKGROUND;
  124. else
  125. tmp[17] = ddata->blizzard_ver == BLIZZARD_VERSION_S1D13744 ?
  126. BLIZZARD_SRC_WRITE_LCD :
  127. BLIZZARD_SRC_WRITE_LCD_DESTRUCTIVE;
  128. omap_rfbi_configure(dssdev, 16, 8);
  129. blizzard_write(BLIZZARD_INPUT_WIN_X_START_0, tmp, 18);
  130. omap_rfbi_configure(dssdev, 16, 16);
  131. }
  132. static void mipid_transfer(struct spi_device *spi, int cmd, const u8 *wbuf,
  133. int wlen, u8 *rbuf, int rlen)
  134. {
  135. struct spi_message m;
  136. struct spi_transfer *x, xfer[4];
  137. u16 w;
  138. int r;
  139. spi_message_init(&m);
  140. memset(xfer, 0, sizeof(xfer));
  141. x = &xfer[0];
  142. cmd &= 0xff;
  143. x->tx_buf = &cmd;
  144. x->bits_per_word = 9;
  145. x->len = 2;
  146. spi_message_add_tail(x, &m);
  147. if (wlen) {
  148. x++;
  149. x->tx_buf = wbuf;
  150. x->len = wlen;
  151. x->bits_per_word = 9;
  152. spi_message_add_tail(x, &m);
  153. }
  154. if (rlen) {
  155. x++;
  156. x->rx_buf = &w;
  157. x->len = 1;
  158. spi_message_add_tail(x, &m);
  159. if (rlen > 1) {
  160. /* Arrange for the extra clock before the first
  161. * data bit.
  162. */
  163. x->bits_per_word = 9;
  164. x->len = 2;
  165. x++;
  166. x->rx_buf = &rbuf[1];
  167. x->len = rlen - 1;
  168. spi_message_add_tail(x, &m);
  169. }
  170. }
  171. r = spi_sync(spi, &m);
  172. if (r < 0)
  173. dev_dbg(&spi->dev, "spi_sync %d\n", r);
  174. if (rlen)
  175. rbuf[0] = w & 0xff;
  176. }
  177. static inline void mipid_cmd(struct spi_device *spi, int cmd)
  178. {
  179. mipid_transfer(spi, cmd, NULL, 0, NULL, 0);
  180. }
  181. static inline void mipid_write(struct spi_device *spi,
  182. int reg, const u8 *buf, int len)
  183. {
  184. mipid_transfer(spi, reg, buf, len, NULL, 0);
  185. }
  186. static inline void mipid_read(struct spi_device *spi,
  187. int reg, u8 *buf, int len)
  188. {
  189. mipid_transfer(spi, reg, NULL, 0, buf, len);
  190. }
  191. static void set_data_lines(struct spi_device *spi, int data_lines)
  192. {
  193. u16 par;
  194. switch (data_lines) {
  195. case 16:
  196. par = 0x150;
  197. break;
  198. case 18:
  199. par = 0x160;
  200. break;
  201. case 24:
  202. par = 0x170;
  203. break;
  204. }
  205. mipid_write(spi, 0x3a, (u8 *)&par, 2);
  206. }
  207. static void send_init_string(struct spi_device *spi)
  208. {
  209. u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
  210. mipid_write(spi, 0xc2, (u8 *)initpar, sizeof(initpar));
  211. }
  212. static void send_display_on(struct spi_device *spi)
  213. {
  214. mipid_cmd(spi, MIPID_CMD_DISP_ON);
  215. }
  216. static void send_display_off(struct spi_device *spi)
  217. {
  218. mipid_cmd(spi, MIPID_CMD_DISP_OFF);
  219. }
  220. static void send_sleep_out(struct spi_device *spi)
  221. {
  222. mipid_cmd(spi, MIPID_CMD_SLEEP_OUT);
  223. msleep(120);
  224. }
  225. static void send_sleep_in(struct spi_device *spi)
  226. {
  227. mipid_cmd(spi, MIPID_CMD_SLEEP_IN);
  228. msleep(50);
  229. }
  230. static int n8x0_panel_power_on(struct omap_dss_device *dssdev)
  231. {
  232. int r;
  233. struct panel_n8x0_data *bdata = get_board_data(dssdev);
  234. struct panel_drv_data *ddata = get_drv_data(dssdev);
  235. struct spi_device *spi = ddata->spidev;
  236. u8 rev, conf;
  237. u8 display_id[3];
  238. const char *panel_name;
  239. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
  240. return 0;
  241. gpio_direction_output(bdata->ctrl_pwrdown, 1);
  242. if (bdata->platform_enable) {
  243. r = bdata->platform_enable(dssdev);
  244. if (r)
  245. goto err_plat_en;
  246. }
  247. r = omapdss_rfbi_display_enable(dssdev);
  248. if (r)
  249. goto err_rfbi_en;
  250. rev = blizzard_read_reg(BLIZZARD_REV_CODE);
  251. conf = blizzard_read_reg(BLIZZARD_CONFIG);
  252. switch (rev & 0xfc) {
  253. case 0x9c:
  254. ddata->blizzard_ver = BLIZZARD_VERSION_S1D13744;
  255. dev_info(&dssdev->dev, "s1d13744 LCD controller rev %d "
  256. "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
  257. break;
  258. case 0xa4:
  259. ddata->blizzard_ver = BLIZZARD_VERSION_S1D13745;
  260. dev_info(&dssdev->dev, "s1d13745 LCD controller rev %d "
  261. "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
  262. break;
  263. default:
  264. dev_err(&dssdev->dev, "invalid s1d1374x revision %02x\n", rev);
  265. r = -ENODEV;
  266. goto err_inv_chip;
  267. }
  268. /* panel */
  269. gpio_direction_output(bdata->panel_reset, 1);
  270. mipid_read(spi, MIPID_CMD_READ_DISP_ID, display_id, 3);
  271. dev_dbg(&spi->dev, "MIPI display ID: %02x%02x%02x\n",
  272. display_id[0], display_id[1], display_id[2]);
  273. switch (display_id[0]) {
  274. case 0x45:
  275. panel_name = "lph8923";
  276. break;
  277. case 0x83:
  278. panel_name = "ls041y3";
  279. break;
  280. default:
  281. dev_err(&dssdev->dev, "invalid display ID 0x%x\n",
  282. display_id[0]);
  283. r = -ENODEV;
  284. goto err_inv_panel;
  285. }
  286. dev_info(&dssdev->dev, "%s rev %02x LCD detected\n",
  287. panel_name, display_id[1]);
  288. send_sleep_out(spi);
  289. send_init_string(spi);
  290. set_data_lines(spi, 24);
  291. send_display_on(spi);
  292. return 0;
  293. err_inv_panel:
  294. /*
  295. * HACK: we should turn off the panel here, but there is some problem
  296. * with the initialization sequence, and we fail to init the panel if we
  297. * have turned it off
  298. */
  299. /* gpio_direction_output(bdata->panel_reset, 0); */
  300. err_inv_chip:
  301. omapdss_rfbi_display_disable(dssdev);
  302. err_rfbi_en:
  303. if (bdata->platform_disable)
  304. bdata->platform_disable(dssdev);
  305. err_plat_en:
  306. gpio_direction_output(bdata->ctrl_pwrdown, 0);
  307. return r;
  308. }
  309. static void n8x0_panel_power_off(struct omap_dss_device *dssdev)
  310. {
  311. struct panel_n8x0_data *bdata = get_board_data(dssdev);
  312. struct panel_drv_data *ddata = get_drv_data(dssdev);
  313. struct spi_device *spi = ddata->spidev;
  314. if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
  315. return;
  316. send_display_off(spi);
  317. send_sleep_in(spi);
  318. if (bdata->platform_disable)
  319. bdata->platform_disable(dssdev);
  320. /*
  321. * HACK: we should turn off the panel here, but there is some problem
  322. * with the initialization sequence, and we fail to init the panel if we
  323. * have turned it off
  324. */
  325. /* gpio_direction_output(bdata->panel_reset, 0); */
  326. gpio_direction_output(bdata->ctrl_pwrdown, 0);
  327. omapdss_rfbi_display_disable(dssdev);
  328. }
  329. static const struct rfbi_timings n8x0_panel_timings = {
  330. .cs_on_time = 0,
  331. .we_on_time = 9000,
  332. .we_off_time = 18000,
  333. .we_cycle_time = 36000,
  334. .re_on_time = 9000,
  335. .re_off_time = 27000,
  336. .re_cycle_time = 36000,
  337. .access_time = 27000,
  338. .cs_off_time = 36000,
  339. .cs_pulse_width = 0,
  340. };
  341. static int n8x0_bl_update_status(struct backlight_device *dev)
  342. {
  343. struct omap_dss_device *dssdev = dev_get_drvdata(&dev->dev);
  344. struct panel_n8x0_data *bdata = get_board_data(dssdev);
  345. struct panel_drv_data *ddata = get_drv_data(dssdev);
  346. int r;
  347. int level;
  348. mutex_lock(&ddata->lock);
  349. if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
  350. dev->props.power == FB_BLANK_UNBLANK)
  351. level = dev->props.brightness;
  352. else
  353. level = 0;
  354. dev_dbg(&dssdev->dev, "update brightness to %d\n", level);
  355. if (!bdata->set_backlight)
  356. r = -EINVAL;
  357. else
  358. r = bdata->set_backlight(dssdev, level);
  359. mutex_unlock(&ddata->lock);
  360. return r;
  361. }
  362. static int n8x0_bl_get_intensity(struct backlight_device *dev)
  363. {
  364. if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
  365. dev->props.power == FB_BLANK_UNBLANK)
  366. return dev->props.brightness;
  367. return 0;
  368. }
  369. static const struct backlight_ops n8x0_bl_ops = {
  370. .get_brightness = n8x0_bl_get_intensity,
  371. .update_status = n8x0_bl_update_status,
  372. };
  373. static int n8x0_panel_probe(struct omap_dss_device *dssdev)
  374. {
  375. struct panel_n8x0_data *bdata = get_board_data(dssdev);
  376. struct panel_drv_data *ddata;
  377. struct backlight_device *bldev;
  378. struct backlight_properties props;
  379. int r;
  380. dev_dbg(&dssdev->dev, "probe\n");
  381. if (!bdata)
  382. return -EINVAL;
  383. s_drv_data.dssdev = dssdev;
  384. ddata = &s_drv_data;
  385. mutex_init(&ddata->lock);
  386. dssdev->panel.config = OMAP_DSS_LCD_TFT;
  387. dssdev->panel.timings.x_res = 800;
  388. dssdev->panel.timings.y_res = 480;
  389. dssdev->ctrl.pixel_size = 16;
  390. dssdev->ctrl.rfbi_timings = n8x0_panel_timings;
  391. memset(&props, 0, sizeof(props));
  392. props.max_brightness = 127;
  393. props.type = BACKLIGHT_PLATFORM;
  394. bldev = backlight_device_register(dev_name(&dssdev->dev), &dssdev->dev,
  395. dssdev, &n8x0_bl_ops, &props);
  396. if (IS_ERR(bldev)) {
  397. r = PTR_ERR(bldev);
  398. dev_err(&dssdev->dev, "register backlight failed\n");
  399. return r;
  400. }
  401. ddata->bldev = bldev;
  402. bldev->props.fb_blank = FB_BLANK_UNBLANK;
  403. bldev->props.power = FB_BLANK_UNBLANK;
  404. bldev->props.brightness = 127;
  405. n8x0_bl_update_status(bldev);
  406. return 0;
  407. }
  408. static void n8x0_panel_remove(struct omap_dss_device *dssdev)
  409. {
  410. struct panel_drv_data *ddata = get_drv_data(dssdev);
  411. struct backlight_device *bldev;
  412. dev_dbg(&dssdev->dev, "remove\n");
  413. bldev = ddata->bldev;
  414. bldev->props.power = FB_BLANK_POWERDOWN;
  415. n8x0_bl_update_status(bldev);
  416. backlight_device_unregister(bldev);
  417. dev_set_drvdata(&dssdev->dev, NULL);
  418. }
  419. static int n8x0_panel_enable(struct omap_dss_device *dssdev)
  420. {
  421. struct panel_drv_data *ddata = get_drv_data(dssdev);
  422. int r;
  423. dev_dbg(&dssdev->dev, "enable\n");
  424. mutex_lock(&ddata->lock);
  425. rfbi_bus_lock();
  426. r = n8x0_panel_power_on(dssdev);
  427. rfbi_bus_unlock();
  428. if (r) {
  429. mutex_unlock(&ddata->lock);
  430. return r;
  431. }
  432. dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
  433. mutex_unlock(&ddata->lock);
  434. return 0;
  435. }
  436. static void n8x0_panel_disable(struct omap_dss_device *dssdev)
  437. {
  438. struct panel_drv_data *ddata = get_drv_data(dssdev);
  439. dev_dbg(&dssdev->dev, "disable\n");
  440. mutex_lock(&ddata->lock);
  441. rfbi_bus_lock();
  442. n8x0_panel_power_off(dssdev);
  443. rfbi_bus_unlock();
  444. dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
  445. mutex_unlock(&ddata->lock);
  446. }
  447. static int n8x0_panel_suspend(struct omap_dss_device *dssdev)
  448. {
  449. struct panel_drv_data *ddata = get_drv_data(dssdev);
  450. dev_dbg(&dssdev->dev, "suspend\n");
  451. mutex_lock(&ddata->lock);
  452. rfbi_bus_lock();
  453. n8x0_panel_power_off(dssdev);
  454. rfbi_bus_unlock();
  455. dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
  456. mutex_unlock(&ddata->lock);
  457. return 0;
  458. }
  459. static int n8x0_panel_resume(struct omap_dss_device *dssdev)
  460. {
  461. struct panel_drv_data *ddata = get_drv_data(dssdev);
  462. int r;
  463. dev_dbg(&dssdev->dev, "resume\n");
  464. mutex_lock(&ddata->lock);
  465. rfbi_bus_lock();
  466. r = n8x0_panel_power_on(dssdev);
  467. rfbi_bus_unlock();
  468. if (r) {
  469. mutex_unlock(&ddata->lock);
  470. return r;
  471. }
  472. dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
  473. mutex_unlock(&ddata->lock);
  474. return 0;
  475. }
  476. static void n8x0_panel_get_timings(struct omap_dss_device *dssdev,
  477. struct omap_video_timings *timings)
  478. {
  479. *timings = dssdev->panel.timings;
  480. }
  481. static void n8x0_panel_get_resolution(struct omap_dss_device *dssdev,
  482. u16 *xres, u16 *yres)
  483. {
  484. *xres = dssdev->panel.timings.x_res;
  485. *yres = dssdev->panel.timings.y_res;
  486. }
  487. static void update_done(void *data)
  488. {
  489. rfbi_bus_unlock();
  490. }
  491. static int n8x0_panel_update(struct omap_dss_device *dssdev,
  492. u16 x, u16 y, u16 w, u16 h)
  493. {
  494. struct panel_drv_data *ddata = get_drv_data(dssdev);
  495. dev_dbg(&dssdev->dev, "update\n");
  496. mutex_lock(&ddata->lock);
  497. rfbi_bus_lock();
  498. omap_rfbi_prepare_update(dssdev, &x, &y, &w, &h);
  499. blizzard_ctrl_setup_update(dssdev, x, y, w, h);
  500. omap_rfbi_update(dssdev, x, y, w, h, update_done, NULL);
  501. mutex_unlock(&ddata->lock);
  502. return 0;
  503. }
  504. static int n8x0_panel_sync(struct omap_dss_device *dssdev)
  505. {
  506. struct panel_drv_data *ddata = get_drv_data(dssdev);
  507. dev_dbg(&dssdev->dev, "sync\n");
  508. mutex_lock(&ddata->lock);
  509. rfbi_bus_lock();
  510. rfbi_bus_unlock();
  511. mutex_unlock(&ddata->lock);
  512. return 0;
  513. }
  514. static struct omap_dss_driver n8x0_panel_driver = {
  515. .probe = n8x0_panel_probe,
  516. .remove = n8x0_panel_remove,
  517. .enable = n8x0_panel_enable,
  518. .disable = n8x0_panel_disable,
  519. .suspend = n8x0_panel_suspend,
  520. .resume = n8x0_panel_resume,
  521. .update = n8x0_panel_update,
  522. .sync = n8x0_panel_sync,
  523. .get_resolution = n8x0_panel_get_resolution,
  524. .get_recommended_bpp = omapdss_default_get_recommended_bpp,
  525. .get_timings = n8x0_panel_get_timings,
  526. .driver = {
  527. .name = "n8x0_panel",
  528. .owner = THIS_MODULE,
  529. },
  530. };
  531. /* PANEL */
  532. static int mipid_spi_probe(struct spi_device *spi)
  533. {
  534. dev_dbg(&spi->dev, "mipid_spi_probe\n");
  535. spi->mode = SPI_MODE_0;
  536. s_drv_data.spidev = spi;
  537. return 0;
  538. }
  539. static int mipid_spi_remove(struct spi_device *spi)
  540. {
  541. dev_dbg(&spi->dev, "mipid_spi_remove\n");
  542. return 0;
  543. }
  544. static struct spi_driver mipid_spi_driver = {
  545. .driver = {
  546. .name = "lcd_mipid",
  547. .owner = THIS_MODULE,
  548. },
  549. .probe = mipid_spi_probe,
  550. .remove = __devexit_p(mipid_spi_remove),
  551. };
  552. static int __init n8x0_panel_drv_init(void)
  553. {
  554. int r;
  555. r = spi_register_driver(&mipid_spi_driver);
  556. if (r) {
  557. pr_err("n8x0_panel: spi driver registration failed\n");
  558. return r;
  559. }
  560. r = omap_dss_register_driver(&n8x0_panel_driver);
  561. if (r) {
  562. pr_err("n8x0_panel: dss driver registration failed\n");
  563. spi_unregister_driver(&mipid_spi_driver);
  564. return r;
  565. }
  566. return 0;
  567. }
  568. static void __exit n8x0_panel_drv_exit(void)
  569. {
  570. spi_unregister_driver(&mipid_spi_driver);
  571. omap_dss_unregister_driver(&n8x0_panel_driver);
  572. }
  573. module_init(n8x0_panel_drv_init);
  574. module_exit(n8x0_panel_drv_exit);
  575. MODULE_LICENSE("GPL");