xhci-hub.c 30 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/gfp.h>
  23. #include <asm/unaligned.h>
  24. #include "xhci.h"
  25. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  26. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  27. PORT_RC | PORT_PLC | PORT_PE)
  28. /* usb 1.1 root hub device descriptor */
  29. static u8 usb_bos_descriptor [] = {
  30. USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
  31. USB_DT_BOS, /* __u8 bDescriptorType */
  32. 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
  33. 0x1, /* __u8 bNumDeviceCaps */
  34. /* First device capability */
  35. USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
  36. USB_DT_DEVICE_CAPABILITY, /* Device Capability */
  37. USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
  38. 0x00, /* bmAttributes, LTM off by default */
  39. USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
  40. 0x03, /* bFunctionalitySupport,
  41. USB 3.0 speed only */
  42. 0x00, /* bU1DevExitLat, set later. */
  43. 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
  44. };
  45. static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  46. struct usb_hub_descriptor *desc, int ports)
  47. {
  48. u16 temp;
  49. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  50. desc->bHubContrCurrent = 0;
  51. desc->bNbrPorts = ports;
  52. temp = 0;
  53. /* Bits 1:0 - support per-port power switching, or power always on */
  54. if (HCC_PPC(xhci->hcc_params))
  55. temp |= HUB_CHAR_INDV_PORT_LPSM;
  56. else
  57. temp |= HUB_CHAR_NO_LPSM;
  58. /* Bit 2 - root hubs are not part of a compound device */
  59. /* Bits 4:3 - individual port over current protection */
  60. temp |= HUB_CHAR_INDV_PORT_OCPM;
  61. /* Bits 6:5 - no TTs in root ports */
  62. /* Bit 7 - no port indicators */
  63. desc->wHubCharacteristics = cpu_to_le16(temp);
  64. }
  65. /* Fill in the USB 2.0 roothub descriptor */
  66. static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  67. struct usb_hub_descriptor *desc)
  68. {
  69. int ports;
  70. u16 temp;
  71. __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  72. u32 portsc;
  73. unsigned int i;
  74. ports = xhci->num_usb2_ports;
  75. xhci_common_hub_descriptor(xhci, desc, ports);
  76. desc->bDescriptorType = USB_DT_HUB;
  77. temp = 1 + (ports / 8);
  78. desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  79. /* The Device Removable bits are reported on a byte granularity.
  80. * If the port doesn't exist within that byte, the bit is set to 0.
  81. */
  82. memset(port_removable, 0, sizeof(port_removable));
  83. for (i = 0; i < ports; i++) {
  84. portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
  85. /* If a device is removable, PORTSC reports a 0, same as in the
  86. * hub descriptor DeviceRemovable bits.
  87. */
  88. if (portsc & PORT_DEV_REMOVE)
  89. /* This math is hairy because bit 0 of DeviceRemovable
  90. * is reserved, and bit 1 is for port 1, etc.
  91. */
  92. port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
  93. }
  94. /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
  95. * ports on it. The USB 2.0 specification says that there are two
  96. * variable length fields at the end of the hub descriptor:
  97. * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
  98. * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
  99. * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
  100. * 0xFF, so we initialize the both arrays (DeviceRemovable and
  101. * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
  102. * set of ports that actually exist.
  103. */
  104. memset(desc->u.hs.DeviceRemovable, 0xff,
  105. sizeof(desc->u.hs.DeviceRemovable));
  106. memset(desc->u.hs.PortPwrCtrlMask, 0xff,
  107. sizeof(desc->u.hs.PortPwrCtrlMask));
  108. for (i = 0; i < (ports + 1 + 7) / 8; i++)
  109. memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
  110. sizeof(__u8));
  111. }
  112. /* Fill in the USB 3.0 roothub descriptor */
  113. static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  114. struct usb_hub_descriptor *desc)
  115. {
  116. int ports;
  117. u16 port_removable;
  118. u32 portsc;
  119. unsigned int i;
  120. ports = xhci->num_usb3_ports;
  121. xhci_common_hub_descriptor(xhci, desc, ports);
  122. desc->bDescriptorType = USB_DT_SS_HUB;
  123. desc->bDescLength = USB_DT_SS_HUB_SIZE;
  124. /* header decode latency should be zero for roothubs,
  125. * see section 4.23.5.2.
  126. */
  127. desc->u.ss.bHubHdrDecLat = 0;
  128. desc->u.ss.wHubDelay = 0;
  129. port_removable = 0;
  130. /* bit 0 is reserved, bit 1 is for port 1, etc. */
  131. for (i = 0; i < ports; i++) {
  132. portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
  133. if (portsc & PORT_DEV_REMOVE)
  134. port_removable |= 1 << (i + 1);
  135. }
  136. memset(&desc->u.ss.DeviceRemovable,
  137. (__force __u16) cpu_to_le16(port_removable),
  138. sizeof(__u16));
  139. }
  140. static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  141. struct usb_hub_descriptor *desc)
  142. {
  143. if (hcd->speed == HCD_USB3)
  144. xhci_usb3_hub_descriptor(hcd, xhci, desc);
  145. else
  146. xhci_usb2_hub_descriptor(hcd, xhci, desc);
  147. }
  148. static unsigned int xhci_port_speed(unsigned int port_status)
  149. {
  150. if (DEV_LOWSPEED(port_status))
  151. return USB_PORT_STAT_LOW_SPEED;
  152. if (DEV_HIGHSPEED(port_status))
  153. return USB_PORT_STAT_HIGH_SPEED;
  154. /*
  155. * FIXME: Yes, we should check for full speed, but the core uses that as
  156. * a default in portspeed() in usb/core/hub.c (which is the only place
  157. * USB_PORT_STAT_*_SPEED is used).
  158. */
  159. return 0;
  160. }
  161. /*
  162. * These bits are Read Only (RO) and should be saved and written to the
  163. * registers: 0, 3, 10:13, 30
  164. * connect status, over-current status, port speed, and device removable.
  165. * connect status and port speed are also sticky - meaning they're in
  166. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  167. */
  168. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  169. /*
  170. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  171. * bits 5:8, 9, 14:15, 25:27
  172. * link state, port power, port indicator state, "wake on" enable state
  173. */
  174. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  175. /*
  176. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  177. * bit 4 (port reset)
  178. */
  179. #define XHCI_PORT_RW1S ((1<<4))
  180. /*
  181. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  182. * bits 1, 17, 18, 19, 20, 21, 22, 23
  183. * port enable/disable, and
  184. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  185. * over-current, reset, link state, and L1 change
  186. */
  187. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  188. /*
  189. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  190. * latched in
  191. */
  192. #define XHCI_PORT_RW ((1<<16))
  193. /*
  194. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  195. * bits 2, 24, 28:31
  196. */
  197. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  198. /*
  199. * Given a port state, this function returns a value that would result in the
  200. * port being in the same state, if the value was written to the port status
  201. * control register.
  202. * Save Read Only (RO) bits and save read/write bits where
  203. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  204. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  205. */
  206. u32 xhci_port_state_to_neutral(u32 state)
  207. {
  208. /* Save read-only status and port state */
  209. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  210. }
  211. /*
  212. * find slot id based on port number.
  213. * @port: The one-based port number from one of the two split roothubs.
  214. */
  215. int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  216. u16 port)
  217. {
  218. int slot_id;
  219. int i;
  220. enum usb_device_speed speed;
  221. slot_id = 0;
  222. for (i = 0; i < MAX_HC_SLOTS; i++) {
  223. if (!xhci->devs[i])
  224. continue;
  225. speed = xhci->devs[i]->udev->speed;
  226. if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
  227. && xhci->devs[i]->fake_port == port) {
  228. slot_id = i;
  229. break;
  230. }
  231. }
  232. return slot_id;
  233. }
  234. /*
  235. * Stop device
  236. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  237. * to complete.
  238. * suspend will set to 1, if suspend bit need to set in command.
  239. */
  240. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  241. {
  242. struct xhci_virt_device *virt_dev;
  243. struct xhci_command *cmd;
  244. unsigned long flags;
  245. int timeleft;
  246. int ret;
  247. int i;
  248. ret = 0;
  249. virt_dev = xhci->devs[slot_id];
  250. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  251. if (!cmd) {
  252. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  253. return -ENOMEM;
  254. }
  255. spin_lock_irqsave(&xhci->lock, flags);
  256. for (i = LAST_EP_INDEX; i > 0; i--) {
  257. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
  258. xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
  259. }
  260. cmd->command_trb = xhci->cmd_ring->enqueue;
  261. list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
  262. xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
  263. xhci_ring_cmd_db(xhci);
  264. spin_unlock_irqrestore(&xhci->lock, flags);
  265. /* Wait for last stop endpoint command to finish */
  266. timeleft = wait_for_completion_interruptible_timeout(
  267. cmd->completion,
  268. USB_CTRL_SET_TIMEOUT);
  269. if (timeleft <= 0) {
  270. xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
  271. timeleft == 0 ? "Timeout" : "Signal");
  272. spin_lock_irqsave(&xhci->lock, flags);
  273. /* The timeout might have raced with the event ring handler, so
  274. * only delete from the list if the item isn't poisoned.
  275. */
  276. if (cmd->cmd_list.next != LIST_POISON1)
  277. list_del(&cmd->cmd_list);
  278. spin_unlock_irqrestore(&xhci->lock, flags);
  279. ret = -ETIME;
  280. goto command_cleanup;
  281. }
  282. command_cleanup:
  283. xhci_free_command(xhci, cmd);
  284. return ret;
  285. }
  286. /*
  287. * Ring device, it rings the all doorbells unconditionally.
  288. */
  289. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  290. {
  291. int i;
  292. for (i = 0; i < LAST_EP_INDEX + 1; i++)
  293. if (xhci->devs[slot_id]->eps[i].ring &&
  294. xhci->devs[slot_id]->eps[i].ring->dequeue)
  295. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  296. return;
  297. }
  298. static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  299. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  300. {
  301. /* Don't allow the USB core to disable SuperSpeed ports. */
  302. if (hcd->speed == HCD_USB3) {
  303. xhci_dbg(xhci, "Ignoring request to disable "
  304. "SuperSpeed port.\n");
  305. return;
  306. }
  307. /* Write 1 to disable the port */
  308. xhci_writel(xhci, port_status | PORT_PE, addr);
  309. port_status = xhci_readl(xhci, addr);
  310. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  311. wIndex, port_status);
  312. }
  313. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  314. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  315. {
  316. char *port_change_bit;
  317. u32 status;
  318. switch (wValue) {
  319. case USB_PORT_FEAT_C_RESET:
  320. status = PORT_RC;
  321. port_change_bit = "reset";
  322. break;
  323. case USB_PORT_FEAT_C_BH_PORT_RESET:
  324. status = PORT_WRC;
  325. port_change_bit = "warm(BH) reset";
  326. break;
  327. case USB_PORT_FEAT_C_CONNECTION:
  328. status = PORT_CSC;
  329. port_change_bit = "connect";
  330. break;
  331. case USB_PORT_FEAT_C_OVER_CURRENT:
  332. status = PORT_OCC;
  333. port_change_bit = "over-current";
  334. break;
  335. case USB_PORT_FEAT_C_ENABLE:
  336. status = PORT_PEC;
  337. port_change_bit = "enable/disable";
  338. break;
  339. case USB_PORT_FEAT_C_SUSPEND:
  340. status = PORT_PLC;
  341. port_change_bit = "suspend/resume";
  342. break;
  343. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  344. status = PORT_PLC;
  345. port_change_bit = "link state";
  346. break;
  347. default:
  348. /* Should never happen */
  349. return;
  350. }
  351. /* Change bits are all write 1 to clear */
  352. xhci_writel(xhci, port_status | status, addr);
  353. port_status = xhci_readl(xhci, addr);
  354. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  355. port_change_bit, wIndex, port_status);
  356. }
  357. static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
  358. {
  359. int max_ports;
  360. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  361. if (hcd->speed == HCD_USB3) {
  362. max_ports = xhci->num_usb3_ports;
  363. *port_array = xhci->usb3_ports;
  364. } else {
  365. max_ports = xhci->num_usb2_ports;
  366. *port_array = xhci->usb2_ports;
  367. }
  368. return max_ports;
  369. }
  370. void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  371. int port_id, u32 link_state)
  372. {
  373. u32 temp;
  374. temp = xhci_readl(xhci, port_array[port_id]);
  375. temp = xhci_port_state_to_neutral(temp);
  376. temp &= ~PORT_PLS_MASK;
  377. temp |= PORT_LINK_STROBE | link_state;
  378. xhci_writel(xhci, temp, port_array[port_id]);
  379. }
  380. void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
  381. __le32 __iomem **port_array, int port_id, u16 wake_mask)
  382. {
  383. u32 temp;
  384. temp = xhci_readl(xhci, port_array[port_id]);
  385. temp = xhci_port_state_to_neutral(temp);
  386. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
  387. temp |= PORT_WKCONN_E;
  388. else
  389. temp &= ~PORT_WKCONN_E;
  390. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
  391. temp |= PORT_WKDISC_E;
  392. else
  393. temp &= ~PORT_WKDISC_E;
  394. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
  395. temp |= PORT_WKOC_E;
  396. else
  397. temp &= ~PORT_WKOC_E;
  398. xhci_writel(xhci, temp, port_array[port_id]);
  399. }
  400. /* Test and clear port RWC bit */
  401. void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  402. int port_id, u32 port_bit)
  403. {
  404. u32 temp;
  405. temp = xhci_readl(xhci, port_array[port_id]);
  406. if (temp & port_bit) {
  407. temp = xhci_port_state_to_neutral(temp);
  408. temp |= port_bit;
  409. xhci_writel(xhci, temp, port_array[port_id]);
  410. }
  411. }
  412. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  413. u16 wIndex, char *buf, u16 wLength)
  414. {
  415. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  416. int max_ports;
  417. unsigned long flags;
  418. u32 temp, status;
  419. int retval = 0;
  420. __le32 __iomem **port_array;
  421. int slot_id;
  422. struct xhci_bus_state *bus_state;
  423. u16 link_state = 0;
  424. u16 wake_mask = 0;
  425. max_ports = xhci_get_ports(hcd, &port_array);
  426. bus_state = &xhci->bus_state[hcd_index(hcd)];
  427. spin_lock_irqsave(&xhci->lock, flags);
  428. switch (typeReq) {
  429. case GetHubStatus:
  430. /* No power source, over-current reported per port */
  431. memset(buf, 0, 4);
  432. break;
  433. case GetHubDescriptor:
  434. /* Check to make sure userspace is asking for the USB 3.0 hub
  435. * descriptor for the USB 3.0 roothub. If not, we stall the
  436. * endpoint, like external hubs do.
  437. */
  438. if (hcd->speed == HCD_USB3 &&
  439. (wLength < USB_DT_SS_HUB_SIZE ||
  440. wValue != (USB_DT_SS_HUB << 8))) {
  441. xhci_dbg(xhci, "Wrong hub descriptor type for "
  442. "USB 3.0 roothub.\n");
  443. goto error;
  444. }
  445. xhci_hub_descriptor(hcd, xhci,
  446. (struct usb_hub_descriptor *) buf);
  447. break;
  448. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  449. if ((wValue & 0xff00) != (USB_DT_BOS << 8))
  450. goto error;
  451. if (hcd->speed != HCD_USB3)
  452. goto error;
  453. memcpy(buf, &usb_bos_descriptor,
  454. USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
  455. temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
  456. buf[12] = HCS_U1_LATENCY(temp);
  457. put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  458. spin_unlock_irqrestore(&xhci->lock, flags);
  459. return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  460. case GetPortStatus:
  461. if (!wIndex || wIndex > max_ports)
  462. goto error;
  463. wIndex--;
  464. status = 0;
  465. temp = xhci_readl(xhci, port_array[wIndex]);
  466. if (temp == 0xffffffff) {
  467. retval = -ENODEV;
  468. break;
  469. }
  470. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
  471. /* wPortChange bits */
  472. if (temp & PORT_CSC)
  473. status |= USB_PORT_STAT_C_CONNECTION << 16;
  474. if (temp & PORT_PEC)
  475. status |= USB_PORT_STAT_C_ENABLE << 16;
  476. if ((temp & PORT_OCC))
  477. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  478. if ((temp & PORT_RC))
  479. status |= USB_PORT_STAT_C_RESET << 16;
  480. /* USB3.0 only */
  481. if (hcd->speed == HCD_USB3) {
  482. if ((temp & PORT_PLC))
  483. status |= USB_PORT_STAT_C_LINK_STATE << 16;
  484. if ((temp & PORT_WRC))
  485. status |= USB_PORT_STAT_C_BH_RESET << 16;
  486. }
  487. if (hcd->speed != HCD_USB3) {
  488. if ((temp & PORT_PLS_MASK) == XDEV_U3
  489. && (temp & PORT_POWER))
  490. status |= USB_PORT_STAT_SUSPEND;
  491. }
  492. if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
  493. !DEV_SUPERSPEED(temp)) {
  494. if ((temp & PORT_RESET) || !(temp & PORT_PE))
  495. goto error;
  496. if (time_after_eq(jiffies,
  497. bus_state->resume_done[wIndex])) {
  498. xhci_dbg(xhci, "Resume USB2 port %d\n",
  499. wIndex + 1);
  500. bus_state->resume_done[wIndex] = 0;
  501. xhci_set_link_state(xhci, port_array, wIndex,
  502. XDEV_U0);
  503. xhci_dbg(xhci, "set port %d resume\n",
  504. wIndex + 1);
  505. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  506. wIndex + 1);
  507. if (!slot_id) {
  508. xhci_dbg(xhci, "slot_id is zero\n");
  509. goto error;
  510. }
  511. xhci_ring_device(xhci, slot_id);
  512. bus_state->port_c_suspend |= 1 << wIndex;
  513. bus_state->suspended_ports &= ~(1 << wIndex);
  514. } else {
  515. /*
  516. * The resume has been signaling for less than
  517. * 20ms. Report the port status as SUSPEND,
  518. * let the usbcore check port status again
  519. * and clear resume signaling later.
  520. */
  521. status |= USB_PORT_STAT_SUSPEND;
  522. }
  523. }
  524. if ((temp & PORT_PLS_MASK) == XDEV_U0
  525. && (temp & PORT_POWER)
  526. && (bus_state->suspended_ports & (1 << wIndex))) {
  527. bus_state->suspended_ports &= ~(1 << wIndex);
  528. if (hcd->speed != HCD_USB3)
  529. bus_state->port_c_suspend |= 1 << wIndex;
  530. }
  531. if (temp & PORT_CONNECT) {
  532. status |= USB_PORT_STAT_CONNECTION;
  533. status |= xhci_port_speed(temp);
  534. }
  535. if (temp & PORT_PE)
  536. status |= USB_PORT_STAT_ENABLE;
  537. if (temp & PORT_OC)
  538. status |= USB_PORT_STAT_OVERCURRENT;
  539. if (temp & PORT_RESET)
  540. status |= USB_PORT_STAT_RESET;
  541. if (temp & PORT_POWER) {
  542. if (hcd->speed == HCD_USB3)
  543. status |= USB_SS_PORT_STAT_POWER;
  544. else
  545. status |= USB_PORT_STAT_POWER;
  546. }
  547. /* Port Link State */
  548. if (hcd->speed == HCD_USB3) {
  549. /* resume state is a xHCI internal state.
  550. * Do not report it to usb core.
  551. */
  552. if ((temp & PORT_PLS_MASK) != XDEV_RESUME)
  553. status |= (temp & PORT_PLS_MASK);
  554. }
  555. if (bus_state->port_c_suspend & (1 << wIndex))
  556. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  557. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  558. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  559. break;
  560. case SetPortFeature:
  561. if (wValue == USB_PORT_FEAT_LINK_STATE)
  562. link_state = (wIndex & 0xff00) >> 3;
  563. if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
  564. wake_mask = wIndex & 0xff00;
  565. wIndex &= 0xff;
  566. if (!wIndex || wIndex > max_ports)
  567. goto error;
  568. wIndex--;
  569. temp = xhci_readl(xhci, port_array[wIndex]);
  570. if (temp == 0xffffffff) {
  571. retval = -ENODEV;
  572. break;
  573. }
  574. temp = xhci_port_state_to_neutral(temp);
  575. /* FIXME: What new port features do we need to support? */
  576. switch (wValue) {
  577. case USB_PORT_FEAT_SUSPEND:
  578. temp = xhci_readl(xhci, port_array[wIndex]);
  579. if ((temp & PORT_PLS_MASK) != XDEV_U0) {
  580. /* Resume the port to U0 first */
  581. xhci_set_link_state(xhci, port_array, wIndex,
  582. XDEV_U0);
  583. spin_unlock_irqrestore(&xhci->lock, flags);
  584. msleep(10);
  585. spin_lock_irqsave(&xhci->lock, flags);
  586. }
  587. /* In spec software should not attempt to suspend
  588. * a port unless the port reports that it is in the
  589. * enabled (PED = ‘1’,PLS < ‘3’) state.
  590. */
  591. temp = xhci_readl(xhci, port_array[wIndex]);
  592. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  593. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  594. xhci_warn(xhci, "USB core suspending device "
  595. "not in U0/U1/U2.\n");
  596. goto error;
  597. }
  598. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  599. wIndex + 1);
  600. if (!slot_id) {
  601. xhci_warn(xhci, "slot_id is zero\n");
  602. goto error;
  603. }
  604. /* unlock to execute stop endpoint commands */
  605. spin_unlock_irqrestore(&xhci->lock, flags);
  606. xhci_stop_device(xhci, slot_id, 1);
  607. spin_lock_irqsave(&xhci->lock, flags);
  608. xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
  609. spin_unlock_irqrestore(&xhci->lock, flags);
  610. msleep(10); /* wait device to enter */
  611. spin_lock_irqsave(&xhci->lock, flags);
  612. temp = xhci_readl(xhci, port_array[wIndex]);
  613. bus_state->suspended_ports |= 1 << wIndex;
  614. break;
  615. case USB_PORT_FEAT_LINK_STATE:
  616. temp = xhci_readl(xhci, port_array[wIndex]);
  617. /* Software should not attempt to set
  618. * port link state above '5' (Rx.Detect) and the port
  619. * must be enabled.
  620. */
  621. if ((temp & PORT_PE) == 0 ||
  622. (link_state > USB_SS_PORT_LS_RX_DETECT)) {
  623. xhci_warn(xhci, "Cannot set link state.\n");
  624. goto error;
  625. }
  626. if (link_state == USB_SS_PORT_LS_U3) {
  627. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  628. wIndex + 1);
  629. if (slot_id) {
  630. /* unlock to execute stop endpoint
  631. * commands */
  632. spin_unlock_irqrestore(&xhci->lock,
  633. flags);
  634. xhci_stop_device(xhci, slot_id, 1);
  635. spin_lock_irqsave(&xhci->lock, flags);
  636. }
  637. }
  638. xhci_set_link_state(xhci, port_array, wIndex,
  639. link_state);
  640. spin_unlock_irqrestore(&xhci->lock, flags);
  641. msleep(20); /* wait device to enter */
  642. spin_lock_irqsave(&xhci->lock, flags);
  643. temp = xhci_readl(xhci, port_array[wIndex]);
  644. if (link_state == USB_SS_PORT_LS_U3)
  645. bus_state->suspended_ports |= 1 << wIndex;
  646. break;
  647. case USB_PORT_FEAT_POWER:
  648. /*
  649. * Turn on ports, even if there isn't per-port switching.
  650. * HC will report connect events even before this is set.
  651. * However, khubd will ignore the roothub events until
  652. * the roothub is registered.
  653. */
  654. xhci_writel(xhci, temp | PORT_POWER,
  655. port_array[wIndex]);
  656. temp = xhci_readl(xhci, port_array[wIndex]);
  657. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  658. break;
  659. case USB_PORT_FEAT_RESET:
  660. temp = (temp | PORT_RESET);
  661. xhci_writel(xhci, temp, port_array[wIndex]);
  662. temp = xhci_readl(xhci, port_array[wIndex]);
  663. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  664. break;
  665. case USB_PORT_FEAT_REMOTE_WAKE_MASK:
  666. xhci_set_remote_wake_mask(xhci, port_array,
  667. wIndex, wake_mask);
  668. temp = xhci_readl(xhci, port_array[wIndex]);
  669. xhci_dbg(xhci, "set port remote wake mask, "
  670. "actual port %d status = 0x%x\n",
  671. wIndex, temp);
  672. break;
  673. case USB_PORT_FEAT_BH_PORT_RESET:
  674. temp |= PORT_WR;
  675. xhci_writel(xhci, temp, port_array[wIndex]);
  676. temp = xhci_readl(xhci, port_array[wIndex]);
  677. break;
  678. default:
  679. goto error;
  680. }
  681. /* unblock any posted writes */
  682. temp = xhci_readl(xhci, port_array[wIndex]);
  683. break;
  684. case ClearPortFeature:
  685. if (!wIndex || wIndex > max_ports)
  686. goto error;
  687. wIndex--;
  688. temp = xhci_readl(xhci, port_array[wIndex]);
  689. if (temp == 0xffffffff) {
  690. retval = -ENODEV;
  691. break;
  692. }
  693. /* FIXME: What new port features do we need to support? */
  694. temp = xhci_port_state_to_neutral(temp);
  695. switch (wValue) {
  696. case USB_PORT_FEAT_SUSPEND:
  697. temp = xhci_readl(xhci, port_array[wIndex]);
  698. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  699. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  700. if (temp & PORT_RESET)
  701. goto error;
  702. if ((temp & PORT_PLS_MASK) == XDEV_U3) {
  703. if ((temp & PORT_PE) == 0)
  704. goto error;
  705. xhci_set_link_state(xhci, port_array, wIndex,
  706. XDEV_RESUME);
  707. spin_unlock_irqrestore(&xhci->lock, flags);
  708. msleep(20);
  709. spin_lock_irqsave(&xhci->lock, flags);
  710. xhci_set_link_state(xhci, port_array, wIndex,
  711. XDEV_U0);
  712. }
  713. bus_state->port_c_suspend |= 1 << wIndex;
  714. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  715. wIndex + 1);
  716. if (!slot_id) {
  717. xhci_dbg(xhci, "slot_id is zero\n");
  718. goto error;
  719. }
  720. xhci_ring_device(xhci, slot_id);
  721. break;
  722. case USB_PORT_FEAT_C_SUSPEND:
  723. bus_state->port_c_suspend &= ~(1 << wIndex);
  724. case USB_PORT_FEAT_C_RESET:
  725. case USB_PORT_FEAT_C_BH_PORT_RESET:
  726. case USB_PORT_FEAT_C_CONNECTION:
  727. case USB_PORT_FEAT_C_OVER_CURRENT:
  728. case USB_PORT_FEAT_C_ENABLE:
  729. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  730. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  731. port_array[wIndex], temp);
  732. break;
  733. case USB_PORT_FEAT_ENABLE:
  734. xhci_disable_port(hcd, xhci, wIndex,
  735. port_array[wIndex], temp);
  736. break;
  737. default:
  738. goto error;
  739. }
  740. break;
  741. default:
  742. error:
  743. /* "stall" on error */
  744. retval = -EPIPE;
  745. }
  746. spin_unlock_irqrestore(&xhci->lock, flags);
  747. return retval;
  748. }
  749. /*
  750. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  751. * Ports are 0-indexed from the HCD point of view,
  752. * and 1-indexed from the USB core pointer of view.
  753. *
  754. * Note that the status change bits will be cleared as soon as a port status
  755. * change event is generated, so we use the saved status from that event.
  756. */
  757. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  758. {
  759. unsigned long flags;
  760. u32 temp, status;
  761. u32 mask;
  762. int i, retval;
  763. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  764. int max_ports;
  765. __le32 __iomem **port_array;
  766. struct xhci_bus_state *bus_state;
  767. max_ports = xhci_get_ports(hcd, &port_array);
  768. bus_state = &xhci->bus_state[hcd_index(hcd)];
  769. /* Initial status is no changes */
  770. retval = (max_ports + 8) / 8;
  771. memset(buf, 0, retval);
  772. status = 0;
  773. mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
  774. spin_lock_irqsave(&xhci->lock, flags);
  775. /* For each port, did anything change? If so, set that bit in buf. */
  776. for (i = 0; i < max_ports; i++) {
  777. temp = xhci_readl(xhci, port_array[i]);
  778. if (temp == 0xffffffff) {
  779. retval = -ENODEV;
  780. break;
  781. }
  782. if ((temp & mask) != 0 ||
  783. (bus_state->port_c_suspend & 1 << i) ||
  784. (bus_state->resume_done[i] && time_after_eq(
  785. jiffies, bus_state->resume_done[i]))) {
  786. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  787. status = 1;
  788. }
  789. }
  790. spin_unlock_irqrestore(&xhci->lock, flags);
  791. return status ? retval : 0;
  792. }
  793. #ifdef CONFIG_PM
  794. int xhci_bus_suspend(struct usb_hcd *hcd)
  795. {
  796. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  797. int max_ports, port_index;
  798. __le32 __iomem **port_array;
  799. struct xhci_bus_state *bus_state;
  800. unsigned long flags;
  801. max_ports = xhci_get_ports(hcd, &port_array);
  802. bus_state = &xhci->bus_state[hcd_index(hcd)];
  803. spin_lock_irqsave(&xhci->lock, flags);
  804. if (hcd->self.root_hub->do_remote_wakeup) {
  805. port_index = max_ports;
  806. while (port_index--) {
  807. if (bus_state->resume_done[port_index] != 0) {
  808. spin_unlock_irqrestore(&xhci->lock, flags);
  809. xhci_dbg(xhci, "suspend failed because "
  810. "port %d is resuming\n",
  811. port_index + 1);
  812. return -EBUSY;
  813. }
  814. }
  815. }
  816. port_index = max_ports;
  817. bus_state->bus_suspended = 0;
  818. while (port_index--) {
  819. /* suspend the port if the port is not suspended */
  820. u32 t1, t2;
  821. int slot_id;
  822. t1 = xhci_readl(xhci, port_array[port_index]);
  823. t2 = xhci_port_state_to_neutral(t1);
  824. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  825. xhci_dbg(xhci, "port %d not suspended\n", port_index);
  826. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  827. port_index + 1);
  828. if (slot_id) {
  829. spin_unlock_irqrestore(&xhci->lock, flags);
  830. xhci_stop_device(xhci, slot_id, 1);
  831. spin_lock_irqsave(&xhci->lock, flags);
  832. }
  833. t2 &= ~PORT_PLS_MASK;
  834. t2 |= PORT_LINK_STROBE | XDEV_U3;
  835. set_bit(port_index, &bus_state->bus_suspended);
  836. }
  837. /* USB core sets remote wake mask for USB 3.0 hubs,
  838. * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
  839. * is enabled, so also enable remote wake here.
  840. */
  841. if (hcd->self.root_hub->do_remote_wakeup) {
  842. if (t1 & PORT_CONNECT) {
  843. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  844. t2 &= ~PORT_WKCONN_E;
  845. } else {
  846. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  847. t2 &= ~PORT_WKDISC_E;
  848. }
  849. } else
  850. t2 &= ~PORT_WAKE_BITS;
  851. t1 = xhci_port_state_to_neutral(t1);
  852. if (t1 != t2)
  853. xhci_writel(xhci, t2, port_array[port_index]);
  854. if (hcd->speed != HCD_USB3) {
  855. /* enable remote wake up for USB 2.0 */
  856. __le32 __iomem *addr;
  857. u32 tmp;
  858. /* Add one to the port status register address to get
  859. * the port power control register address.
  860. */
  861. addr = port_array[port_index] + 1;
  862. tmp = xhci_readl(xhci, addr);
  863. tmp |= PORT_RWE;
  864. xhci_writel(xhci, tmp, addr);
  865. }
  866. }
  867. hcd->state = HC_STATE_SUSPENDED;
  868. bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
  869. spin_unlock_irqrestore(&xhci->lock, flags);
  870. return 0;
  871. }
  872. int xhci_bus_resume(struct usb_hcd *hcd)
  873. {
  874. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  875. int max_ports, port_index;
  876. __le32 __iomem **port_array;
  877. struct xhci_bus_state *bus_state;
  878. u32 temp;
  879. unsigned long flags;
  880. max_ports = xhci_get_ports(hcd, &port_array);
  881. bus_state = &xhci->bus_state[hcd_index(hcd)];
  882. if (time_before(jiffies, bus_state->next_statechange))
  883. msleep(5);
  884. spin_lock_irqsave(&xhci->lock, flags);
  885. if (!HCD_HW_ACCESSIBLE(hcd)) {
  886. spin_unlock_irqrestore(&xhci->lock, flags);
  887. return -ESHUTDOWN;
  888. }
  889. /* delay the irqs */
  890. temp = xhci_readl(xhci, &xhci->op_regs->command);
  891. temp &= ~CMD_EIE;
  892. xhci_writel(xhci, temp, &xhci->op_regs->command);
  893. port_index = max_ports;
  894. while (port_index--) {
  895. /* Check whether need resume ports. If needed
  896. resume port and disable remote wakeup */
  897. u32 temp;
  898. int slot_id;
  899. temp = xhci_readl(xhci, port_array[port_index]);
  900. if (DEV_SUPERSPEED(temp))
  901. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  902. else
  903. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  904. if (test_bit(port_index, &bus_state->bus_suspended) &&
  905. (temp & PORT_PLS_MASK)) {
  906. if (DEV_SUPERSPEED(temp)) {
  907. xhci_set_link_state(xhci, port_array,
  908. port_index, XDEV_U0);
  909. } else {
  910. xhci_set_link_state(xhci, port_array,
  911. port_index, XDEV_RESUME);
  912. spin_unlock_irqrestore(&xhci->lock, flags);
  913. msleep(20);
  914. spin_lock_irqsave(&xhci->lock, flags);
  915. xhci_set_link_state(xhci, port_array,
  916. port_index, XDEV_U0);
  917. }
  918. /* wait for the port to enter U0 and report port link
  919. * state change.
  920. */
  921. spin_unlock_irqrestore(&xhci->lock, flags);
  922. msleep(20);
  923. spin_lock_irqsave(&xhci->lock, flags);
  924. /* Clear PLC */
  925. xhci_test_and_clear_bit(xhci, port_array, port_index,
  926. PORT_PLC);
  927. slot_id = xhci_find_slot_id_by_port(hcd,
  928. xhci, port_index + 1);
  929. if (slot_id)
  930. xhci_ring_device(xhci, slot_id);
  931. } else
  932. xhci_writel(xhci, temp, port_array[port_index]);
  933. if (hcd->speed != HCD_USB3) {
  934. /* disable remote wake up for USB 2.0 */
  935. __le32 __iomem *addr;
  936. u32 tmp;
  937. /* Add one to the port status register address to get
  938. * the port power control register address.
  939. */
  940. addr = port_array[port_index] + 1;
  941. tmp = xhci_readl(xhci, addr);
  942. tmp &= ~PORT_RWE;
  943. xhci_writel(xhci, tmp, addr);
  944. }
  945. }
  946. (void) xhci_readl(xhci, &xhci->op_regs->command);
  947. bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
  948. /* re-enable irqs */
  949. temp = xhci_readl(xhci, &xhci->op_regs->command);
  950. temp |= CMD_EIE;
  951. xhci_writel(xhci, temp, &xhci->op_regs->command);
  952. temp = xhci_readl(xhci, &xhci->op_regs->command);
  953. spin_unlock_irqrestore(&xhci->lock, flags);
  954. return 0;
  955. }
  956. #endif /* CONFIG_PM */