rtc-twl.c 14 KB

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  1. /*
  2. * rtc-twl.c -- TWL Real Time Clock interface
  3. *
  4. * Copyright (C) 2007 MontaVista Software, Inc
  5. * Author: Alexandre Rusev <source@mvista.com>
  6. *
  7. * Based on original TI driver twl4030-rtc.c
  8. * Copyright (C) 2006 Texas Instruments, Inc.
  9. *
  10. * Based on rtc-omap.c
  11. * Copyright (C) 2003 MontaVista Software, Inc.
  12. * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  13. * Copyright (C) 2006 David Brownell
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version
  18. * 2 of the License, or (at your option) any later version.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/errno.h>
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/types.h>
  25. #include <linux/rtc.h>
  26. #include <linux/bcd.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/i2c/twl.h>
  30. /*
  31. * RTC block register offsets (use TWL_MODULE_RTC)
  32. */
  33. enum {
  34. REG_SECONDS_REG = 0,
  35. REG_MINUTES_REG,
  36. REG_HOURS_REG,
  37. REG_DAYS_REG,
  38. REG_MONTHS_REG,
  39. REG_YEARS_REG,
  40. REG_WEEKS_REG,
  41. REG_ALARM_SECONDS_REG,
  42. REG_ALARM_MINUTES_REG,
  43. REG_ALARM_HOURS_REG,
  44. REG_ALARM_DAYS_REG,
  45. REG_ALARM_MONTHS_REG,
  46. REG_ALARM_YEARS_REG,
  47. REG_RTC_CTRL_REG,
  48. REG_RTC_STATUS_REG,
  49. REG_RTC_INTERRUPTS_REG,
  50. REG_RTC_COMP_LSB_REG,
  51. REG_RTC_COMP_MSB_REG,
  52. };
  53. static const u8 twl4030_rtc_reg_map[] = {
  54. [REG_SECONDS_REG] = 0x00,
  55. [REG_MINUTES_REG] = 0x01,
  56. [REG_HOURS_REG] = 0x02,
  57. [REG_DAYS_REG] = 0x03,
  58. [REG_MONTHS_REG] = 0x04,
  59. [REG_YEARS_REG] = 0x05,
  60. [REG_WEEKS_REG] = 0x06,
  61. [REG_ALARM_SECONDS_REG] = 0x07,
  62. [REG_ALARM_MINUTES_REG] = 0x08,
  63. [REG_ALARM_HOURS_REG] = 0x09,
  64. [REG_ALARM_DAYS_REG] = 0x0A,
  65. [REG_ALARM_MONTHS_REG] = 0x0B,
  66. [REG_ALARM_YEARS_REG] = 0x0C,
  67. [REG_RTC_CTRL_REG] = 0x0D,
  68. [REG_RTC_STATUS_REG] = 0x0E,
  69. [REG_RTC_INTERRUPTS_REG] = 0x0F,
  70. [REG_RTC_COMP_LSB_REG] = 0x10,
  71. [REG_RTC_COMP_MSB_REG] = 0x11,
  72. };
  73. static const u8 twl6030_rtc_reg_map[] = {
  74. [REG_SECONDS_REG] = 0x00,
  75. [REG_MINUTES_REG] = 0x01,
  76. [REG_HOURS_REG] = 0x02,
  77. [REG_DAYS_REG] = 0x03,
  78. [REG_MONTHS_REG] = 0x04,
  79. [REG_YEARS_REG] = 0x05,
  80. [REG_WEEKS_REG] = 0x06,
  81. [REG_ALARM_SECONDS_REG] = 0x08,
  82. [REG_ALARM_MINUTES_REG] = 0x09,
  83. [REG_ALARM_HOURS_REG] = 0x0A,
  84. [REG_ALARM_DAYS_REG] = 0x0B,
  85. [REG_ALARM_MONTHS_REG] = 0x0C,
  86. [REG_ALARM_YEARS_REG] = 0x0D,
  87. [REG_RTC_CTRL_REG] = 0x10,
  88. [REG_RTC_STATUS_REG] = 0x11,
  89. [REG_RTC_INTERRUPTS_REG] = 0x12,
  90. [REG_RTC_COMP_LSB_REG] = 0x13,
  91. [REG_RTC_COMP_MSB_REG] = 0x14,
  92. };
  93. /* RTC_CTRL_REG bitfields */
  94. #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
  95. #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
  96. #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
  97. #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
  98. #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
  99. #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
  100. #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
  101. /* RTC_STATUS_REG bitfields */
  102. #define BIT_RTC_STATUS_REG_RUN_M 0x02
  103. #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
  104. #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
  105. #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
  106. #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
  107. #define BIT_RTC_STATUS_REG_ALARM_M 0x40
  108. #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
  109. /* RTC_INTERRUPTS_REG bitfields */
  110. #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
  111. #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
  112. #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
  113. /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
  114. #define ALL_TIME_REGS 6
  115. /*----------------------------------------------------------------------*/
  116. static u8 *rtc_reg_map;
  117. /*
  118. * Supports 1 byte read from TWL RTC register.
  119. */
  120. static int twl_rtc_read_u8(u8 *data, u8 reg)
  121. {
  122. int ret;
  123. ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
  124. if (ret < 0)
  125. pr_err("twl_rtc: Could not read TWL"
  126. "register %X - error %d\n", reg, ret);
  127. return ret;
  128. }
  129. /*
  130. * Supports 1 byte write to TWL RTC registers.
  131. */
  132. static int twl_rtc_write_u8(u8 data, u8 reg)
  133. {
  134. int ret;
  135. ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
  136. if (ret < 0)
  137. pr_err("twl_rtc: Could not write TWL"
  138. "register %X - error %d\n", reg, ret);
  139. return ret;
  140. }
  141. /*
  142. * Cache the value for timer/alarm interrupts register; this is
  143. * only changed by callers holding rtc ops lock (or resume).
  144. */
  145. static unsigned char rtc_irq_bits;
  146. /*
  147. * Enable 1/second update and/or alarm interrupts.
  148. */
  149. static int set_rtc_irq_bit(unsigned char bit)
  150. {
  151. unsigned char val;
  152. int ret;
  153. /* if the bit is set, return from here */
  154. if (rtc_irq_bits & bit)
  155. return 0;
  156. val = rtc_irq_bits | bit;
  157. val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
  158. ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
  159. if (ret == 0)
  160. rtc_irq_bits = val;
  161. return ret;
  162. }
  163. /*
  164. * Disable update and/or alarm interrupts.
  165. */
  166. static int mask_rtc_irq_bit(unsigned char bit)
  167. {
  168. unsigned char val;
  169. int ret;
  170. /* if the bit is clear, return from here */
  171. if (!(rtc_irq_bits & bit))
  172. return 0;
  173. val = rtc_irq_bits & ~bit;
  174. ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
  175. if (ret == 0)
  176. rtc_irq_bits = val;
  177. return ret;
  178. }
  179. static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
  180. {
  181. int ret;
  182. if (enabled)
  183. ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  184. else
  185. ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  186. return ret;
  187. }
  188. /*
  189. * Gets current TWL RTC time and date parameters.
  190. *
  191. * The RTC's time/alarm representation is not what gmtime(3) requires
  192. * Linux to use:
  193. *
  194. * - Months are 1..12 vs Linux 0-11
  195. * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
  196. */
  197. static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
  198. {
  199. unsigned char rtc_data[ALL_TIME_REGS + 1];
  200. int ret;
  201. u8 save_control;
  202. ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
  203. if (ret < 0)
  204. return ret;
  205. save_control |= BIT_RTC_CTRL_REG_GET_TIME_M;
  206. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  207. if (ret < 0)
  208. return ret;
  209. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  210. (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  211. if (ret < 0) {
  212. dev_err(dev, "rtc_read_time error %d\n", ret);
  213. return ret;
  214. }
  215. tm->tm_sec = bcd2bin(rtc_data[0]);
  216. tm->tm_min = bcd2bin(rtc_data[1]);
  217. tm->tm_hour = bcd2bin(rtc_data[2]);
  218. tm->tm_mday = bcd2bin(rtc_data[3]);
  219. tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
  220. tm->tm_year = bcd2bin(rtc_data[5]) + 100;
  221. return ret;
  222. }
  223. static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
  224. {
  225. unsigned char save_control;
  226. unsigned char rtc_data[ALL_TIME_REGS + 1];
  227. int ret;
  228. rtc_data[1] = bin2bcd(tm->tm_sec);
  229. rtc_data[2] = bin2bcd(tm->tm_min);
  230. rtc_data[3] = bin2bcd(tm->tm_hour);
  231. rtc_data[4] = bin2bcd(tm->tm_mday);
  232. rtc_data[5] = bin2bcd(tm->tm_mon + 1);
  233. rtc_data[6] = bin2bcd(tm->tm_year - 100);
  234. /* Stop RTC while updating the TC registers */
  235. ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
  236. if (ret < 0)
  237. goto out;
  238. save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
  239. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  240. if (ret < 0)
  241. goto out;
  242. /* update all the time registers in one shot */
  243. ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
  244. (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  245. if (ret < 0) {
  246. dev_err(dev, "rtc_set_time error %d\n", ret);
  247. goto out;
  248. }
  249. /* Start back RTC */
  250. save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
  251. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  252. out:
  253. return ret;
  254. }
  255. /*
  256. * Gets current TWL RTC alarm time.
  257. */
  258. static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  259. {
  260. unsigned char rtc_data[ALL_TIME_REGS + 1];
  261. int ret;
  262. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  263. (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
  264. if (ret < 0) {
  265. dev_err(dev, "rtc_read_alarm error %d\n", ret);
  266. return ret;
  267. }
  268. /* some of these fields may be wildcard/"match all" */
  269. alm->time.tm_sec = bcd2bin(rtc_data[0]);
  270. alm->time.tm_min = bcd2bin(rtc_data[1]);
  271. alm->time.tm_hour = bcd2bin(rtc_data[2]);
  272. alm->time.tm_mday = bcd2bin(rtc_data[3]);
  273. alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
  274. alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
  275. /* report cached alarm enable state */
  276. if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
  277. alm->enabled = 1;
  278. return ret;
  279. }
  280. static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  281. {
  282. unsigned char alarm_data[ALL_TIME_REGS + 1];
  283. int ret;
  284. ret = twl_rtc_alarm_irq_enable(dev, 0);
  285. if (ret)
  286. goto out;
  287. alarm_data[1] = bin2bcd(alm->time.tm_sec);
  288. alarm_data[2] = bin2bcd(alm->time.tm_min);
  289. alarm_data[3] = bin2bcd(alm->time.tm_hour);
  290. alarm_data[4] = bin2bcd(alm->time.tm_mday);
  291. alarm_data[5] = bin2bcd(alm->time.tm_mon + 1);
  292. alarm_data[6] = bin2bcd(alm->time.tm_year - 100);
  293. /* update all the alarm registers in one shot */
  294. ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
  295. (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
  296. if (ret) {
  297. dev_err(dev, "rtc_set_alarm error %d\n", ret);
  298. goto out;
  299. }
  300. if (alm->enabled)
  301. ret = twl_rtc_alarm_irq_enable(dev, 1);
  302. out:
  303. return ret;
  304. }
  305. static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
  306. {
  307. unsigned long events;
  308. int ret = IRQ_NONE;
  309. int res;
  310. u8 rd_reg;
  311. res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
  312. if (res)
  313. goto out;
  314. /*
  315. * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
  316. * only one (ALARM or RTC) interrupt source may be enabled
  317. * at time, we also could check our results
  318. * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
  319. */
  320. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  321. events = RTC_IRQF | RTC_AF;
  322. else
  323. events = RTC_IRQF | RTC_PF;
  324. res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
  325. REG_RTC_STATUS_REG);
  326. if (res)
  327. goto out;
  328. if (twl_class_is_4030()) {
  329. /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
  330. * needs 2 reads to clear the interrupt. One read is done in
  331. * do_twl_pwrirq(). Doing the second read, to clear
  332. * the bit.
  333. *
  334. * FIXME the reason PWR_ISR1 needs an extra read is that
  335. * RTC_IF retriggered until we cleared REG_ALARM_M above.
  336. * But re-reading like this is a bad hack; by doing so we
  337. * risk wrongly clearing status for some other IRQ (losing
  338. * the interrupt). Be smarter about handling RTC_UF ...
  339. */
  340. res = twl_i2c_read_u8(TWL4030_MODULE_INT,
  341. &rd_reg, TWL4030_INT_PWR_ISR1);
  342. if (res)
  343. goto out;
  344. }
  345. /* Notify RTC core on event */
  346. rtc_update_irq(rtc, 1, events);
  347. ret = IRQ_HANDLED;
  348. out:
  349. return ret;
  350. }
  351. static struct rtc_class_ops twl_rtc_ops = {
  352. .read_time = twl_rtc_read_time,
  353. .set_time = twl_rtc_set_time,
  354. .read_alarm = twl_rtc_read_alarm,
  355. .set_alarm = twl_rtc_set_alarm,
  356. .alarm_irq_enable = twl_rtc_alarm_irq_enable,
  357. };
  358. /*----------------------------------------------------------------------*/
  359. static int __devinit twl_rtc_probe(struct platform_device *pdev)
  360. {
  361. struct rtc_device *rtc;
  362. int ret = -EINVAL;
  363. int irq = platform_get_irq(pdev, 0);
  364. u8 rd_reg;
  365. if (irq <= 0)
  366. goto out1;
  367. ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
  368. if (ret < 0)
  369. goto out1;
  370. if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
  371. dev_warn(&pdev->dev, "Power up reset detected.\n");
  372. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  373. dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
  374. /* Clear RTC Power up reset and pending alarm interrupts */
  375. ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
  376. if (ret < 0)
  377. goto out1;
  378. if (twl_class_is_6030()) {
  379. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  380. REG_INT_MSK_LINE_A);
  381. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  382. REG_INT_MSK_STS_A);
  383. }
  384. dev_info(&pdev->dev, "Enabling TWL-RTC\n");
  385. ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
  386. if (ret < 0)
  387. goto out1;
  388. /* init cached IRQ enable bits */
  389. ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
  390. if (ret < 0)
  391. goto out1;
  392. rtc = rtc_device_register(pdev->name,
  393. &pdev->dev, &twl_rtc_ops, THIS_MODULE);
  394. if (IS_ERR(rtc)) {
  395. ret = PTR_ERR(rtc);
  396. dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
  397. PTR_ERR(rtc));
  398. goto out1;
  399. }
  400. ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
  401. IRQF_TRIGGER_RISING,
  402. dev_name(&rtc->dev), rtc);
  403. if (ret < 0) {
  404. dev_err(&pdev->dev, "IRQ is not free.\n");
  405. goto out2;
  406. }
  407. platform_set_drvdata(pdev, rtc);
  408. return 0;
  409. out2:
  410. rtc_device_unregister(rtc);
  411. out1:
  412. return ret;
  413. }
  414. /*
  415. * Disable all TWL RTC module interrupts.
  416. * Sets status flag to free.
  417. */
  418. static int __devexit twl_rtc_remove(struct platform_device *pdev)
  419. {
  420. /* leave rtc running, but disable irqs */
  421. struct rtc_device *rtc = platform_get_drvdata(pdev);
  422. int irq = platform_get_irq(pdev, 0);
  423. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  424. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  425. if (twl_class_is_6030()) {
  426. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  427. REG_INT_MSK_LINE_A);
  428. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  429. REG_INT_MSK_STS_A);
  430. }
  431. free_irq(irq, rtc);
  432. rtc_device_unregister(rtc);
  433. platform_set_drvdata(pdev, NULL);
  434. return 0;
  435. }
  436. static void twl_rtc_shutdown(struct platform_device *pdev)
  437. {
  438. /* mask timer interrupts, but leave alarm interrupts on to enable
  439. power-on when alarm is triggered */
  440. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  441. }
  442. #ifdef CONFIG_PM
  443. static unsigned char irqstat;
  444. static int twl_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  445. {
  446. irqstat = rtc_irq_bits;
  447. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  448. return 0;
  449. }
  450. static int twl_rtc_resume(struct platform_device *pdev)
  451. {
  452. set_rtc_irq_bit(irqstat);
  453. return 0;
  454. }
  455. #else
  456. #define twl_rtc_suspend NULL
  457. #define twl_rtc_resume NULL
  458. #endif
  459. static const struct of_device_id twl_rtc_of_match[] = {
  460. {.compatible = "ti,twl4030-rtc", },
  461. { },
  462. };
  463. MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
  464. MODULE_ALIAS("platform:twl_rtc");
  465. static struct platform_driver twl4030rtc_driver = {
  466. .probe = twl_rtc_probe,
  467. .remove = __devexit_p(twl_rtc_remove),
  468. .shutdown = twl_rtc_shutdown,
  469. .suspend = twl_rtc_suspend,
  470. .resume = twl_rtc_resume,
  471. .driver = {
  472. .owner = THIS_MODULE,
  473. .name = "twl_rtc",
  474. .of_match_table = twl_rtc_of_match,
  475. },
  476. };
  477. static int __init twl_rtc_init(void)
  478. {
  479. if (twl_class_is_4030())
  480. rtc_reg_map = (u8 *) twl4030_rtc_reg_map;
  481. else
  482. rtc_reg_map = (u8 *) twl6030_rtc_reg_map;
  483. return platform_driver_register(&twl4030rtc_driver);
  484. }
  485. module_init(twl_rtc_init);
  486. static void __exit twl_rtc_exit(void)
  487. {
  488. platform_driver_unregister(&twl4030rtc_driver);
  489. }
  490. module_exit(twl_rtc_exit);
  491. MODULE_AUTHOR("Texas Instruments, MontaVista Software");
  492. MODULE_LICENSE("GPL");