rtc-s3c.c 17 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <mach/hardware.h>
  29. #include <asm/uaccess.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <plat/regs-rtc.h>
  33. enum s3c_cpu_type {
  34. TYPE_S3C2410,
  35. TYPE_S3C2416,
  36. TYPE_S3C2443,
  37. TYPE_S3C64XX,
  38. };
  39. /* I have yet to find an S3C implementation with more than one
  40. * of these rtc blocks in */
  41. static struct resource *s3c_rtc_mem;
  42. static struct clk *rtc_clk;
  43. static void __iomem *s3c_rtc_base;
  44. static int s3c_rtc_alarmno = NO_IRQ;
  45. static int s3c_rtc_tickno = NO_IRQ;
  46. static bool wake_en;
  47. static enum s3c_cpu_type s3c_rtc_cpu_type;
  48. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  49. static void s3c_rtc_alarm_clk_enable(bool enable)
  50. {
  51. static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
  52. static bool alarm_clk_enabled;
  53. unsigned long irq_flags;
  54. spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
  55. if (enable) {
  56. if (!alarm_clk_enabled) {
  57. clk_enable(rtc_clk);
  58. alarm_clk_enabled = true;
  59. }
  60. } else {
  61. if (alarm_clk_enabled) {
  62. clk_disable(rtc_clk);
  63. alarm_clk_enabled = false;
  64. }
  65. }
  66. spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
  67. }
  68. /* IRQ Handlers */
  69. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  70. {
  71. struct rtc_device *rdev = id;
  72. clk_enable(rtc_clk);
  73. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  74. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  75. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  76. clk_disable(rtc_clk);
  77. s3c_rtc_alarm_clk_enable(false);
  78. return IRQ_HANDLED;
  79. }
  80. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  81. {
  82. struct rtc_device *rdev = id;
  83. clk_enable(rtc_clk);
  84. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  85. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  86. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  87. clk_disable(rtc_clk);
  88. return IRQ_HANDLED;
  89. }
  90. /* Update control registers */
  91. static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
  92. {
  93. unsigned int tmp;
  94. pr_debug("%s: aie=%d\n", __func__, enabled);
  95. clk_enable(rtc_clk);
  96. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  97. if (enabled)
  98. tmp |= S3C2410_RTCALM_ALMEN;
  99. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  100. clk_disable(rtc_clk);
  101. s3c_rtc_alarm_clk_enable(enabled);
  102. return 0;
  103. }
  104. static int s3c_rtc_setfreq(struct device *dev, int freq)
  105. {
  106. struct platform_device *pdev = to_platform_device(dev);
  107. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  108. unsigned int tmp = 0;
  109. int val;
  110. if (!is_power_of_2(freq))
  111. return -EINVAL;
  112. clk_enable(rtc_clk);
  113. spin_lock_irq(&s3c_rtc_pie_lock);
  114. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  115. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  116. tmp &= S3C2410_TICNT_ENABLE;
  117. }
  118. val = (rtc_dev->max_user_freq / freq) - 1;
  119. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  120. tmp |= S3C2443_TICNT_PART(val);
  121. writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
  122. if (s3c_rtc_cpu_type == TYPE_S3C2416)
  123. writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
  124. } else {
  125. tmp |= val;
  126. }
  127. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  128. spin_unlock_irq(&s3c_rtc_pie_lock);
  129. clk_disable(rtc_clk);
  130. return 0;
  131. }
  132. /* Time read/write */
  133. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  134. {
  135. unsigned int have_retried = 0;
  136. void __iomem *base = s3c_rtc_base;
  137. clk_enable(rtc_clk);
  138. retry_get_time:
  139. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  140. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  141. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  142. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  143. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  144. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  145. /* the only way to work out wether the system was mid-update
  146. * when we read it is to check the second counter, and if it
  147. * is zero, then we re-try the entire read
  148. */
  149. if (rtc_tm->tm_sec == 0 && !have_retried) {
  150. have_retried = 1;
  151. goto retry_get_time;
  152. }
  153. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  154. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  155. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  156. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  157. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  158. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  159. rtc_tm->tm_year += 100;
  160. pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n",
  161. 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  162. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  163. rtc_tm->tm_mon -= 1;
  164. clk_disable(rtc_clk);
  165. return rtc_valid_tm(rtc_tm);
  166. }
  167. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  168. {
  169. void __iomem *base = s3c_rtc_base;
  170. int year = tm->tm_year - 100;
  171. pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n",
  172. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  173. tm->tm_hour, tm->tm_min, tm->tm_sec);
  174. /* we get around y2k by simply not supporting it */
  175. if (year < 0 || year >= 100) {
  176. dev_err(dev, "rtc only supports 100 years\n");
  177. return -EINVAL;
  178. }
  179. clk_enable(rtc_clk);
  180. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  181. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  182. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  183. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  184. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  185. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  186. clk_disable(rtc_clk);
  187. return 0;
  188. }
  189. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  190. {
  191. struct rtc_time *alm_tm = &alrm->time;
  192. void __iomem *base = s3c_rtc_base;
  193. unsigned int alm_en;
  194. clk_enable(rtc_clk);
  195. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  196. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  197. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  198. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  199. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  200. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  201. alm_en = readb(base + S3C2410_RTCALM);
  202. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  203. pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  204. alm_en,
  205. 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  206. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  207. /* decode the alarm enable field */
  208. if (alm_en & S3C2410_RTCALM_SECEN)
  209. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  210. else
  211. alm_tm->tm_sec = -1;
  212. if (alm_en & S3C2410_RTCALM_MINEN)
  213. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  214. else
  215. alm_tm->tm_min = -1;
  216. if (alm_en & S3C2410_RTCALM_HOUREN)
  217. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  218. else
  219. alm_tm->tm_hour = -1;
  220. if (alm_en & S3C2410_RTCALM_DAYEN)
  221. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  222. else
  223. alm_tm->tm_mday = -1;
  224. if (alm_en & S3C2410_RTCALM_MONEN) {
  225. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  226. alm_tm->tm_mon -= 1;
  227. } else {
  228. alm_tm->tm_mon = -1;
  229. }
  230. if (alm_en & S3C2410_RTCALM_YEAREN)
  231. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  232. else
  233. alm_tm->tm_year = -1;
  234. clk_disable(rtc_clk);
  235. return 0;
  236. }
  237. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  238. {
  239. struct rtc_time *tm = &alrm->time;
  240. void __iomem *base = s3c_rtc_base;
  241. unsigned int alrm_en;
  242. clk_enable(rtc_clk);
  243. pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  244. alrm->enabled,
  245. 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
  246. tm->tm_hour, tm->tm_min, tm->tm_sec);
  247. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  248. writeb(0x00, base + S3C2410_RTCALM);
  249. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  250. alrm_en |= S3C2410_RTCALM_SECEN;
  251. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  252. }
  253. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  254. alrm_en |= S3C2410_RTCALM_MINEN;
  255. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  256. }
  257. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  258. alrm_en |= S3C2410_RTCALM_HOUREN;
  259. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  260. }
  261. pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en);
  262. writeb(alrm_en, base + S3C2410_RTCALM);
  263. s3c_rtc_setaie(dev, alrm->enabled);
  264. clk_disable(rtc_clk);
  265. return 0;
  266. }
  267. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  268. {
  269. unsigned int ticnt;
  270. clk_enable(rtc_clk);
  271. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  272. ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
  273. ticnt &= S3C64XX_RTCCON_TICEN;
  274. } else {
  275. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  276. ticnt &= S3C2410_TICNT_ENABLE;
  277. }
  278. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  279. clk_disable(rtc_clk);
  280. return 0;
  281. }
  282. static const struct rtc_class_ops s3c_rtcops = {
  283. .read_time = s3c_rtc_gettime,
  284. .set_time = s3c_rtc_settime,
  285. .read_alarm = s3c_rtc_getalarm,
  286. .set_alarm = s3c_rtc_setalarm,
  287. .proc = s3c_rtc_proc,
  288. .alarm_irq_enable = s3c_rtc_setaie,
  289. };
  290. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  291. {
  292. void __iomem *base = s3c_rtc_base;
  293. unsigned int tmp;
  294. if (s3c_rtc_base == NULL)
  295. return;
  296. clk_enable(rtc_clk);
  297. if (!en) {
  298. tmp = readw(base + S3C2410_RTCCON);
  299. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  300. tmp &= ~S3C64XX_RTCCON_TICEN;
  301. tmp &= ~S3C2410_RTCCON_RTCEN;
  302. writew(tmp, base + S3C2410_RTCCON);
  303. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  304. tmp = readb(base + S3C2410_TICNT);
  305. tmp &= ~S3C2410_TICNT_ENABLE;
  306. writeb(tmp, base + S3C2410_TICNT);
  307. }
  308. } else {
  309. /* re-enable the device, and check it is ok */
  310. if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
  311. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  312. tmp = readw(base + S3C2410_RTCCON);
  313. writew(tmp | S3C2410_RTCCON_RTCEN,
  314. base + S3C2410_RTCCON);
  315. }
  316. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
  317. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  318. tmp = readw(base + S3C2410_RTCCON);
  319. writew(tmp & ~S3C2410_RTCCON_CNTSEL,
  320. base + S3C2410_RTCCON);
  321. }
  322. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
  323. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  324. tmp = readw(base + S3C2410_RTCCON);
  325. writew(tmp & ~S3C2410_RTCCON_CLKRST,
  326. base + S3C2410_RTCCON);
  327. }
  328. }
  329. clk_disable(rtc_clk);
  330. }
  331. static int __devexit s3c_rtc_remove(struct platform_device *dev)
  332. {
  333. struct rtc_device *rtc = platform_get_drvdata(dev);
  334. free_irq(s3c_rtc_alarmno, rtc);
  335. free_irq(s3c_rtc_tickno, rtc);
  336. platform_set_drvdata(dev, NULL);
  337. rtc_device_unregister(rtc);
  338. s3c_rtc_setaie(&dev->dev, 0);
  339. clk_put(rtc_clk);
  340. rtc_clk = NULL;
  341. iounmap(s3c_rtc_base);
  342. release_resource(s3c_rtc_mem);
  343. kfree(s3c_rtc_mem);
  344. return 0;
  345. }
  346. static const struct of_device_id s3c_rtc_dt_match[];
  347. static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
  348. {
  349. #ifdef CONFIG_OF
  350. if (pdev->dev.of_node) {
  351. const struct of_device_id *match;
  352. match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
  353. return match->data;
  354. }
  355. #endif
  356. return platform_get_device_id(pdev)->driver_data;
  357. }
  358. static int __devinit s3c_rtc_probe(struct platform_device *pdev)
  359. {
  360. struct rtc_device *rtc;
  361. struct rtc_time rtc_tm;
  362. struct resource *res;
  363. int ret;
  364. int tmp;
  365. pr_debug("%s: probe=%p\n", __func__, pdev);
  366. /* find the IRQs */
  367. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  368. if (s3c_rtc_tickno < 0) {
  369. dev_err(&pdev->dev, "no irq for rtc tick\n");
  370. return -ENOENT;
  371. }
  372. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  373. if (s3c_rtc_alarmno < 0) {
  374. dev_err(&pdev->dev, "no irq for alarm\n");
  375. return -ENOENT;
  376. }
  377. pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n",
  378. s3c_rtc_tickno, s3c_rtc_alarmno);
  379. /* get the memory region */
  380. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  381. if (res == NULL) {
  382. dev_err(&pdev->dev, "failed to get memory region resource\n");
  383. return -ENOENT;
  384. }
  385. s3c_rtc_mem = request_mem_region(res->start, resource_size(res),
  386. pdev->name);
  387. if (s3c_rtc_mem == NULL) {
  388. dev_err(&pdev->dev, "failed to reserve memory region\n");
  389. ret = -ENOENT;
  390. goto err_nores;
  391. }
  392. s3c_rtc_base = ioremap(res->start, resource_size(res));
  393. if (s3c_rtc_base == NULL) {
  394. dev_err(&pdev->dev, "failed ioremap()\n");
  395. ret = -EINVAL;
  396. goto err_nomap;
  397. }
  398. rtc_clk = clk_get(&pdev->dev, "rtc");
  399. if (IS_ERR(rtc_clk)) {
  400. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  401. ret = PTR_ERR(rtc_clk);
  402. rtc_clk = NULL;
  403. goto err_clk;
  404. }
  405. clk_enable(rtc_clk);
  406. /* check to see if everything is setup correctly */
  407. s3c_rtc_enable(pdev, 1);
  408. pr_debug("s3c2410_rtc: RTCCON=%02x\n",
  409. readw(s3c_rtc_base + S3C2410_RTCCON));
  410. device_init_wakeup(&pdev->dev, 1);
  411. /* register RTC and exit */
  412. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  413. THIS_MODULE);
  414. if (IS_ERR(rtc)) {
  415. dev_err(&pdev->dev, "cannot attach rtc\n");
  416. ret = PTR_ERR(rtc);
  417. goto err_nortc;
  418. }
  419. s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
  420. /* Check RTC Time */
  421. s3c_rtc_gettime(NULL, &rtc_tm);
  422. if (rtc_valid_tm(&rtc_tm)) {
  423. rtc_tm.tm_year = 100;
  424. rtc_tm.tm_mon = 0;
  425. rtc_tm.tm_mday = 1;
  426. rtc_tm.tm_hour = 0;
  427. rtc_tm.tm_min = 0;
  428. rtc_tm.tm_sec = 0;
  429. s3c_rtc_settime(NULL, &rtc_tm);
  430. dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
  431. }
  432. if (s3c_rtc_cpu_type != TYPE_S3C2410)
  433. rtc->max_user_freq = 32768;
  434. else
  435. rtc->max_user_freq = 128;
  436. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  437. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  438. tmp |= S3C2443_RTCCON_TICSEL;
  439. writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
  440. }
  441. platform_set_drvdata(pdev, rtc);
  442. s3c_rtc_setfreq(&pdev->dev, 1);
  443. ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq,
  444. 0, "s3c2410-rtc alarm", rtc);
  445. if (ret) {
  446. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  447. goto err_alarm_irq;
  448. }
  449. ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq,
  450. 0, "s3c2410-rtc tick", rtc);
  451. if (ret) {
  452. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  453. free_irq(s3c_rtc_alarmno, rtc);
  454. goto err_tick_irq;
  455. }
  456. clk_disable(rtc_clk);
  457. return 0;
  458. err_tick_irq:
  459. free_irq(s3c_rtc_alarmno, rtc);
  460. err_alarm_irq:
  461. platform_set_drvdata(pdev, NULL);
  462. rtc_device_unregister(rtc);
  463. err_nortc:
  464. s3c_rtc_enable(pdev, 0);
  465. clk_disable(rtc_clk);
  466. clk_put(rtc_clk);
  467. err_clk:
  468. iounmap(s3c_rtc_base);
  469. err_nomap:
  470. release_resource(s3c_rtc_mem);
  471. err_nores:
  472. return ret;
  473. }
  474. #ifdef CONFIG_PM
  475. /* RTC Power management control */
  476. static int ticnt_save, ticnt_en_save;
  477. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  478. {
  479. clk_enable(rtc_clk);
  480. /* save TICNT for anyone using periodic interrupts */
  481. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  482. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  483. ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
  484. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  485. }
  486. s3c_rtc_enable(pdev, 0);
  487. if (device_may_wakeup(&pdev->dev) && !wake_en) {
  488. if (enable_irq_wake(s3c_rtc_alarmno) == 0)
  489. wake_en = true;
  490. else
  491. dev_err(&pdev->dev, "enable_irq_wake failed\n");
  492. }
  493. clk_disable(rtc_clk);
  494. return 0;
  495. }
  496. static int s3c_rtc_resume(struct platform_device *pdev)
  497. {
  498. unsigned int tmp;
  499. clk_enable(rtc_clk);
  500. s3c_rtc_enable(pdev, 1);
  501. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  502. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  503. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  504. writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  505. }
  506. if (device_may_wakeup(&pdev->dev) && wake_en) {
  507. disable_irq_wake(s3c_rtc_alarmno);
  508. wake_en = false;
  509. }
  510. clk_disable(rtc_clk);
  511. return 0;
  512. }
  513. #else
  514. #define s3c_rtc_suspend NULL
  515. #define s3c_rtc_resume NULL
  516. #endif
  517. #ifdef CONFIG_OF
  518. static const struct of_device_id s3c_rtc_dt_match[] = {
  519. {
  520. .compatible = "samsung,s3c2410-rtc"
  521. .data = TYPE_S3C2410,
  522. }, {
  523. .compatible = "samsung,s3c2416-rtc"
  524. .data = TYPE_S3C2416,
  525. }, {
  526. .compatible = "samsung,s3c2443-rtc"
  527. .data = TYPE_S3C2443,
  528. }, {
  529. .compatible = "samsung,s3c6410-rtc"
  530. .data = TYPE_S3C64XX,
  531. },
  532. {},
  533. };
  534. MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
  535. #else
  536. #define s3c_rtc_dt_match NULL
  537. #endif
  538. static struct platform_device_id s3c_rtc_driver_ids[] = {
  539. {
  540. .name = "s3c2410-rtc",
  541. .driver_data = TYPE_S3C2410,
  542. }, {
  543. .name = "s3c2416-rtc",
  544. .driver_data = TYPE_S3C2416,
  545. }, {
  546. .name = "s3c2443-rtc",
  547. .driver_data = TYPE_S3C2443,
  548. }, {
  549. .name = "s3c64xx-rtc",
  550. .driver_data = TYPE_S3C64XX,
  551. },
  552. { }
  553. };
  554. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  555. static struct platform_driver s3c_rtc_driver = {
  556. .probe = s3c_rtc_probe,
  557. .remove = __devexit_p(s3c_rtc_remove),
  558. .suspend = s3c_rtc_suspend,
  559. .resume = s3c_rtc_resume,
  560. .id_table = s3c_rtc_driver_ids,
  561. .driver = {
  562. .name = "s3c-rtc",
  563. .owner = THIS_MODULE,
  564. .of_match_table = s3c_rtc_dt_match,
  565. },
  566. };
  567. module_platform_driver(s3c_rtc_driver);
  568. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  569. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  570. MODULE_LICENSE("GPL");
  571. MODULE_ALIAS("platform:s3c2410-rtc");