msm_iommu.c 17 KB

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  1. /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/errno.h>
  22. #include <linux/io.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/list.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/slab.h>
  27. #include <linux/iommu.h>
  28. #include <linux/clk.h>
  29. #include <asm/cacheflush.h>
  30. #include <asm/sizes.h>
  31. #include <mach/iommu_hw-8xxx.h>
  32. #include <mach/iommu.h>
  33. #define MRC(reg, processor, op1, crn, crm, op2) \
  34. __asm__ __volatile__ ( \
  35. " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
  36. : "=r" (reg))
  37. #define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0)
  38. #define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1)
  39. /* bitmap of the page sizes currently supported */
  40. #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
  41. static int msm_iommu_tex_class[4];
  42. DEFINE_SPINLOCK(msm_iommu_lock);
  43. struct msm_priv {
  44. unsigned long *pgtable;
  45. struct list_head list_attached;
  46. };
  47. static int __enable_clocks(struct msm_iommu_drvdata *drvdata)
  48. {
  49. int ret;
  50. ret = clk_enable(drvdata->pclk);
  51. if (ret)
  52. goto fail;
  53. if (drvdata->clk) {
  54. ret = clk_enable(drvdata->clk);
  55. if (ret)
  56. clk_disable(drvdata->pclk);
  57. }
  58. fail:
  59. return ret;
  60. }
  61. static void __disable_clocks(struct msm_iommu_drvdata *drvdata)
  62. {
  63. if (drvdata->clk)
  64. clk_disable(drvdata->clk);
  65. clk_disable(drvdata->pclk);
  66. }
  67. static int __flush_iotlb(struct iommu_domain *domain)
  68. {
  69. struct msm_priv *priv = domain->priv;
  70. struct msm_iommu_drvdata *iommu_drvdata;
  71. struct msm_iommu_ctx_drvdata *ctx_drvdata;
  72. int ret = 0;
  73. #ifndef CONFIG_IOMMU_PGTABLES_L2
  74. unsigned long *fl_table = priv->pgtable;
  75. int i;
  76. if (!list_empty(&priv->list_attached)) {
  77. dmac_flush_range(fl_table, fl_table + SZ_16K);
  78. for (i = 0; i < NUM_FL_PTE; i++)
  79. if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
  80. void *sl_table = __va(fl_table[i] &
  81. FL_BASE_MASK);
  82. dmac_flush_range(sl_table, sl_table + SZ_4K);
  83. }
  84. }
  85. #endif
  86. list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
  87. if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
  88. BUG();
  89. iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
  90. BUG_ON(!iommu_drvdata);
  91. ret = __enable_clocks(iommu_drvdata);
  92. if (ret)
  93. goto fail;
  94. SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
  95. __disable_clocks(iommu_drvdata);
  96. }
  97. fail:
  98. return ret;
  99. }
  100. static void __reset_context(void __iomem *base, int ctx)
  101. {
  102. SET_BPRCOSH(base, ctx, 0);
  103. SET_BPRCISH(base, ctx, 0);
  104. SET_BPRCNSH(base, ctx, 0);
  105. SET_BPSHCFG(base, ctx, 0);
  106. SET_BPMTCFG(base, ctx, 0);
  107. SET_ACTLR(base, ctx, 0);
  108. SET_SCTLR(base, ctx, 0);
  109. SET_FSRRESTORE(base, ctx, 0);
  110. SET_TTBR0(base, ctx, 0);
  111. SET_TTBR1(base, ctx, 0);
  112. SET_TTBCR(base, ctx, 0);
  113. SET_BFBCR(base, ctx, 0);
  114. SET_PAR(base, ctx, 0);
  115. SET_FAR(base, ctx, 0);
  116. SET_CTX_TLBIALL(base, ctx, 0);
  117. SET_TLBFLPTER(base, ctx, 0);
  118. SET_TLBSLPTER(base, ctx, 0);
  119. SET_TLBLKCR(base, ctx, 0);
  120. SET_PRRR(base, ctx, 0);
  121. SET_NMRR(base, ctx, 0);
  122. }
  123. static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
  124. {
  125. unsigned int prrr, nmrr;
  126. __reset_context(base, ctx);
  127. /* Set up HTW mode */
  128. /* TLB miss configuration: perform HTW on miss */
  129. SET_TLBMCFG(base, ctx, 0x3);
  130. /* V2P configuration: HTW for access */
  131. SET_V2PCFG(base, ctx, 0x3);
  132. SET_TTBCR(base, ctx, 0);
  133. SET_TTBR0_PA(base, ctx, (pgtable >> 14));
  134. /* Invalidate the TLB for this context */
  135. SET_CTX_TLBIALL(base, ctx, 0);
  136. /* Set interrupt number to "secure" interrupt */
  137. SET_IRPTNDX(base, ctx, 0);
  138. /* Enable context fault interrupt */
  139. SET_CFEIE(base, ctx, 1);
  140. /* Stall access on a context fault and let the handler deal with it */
  141. SET_CFCFG(base, ctx, 1);
  142. /* Redirect all cacheable requests to L2 slave port. */
  143. SET_RCISH(base, ctx, 1);
  144. SET_RCOSH(base, ctx, 1);
  145. SET_RCNSH(base, ctx, 1);
  146. /* Turn on TEX Remap */
  147. SET_TRE(base, ctx, 1);
  148. /* Set TEX remap attributes */
  149. RCP15_PRRR(prrr);
  150. RCP15_NMRR(nmrr);
  151. SET_PRRR(base, ctx, prrr);
  152. SET_NMRR(base, ctx, nmrr);
  153. /* Turn on BFB prefetch */
  154. SET_BFBDFE(base, ctx, 1);
  155. #ifdef CONFIG_IOMMU_PGTABLES_L2
  156. /* Configure page tables as inner-cacheable and shareable to reduce
  157. * the TLB miss penalty.
  158. */
  159. SET_TTBR0_SH(base, ctx, 1);
  160. SET_TTBR1_SH(base, ctx, 1);
  161. SET_TTBR0_NOS(base, ctx, 1);
  162. SET_TTBR1_NOS(base, ctx, 1);
  163. SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
  164. SET_TTBR0_IRGNL(base, ctx, 1);
  165. SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
  166. SET_TTBR1_IRGNL(base, ctx, 1);
  167. SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
  168. SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
  169. #endif
  170. /* Enable the MMU */
  171. SET_M(base, ctx, 1);
  172. }
  173. static int msm_iommu_domain_init(struct iommu_domain *domain)
  174. {
  175. struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  176. if (!priv)
  177. goto fail_nomem;
  178. INIT_LIST_HEAD(&priv->list_attached);
  179. priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
  180. get_order(SZ_16K));
  181. if (!priv->pgtable)
  182. goto fail_nomem;
  183. memset(priv->pgtable, 0, SZ_16K);
  184. domain->priv = priv;
  185. return 0;
  186. fail_nomem:
  187. kfree(priv);
  188. return -ENOMEM;
  189. }
  190. static void msm_iommu_domain_destroy(struct iommu_domain *domain)
  191. {
  192. struct msm_priv *priv;
  193. unsigned long flags;
  194. unsigned long *fl_table;
  195. int i;
  196. spin_lock_irqsave(&msm_iommu_lock, flags);
  197. priv = domain->priv;
  198. domain->priv = NULL;
  199. if (priv) {
  200. fl_table = priv->pgtable;
  201. for (i = 0; i < NUM_FL_PTE; i++)
  202. if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
  203. free_page((unsigned long) __va(((fl_table[i]) &
  204. FL_BASE_MASK)));
  205. free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
  206. priv->pgtable = NULL;
  207. }
  208. kfree(priv);
  209. spin_unlock_irqrestore(&msm_iommu_lock, flags);
  210. }
  211. static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
  212. {
  213. struct msm_priv *priv;
  214. struct msm_iommu_ctx_dev *ctx_dev;
  215. struct msm_iommu_drvdata *iommu_drvdata;
  216. struct msm_iommu_ctx_drvdata *ctx_drvdata;
  217. struct msm_iommu_ctx_drvdata *tmp_drvdata;
  218. int ret = 0;
  219. unsigned long flags;
  220. spin_lock_irqsave(&msm_iommu_lock, flags);
  221. priv = domain->priv;
  222. if (!priv || !dev) {
  223. ret = -EINVAL;
  224. goto fail;
  225. }
  226. iommu_drvdata = dev_get_drvdata(dev->parent);
  227. ctx_drvdata = dev_get_drvdata(dev);
  228. ctx_dev = dev->platform_data;
  229. if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
  230. ret = -EINVAL;
  231. goto fail;
  232. }
  233. if (!list_empty(&ctx_drvdata->attached_elm)) {
  234. ret = -EBUSY;
  235. goto fail;
  236. }
  237. list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
  238. if (tmp_drvdata == ctx_drvdata) {
  239. ret = -EBUSY;
  240. goto fail;
  241. }
  242. ret = __enable_clocks(iommu_drvdata);
  243. if (ret)
  244. goto fail;
  245. __program_context(iommu_drvdata->base, ctx_dev->num,
  246. __pa(priv->pgtable));
  247. __disable_clocks(iommu_drvdata);
  248. list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
  249. ret = __flush_iotlb(domain);
  250. fail:
  251. spin_unlock_irqrestore(&msm_iommu_lock, flags);
  252. return ret;
  253. }
  254. static void msm_iommu_detach_dev(struct iommu_domain *domain,
  255. struct device *dev)
  256. {
  257. struct msm_priv *priv;
  258. struct msm_iommu_ctx_dev *ctx_dev;
  259. struct msm_iommu_drvdata *iommu_drvdata;
  260. struct msm_iommu_ctx_drvdata *ctx_drvdata;
  261. unsigned long flags;
  262. int ret;
  263. spin_lock_irqsave(&msm_iommu_lock, flags);
  264. priv = domain->priv;
  265. if (!priv || !dev)
  266. goto fail;
  267. iommu_drvdata = dev_get_drvdata(dev->parent);
  268. ctx_drvdata = dev_get_drvdata(dev);
  269. ctx_dev = dev->platform_data;
  270. if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
  271. goto fail;
  272. ret = __flush_iotlb(domain);
  273. if (ret)
  274. goto fail;
  275. ret = __enable_clocks(iommu_drvdata);
  276. if (ret)
  277. goto fail;
  278. __reset_context(iommu_drvdata->base, ctx_dev->num);
  279. __disable_clocks(iommu_drvdata);
  280. list_del_init(&ctx_drvdata->attached_elm);
  281. fail:
  282. spin_unlock_irqrestore(&msm_iommu_lock, flags);
  283. }
  284. static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
  285. phys_addr_t pa, size_t len, int prot)
  286. {
  287. struct msm_priv *priv;
  288. unsigned long flags;
  289. unsigned long *fl_table;
  290. unsigned long *fl_pte;
  291. unsigned long fl_offset;
  292. unsigned long *sl_table;
  293. unsigned long *sl_pte;
  294. unsigned long sl_offset;
  295. unsigned int pgprot;
  296. int ret = 0, tex, sh;
  297. spin_lock_irqsave(&msm_iommu_lock, flags);
  298. sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
  299. tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
  300. if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
  301. ret = -EINVAL;
  302. goto fail;
  303. }
  304. priv = domain->priv;
  305. if (!priv) {
  306. ret = -EINVAL;
  307. goto fail;
  308. }
  309. fl_table = priv->pgtable;
  310. if (len != SZ_16M && len != SZ_1M &&
  311. len != SZ_64K && len != SZ_4K) {
  312. pr_debug("Bad size: %d\n", len);
  313. ret = -EINVAL;
  314. goto fail;
  315. }
  316. if (!fl_table) {
  317. pr_debug("Null page table\n");
  318. ret = -EINVAL;
  319. goto fail;
  320. }
  321. if (len == SZ_16M || len == SZ_1M) {
  322. pgprot = sh ? FL_SHARED : 0;
  323. pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
  324. pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
  325. pgprot |= tex & 0x04 ? FL_TEX0 : 0;
  326. } else {
  327. pgprot = sh ? SL_SHARED : 0;
  328. pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
  329. pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
  330. pgprot |= tex & 0x04 ? SL_TEX0 : 0;
  331. }
  332. fl_offset = FL_OFFSET(va); /* Upper 12 bits */
  333. fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
  334. if (len == SZ_16M) {
  335. int i = 0;
  336. for (i = 0; i < 16; i++)
  337. *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
  338. FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
  339. FL_SHARED | FL_NG | pgprot;
  340. }
  341. if (len == SZ_1M)
  342. *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG |
  343. FL_TYPE_SECT | FL_SHARED | pgprot;
  344. /* Need a 2nd level table */
  345. if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
  346. unsigned long *sl;
  347. sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
  348. get_order(SZ_4K));
  349. if (!sl) {
  350. pr_debug("Could not allocate second level table\n");
  351. ret = -ENOMEM;
  352. goto fail;
  353. }
  354. memset(sl, 0, SZ_4K);
  355. *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
  356. }
  357. sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
  358. sl_offset = SL_OFFSET(va);
  359. sl_pte = sl_table + sl_offset;
  360. if (len == SZ_4K)
  361. *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG |
  362. SL_SHARED | SL_TYPE_SMALL | pgprot;
  363. if (len == SZ_64K) {
  364. int i;
  365. for (i = 0; i < 16; i++)
  366. *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
  367. SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
  368. }
  369. ret = __flush_iotlb(domain);
  370. fail:
  371. spin_unlock_irqrestore(&msm_iommu_lock, flags);
  372. return ret;
  373. }
  374. static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
  375. size_t len)
  376. {
  377. struct msm_priv *priv;
  378. unsigned long flags;
  379. unsigned long *fl_table;
  380. unsigned long *fl_pte;
  381. unsigned long fl_offset;
  382. unsigned long *sl_table;
  383. unsigned long *sl_pte;
  384. unsigned long sl_offset;
  385. int i, ret = 0;
  386. spin_lock_irqsave(&msm_iommu_lock, flags);
  387. priv = domain->priv;
  388. if (!priv)
  389. goto fail;
  390. fl_table = priv->pgtable;
  391. if (len != SZ_16M && len != SZ_1M &&
  392. len != SZ_64K && len != SZ_4K) {
  393. pr_debug("Bad length: %d\n", len);
  394. goto fail;
  395. }
  396. if (!fl_table) {
  397. pr_debug("Null page table\n");
  398. goto fail;
  399. }
  400. fl_offset = FL_OFFSET(va); /* Upper 12 bits */
  401. fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
  402. if (*fl_pte == 0) {
  403. pr_debug("First level PTE is 0\n");
  404. goto fail;
  405. }
  406. /* Unmap supersection */
  407. if (len == SZ_16M)
  408. for (i = 0; i < 16; i++)
  409. *(fl_pte+i) = 0;
  410. if (len == SZ_1M)
  411. *fl_pte = 0;
  412. sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
  413. sl_offset = SL_OFFSET(va);
  414. sl_pte = sl_table + sl_offset;
  415. if (len == SZ_64K) {
  416. for (i = 0; i < 16; i++)
  417. *(sl_pte+i) = 0;
  418. }
  419. if (len == SZ_4K)
  420. *sl_pte = 0;
  421. if (len == SZ_4K || len == SZ_64K) {
  422. int used = 0;
  423. for (i = 0; i < NUM_SL_PTE; i++)
  424. if (sl_table[i])
  425. used = 1;
  426. if (!used) {
  427. free_page((unsigned long)sl_table);
  428. *fl_pte = 0;
  429. }
  430. }
  431. ret = __flush_iotlb(domain);
  432. fail:
  433. spin_unlock_irqrestore(&msm_iommu_lock, flags);
  434. /* the IOMMU API requires us to return how many bytes were unmapped */
  435. len = ret ? 0 : len;
  436. return len;
  437. }
  438. static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
  439. unsigned long va)
  440. {
  441. struct msm_priv *priv;
  442. struct msm_iommu_drvdata *iommu_drvdata;
  443. struct msm_iommu_ctx_drvdata *ctx_drvdata;
  444. unsigned int par;
  445. unsigned long flags;
  446. void __iomem *base;
  447. phys_addr_t ret = 0;
  448. int ctx;
  449. spin_lock_irqsave(&msm_iommu_lock, flags);
  450. priv = domain->priv;
  451. if (list_empty(&priv->list_attached))
  452. goto fail;
  453. ctx_drvdata = list_entry(priv->list_attached.next,
  454. struct msm_iommu_ctx_drvdata, attached_elm);
  455. iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
  456. base = iommu_drvdata->base;
  457. ctx = ctx_drvdata->num;
  458. ret = __enable_clocks(iommu_drvdata);
  459. if (ret)
  460. goto fail;
  461. /* Invalidate context TLB */
  462. SET_CTX_TLBIALL(base, ctx, 0);
  463. SET_V2PPR(base, ctx, va & V2Pxx_VA);
  464. par = GET_PAR(base, ctx);
  465. /* We are dealing with a supersection */
  466. if (GET_NOFAULT_SS(base, ctx))
  467. ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
  468. else /* Upper 20 bits from PAR, lower 12 from VA */
  469. ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
  470. if (GET_FAULT(base, ctx))
  471. ret = 0;
  472. __disable_clocks(iommu_drvdata);
  473. fail:
  474. spin_unlock_irqrestore(&msm_iommu_lock, flags);
  475. return ret;
  476. }
  477. static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
  478. unsigned long cap)
  479. {
  480. return 0;
  481. }
  482. static void print_ctx_regs(void __iomem *base, int ctx)
  483. {
  484. unsigned int fsr = GET_FSR(base, ctx);
  485. pr_err("FAR = %08x PAR = %08x\n",
  486. GET_FAR(base, ctx), GET_PAR(base, ctx));
  487. pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
  488. (fsr & 0x02) ? "TF " : "",
  489. (fsr & 0x04) ? "AFF " : "",
  490. (fsr & 0x08) ? "APF " : "",
  491. (fsr & 0x10) ? "TLBMF " : "",
  492. (fsr & 0x20) ? "HTWDEEF " : "",
  493. (fsr & 0x40) ? "HTWSEEF " : "",
  494. (fsr & 0x80) ? "MHF " : "",
  495. (fsr & 0x10000) ? "SL " : "",
  496. (fsr & 0x40000000) ? "SS " : "",
  497. (fsr & 0x80000000) ? "MULTI " : "");
  498. pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
  499. GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
  500. pr_err("TTBR0 = %08x TTBR1 = %08x\n",
  501. GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
  502. pr_err("SCTLR = %08x ACTLR = %08x\n",
  503. GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
  504. pr_err("PRRR = %08x NMRR = %08x\n",
  505. GET_PRRR(base, ctx), GET_NMRR(base, ctx));
  506. }
  507. irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
  508. {
  509. struct msm_iommu_drvdata *drvdata = dev_id;
  510. void __iomem *base;
  511. unsigned int fsr;
  512. int i, ret;
  513. spin_lock(&msm_iommu_lock);
  514. if (!drvdata) {
  515. pr_err("Invalid device ID in context interrupt handler\n");
  516. goto fail;
  517. }
  518. base = drvdata->base;
  519. pr_err("Unexpected IOMMU page fault!\n");
  520. pr_err("base = %08x\n", (unsigned int) base);
  521. ret = __enable_clocks(drvdata);
  522. if (ret)
  523. goto fail;
  524. for (i = 0; i < drvdata->ncb; i++) {
  525. fsr = GET_FSR(base, i);
  526. if (fsr) {
  527. pr_err("Fault occurred in context %d.\n", i);
  528. pr_err("Interesting registers:\n");
  529. print_ctx_regs(base, i);
  530. SET_FSR(base, i, 0x4000000F);
  531. }
  532. }
  533. __disable_clocks(drvdata);
  534. fail:
  535. spin_unlock(&msm_iommu_lock);
  536. return 0;
  537. }
  538. static struct iommu_ops msm_iommu_ops = {
  539. .domain_init = msm_iommu_domain_init,
  540. .domain_destroy = msm_iommu_domain_destroy,
  541. .attach_dev = msm_iommu_attach_dev,
  542. .detach_dev = msm_iommu_detach_dev,
  543. .map = msm_iommu_map,
  544. .unmap = msm_iommu_unmap,
  545. .iova_to_phys = msm_iommu_iova_to_phys,
  546. .domain_has_cap = msm_iommu_domain_has_cap,
  547. .pgsize_bitmap = MSM_IOMMU_PGSIZES,
  548. };
  549. static int __init get_tex_class(int icp, int ocp, int mt, int nos)
  550. {
  551. int i = 0;
  552. unsigned int prrr = 0;
  553. unsigned int nmrr = 0;
  554. int c_icp, c_ocp, c_mt, c_nos;
  555. RCP15_PRRR(prrr);
  556. RCP15_NMRR(nmrr);
  557. for (i = 0; i < NUM_TEX_CLASS; i++) {
  558. c_nos = PRRR_NOS(prrr, i);
  559. c_mt = PRRR_MT(prrr, i);
  560. c_icp = NMRR_ICP(nmrr, i);
  561. c_ocp = NMRR_OCP(nmrr, i);
  562. if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
  563. return i;
  564. }
  565. return -ENODEV;
  566. }
  567. static void __init setup_iommu_tex_classes(void)
  568. {
  569. msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
  570. get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
  571. msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
  572. get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
  573. msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
  574. get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
  575. msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
  576. get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
  577. }
  578. static int __init msm_iommu_init(void)
  579. {
  580. setup_iommu_tex_classes();
  581. bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
  582. return 0;
  583. }
  584. subsys_initcall(msm_iommu_init);
  585. MODULE_LICENSE("GPL v2");
  586. MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");